GE MAC 5000 Service Manual page 37

Equipment Overview: Theory of Operation
pixel. In that scheme, pixel manipulations required the CPU to read the
combined pixel, modify either the static or dynamic component, and
write the result back to memory. Such read-modify-write operations are
time consuming.
In contrast, the FPGA implementation of the frame buffer takes
advantage of SDRAM's high speed, large size, individual byte
addressability, and 16-bit width, to access both the static (5 bits) and
dynamic (3 bits) portions of a pixel separately, and simultaneously.
The SDRAM bus is effectively split into a "dynamic byte lane" and a
"static byte lane". The resulting improvement in drawing algorithm
speed is substantial.
The 16-bit wide bus of the SDRAM allows each read/write cycle to access
two bytes of data. During writes, upper and lower byte strobes allow
independent writing of either or both bytes. During reads, both bytes are
always presented. Unneeded read data bits are ignored by the CPU. The
LCD controller takes advantage of the individual accessibility of the
bytes to eliminate the need for the CPU to pack and unpack the static
and dynamic pixels. At the expense of unused memory bits (a small
expense as less than 1/16th of the entire SDRAM space is needed at all)
the LCD controller maps the 5 bits of each static pixel into one SDRAM
byte lane (the static lane), and the 3 bits of each static pixel into the
other (the dynamic lane). Unused bits in each lane are written as zeroes,
and ignored on reading.
On the CPU side, the SDRAM frame buffer appears as two regions, the
static and dynamic planes. Each plane is a contiguous array of 480 lines
of 640 pixels each. Within the static plane, the lower 3 bits (the dynamic
bits) of each pixel byte are ignored on writes, and read as zeroes. Within
the dynamic plane, the upper 5 bits of each pixel byte (the static bits)
are ignored on writes and read as zeroes. The dynamic plane is located
1/2 Mbyte above the static plane and address bit A19 is used to
differentiate between them. The interface from the LCD controller to the
CPU is 16-bits wide, allowing two pixel bytes to be moved in each read/
write cycle.
In the 16-bit wide SDRAM, each word (independently byte addressable)
contains both a static and a dynamic pixel byte, each in their own lanes.
When the CPU writes a pixel to the static plane, the upper five bits of the
byte are routed to the static byte lane (the lower three bits are set to
zero) and the dynamic byte lane is disabled. When the CPU reads a static
pixel, both the static and dynamic byte lanes are accessed, but only the
upper five bits of the static byte lane are passed on to the CPU (the lower
three bits are zeroed). Access to the dynamic plane proceed in much the
same manner, with the appropriate bits being routed to the dynamic byte
lane while the static byte lane is disabled.
Because each 16-bit word of SDRAM contains one pixel, and each 16-bit
access of the CPU into the frame buffer contains two, the LCD controller
must pack/unpack pixels on the fly. During writes, if the CPU signals a
single byte write, the LCD controller writes the byte onto the proper lane
(as determined by A19) of one memory word. If the CPU signals a two
byte write, the LCD controller queues a two cycle burst write into two
consecutive words of SDRAM. On reads, the LCD controller always reads
Revision B MAC™ 5000 resting ECG analysis system 2-17
2024917-010