GE MAC 5000 Service Manual page 38

Equipment Overview: Theory of Operation
two pixels from memory and packs them into a single word for access by
the CPU, which may use both pixels, or ignore one.
By design, SDRAMs are faster when data can be moved in sequential
bursts. The Atmel ARM CPU asynchronous bus interface does not
support burst accesses, so the opportunity to burst is limited. The LCD
controller does take advantage of the 16-bit wide nature of the
asynchronous bus to allow bursts of two pixels into and out of memory
when possible. This nearly doubles frame buffer bandwidth over a
byte-at-a-time interface. Finally, as mentioned previously, the CPU is
able to manipulate individual pixels in either plane without resorting to
read-modify-write access cycles. This provides another twofold
improvement in memory bandwidth.
Line Buffer – Within each line of LCD video data, bytes must move
from the frame buffer to the scroller/CLUT in an unbroken stream at
24Mhz. Although the frame buffer is capable of burst transfers of
60Mpixels/sec, it cannot be depended on to maintain that speed for more
than one SDRAM page (256 pixels). At page boundaries, the SDRAM
must initiate a new page access, and potentially satisfy refresh
requirements. Since video lines are longer (640 pixels) than SDRAM
pages, some mechanism is required to smooth the flow of pixels from the
frame buffer to the LCD.
This smoothing is provided by a 1024 byte dual port line buffer,
implemented in a pair of FPGA block RAMs. At the end of each active
LCD line, the video timing generator requests a new line of pixels from
the frame buffer. The memory arbiter services the request by bursting
640 pixels from the frame buffer to the line buffer, using the video
address supplied by the timing controller. The entire line of 640 pixels is
moved at maximum memory speed, taking a little over 11μs to complete
at 60Mhz. The pixels are then clocked out of the line buffer and
presented to the scroller/CLUT at a constant 24Mhz, taking about 30μs
per line. Double buffering is not required, as the burst fill rate far
exceeds the 24Mhz drain rate, and the fill begins during the generation
of horizontal sync, giving the controller plenty of head start on filling the
line buffer before the timing generator begins draining them out.
To keep the control logic simple, and minimize SDRAM access overhead,
each 640 pixel line is transferred from SDRAM in one transaction. This
does hold off the ARM CPU for up to 11μs at a time, but as the ARM CPU
does not access the frame buffer often, this is not thought to be an issue.
Fill Engine – The MAC 5000 routinely draws rectangular regions on
screen for use in dialog boxes and buttons. When drawn by the CPU,
frame buffer bandwidth becomes an issue, as random accesses to the
SDRAM buffer are inefficient, and many of them are required to fill large
regions of the display. To reduce both CPU and frame buffer loading, the
LCD controller provides a simple fill engine which automates the filling
of rectangular regions of the frame buffer, and takes advantage of the
burst capabilities of the SDRAM.
2-18 MAC™ 5000 resting ECG analysis system Revision B
2024917-010