Interrupt Controller - GE MAC 5000 Service Manual

Interrupt Controller

Revision B
Equipment Overview: Theory of Operation
The 5.3 format provides a palette of 2^3=8 colors for dynamic objects and
(2^5)-1=31 colors for static objects (1 of the colors is transparent, leaving
31 real colors). In practice, to "freeze" dynamic objects in the static plane
requires that the 8 dynamic colors be replicated in the static color map,
leaving only 31-8=23 new colors available for static objects. The FPGA
implements a writable color lookup table (CLUT) to map the pixel values
to sensible colors on the LCD. The CLUT provides 32- to 24-bit entries,
providing access to the complete color space offered by the LCD panel.
The color mapped LCD data is also fed to three external discrete 6-bit
DAC's to create analog video for an external CRT.
Blank/Sync
External VGA monitors are supported with two styles of video sync
signal as well as retrace blanking.
Video Sync – The horizontal and vertical sync pulses from the LCD
controller are combined to produce a composite sync signal that is added
to the video signal. The video sync signal may be disabled under software
control to accommodate monitors that do not accept sync on green. The
sync signal is applied to all three video guns to eliminate color shifting in
systems that do not perform blank level video clamping.
TTL Sync – For monitors that do not accept sync on green, TTL logic
level horizontal and vertical sync signals are provided. These may be
enabled/disabled to implement a rudimentary "sleep" operation on
Energy Star compliant monitors.
Blank – Unlike LC displays, CRT's emit light from more than just their
active display surface. The electron beam is visible even during retrace
and precautions must be taken to ensure that the guns are off in non-
active areas of the display. To ensure black borders on external monitors
(and reset the DC restore clamps in the video output buffers). The CLUT
video passes through a gating register before leaving the FPGA. This
allows the LCD DE (display enable) signal to force the guns to a blanking
level during inactive portions of the display frame.
ATMEL AT91RM9200 supports one external fast interrupt input(FIQ)
and seven external interrupt inputs. In addition all the GPIO lines can
act as an interrupt inputs. All the dedicated external interrupt inputs
are multiplexed with GPIO ports. The FPGA interrupt logic combines the
interrupts form System Timer, Acquisition interface, BBUS interface,
Thermal printhead interface and LCD controller to FIQ and Slow
Interrupt. The FIQ and Slow Interrupt from FPGA Interrupt controller
are fed to processor FIQ and IRQ0 respectively. For more detail on the
operation of the interrupt mask/status registers, see the source file
"hardware.h".
MAC™ 5000 resting ECG analysis system
2024917-010
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