Thermal Printhead Interface - GE MAC 5000 Service Manual

Thermal Printhead Interface

Revision B
Equipment Overview: Theory of Operation
Data from the acquisition module is packed into 257 bit NRZ frames. The
receive line idle state is high. The first bit of each packet is a zero and
serves as the packet start bit. As with a UART, the start bit is discarded.
The following 256 bits are received into a 16-word x 16-bit buffer for use
by the ATMEL CPU. The receive logic then looks for an idle period
(analogous to a UART stop bit) of at least 125μs in length as an indicator
that the link is again idle. Special marker words are inserted into the
ECG data packet (words 5, 10 and 15) to guarantee there will never be a
run of more than 80 bits of one's (or zeros for that matter), so there is no
possibility of satisfying the idle period requirement in the middle of a
data packet.
Because the acquisition module clock is supplied by the FPGA, receive
timing errors are limited to phase uncertainty. By searching for the
beginning of the start bit in a fashion similar to that used by a UART,
the phase uncertainty is eliminated and the remainder of the packet may
be received without further synchronization. In practice, the FPGA uses
every edge in the receive data stream to re-sync its bit sampling circuit.
It is possible for the ECG data to be all zeros or ones, so runs of as many
as 80 zeros or ones could occur before a marker word is encountered in
the data stream (which contains at least one "1" and one "0" to break any
runs in the data).
The acquisition module supports a special "code update" mode for rapid
reprogramming of its on-board code memory. To increase the update
speed, the acquisition module echoes each uploaded code byte with a
single reply word rather than the usual 16-word data packet. The FPGA
receive logic provides a special 1 word reception mode to accommodate
this.
The ATMEL CPU sends print data to the thermal print head through a
buffered serial interface. The FPGA implements the data buffer,
serializer, strobe/latch pulse generator and power switch gate drive
pump. Special interlocks are implemented to prevent stuck strobe
signals or printing when the battery voltage is critically low.
Each print line requires 1728 bits of data. To conserve FPGA resources,
each line is divided into three chunks of 512 bits each, with one leftover
chunk of 192 bits. The FPGA provides a single 32 word x 16 bit buffer
(512 bits) to hold the print line data. After writing a chunk of data to the
buffer, the ATMEL CPU enables serialization of the data by reading one
of two registers (to support the serialization of either a full 512 bit or
partial 192-bit buffer). When the entire print line has been loaded, the
ATMEL CPU cues a print strobe by writing the required strobe width
value to the strobe/latch pulse generator.
When the strobe register contains a non-zero value, the power switch
gate pump produces a differential clock signal to drive an external diode
voltage doubler (CR132-133, C262-C264, R290). The output of the
voltage doubler drives the gate of a power MOSFET (Q6) that provides
power to the print head. R288 provides gate bleed off to ensure that Q6
turns off when the pump stops. C279 filters the doubler output to DC.
MAC™ 5000 resting ECG analysis system
2024917-010
2-23