GE MAC 5000 Service Manual page 36

2-16
Equipment Overview: Theory of Operation
Format pack/unpack logic (See
page 2-16)
Line buffer (See "Line Buffer"
Fill Engine (See "Fill Engine"
Main State Machine (See
Interrupt management (See
Video Timing – The LCD controller generates video pixel and line
timing from a global 48Mhz clock inside the FPGA. The timing generator
consists of one counter for timing pixels within a line (including
generation of horizontal sync, horizontal front and back porches, and
LCD data enable timing) and another for timing lines with a frame
(including generation of vertical sync, vertical front and back porches
and generation of Line FIFO fill requests). In addition, the timing
generator increments a memory address register by the line pitch (640)
at the beginning of each video line, so the Line FIFO knows where to get
the next line of pixels. The controller produces fixed timing for a 640x480
LCD, and requires no initialization to produce that timing. Support for
future, higher resolution displays, can be obtained by modifying the
source code for the controller itself, providing the most efficient hardware
implementation possible.
SDRAM Frame Buffer Controller – The LCD obtains pixel data from
a 1Mbyte region of a 32Mbyte, 16-bit wide synchronous DRAM
(SDRAM). The SDRAM buffer is shared by the display controller and the
CPU, allowing system software to directly manipulate screen pixels.
At power-up, SDRAMs must be configured for proper operation.
Properties such as RAS/CAS latency and burst length are written into a
control register in the SDRAM, and an initial burst of refresh cycles are
performed to prepare the memory array for operations. The SDRAM
controller does this all automatically at startup, requiring no
initialization by the CPU.
SDRAMs, being dynamic, require periodic refresh to maintain the
contents of the memory array. The SDRAM controller performs this
refresh automatically between accesses. All details of SDRAM bank
management and page boundary crossing are managed automatically in
the SDRAM controller. In addition, through the use of pipelining, the
SDRAM controller allows burst accesses to and from SDRAM at full
memory speed. All details of burst cycle management, including setup
and page boundary crossings, are handled transparently by the SDRAM
controller. The SDRAM memory clock is derived from the CPU memory
clock, and is passed out of the FPGA and back in to allow one of the
FPGA's on-board DLL's to "zero out" all internal FPGA delays. This
delay compensation allows the SDRAM controller to operate reliably at
very high speeds (>= 100Mhz).
Format pack/unpack logic – The MAC 5000 display architecture is
based on the division of pixels into static and dynamic planes. As
discussed elsewhere, this technique allows the smooth scrolling of ECG
waveforms across the screen while buttons, annotations and other
graphics remain stationary. Previous generations of MAC 5000 display
controllers packed the five bits of each static plane pixels into the same
byte of memory as the three bits from the corresponding dynamic plane
MAC™ 5000 resting ECG analysis system
2024917-010
"Format pack/unpack logic"
on page 2-18)
on page 2-18)
"Main State Machine" on page 2-19)
"Interrupt Management"
on
on page 2-20)
Revision B