GE MAC 5000 Service Manual page 39

Equipment Overview: Theory of Operation
The fill engine interface is simple, consisting of four boundary registers
to define the fill region, and one register to record the fill value, and
planes to be filled. The fill engine can fill any value into any rectangular
region of the display in either or both planes simultaneously. The
bounding values (top, bottom, left, right) define the rectangle to be filled
in screen coordinates, with 0,0 at the upper left, and 639,479 at the
bottom right. The fill value contains both the dynamic (5) and static (3)
pixel bits as well as two plane enable bits.
After loading the boundary control registers, the CPU initiates the fill by
writing the requested fill value and plane enable bits to the fill value
register. The fill is then queued for the next video frame and the fill
engine becomes "busy".
Fills are implemented synchronous with frame refresh. At the
completion of each line buffer fill request from the video timing generator
the fill engine checks to see if a fill is underway. If so, the current video
line position (from the timing generator) is compared to the top and
bottom boundary registers. If the current line is between the top and
bottom, the fill engine adds the left boundary value to the current line
memory address (as provided by the timing generator) and proceeds to
write the fill value into memory until the address matches the right
boundary. Depending on the width of the filled rectangle, fill bursts can
take anywhere from 100ns to 11μs.
In this way, the fill engine follows the video timing generator down the
screen, replacing pixels in the frame buffer immediately after they are
sent to the LCD. This synchronous operation makes efficient use of the
existing address generation hardware and provides "flicker-free" fills,
regardless of region size. If fills were unsynchronized, they would often
cross two successive display frames and result in visible tearing or
flicker. As a result of this frame synchronous operation, fills always take
one frame time, regardless of their size, and complete coincident with the
end of the frame.
Main State Machine – The SDRAM frame buffer is constantly in
demand by the CPU, the video timing controller and the fill engine. The
CPU manipulates pixels in the frame buffer in real time to construct the
visible display while the video timing controller manages the constant
stream of pixels from the frame buffer into the line buffer, and on to the
scroller/CLUT. At the same time, any requested fills must access the
frame buffer to write the requested fill region. When all three contend for
access to the frame buffer simultaneously, memory bandwidth can
exceed 100Mbytes/sec.
The Main State Machine manages all these competing requests on a
priority basis, with display refresh taking top priority, followed by fills
and finally CPU accesses. The state machine runs at 60Mhz, processing
line buffer fill requests from the video timing generator, fill requests
from the fill engine and read/write requests from the CPU. The 5.3 pack/
unpack logic and fill engine logic are actually various states of the Main
State Machine.
Revision B MAC™ 5000 resting ECG analysis system 2-19
2024917-010