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Table 1-9: Expansion I/O Differential Connections (J4)
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
J4 Differential Pin Pair
Pos
Neg
4
2
8
6
12
10
16
14
20
18
24
22
28
26
32
30
36
34
40
38
44
42
48
46
52
50
56
54
60
58
64
62
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Schematic Net Name
Pos
Neg
HDR2_4
HDR2_2
HDR2_8
HDR2_6
HDR2_12
HDR2_10
HDR2_16
HDR2_14
HDR2_20
HDR2_18
HDR2_24
HDR2_22
HDR2_28
HDR2_26
HDR2_32
HDR2_30
HDR2_36
HDR2_34
HDR2_40
HDR2_38
HDR2_44
HDR2_42
HDR2_48
HDR2_46
HDR2_52
HDR2_50
HDR2_56
HDR2_54
HDR2_60
HDR2_58
HDR2_64
HDR2_62
Detailed Description
FPGA Pin
Pos
Neg
F24
F25
E25
E26
G21
G22
P19
N19
J25
J26
R22
R23
N22
N21
V26
U26
K23
K22
G26
H26
L20
L19
P23
N23
G24
G25
M20
M19
H24
J24
P21
P20
21
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