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Chapter 1: ML501 Evaluation Platform
4. Oscillator Sockets
The board has one crystal oscillator socket (X1) wired for standard LVTTL-type oscillators.
It connects to the FPGA clock pin as shown in
100-MHz oscillator and is powered by the 3.3V supply.
The board also provides an IDT5V9885 (U8) EEPROM programmable clock generator
device. This device is used to generate a variety of clocks to the board peripherals and
FPGA. The programmable clock generator provides the following factory default single-
ended outputs:
•
•
•
•
•
If users change the factory default configuration of the clock generator chip, the related
reference design material might not work as designed. Instructions for returning the
IDT5V9885 to the factory default configuration are provided in
"Programming the IDT Clock Chip."
Table 1-4: Oscillator Socket Connection
5. LCD Brightness and Contrast Adjustment
Turning potentiometer R87 adjusts the image contrast of the character LCD. The
potentiometer should be turned with a screwdriver.
6. DIP Switches (Active-High)
Eight general-purpose (active-High) DIP switches are connected to the user I/O pins of the
FPGA.
Table 1-5: DIP Switch Connections (SW4)
18
25 MHz to the Ethernet PHY (U13)
24.5 MHz to the audio codec (U16)
27 MHz to the USB controller (U18)
33 MHz to the Xilinx System ACE CF (U2)
33 MHz, 27 MHz, and a differential 200 MHz clock to the Xilinx FPGA
Label
Clock Name
X1
USER_CLK
U8
CLK_33MHZ_FPGA
U8
CLK_27MHZ_FPGA
U8
CLK_DIFF_FPGA_P
U8
CLK_DIFF_FPGA_N
Table 1-5
summarizes these connections.
SW4
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
www.xilinx.com
Table
1-4. The X1 socket is populated with a
FPGA Pin
AD8
100 MHz single-ended
AB12
33 MHz single-ended
AD13
27 MHz single-ended
E16
200 MHz differential pair (pos)
E17
200 MHz differential pair (neg)
FPGA Pin
U4
V3
T4
T5
U6
Appendix A,
Description
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
R
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