Appendix A: Programming The Idt Clock Chip; Overview; Downloading To The Ml50X Board - Xilinx ML50 Series User Manual

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Programming the IDT Clock Chip

Overview

ML50x evaluation boards feature an Integrated Device Technology (IDT) 3.3V EEPROM
Programmable Clock Generator that is pre-programmed at the factory. In the event the
chip programming is changed, the instructions in this appendix show how to return the
clock chip to its factory default settings using the following equipment:
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Downloading to the ML50x Board

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ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
Xilinx download cable
JTAG flying wires
Connect a Xilinx download cable to the board using flying leads connected to jumper
J3 (Figure A-1).
Figure A-1: J3 IDT5V9885 JTAG Connector
Click Start → iMPACT.
Click Boundary Scan.
Right-click Add Xilinx Device...
Locate the SVF file (ML50X_clock_setup.svf in the example shown in
page 40) and click Open.
Note:
The ML50X_clock_setup.svf file is available on the ML50x product page.
Right-click on the device and select Execute XSVF/SVF.
www.xilinx.com
CLK Prog
J3
TMS
1
TDI
TDO
TCK
GND
3.3V
UG226_apdx_a_01_031207
Appendix A
Figure A-2,
39