Xilinx ML50 Series User Manual page 24

Evaluation platform
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Chapter 1: ML501 Evaluation Platform
Table 1-11: Additional Expansion I/O Connections (J5)
24
J5 Pin
Label
1
VCC5
2
VCC5
3
VCC5
4
VCC5
5
NC
6
VCC3V3
7
VCC3V3
8
VCC3V3
9
VCC3V3
10
NC
11
FPGA_EXP_TMS
12
FPGA_EXP_TCK
13
FPGA_EXP_TDO
FPGA_EXP_TDI
14
15
GPIO_LED_N
16
SW3 (N)
17
GPIO_LED_C
18
SW14 (C)
19
GPIO_LED_W
20
SW13 (W)
21
GPIO_LED_S
22
SW11 (S)
23
GPIO_LED_E
24
SW12 (E)
25
GPIOLED 0
26
GPIOLED 1
27
GPIOLED 2
28
GPIOLED 3
29
NC
30
NC
31
IIC_SCL_EXP
IIC_SDA_EXP
32
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FPGA Pin
Description
5V Power Supply
5V Power Supply
5V Power Supply
5V Power Supply
Not Connected
3.3V Power Supply
3.3V Power Supply
3.3V Power Supply
3.3V Power Supply
Not Connected
Expansion TMS
Expansion TCK
Expansion TDO
Expansion TDI
Y8
LED North
A22
GPIO Switch North
T22
LED Center
B21
GPIO Switch Center
AA18
LED West
C21
GPIO Switch West
AA8
LED South
B22
GPIO Switch South
Y18
LED East
A23
GPIO Switch East
E13
GPIO LED 0
D14
GPIO LED 1
E12
GPIO LED 2
F12
GPIO LED 3
-
Not Connected
-
Not Connected
R20
Expansion IIC SCL
T20
Expansion IIC SDA
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
R

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