Table of Contents
Advertisement
R
Table 1-16: System Monitor Connections (Continued)
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
External Input
FPGA Pin
VAUXP[1]
M25
VAUXN[2]
K26
VAUXP[2]
K25
VAUXN[3]
L25
VAUXP[3]
L24
VAUXN[4]
J24
VAUXP[4]
H24
VAUXN[5]
G25
VAUXP[5]
G24
VAUXN[6]
H26
VAUXP[6]
G26
VAUXN[7]
E26
VAUXP[7]
E25
VAUXN[8]
F25
VAUXP[8]
F24
VAUXN[9]
P20
VAUXP[9]
P21
VAUXN[10]
R23
VAUXP[10]
R22
VAUXN[11]
N21
VAUXP[11]
N22
VAUXN[12]
N23
VAUXP[12]
P23
VAUXN[13]
M19
VAUXP[13]
M20
VAUXN[14]
L19
VAUXP[14]
L20
VAUXN[15]
K22
VAUXP[15]
K23
www.xilinx.com
Header Pin
Schematic Net Name
J6-28
HDR1_28_SM_1_P
J6-22
HDR1_22_SM_2_N
J6-24
HDR1_24_SM_2_P
J6-18
HDR1_18_SM_3_N
J6-20
HDR1_20_SM_3_P
J4-58
HDR2_58_SM_4_N
J4-60
HDR2_60_SM_4_P
J4-50
HDR2_50_SM_5_P
J4-52
HDR2_52_SM_5_P
J4-38
HDR2_38_SM_6_N
J4-40
HDR2_40_SM_6_P
J4-6
HDR2_6_SM_7_N
J4-8
HDR2_8_SM_7_P
J4-2
HDR2_2_SM_8_N
J4-4
HDR2_4_SM_8_P
J4-62
HDR2_62_SM_9_N
J4-64
HDR2_64_SM_9_P
J4-22
HDR2_22_SM_10_N
J4-22
HDR2_24_SM_10_P
J4-26
HDR2_26_SM_11_N
J4-28
HDR2_28_SM_11_P
J4-46
HDR2_46_SM_12_N
J4-48
HDR2_48_SM_12_P
J4-54
HDR2_54_SM_13_N
J4-56
HDR2_56_SM_13_P
J4-42
HDR2_42_SM_14_N
J4-44
HDR2_44_SM_14_P
J4-34
HDR2_34_SM_15_N
J4-36
HDR2_36_SM_15_P
Detailed Description
35
Advertisement
Table of Contents
