Xilinx ML50 Series User Manual page 17

R
A differential clock output from the FPGA is driven out through a second pair of SMA
connectors. This allows the FPGA to drive a precision clock to an external device such as a
piece of test equipment.
Table 1-3: Differential SMA Clock Connections
ML501 Evaluation Platform
UG226 (v1.3) November 10, 2008
Table 1-3
Label Clock Name
J10 SMA_DIFF_CLK_IN_N
J11 SMA_DIFF_CLK_IN_P
J12 SMA_DIFF_CLK_OUT_N
J13 SMA_DIFF_CLK_OUT_P
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summarizes the differential SMA clock pin connections.
FPGA Pin
F10
F9
F19
E18
Detailed Description
17