Single-Ended Expansion I/O Connectors - Xilinx ML50 Series User Manual

Chapter 1: ML501 Evaluation Platform

Single-Ended Expansion I/O Connectors

Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed, single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
3.3V by setting jumper J20.
expansion I/O connector.
Table 1-10: Expansion I/O Single-Ended Connections (J6)
22
Table 1-10
J6 Pin Schematic Net Name
2 HDR1_2
4 HDR1_4
6 HDR1_6
8 HDR1_8
10 HDR1_10
12 HDR1_12
14 HDR1_14
16 HDR1_16
18 HDR1_18
20 HDR1_20
22 HDR1_22
24 HDR1_24
26 HDR1_26
28 HDR1_28
30 HDR1_30
32 HDR1_32
34 HDR1_34
36 HDR1_36
38 HDR1_38
40 HDR1_40
42 HDR1_42
44 HDR1_44
46 HDR1_46
48 HDR1_48
50 HDR1_50
52 HDR1_52
54 HDR1_54
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of these signals can be set to 2.5V or
CCIO
summarizes the single-ended connections on this
FPGA Pin
J20
J23
J21
H23
M22
K20
K21
M21
L25
L24
K26
K25
M26
M25
N24
M24
AB25
N26
P25
P24
T24
T25
U24
U25
W25
W26
Y25
UG226 (v1.3) November 10, 2008
ML501 Evaluation Platform
R