Figure 18-40. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0) - GigaDevice Semiconductor GD32VF103 User Manual

(DTLEN=01, CHLEN=1, CKPL=1)
18 38
Figure - . PCM standard short frame synchronization mode timing diagram
(DTLEN=00, CHLEN=1, CKPL=0)
18 39
Figure - . PCM standard short frame synchronization mode timing diagram
(DTLEN=00, CHLEN=1, CKPL=1)
The timing diagrams for each configuration of the long frame synchronization mode are shown
below.
18 40
Figure - . PCM standard long frame synchronization mode timing diagram
(DTLEN=00, CHLEN=0, CKPL=0)
18 41
Figure - . PCM standard long frame synchronization mode timing diagram
(DTLEN=00, CHLEN=0, CKPL=1)
I2S_CK
I2S_WS
I2S_SD
18 42
Figure - . PCM standard long frame synchronization mode timing diagram
frame 1
16-bit data
MSB
frame 1
13 bits
MSB
frame 1
13 bits
MSB
GD32VF103 User Manual
16-bit 0
16 bits
16 bits
frame 2
MSB
frame 2
LSB MSB
frame 2
LSB MSB
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