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Summary of Contents for GigaDevice Semiconductor BootLoader GD32H7 Series
- Page 1 GigaDevice Semiconductor Inc. Precautions for GD32H7xx BootLoader Operation Application Notes AN126 Version 1.0 (April 2023)
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Page 2: Table Of Contents
AN126 Precautions for GD32H7xx BootLoader Operation Table of Contents Table of Contents ......................2 List of Tables ........................3 Foreword ....................... 4 Option byte operation ..................5 2.1. DCRP operation ......................5 2.2. SCR operation ......................5 2.3. Hybrid operation of SCR and DCRP ................7 Efuse operation ..................... -
Page 3: List Of Tables
AN126 Precautions for GD32H7xx BootLoader Operation List of Tables Table 7-1. Revision history ........................ 12... -
Page 4: Foreword
AN126 Precautions for GD32H7xx BootLoader Operation Foreword BootLoader of GD32H7xx supports three types of communication interfaces, including Usart, DFU and SDIO. Different interfaces require different hardware support. There are three Usart interfaces, including Usart0 (PA9, PA10), Usart1 (PA2, PA3), and Usart2 (PB10, PB11). There is only one DFU interface, namely USB0 (USBHS0_DP, USBHS0_DM). -
Page 5: Option Byte Operation
AN126 Precautions for GD32H7xx BootLoader Operation Option byte operation Operations of option bytes of GD32H7xx are mainly achieved by modifying related register. Each register consists of two groups (EFT register and MDF register). Users can modify MDF register only. For details, please refer to GD32H737_757_759 User Manual. - Page 6 AN126 Precautions for GD32H7xx BootLoader Operation 1. Once SCR is enabled, MCU will be activated from the address set in BOOT_ADDR0, regardless of Boot pin status. 2. Enabled SCR can be connected to MCU through JTAG or SWD interface, but the application can't be debugged or downloaded in IDE.
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Page 7: Hybrid Operation Of Scr And Dcrp
AN126 Precautions for GD32H7xx BootLoader Operation Hybrid operation of SCR and DCRP 2.3. After DCRP area and SCR bit are set, SCR bit can not be cleared directly. At this time, SCR bit and other bits in the register where SCR bit is located can not be modified simultaneously, and all modifications do not work. -
Page 8: Efuse Operation
AN126 Precautions for GD32H7xx BootLoader Operation Efuse operation Efuse can be operated with Bootloader, but once a byte of Efuse is rewritten from 0 to 1, it can not be recovered to 0, so the operation is stricter. Therefore, it is recommended not to modify Efuse at will. -
Page 9: Sdio Interface
AN126 Precautions for GD32H7xx BootLoader Operation SDIO interface Precautions for option byte and Efuse operation described above also apply to SDIO interface of Bootloader. Please note that written option bytes and Efuse can usually take effect only if Bootloader is subject to soft reset. However, as SD card update is an offline operation, to complete option byte or sequential Efuse operation mentioned above, users should copy different upgrade files from PC (option byte and Efuse configuration are different) to SD card for many times. -
Page 10: Usb Interface
AN126 Precautions for GD32H7xx BootLoader Operation USB interface As PHY of USB interface of GD32H7xx needs to be powered individually, special attention is required for the power supply mode of PHY of USB interface. If the power supply mode of PHY of USB interface is incorrect, DFU will not be identified. -
Page 11: Ospi
AN126 Precautions for GD32H7xx BootLoader Operation OSPI USART interface of GD32H7xx BootLoader is able to write data to OSPI FLASH. OSPI includes two sets of sub-interfaces, namely OSPI0 and OSPI1. Users can choose default GPIO pin or designate required pins through the host computer. OSPI FLASH operation includes clock frequency division, single-line mode configuration, and eight-line mode configuration. -
Page 12: Revision History
AN126 Precautions for GD32H7xx BootLoader Operation Revision history Table 7-1. Revision history Revision No. Description Date Initial release Jun.14, 2023... - Page 13 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.
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