GigaDevice Semiconductor GD32H737 Manuals

Manuals and User Guides for GigaDevice Semiconductor GD32H737. We have 2 GigaDevice Semiconductor GD32H737 manuals available for free PDF download: User Manual, Errata Sheet

GigaDevice Semiconductor GD32H737 User Manual (1884 pages)

Arm Cortex-M7 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 15 MB

Table of Contents
2
List of Figures
38
List of Tables
52
System and Memory Architecture
59
Arm ® Cortex ® -M7 Processor
59
System Architecture
60
Figure 1-1. the Structure of the Cortex
60
Table 1-1. the Interconnection Relationship of the Interconnect Matrix
61
Figure 1-5. the System Architecture of Gd32H7Xx Devices
62
Bus Matrix Region 0
63
Bus Matrix Region 1
63
Figure 1-2. Bus Matrix Region 0
63
Bus Matrix Region 2
64
Figure 1-3. Bus Matrix Region 1
64
Figure 1-4. Bus Matrix Region 2
64
Memory Map
65
Table 1-2. Memory Map of Gd32H7Xx Devices
65
On-Chip SRAM Memory
73
Figure 1-6. Block Digram of AXI SRAM Controller
73
Figure 1-7. Block Digram of RAM Shared by ITCM/DTCM/AXI SRAM
74
Table 1-3. Configuration of ITCM/DTCM/AXI SRAM
74
On-Chip Flash Memory Overview
75
Boot Configuration
75
Table 1-4. Boot Mode Selection
75
System Configuration Controller (SYSCFG)
76
Table 1-5. Details of Boot Mode
76
Timer Break Input Lock
77
AXI Interconnect Matrix (AXIIM)
77
Characteristics
77
Function Overview
77
Figure 1-8. Block Diagram of AXI Interconnect Matrix
77
Table 1-6. Configuration of Asibs
78
Table 1-7. Configuration of Amibs
78
System Configuration Registers
79
Peripheral Mode Configuration Register (SYSCFG_PMCFG)
79
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
81
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
82
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
83
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
84
Lockup Control Register (SYSCFG_LKCTL)
86
I/O Compensation Control Register (SYSCFG_CPSCTL)
87
I/O Compensation Cell Code Configuration Register (SYSCFG_CPSCCCFG)
88
Timer Input Selection Register 0 (SYSCFG_TIMERCISEL0)
89
Timer Input Selection Register 1 (SYSCFG_TIMERCISEL1)
90
Timer Input Selection Register 2 (SYSCFG_TIMERCISEL2)
91
Timer Input Selection Register 3 (SYSCFG_TIMERCISEL3)
92
Timer Input Selection Register 4 (SYSCFG_TIMERCISEL4)
94
Timer Input Selection Register 5 (SYSCFG_TIMERCISEL5)
95
Timer Input Selection Register 6 (SYSCFG_TIMERCISEL6)
97
CPU ICACHE Error Status Register(SYSCFG_CPUICAC)
98
CPU DCACHE Error Status Register (SYSCFG_CPUDCAC)
99
FPU Interrupt Enable Register (SYSCFG_FPUINTEN)
99
SRAM Configuration Register 0 (SYSCFG_SRAMCFG0)
100
SRAM Configuration Register 1 (SYSCFG_SRAMCFG1)
101
Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=0, 7)
101
Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=0, 7)
104
Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=0, 7)
106
Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=1, 2, 3, 4, 22, 23, 30, 31)
107
Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=1, 2, 3, 4, 22, 23, 30, 31)
109
Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=1, 2, 3, 4, 22, 23, 30, 31)
112
Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=14, 40, 41, 42, 43, 44)
113
Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=14, 40, 41, 42, 43, 44)
115
Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=14, 40, 41, 42, 43, 44)
116
User Configuration Register (SYSCFG_USERCFG)
117
AXI Interconnect Registers
118
AXI Peripheral ID4 Register (AXI_PERIPH_ID4)
118
AXI Peripheral ID0 Register (AXI_PERIPH_ID0)
118
AXI Peripheral ID1 Register (AXI_PERIPH_ID1)
119
AXI Peripheral ID2 Register (AXI_PERIPH_ID2)
119
AXI Peripheral ID3 Register (AXI_PERIPH_ID3)
120
AXI Componet ID0 Register (AXI_COMP_ID0)
120
AXI Componet ID1 Register (AXI_COMP_ID1)
120
AXI Componet ID2 Register (AXI_COMP_ID2)
121
AXI Componet ID3 Register (AXI_COMP_ID3)
121
AXI Master Port X Bus Matrix Issuing Functionality Control Register (Axi_Mpxbm_Iss_Ctl)
122
AXI Master Port X Bus Matrix Functionality Control Register (Axi_Mpxbm_Ctl)
122
AXI Master Port X Long Burst Functionality Control Register (Axi_Mpx_Lb_Ctl)
123
AXI Master Port X Issuing Functionality Control Register (Axi_Mpx_Iss_Ctl)
123
AXI Slave Port X Functionality Control Register (Axi_Spx_Ctl)
124
AXI Slave Port X AHB Issuing Functionality Control Register (Axi_Spx_Ahbiss_Ctl)
124
AXI Slave Port X Read QOS Control Register (Axi_Spx_Rdqos_Ctl)
125
AXI Slave Port X Write QOS Control Register (Axi_Spx_Wrqos_Ctl)
125
AXI Slave Port X Issuing Functionality Control Register (Axi_Spx_Iss_Ctl)
126
Device Electronic Signature
126
Memory Density Information
127
Unique Device ID (96 Bits)
127
RAM ECC Monitor Unit (RAMECCMU)
129
Characteristics
129
Function Overview
129
Figure 2-1. Block Architecture of RAMECCMU
129
Table 2-1. RAMECC Monitor X Unit for Region 0 (X=0
130
Table 2-2. RAMECC Monitor X Unit for Region 1 (X=0
130
Register Definition
131
RAMECCMU Global Interruput Register (RAMECCMU_INT)
131
RAMECCMU Monitor X Control Register (Rameccmu_Mxctl)
131
RAMECCMU Monitor X Status Register (Rameccmu_Mxstat)
132
RAMECCMU Monitor X Failing Address Register (Rameccmu_Mxfaddr)
133
RAMECCMU Monitor X Failing Data Low Register (Rameccmu_Mxfdl)
134
RAMECCMU Monitor X Failing Data High Register (Rameccmu_Mxfdh)
134
RAMECCMU Monitor X Failing ECC Error Code Register (Rameccmu_Mxfecode)
134
Flash Memory Controller (FMC)
136
Overview
136
Characteristics
136
Function Overview
136
Flash Memory Architecture
136
Figure 3-1. FMC Block Diagram
136
Read Operations
137
Table 3-1. Gd32H7Xx Base Address and Size for Flash Memory
137
Unlock the FMC_CTL and FMC_OBCTL Register
138
Sector Erase
139
Figure 3-2. Proccess of Sector Erase Operation
139
Mass Erase
140
Figure 3-3. Process of Typical Mass Erase Operation
141
Figure 3-4. Process of Protection-Removed Mass Erase Operation
142
Main Flash Programming
144
Figure 3-5. Proccess of Program Operation
144
Option Bytes
145
Table 3-2. Option Byte
146
Sector Erase/Program Protection
148
Security Protection
149
Table 3-3. WP Bit for Sectors Protected
149
Dedicated Code Read Protection Area
151
Table 3-4. SPC Protection Level Configuration
151
Table 3-5. DCRP Area Configuration
152
Secure User Area
153
Secure Mode
154
Table 3-6. Secure User Area Configuration
154
Figure 3-6. Secure Access Mode
155
Basic Security Service
156
Table 3-7. Function Resetandinitializesecureareas
156
Table 3-8. Function Exitsecurearea
156
Error Description
157
FMC Interrupts
159
Table 3-9 FMC Interrupt Requests
159
Register Definition
160
Unlock Key Register (FMC_KEY)
160
Option Byte Unlock Key Register (FMC_OBKEY)
160
Control Register (FMC_CTL)
160
Status Register (FMC_STAT)
162
Address Register (FMC_ADDR)
163
Option Byte Control Register (FMC_OBCTL)
164
Option Byte Status Register 0 (FMC_OBSTAT0_EFT)
165
Option Byte Status Register 0 (FMC_OBSTAT0_MDF)
166
DCRP Address Register (FMC_DCRPADDR_EFT)
168
DCRP Address Register (FMC_DCRPADDR_MDF)
169
Secure Address Register (FMC_SCRADDR_EFT)
170
Secure Address Register (FMC_SCRADDR_MDF)
170
Erase/Program Protection Register (FMC_WP_EFT)
171
Erase/Program Protection Register (FMC_WP_MDF)
172
Boot Address Register (FMC_BTADDR_EFT)
173
Boot Address Register (FMC_BTADDR_MDF)
173
Option Byte Status Register 1 (FMC_OBSTAT1_EFT)
174
Option Byte Status Register 1 (FMC_OBSTAT1_MDF)
175
RTDEC Area Register (FMC_NODEC)
176
AES IV Register (Fmc_Aesivx_Eft) (X = 0
176
AES IV Register (Fmc_Aesivx_Mdf) (X = 0
177
Product ID Register X (Fmc_Pidx) (X = 0,1)
177
Electronic Fuse (EFUSE)
179
Overview
179
Characteristics
179
Function Overview
179
Block Diagram
179
Figure 4-1. Block Diagram of Efuse Controller
179
Efuse Macro Description
180
Table 4-1. System Parameters
182
Read Operation
183
Program Operation
184
AES Key CRC Function
184
EFUSE Interrupts
185
Table 4-2. EFUSE Interrupt Requests
185
Figure 4-2 EFUSE Interrupt Mapping Diagram
186
Register Definition
187
Control Register (EFUSE_CTL)
187
Address Register (EFUSE_ADDR)
188
Status Register (EFUSE_STAT)
189
Status Flag Clear Register (EFUSE_STATC)
189
User Control Register (EFUSE_USER_CTL)
190
MCU Reserved Register (EFUSE_MCU_RSV)
192
Debug Password Register X (Efuse_Dpx) (X = 0,1)
194
Firmware AES Key Register X (Efuse_Aes_Keyx) (X = 0
195
User Data Register X (Efuse_User_Datax) (X = 0
195
Power Management Unit (PMU)
196
Overview
196
Characteristics
196
Function Overview
197
Backup Domain
197
Figure 5-1. Power Supply Overview
197
VDD / V Dda
199
Figure 5-2. Waveform of the Backup Domain Voltage Thresholds
199
Figure 5-3. Waveform of the por / PDR
200
Figure 5-4. Waveform of the BOR
200
Figure 5-5. Waveform of the LVD Threshold
201
Figure 5-6. Waveform of the VAVD Threshold
202
0.9V Power Domain
203
Figure 5-7. Temperature Thresholds
203
Figure 5-8. LDO Supplies for 0.9V Power Domain
204
Figure 5-9. SMPS Supplies for 0.9V Power Domain
204
Figure 5-10. SMPS Supplies for LDO, LDO Supplies for 0.9V Power Domain
205
Figure 5-11. SMPS Supplies for LDO and External, LDO Supplies for 0.9V Power Domain
206
Figure 5-12. SMPS Supplies for External, External Supplies for 0.9V Power Domain
206
Figure 5-13. Bypass
207
Figure 5-14. Waveform of the VOVD
207
Power Saving Modes
208
Table 5-1. Power Saving Mode Summary
209
Register Definition
210
Control Register 0 (PMU_CTL0)
210
Control and Status Register (PMU_CS)
211
Control Register 1 (PMU_CTL1)
213
Control Register 2 (PMU_CTL2)
215
Control Register 3 (PMU_CTL3)
216
Parameter Register (PMU_PAR)
217
Reset and Clock Unit (RCU)
219
Reset Control Unit (RCTL)
219
Overview
219
Function Overview
219
Clock Control Unit (CCTL)
220
Overview
220
Figure 6-1. the System Reset Circuit
220
Figure 6-2. Clock Tree
221
Characteristics
224
Function Overview
224
Figure 6-3. HXTAL Clock Source
224
Figure 6-4. HXTAL Clock Source in Bypass Mode
225
Table 6-1. Clock Output 0 Source Select
229
Table 6-2. Clock Output 1 Source Select
229
Register Definition
230
Control Register (RCU_CTL)
230
PLL0 Register (RCU_PLL0)
232
Clock Configuration Register 0 (RCU_CFG0)
234
Clock Interrupt Register (RCU_INT)
236
AHB1 Reset Register (RCU_AHB1RST)
239
AHB2 Reset Register (RCU_AHB2RST)
241
AHB3 Reset Register (RCU_AHB3RST)
242
AHB4 Reset Register (RCU_AHB4RST)
243
APB1 Reset Register (RCU_APB1RST)
245
APB2 Reset Register (RCU_APB2RST)
248
APB3 Reset Register (RCU_APB3RST)
251
APB4 Reset Register (RCU_APB4RST)
252
AHB1 Enable Register (RCU_AHB1EN)
253
AHB2 Enable Register (RCU_AHB2EN)
255
AHB3 Enable Register (RCU_AHB3EN)
256
AHB4 Enable Register (RCU_AHB4EN)
258
APB1 Enable Register (RCU_APB1EN)
259
APB2 Enable Register (RCU_APB2EN)
263
APB3 Enable Register (RCU_APB3EN)
266
APB4 Enable Register (RCU_APB4EN)
266
AHB1 Sleep Mode Enable Register (RCU_AHB1SPEN)
267
AHB2 Sleep Mode Enable Register (RCU_AHB2SPEN)
270
AHB3 Sleep Mode Enable Register (RCU_AHB3SPEN)
271
AHB4 Sleep Mode Enable Register (RCU_AHB4SPEN)
273
APB1 Sleep Mode Enable Register (RCU_APB1SPEN)
274
APB2 Sleep Mode Enable Register (RCU_APB2SPEN)
278
APB3 Sleep Mode Enable Register (RCU_APB3SPEN)
281
APB4 Sleep Mode Enable Register (RCU_APB4SPEN)
281
Backup Domain Control Register (RCU_BDCTL)
282
Reset Source/Clock Register (RCU_RSTSCK)
284
PLL Clock Additional Control Register (RCU_PLLADDCTL)
286
PLL1 Register (RCU_PLL1)
288
PLL2 Register (RCU_PLL2)
290
Clock Configuration Register 1 (RCU_CFG1)
292
Clock Configuration Register 2 (RCU_CFG2)
294
Clock Configuration Register 3 (RCU_CFG3)
296
PLL All Configuration Register (RCU_PLLALL)
298
PLL0 Fraction Configuration Register (RCU_PLL0FRA)
300
PLL1 Fraction Configuration Register (RCU_PLL1FRA)
300
PLL2 Fraction Configuration Register (RCU_PLL2FRA)
301
Additional Clock Control Register 0 (RCU_ADDCTL0)
302
Additional Clock Control Register 1(RCU_ADDCTL1)
303
Additional Clock Interrupt Register (RCU_ADDINT)
304
Clock Configuration Register 4 (RCU_CFG4)
306
USB Clock Control Register (RCU_USBCLKCTL)
307
PLLUSB Configuration Register (RCU_PLLUSBCFG)
309
APB2 Additional Reset Register (RCU_ADDAPB2RST)
310
APB2 Additional Enable Register (RCU_ADDAPB2EN)
311
APB2 Additional Sleep Enable Register (RCU_ADDAPB2SPEN)
312
Clock Configuration Register 5 (RCU_CFG5)
312
Clock Trim Controller (CTC)
315
Overview
315
Characteristics
315
Function Overview
315
Figure 7-1. CTC Overview
315
REF Sync Pulse Generator
316
CTC Trim Counter
316
Frequency Evaluation and Automatically Trim Process
317
Figure 7-2. CTC Trim Counter
317
Software Program Guide
318
Register Definition
320
Control Register 0 (CTC_CTL0)
320
Control Register 1 (CTC_CTL1)
321
Status Register (CTC_STAT)
322
Interrupt Clear Register (CTC_INTC)
324
Interrupt / Event Controller (EXTI)
326
Overview
326
Characteristics
326
Interrupts Function Overview
326
Table 8-1. NVIC Exception Types in Cortex ® -M7
327
Table 8-2. Interrupt Vector Table
327
External Interrupt and Event (EXTI) Block Diagram
333
External Interrupt and Event Function Overview
333
Figure 8-1. Block Diagram of EXTI
333
Table 8-3. EXTI Source
334
Register Definition
336
Interrupt Enable Register 0 (EXTI_INTEN0)
336
Event Enable Register 0 (EXTI_EVEN0)
336
Rising Edge Trigger Enable Register 0 (EXTI_RTEN0)
336
Falling Edge Trigger Enable Register 0 (EXTI_FTEN0)
337
Software Interrupt Event Register 0 (EXTI_SWIEV0)
337
Pending Register 0 (EXTI_PD0)
338
Interrupt Enable Register 1 (EXTI_INTEN1)
338
Event Enable Register 1 (EXTI_EVEN1)
339
Rising Edge Trigger Enable Register 1 (EXTI_RTEN1)
339
Falling Edge Trigger Enable Register 1 (EXTI_FTEN1)
339
Software Interrupt Event Register 1 (EXTI_SWIEV1)
340
Pending Register 1 (EXTI_PD1)
340
Trigger Selection Controller (TRIGSEL)
342
Overview
342
Characteristics
342
Function Overview
342
Internal Connect
343
Figure 9-1. TRIGSEL Main Composition Example
343
Table 9-1. Trigger Input Bit Fields Selection
343
Table 9-2. TRIGSEL Input and Output Mapping
347
Register Definition
354
Trigger Selection for EXTOUT0 Register (TRIGSEL_EXTOUT0)
354
Trigger Selection for EXTOUT1 Register (TRIGSEL_EXTOUT1)
354
Trigger Selection for EXTOUT2 Register (TRIGSEL_EXTOUT2)
355
Trigger Selection for EXTOUT3 Register (TRIGSEL_EXTOUT3)
356
Trigger Selection for ADC0 Register (TRIGSEL_ADC0)
356
Trigger Selection for ADC1 Register (TRIGSEL_ADC1)
357
Trigger Selection for ADC2 Register (TRIGSEL_ADC2)
358
Trigger Selection for DAC_OUT0 Register (TRIGSEL_DACOUT0)
358
Trigger Selection for DAC_OUT1 Register (TRIGSEL_DACOUT1)
359
Trigger Selection for TIMER0_BRKIN Register (TRIGSEL_TIMER0BRKIN)
360
Trigger Selection for TIMER7_BRKIN Register (TRIGSEL_TIMER7BRKIN)
360
Trigger Selection for TIMER14_BRKIN Register (TRIGSEL_TIMER14BRKIN)
361
Trigger Selection for TIMER15_BRKIN Register (TRIGSEL_TIMER15BRKIN)
362
Trigger Selection for TIMER16_BRKIN Register (TRIGSEL_TIMER16BRKIN)
363
Trigger Selection for TIMER40_BRKIN Register (TRIGSEL_TIMER40BRKIN)
363
Trigger Selection for TIMER41_BRKIN Register (TRIGSEL_TIMER41BRKIN)
364
Trigger Selection for TIMER42_BRKIN Register (TRIGSEL_TIMER42BRKIN)
365
Trigger Selection for TIMER43_BRKIN Register (TRIGSEL_TIMER43BRKIN)
365
Trigger Selection for TIMER44_BRKIN Register (TRIGSEL_TIMER44BRKIN)
366
Trigger Selection for CAN0 Register (TRIGSEL_CAN0)
366
Trigger Selection for CAN1 Register (TRIGSEL_CAN1)
367
Trigger Selection for CAN2 Register (TRIGSEL_CAN2)
368
Trigger Selection for LPDTS Register (TRIGSEL_LPDTS)
368
Trigger Selection for TIMER0_ETI Register (TRIGSEL_TIMER0ETI)
369
Trigger Selection for TIMER1_ETI Register (TRIGSEL_TIMER1ETI)
369
Trigger Selection for TIMER2_ETI Register (TRIGSEL_TIMER2ETI)
370
Trigger Selection for TIMER3_ETI Register (TRIGSEL_TIMER3ETI)
371
Trigger Selection for TIMER4_ETI Register (TRIGSEL_TIMER4ETI)
371
Trigger Selection for TIMER7_ETI Register (TRIGSEL_TIMER7ETI)
372
Trigger Selection for TIMER22_ETI Register (TRIGSEL_TIMER22ETI)
372
Trigger Selection for TIMER23_ETI Register (TRIGSEL_TIMER23ETI)
373
Trigger Selection for TIMER30_ETI Register (TRIGSEL_TIMER30ETI)
374
Trigger Selection for TIMER31_ETI Register (TRIGSEL_TIMER31ETI)
374
Trigger Selection for EDOUT Register (TRIGSEL_EDOUT)
375
Trigger Selection for HPDF_ITRG Register (TRIGSEL_HPDF)
375
Trigger Selection for TIMER0_ITI14 Register (TRIGSEL_TIMER0ITI14)
376
Trigger Selection for TIMER1_ITI14 Register (TRIGSEL_TIMER1ITI14)
377
Trigger Selection for TIMER2_ITI14 Register (TRIGSEL_TIMER2ITI14)
377
Trigger Selection for TIMER3_ITI14 Register (TRIGSEL_TIMER3ITI14)
378
Trigger Selection for TIMER4_ITI14 Register (TRIGSEL_TIMER4ITI14)
378
Trigger Selection for TIMER7_ITI14 Register (TRIGSEL_TIMER7ITI14)
379
Trigger Selection for TIMER14_ITI14 Register (TRIGSEL_TIMER14ITI14)
380
Trigger Selection for TIMER22_ITI14 Register (TRIGSEL_TIMER22ITI14)
380
Trigger Selection for TIMER23_ITI14 Register (TRIGSEL_TIMER23ITI14)
381
Trigger Selection for TIMER30_ITI14 Register (TRIGSEL_TIMER30ITI14)
381
Trigger Selection for TIMER31_ITI14 Register (TRIGSEL_TIMER31ITI14)
382
Trigger Selection for TIMER40_ITI14 Register (TRIGSEL_TIMER40ITI14)
383
Trigger Selection for TIMER41_ITI14 Register (TRIGSEL_TIMER41ITI14)
383
Trigger Selection for TIMER42_ITI14 Register (TRIGSEL_TIMER42ITI14)
384
Trigger Selection for TIMER43_ITI14 Register (TRIGSEL_TIMER43ITI14)
384
Trigger Selection for TIMER44_ITI14 Register (TRIGSEL_TIMER44ITI14)
385
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
387
Overview
387
Characteristics
387
Function Overview
387
Figure 10-1. Basic Structure of a Standard I/O Port Bit
388
Table 10-1. GPIO Configuration Table
388
GPIO Pin Configuration
389
External Interrupt/Event Lines
390
Alternate Functions (AF)
390
Additional Functions
390
Input Configuration
390
Output Configuration
390
Figure 10-2. Input Configuration
390
Analog Configuration
391
Figure 10-3. Output Configuration
391
Figure 10-4. Analog Configuration
391
Alternate Function (AF) Configuration
392
GPIO Locking Function
392
Figure 10-5. Alternate Function Configuration
392
GPIO Single Cycle Toggle Function
393
I/O Compensation Unit
393
Analog Configuration for ADC
393
Figure 10-6. Analog Configuration for ADC
393
Input Filtering
394
Figure 10-7. Filtering Using the Sampling Window
395
Figure 10-8. Input Filtering Clock Cycle
396
Register Definition
397
Port Control Register (Gpiox_Ctl, X=A
397
Port Output Mode Register (Gpiox_Omode, X=A
399
Port Output Speed Register (Gpiox_Ospd, X=A
400
Port Pull-Up/Down Register (Gpiox_Pud, X=A
402
Port Input Status Register (Gpiox_Istat, X=A
404
Port Output Control Register (Gpiox_Octl, X=A
404
Port Bit Operate Register (Gpiox_Bop, X=A
405
Port Configuration Lock Register (Gpiox_Lock, X=A
405
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
406
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
407
Bit Clear Register (Gpiox_Bc, X=A
408
Port Bit Toggle Register (Gpiox_Tg, X=A
409
Input Filtering Register (Gpiox_Ifl, X=A
409
Input Filtering Type Register (Gpiox_Iftp, X=A
410
Cyclic Redundancy Checks Management Unit (CRC)
412
Overview
412
Characteristics
412
Figure 11-1. Block Diagram of CRC Calculation Unit
412
Function Overview
413
Register Definition
414
Data Register (CRC_DATA)
414
Free Data Register (CRC_FDATA)
414
Control Register (CRC_CTL)
415
Initialization Data Register (CRC_IDATA)
415
Polynomial Register (CRC_POLY)
416
True Random Number Generator (TRNG)
417
Overview
417
Characteristics
417
Function Overview
418
Lfsr
418
Figure 12-1. TRNG Block Diagram
418
Post Processing
419
Conditioning
419
Output FIFO
419
Table 12-1. ALGO Configurations
419
Health Tests
420
NIST Mode State
421
Operation Flow
421
Error Flags
422
Low Power Usage
422
Register Definition
423
Control Register (TRNG_CTL)
423
Status Register (TRNG_STAT)
425
Data Register (TRNG_DATA)
426
Health Tests Configure Register (TRNG_HTCFG)
426
Cryptographic Acceleration Unit (CAU)
428
Overview
428
Characteristics
428
CAU Data Type and Initialization Vectors
429
Data Type
429
Figure 13-1. DATAM no Swapping and Half-Word Swapping
429
Initialization Vectors
430
Cryptographic Acceleration Processor
430
Figure 13-2. DATAM Byte Swapping and Bit Swapping
430
Figure 13-3. CAU Diagram
430
DES / TDES Cryptographic Acceleration Processor
431
Figure 13-4. des / TDES ECB Encryption
432
Figure 13-5. des / TDES ECB Decryption
433
Figure 13-6. des / TDES CBC Encryption
434
AES Cryptographic Acceleration Processor
435
Figure 13-7. des / TDES CBC Decryption
435
Figure 13-8. AES ECB Encryption
436
Figure 13-9. AES ECB Decryption
437
Figure 13-10. AES CBC Encryption
437
Figure 13-11. AES CBC Decryption
438
Figure 13-12. Counter Block Structure
439
Figure 13-13. AES CTR Encryption/Decryption
439
Operating Modes
443
CAU DMA Interface
445
CAU Interrupts
445
CAU Suspended Mode
446
Register Definition
447
Control Register (CAU_CTL)
447
Status Register 0 (CAU_STAT0)
449
Data Input Register (CAU_DI)
449
Data Output Register (CAU_DO)
450
DMA Enable Register (CAU_DMAEN)
451
Interrupt Enable Register (CAU_INTEN)
451
Status Register 1 (CAU_STAT1)
452
Interrupt Flag Register (CAU_INTF)
452
Key Registers (CAU_KEY0
453
Initial Vector Registers (CAU_IV0
455
GCM or CCM Mode Context Switch Register X (Cau_Gcmccmctxsx) (X=0
457
GCM Mode Context Switch Register X (Cau_Gcmctxsx) (X=0
457
Hash Acceleration Unit (HAU)
459
Overview
459
Characteristics
459
HAU Data Type
459
Figure 14-1. DATAM no Swapping and Half-Word Swapping
459
Figure 14-2. DATAM Byte Swapping and Bit Swapping
460
HAU Core
461
Automatic Data Padding
461
Figure 14-3. HAU Block Diagram
461
Digest Computing
462
Hash Mode
463
HMAC Mode
463
HAU Suspended Mode
463
Transfer Data by CPU
464
Transfer Data by DMA
464
HAU Interrupt
465
Input FIFO Interrupt
465
Calculation Completion Interrupt
465
Register Definition
466
Control Register (HAU_CTL)
466
Data Input Register (HAU_DI)
467
Configuration Register (HAU_CFG)
468
Data Output Register (HAU_DO0
469
Interrupt Enable Register (HAU_INTEN)
471
Status and Flag Register (HAU_STAT)
472
Context Switch Register X (Hau_Ctxsx) (X = 0
472
Trigonometric Math Unit (TMU)
474
Overview
474
Characteristics
474
Block Diagram
474
Figure 15-1. TMU Block Diagram
474
Function Overview
475
Data Format and Configuration
475
Table 15-1. Input Data Configuration
475
Mode Configuration
476
Table 15-2. Output Data Configuration
476
Table 15-3. TMU Mode Configuration
476
Table 15-4. Mode 0 Description
476
Table 15-5. Mode 1 Description
478
Table 15-6. Mode 2 Description
479
Table 15-7. Mode 3 Description
480
Table 15-8. Mode 4 Description
481
Table 15-9. Mode 5 Description
481
Table 15-10. Mode 6 Description
482
Table 15-11. Mode 7 Description
483
Table 15-12. Mode 8 Description
484
Table 15-13. Recommended Scaling Factors in Mode 8
484
Table 15-14. Mode 9 Description
484
TMU Operation Pending
485
Table 15-15. Recommended Scaling Factors in Mode 9
485
Zero-Overhead Mode
486
Interrupt and DMA Requests
486
Registers Definition
486
Control and Status Register (TMU_CS)
486
Input Data Register (TMU_IDATA)
489
Output Data Register (TMU_ODATA)
490
Direct Memory Access Controller (DMA)
491
Overview
491
Characteristics
491
Function Overview
492
Block Diagram
492
Figure 16-1. Block Diagram of DMA
492
Figure 16-2. Data Stream for Three Transfer Modes
493
Table 16-1. Transfer Mode
493
Peripheral Handshake
494
Data Process
494
Figure 16-3. Handshake Mechanism
494
Table 16-2. CNT Configuration
496
Table 16-3. FIFO Counter Critical Value Configuration Rules
497
Figure 16-4. Data Packing/Unpacking When PWIDTH = '00
498
Address Generation
499
Figure 16-5. Data Packing/Unpacking When PWIDTH = '01
499
Figure 16-6. Data Packing/Unpacking When PWIDTH = '10
499
Circular Mode
500
Switch-Buffer Mode
500
Transfer Operation
501
Figure 16-7. DMA Operation of Switch-Buffer Mode
501
Transfer Finish
502
Channel Configuration
503
Interrupts
504
Table 16-4. DMA Interrupt Events
504
Flag
505
Exception
505
Error
506
DMA Request Mapping
508
Figure 16-8. System Connection of DMA0 and DMA1
508
Register Definition
509
Interrupt Flag Register 0 (DMA_INTF0)
509
Interrupt Flag Register 1 (DMA_INTF1)
510
Interrupt Flag Clear Register 0 (DMA_INTC0)
511
Interrupt Flag Clear Register 1 (DMA_INTC1)
512
Channel X Control Register (Dma_Chxctl)
512
Channel X Counter Register (Dma_Chxcnt)
516
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
516
Channel X Memory 0 Base Address Register (Dma_Chxm0Addr)
517
Channel X Memory 1 Base Address Register (Dma_Chxm1Addr)
517
Channel X FIFO Control Register (Dma_Chxfctl)
518
Master Direct Memory Access Controller (MDMA)
520
Overview
520
Characteristics
520
Function Overview
521
Figure 17-1. Block Diagram of MDMA
521
Table 17-1. Transfer Mode
521
Figure 17-2. Connections of the Four Modes
522
Table 17-2. MDMA Hardware Request Sources
522
Data Process
523
Figure 17-3. Word, Halfword, Byte Order Exchange
524
Figure 17-4. Data Padding and Alignment (Source Greater than Destination)
524
Figure 17-5. Data Padding and Alignment (Source Less than Destination)
525
Address Generation
526
Figure 17-6. Data Packing / Unpacking
526
Transfer Modes
527
Table 17-3. Source and Destination Address Generation Configuration
527
Table 17-4. Update Mode of Source and Destination Address
529
Table 17-5. Register Link Address
529
Transfer Status
530
MDMA Interrupts and Errors
530
Table 17-6. MDMA Error Flags
530
Table 17-7. MDMA Interrupt Events
531
Figure 17-7. MDMA Interrupt Logic
532
Register Definition
533
Global Interrupt Flag Register (MDMA_GINTF)
533
Channel X Status Register 0 (Mdma_Chxstat0)
533
Channel X Status Clear Register (Mdma_Chxstatc)
534
Channel X Status Register 1 (Mdma_Chxstat1)
535
Channel X Control Register 0 (Mdma_Chxctl0)
536
Channel X Configure Register (Mdma_Chxcfg)
538
Channel X Block Transfer Configure Register (Mdma_Chxbtcfg)
542
Channel X Source Address Register (Mdma_Chxsaddr)
542
Channel X Destination Address Register (Mdma_Chxdaddr)
543
Channel X Multi-Block Address Update Register (Mdma_Chxmbaddru)
543
Channel X Link Address Register (Mdma_Chxladdr)
544
Channel X Control Register 1 (Mdma_Chxctl1)
544
Channel X Mask Address Register (Mdma_Chxmaddr)
545
Channel X Mask Data Register (Mdma_Chxmdata)
546
DMA Request Multiplexer (DMAMUX)
547
Overview
547
Characteristics
547
Block Diagram
548
Signal Description
548
Figure 18-1. Block Diagram of DMAMUX
548
Function Overview
549
DMAMUX Request Multiplexer
549
Figure 18-2. Synchronization Mode
550
Figure 18-3. Event Generation
551
DMAMUX Request Generator
552
Channel Configurations
552
Interrupt
553
DMAMUX Mapping
553
Table 18-1. Interrupt Events
553
Table 18-2. Request Multiplexer Input Mapping
554
Table 18-3. Trigger Input Mapping
559
Table 18-4. Synchronization Input Mapping
560
Register Definition
562
Request Multiplexer Channel X Configuration Register (Dmamux_Rm_Chxcfg)
562
Request Multiplexer Channel Interrupt Flag Register (DMAMUX_RM_INTF)
563
Request Multiplexer Channel Interrupt Flag Clear Register (DMAMUX_RM_INTC)
563
Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
564
Request Generator Channel Interrupt Flag Register (DMAMUX_RG_INTF)
565
Rquest Generator Channel Interrupt Flag Clear Register (DMAMUX_RG_INTC)
565
Debug (DBG)
567
Overview
567
JTAG / SW Function Overview
567
Switch JTAG or SW Interface
567
Pin Assignment
567
Table 19-1. Pin Assignment
567
Jtag
568
Figure 19-1. Block Diagram of JTAG Unit
568
Debug Reset
570
JEDEC-106 ID Code
570
Debug Hold Function Overview
570
Debug Support for Power Saving Mode
570
Debug Support for TIMER, I2C, WWDGT, FWDGT, RTC and CAN
570
Register Definition
571
ID Code Register (DBG_ID)
571
Control Register0 (DBG_CTL0)
571
Control Register1 (DBG_CTL1)
572
Control Register2 (DBG_CTL2)
573
Control Register3 (DBG_CTL3)
575
Control Register4 (DBG_CTL4)
576
Analog-To-Digital Converter (ADC)
578
Overview
578
Characteristics
578
Pins and Internal Signals
579
Figure 20-1. ADC Module Block Diagram
579
Table 20-1. ADC Internal Input Signals
579
Table 20-2. ADC Input Pins Definition
579
Function Overview
580
Foreground Calibration Function
580
Dual Clock Domain Architecture
581
ADC Enable
581
Single-Enden and Differential Input Channels
581
Routine Sequence
582
Table 20-3. ADC Differential Channel Pin Matching
582
Operation Modes
583
Figure 20-2. Single Operation Mode
583
Figure 20-3. Continuous Operation Mode
584
Figure 20-4. Scan Operation Mode, Continuous Disable
585
Figure 20-5. Scan Operation Mode, Continuous Enable
585
Figure 20-6. Discontinuous Operation Mode
585
Conversion Result Threshold Monitor Function
586
Data Storage Mode
586
Sample Time Configuration
587
External Trigger Configuration
587
Figure 20-7. 14-Bit Data Storage Mode
587
Figure 20-8. 12-Bit Data Storage Mode
587
Figure 20-9. 6-Bit Data Storage Mode
587
DMA Request
588
Overflow Detection
588
ADC Internal Channels
588
Table 20-4. Trigger Source for Routine Channels for ADC0/ADC1/ADC2
588
Battery Voltage Monitoring
590
Using HPDF to Managing the Conversion Results
590
Programmable Resolution (DRES)
590
Table 20-5. T CONV Timings Depending on Resolution for ADC0 and ADC1
590
On-Chip Hardware Oversampling
591
Table 20-6. T CONV Timings Depending on Resolution for ADC2
591
Figure 20-11. 20-Bit to 16-Bit Result Truncation (for 12Bit ADC)
592
Figure 20-12. Numerical Example with 5-Bits Shift and Rounding (for 12Bit ADC)
592
Figure 20-13. 14Bit ADC Oversampling with 10Bits Right Shift
592
ADC Sync Mode
593
Figure 20-14. Numerical Example with 10-Bits Shift and Rounding(for 14Bit ADC)
593
Table 20-7. some Examples Show the Maximum Output Results for N and M Combimations
593
Free Mode
594
Routine Parallel Mode
594
Figure 20-15. ADC Sync Block Diagram
594
Table 20-8. ADC Sync Mode Table
594
Routine Follow-Up Mode
595
Figure 20-16. Routine Parallel Mode on 16 Channels
595
Use DMA in ADC Sync Mode
596
Figure 20-17. Routine Follow-Up Mode on 1 Channel in Continuous Operation Mode
596
ADC Interrupts
597
Register Definition
598
Status Register (ADC_STAT)
598
Control Register 0 (ADC_CTL0)
599
Control Register 1 (ADC_CTL1)
601
Watchdog High Threshold Register0 (ADC_WDHT0)
604
Watchdog Low Threshold Register0 (ADC_WDLT0)
604
Routine Sequence Register 0 (ADC_RSQ0)
604
Routine Sequence Register 1 (ADC_RSQ1)
605
Routine Sequence Register 2 (ADC_RSQ2)
606
Routine Sequence Register 3 (ADC_RSQ3)
607
Routine Sequence Register 4 (ADC_RSQ4)
608
Routine Sequence Register 5 (ADC_RSQ5)
609
Routine Sequence Register 6 (ADC_RSQ6)
610
Routine Sequence Register 7 (ADC_RSQ7)
611
Routine Sequence Register 8 (ADC_RSQ8)
612
Routine Data Register (ADC_RDATA)
613
Oversample Control Register (ADC_OVSAMPCTL)
613
Watchdog 1 Channel Selection Register (ADC_WD1SR)
615
Watchdog 2 Channel Selection Register (ADC_WD2SR)
615
Watchdog High Threshold Register1 (ADC_WDHT1)
616
Watchdog Low Threshold Register1 (ADC_WDLT1)
616
Watchdog High Threshold Register2 (ADC_WDHT2)
617
Watchdog Low Threshold Register2 (ADC_WDLT2)
617
Differential Mode Control Register (ADC_DIFCTL)
618
Summary Status Register (ADC_SSTAT)
618
Sync Control Register (ADC_SYNCCTL)
620
Sync Routine Data Register0 (ADC_SYNCDATA0)
621
Sync Routine Data Register1 (ADC_SYNCDATA1)
622
Digital-To-Analog Converter (DAC)
623
Overview
623
Characteristics
623
Figure 21-1. DAC Block Diagram
623
Function Description
624
DAC Enable
624
DAC Output Buffer
624
DAC Data Configuration
624
Table 21-1. DAC Pins
624
DAC Trigger
625
DAC Conversion
625
DAC Noise Wave
625
Table 21-2. Triggers of DAC
625
DAC Modes
626
Figure 21-2. DAC LFSR Algorithm
626
Figure 21-3. DAC Triangle Noise Wave
626
DAC Output Voltage
627
DAC Output Buffer Calibration
627
DMA Request
628
DAC Concurrent Conversion
628
DAC Low-Power Modes
629
DAC Registers
630
Control Register 0 (DAC_CTL0)
630
Software Trigger Register (DAC_SWT)
632
DAC_OUT0 12-Bit Right-Aligned Data Holding Register (OUT0_R12DH)
633
DAC_OUT0 12-Bit Left-Aligned Data Holding Register (OUT0_L12DH)
633
DAC_OUT0 8-Bit Right-Aligned Data Holding Register (OUT0_R8DH)
634
DAC_OUT1 12-Bit Right-Aligned Data Holding Register (OUT1_R12DH)
634
DAC_OUT1 12-Bit Left-Aligned Data Holding Register (OUT1_L12DH)
635
DAC_OUT1 8-Bit Right-Aligned Data Holding Register (OUT1_R8DH)
635
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
636
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
636
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
637
DAC_OUT0 Data Output Register (OUT0_DO)
637
DAC_OUT1 Data Output Register (OUT1_DO)
638
DAC Status Register 0 (DAC_STAT0)
638
DAC Calibration Register (DAC_CALR)
639
DAC Mode Control Register (DAC_MDCR)
639
DAC Sample and Keep Sample Time Register 0 (DAC_SKSTR0)
641
DAC Sample and Keep Sample Time Register 1 (DAC_SKSTR1)
641
DAC Sample and Keep Keep Time Register (DAC_SKKTR)
641
DAC Sample and Keep Refresh Time Register (DAC_SKRTR)
642
Watchdog Timer (WDGT)
643
Free Watchdog Timer (FWDGT)
643
Overview
643
Characteristics
643
Function Overview
644
Figure 22-1. Free Watchdog Block Diagram
644
Table 22-1. Min/Max FWDGT Timeout Period at 32Khz (IRC32K)
645
Register Definition
646
Window Watchdog Timer (WWDGT)
650
Overview
650
Characteristics
650
Function Overview
650
Figure 22-2. Window Watchdog Timer Block Diagram
650
Figure 22-3. Window Watchdog Timing Diagram
651
Table 22-2. Min-Max Timeout Value at 150 Mhz
652
Register Definition
653
Real Time Clock (RTC)
655
Overview
655
Characteristics
655
Function Overview
656
Block Diagram
656
Clock Source and Prescalers
656
Figure 23-1. Block Diagram of RTC
656
Shadow Registers Introduction
657
Configurable and Field Maskable Alarm
657
Configurable Periodic Auto-Wakeup Counter
658
RTC Initialization and Configuration
658
Calendar Reading
659
Resetting the RTC
661
RTC Shift Function
661
RTC Reference Clock Detection
662
RTC Smooth Digital Calibration
662
Time-Stamp Function
664
Tamper Detection
664
Calibration Clock Output
666
Alarm Output
666
RTC Pin Configuration
666
RTC Power Saving Mode Management
667
Table 23-1 RTC Pin Configuration and Function
667
Table 23-2 RTC Power Saving Mode Management
667
RTC Interrupts
668
Table 23-3 RTC Interrupts Control
668
Register Definition
669
Time Register (RTC_TIME)
669
Date Register (RTC_DATE)
669
Control Register (RTC_CTL)
670
Status Register (RTC_STAT)
673
Prescaler Register (RTC_PSC)
675
Wakeup Timer Register (RTC_WUT)
675
Alarm 0 Time and Date Register (RTC_ALRM0TD)
676
Alarm 1 Time and Date Register (RTC_ALRM1TD)
677
Write Protection Key Register (RTC_WPK)
678
Sub Second Register (RTC_SS)
678
Shift Function Control Register (RTC_SHIFTCTL)
679
Time of Time Stamp Register (RTC_TTS)
680
Date of Time Stamp Register (RTC_DTS)
680
Sub Second of Time Stamp Register (RTC_SSTS)
681
High Resolution Frequency Compensation Register (RTC_HRFC)
681
Tamper Register (RTC_TAMP)
682
Alarm 0 Sub Second Register (RTC_ALRM0SS)
684
Alarm 1 Sub Second Register (RTC_ALRM1SS)
685
Configuration Register (RTC_CFG)
686
Backup Registers (Rtc_Bkpx) (X=0
687
TIMER (Timerx)
688

GigaDevice Semiconductor GD32H737 Errata Sheet (19 pages)

Device Limitations

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 0 MB

Table of Contents
2
List of Figures
4
List of Tables
5
Introduction
6
Revision Identification
6
Summary of Device Limitations
6
Descriptions of Device Limitations
9
System
9
Systick Is Clocked with the System Clock (CK_SYS) Divided by 2 When Using External Clock Source
9
ECC Error Due to Illegal Address Access
9
Fmc
9
Protection-Removed Mass Erase Function Cannot be Disabled
9
Pmu
10
Chip Damage Risk in SMPS Mode of the LQFP Package
10
VDDSMPS Cannot be Connected to a Low Level When Not Using SMPS
10
Gpio
10
PXY Pin Connects to PXY_C Pin in Standby Mode
10
Trng
11
LFSR Algorithm Failure
11
Dbg
11
SWD and JTAG Debug Function Failure When Using Low Power Debug Function
11
SWD Connection Fails When PA15 Is Low Level
11
Adc
12
The Analog Watchdog Threshold Comparison Fails When Used Simultaneously with Oversampling in a 14-Bit ADC
12
Rtc
12
When Using RTC Reference Clock Detection Function, PB13/PB15 will be Configured as Input Floating Mode
12
Voltage or Temperature Changes in the Backup Domain Cannot Trigger the Tamper Function
12
Usart
13
When USART FIFO Is Enabled, the Last Byte of the Frame Cannot be Transmitted
13
When USART FIFO Is Enabled, DMA Cannot Transmit Data
13
Data Sample Error Occurs in LIN Mode
13
In Mute Mode, the Parity Error Caused by Non-Wake Frames will Set PERR Bit
14
Ospi
14
Interrupt and DMA Functions Are Invalid When OSPI Is Used in Indirect Write Mode
14
When OSPI Sends Only Data Segments, the First Clock Is Lost
14
When OSPI Running Clock Is Greater than 100Mhz, Read External Memory Status Flag Abnormal in Status Polling Mode
14
Exmc
15
NAND/NOR Cannot be Used with SDRAM at the same Time
15
The Bus May Stuck During SDRAM Access
15
Does Not Support Unaligned Address Access
15
Lpdts
16
The Temperature Sensor Ready Flag Cannot be Cleared after Disabling LPDTS
16
Can
16
The Transmit Mailbox May Experience Transmission Failures When Exiting Inactive Mode
16
CAN Transmit Node Performs Unwanted Automatic Calibration
16
The CAN Peripheral Cannot Function Without Using HXTAL
17
Usbhs
17
USBHS OTG Sensitivity Problem
17
Revision History
18

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GigaDevice Semiconductor GD32H737 User Manual (1884 pages)

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GigaDevice Semiconductor GD32H737 Errata Sheet (19 pages)

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