GigaDevice Semiconductor GD32E51 Series User Manual

Arm cortex-m33 32-bit mcu

page of 1334

/ 1334
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

Download this manual

GigaDevice Semiconductor Inc.

GD32E51x

Arm

Cortex

-M33 32-bit MCU

For GD32E513xx, GD32E517xx, GD32E518xx, GD32EPRTxxA

User Manual

Revision 1.2

(Apr. 2024)

Table of Contents

Chapters

Table of Contents

Need help?

Do you have a question about the GD32E51 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for GigaDevice Semiconductor GD32E51 Series

Page 1 GigaDevice Semiconductor Inc. GD32E51x ® Cortex -M33 32-bit MCU ® For GD32E513xx, GD32E517xx, GD32E518xx, GD32EPRTxxA User Manual Revision 1.2 (Apr. 2024)
Page 2: Table Of Contents
GD32E51x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................21 List of Tables ........................ 32 1. System and memory architecture ................ 37 ® ® 1.1. Cortex -M33 processor ..................37 1.2. System architecture ....................... 38 1.3.
Page 3 GD32E51x User Manual 2.4.4. Status register (FMC_STAT) ....................64 2.4.5. Control register (FMC_CTL) ....................64 2.4.6. Address register (FMC_ADDR) .................... 66 2.4.7. ECC control and status register (FMC_ECCCS) ..............66 2.4.8. Option byte status register (FMC_OBSTAT) ................. 68 2.4.9. Erase/Program protection register (FMC_WP) ..............68 2.4.10.
Page 4 GD32E51x User Manual 5.2.2. Characteristics ........................94 5.2.3. Function overview ......................... 94 5.3. Register definition......................99 5.3.1. Control register (RCU_CTL) ....................99 5.3.2. Clock configuration register 0 (RCU_CFG0) ..............100 5.3.3. Clock interrupt register (RCU_INT) ..................104 5.3.4. APB2 reset register (RCU_APB2RST) ................106 5.3.5.
Page 5 GD32E51x User Manual 5.6.12. Clock configuration register 1 (RCU_CFG1) ..............166 5.6.13. Deep-sleep mode voltage register (RCU_DSV) ..............169 5.6.14. Additional clock control register (RCU_ADDCTL) .............. 170 5.6.15. Additional Clock configuration register (RCU_ADDCFG) ........... 171 5.6.16. Additional clock interrupt register (RCU_ADDINT) ............. 172 5.6.17.
Page 6 GD32E51x User Manual 8.1. Overview ........................199 8.2. Characteristics ......................199 8.3. Function overview......................199 8.3.1. GPIO pin configuration ....................... 200 8.3.2. External interrupt/event lines ....................201 8.3.3. Alternate functions (AF) ...................... 201 8.3.4. Input configuration ......................201 8.3.5. Output configuration ......................202 8.3.6.
Page 7 GD32E51x User Manual 8.5.16. IO compensation control register (AFIO_CPSCTL)............232 8.5.17. AFIO port configuration register A (AFIO_PCFA) ............... 233 8.5.18. AFIO port configuration register B (AFIO_PCFB) ............... 235 8.5.19. AFIO port configuration register C (AFIO_PCFC) .............. 238 8.5.20. AFIO port configuration register D (AFIO_PCFD) .............. 240 8.5.21.
Page 8 GD32E51x User Manual 10.5.6. Status register (TMU_STAT) ....................262 Direct memory access controller (DMA) ............264 11.1. Overview ........................264 11.2. Characteristics ......................264 11.3. Block diagram ......................265 11.4. Function overview ....................265 11.4.1. DMA operation ........................265 11.4.2. Peripheral handshake ......................
Page 9 GD32E51x User Manual 13.2. Characteristics ......................287 13.3. Pins and internal signals ..................288 13.4. Functional overview ....................289 13.4.1. Foreground calibration function ..................290 13.4.2. ADC clock ........................... 291 13.4.3. ADCON enable ........................291 13.4.4. Single-ended and differential input channels ..............291 13.4.5.
Page 10 GD32E51x User Manual Digital-to-analog converter (DAC) ..............319 14.1. Overview ........................319 14.2. Characteristics ......................319 14.3. Function overview ....................321 14.3.1. DAC enable ......................... 321 14.3.2. DAC output buffer ....................... 321 14.3.3. DAC data configuration ....................... 321 14.3.4. DAC trigger ......................... 321 14.3.5.
Page 11 GD32E51x User Manual 15.4.1. CMP1 Control / status register (CMP1_CS) ............... 342 15.4.2. CMP3 Control / status register (CMP3_CS) ............... 344 15.4.3. CMP5 Control / status register (CMP5_CS) ............... 345 Watchdog timer (WDGT) .................. 348 16.1. Free watchdog timer (FWDGT) ................348 16.1.1.
Page 12 GD32E51x User Manual 18.2. General level0 timer (TIMERx, x=1, 2, 3, 4) ............427 18.2.1. Overview ..........................427 18.2.2. Characteristics ........................427 18.2.3. Block diagram ........................427 18.2.4. Function overview ....................... 428 18.2.5. TIMERx registers(x=1, 2, 3, 4) .................... 444 18.3.
Page 13 GD32E51x User Manual 19.4. Function overview ....................599 19.4.1. Master_TIMER unit ......................599 19.4.2. Slave_TIMERx(x=0..4) unit ....................607 19.4.3. DLL calibrate ........................638 19.4.4. Bunch mode ........................638 19.4.5. Synchronization input/output ....................643 19.4.6. External event ........................644 19.4.7. Fault input ........................... 646 19.4.8.
Page 14 GD32E51x User Manual 22.1. Overview ........................912 22.2. Characteristics ......................912 22.2.1. SPI characteristics ......................912 22.2.2. I2S characteristics ......................912 22.3. SPI function overview ....................913 22.3.1. SPI block diagram ....................... 913 22.3.2. SPI signal description ......................913 22.3.3. SPI clock timing and data format ..................
Page 15 GD32E51x User Manual 23.3.6. Read ID command flow ...................... 960 23.3.7. Read/Write operation flow ....................960 23.3.8. SQPI controller mode timing ....................960 23.4. Register definition ....................962 23.4.1. SQPI Initial Register (SQPI_INIT)..................962 23.4.2. SQPI Read Command Register (SQPI_RCMD) ..............963 23.4.3.
Page 16 GD32E51x User Manual 24.8.5. Command index response register (SDIO_RSPCMDIDX) ..........1017 24.8.6. Response register (SDIO_RESPx x=0..3) ................ 1017 24.8.7. Data timeout register (SDIO_DATATO) ................1018 24.8.8. Data length register (SDIO_DATALEN) ................1018 24.8.9. Data control register (SDIO_DATACTL) ................1019 24.8.10. Data counter register (SDIO_DATACNT) ................. 1020 24.8.11.
Page 17 GD32E51x User Manual 26.4.2. Status register (CAN_STAT) ..................... 1086 26.4.3. Transmit status register (CAN_TSTAT) ................1088 26.4.4. Receive message FIFO0 register (CAN_RFIFO0) ............1091 26.4.5. Receive message FIFO1 register (CAN_RFIFO1) ............1091 26.4.6. Interrupt enable register (CAN_INTEN) ................1092 26.4.7. Error register (CAN_ERR) ....................
Page 18 GD32E51x User Manual 27.4.2. MAC frame filter register (ENET_MAC_FRMF) ..............1168 27.4.3. MAC hash list high register (ENET_MAC_HLH) ............... 1170 27.4.4. MAC hash list low register (ENET_MAC_HLL) ..............1171 27.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) ............1171 27.4.6. MAC PHY data register (ENET_MAC_PHY_DATA) ............1172 27.4.7.
Page 19 GD32E51x User Manual 27.4.44. PTP PPS control register (ENET_PTP_PPSCTL) ............. 1199 27.4.45. DMA bus control register (ENET_DMA_BCTL) ..............1199 27.4.46. DMA transmit poll enable register (ENET_DMA_TPEN) ..........1201 27.4.47. DMA receive poll enable register (ENET_DMA_RPEN) ........... 1202 27.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR) ...... 1203 27.4.49.
Page 20 GD32E51x User Manual 28.7.11. USBD LPM control and status register (USBD_LPMCS) ..........1235 Universal serial bus High-Speed interface (USBHS) ........1236 29.1. Overview ........................1236 29.2. Characteristics ......................1236 29.3. Block diagram ......................1237 29.4. Signal description ....................1237 29.5. Function overview ....................
Page 21: List Of Figures
GD32E51x User Manual List of Figures Figure 1-1. The structure of the Cortex ® -M33 processor ............. 38 Figure 1-2. High density devices system architecture ..............40 Figure 1-3. Connectivity line devices system architecture ............41 Figure 2-1. Process of page erase operation .................. 54 Figure 2-2.
Page 22 GD32E51x User Manual Figure 13-6. Scan operation mode, continuous operation mode enable ....... 294 Figure 13-7. Discontinuous operation mode ................. 294 Figure 13-8. 12-bit data storage mode .................... 296 Figure 13-9. 6-bit data storage mode ....................296 Figure 13-10. 20-bit to 16-bit result truncation ................299 Figure 13-11.
Page 23 GD32E51x User Manual Figure 18-22. Hall sensor is used to BLDC motor ................ 392 Figure 18-23. Hall sensor timing between two timers ..............392 Figure 18-24. Restart mode ........................ 393 Figure 18-25. Pause mode ........................394 Figure 18-26. Event mode ........................394 Figure 18-27.
Page 24 GD32E51x User Manual Figure 18-66. Output-compare under three modes ..............503 Figure 18-67. General level3 timer block diagram ............... 517 Figure 18-68. Timing chart of internal clock divided by 1 ............518 Figure 18-69. Timing chart of PSC value change from 0 to 2 ............ 519 Figure 18-70.
Page 25 GD32E51x User Manual Figure 19-9 Reset event resynchronization when prescaling ratio is 128 ......604 Figure 19-10. Slave_TIMERx diagram....................607 Figure 19-11. Capture 0 triggered by EXEV0 and EXEV1 ............611 Figure 19-12．Compare 1 behavior with STxCAR=0x8, STxCMP1V=0x02 ......612 Figure 19-13.
Page 26 GD32E51x User Manual Figure 20-5. Configuration step when using DMA for USART transmission ......778 Figure 20-6. Configuration steps when using DMA for USART reception ......779 Figure 20-7. Hardware flow control between two USARTs ............779 Figure 20-8. Hardware flow control ....................780 Figure 20-9.
Page 27 GD32E51x User Manual Figure 21-14. I2C module block diagram ..................873 Figure 21-15. Data validation ......................874 Figure 21-16. START and STOP signal .................... 875 Figure 21-17. I2C communication flow with 10-bit address (Master Transmit) ....875 Figure 21-18. I2C communication flow with 7-bit address (Master Transmit) ...... 876 Figure 21-19.
Page 28 GD32E51x User Manual Figure 22-20. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ..929 Figure 22-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ..930 Figure 22-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ..930 Figure 22-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ... 930 Figure 22-24.
Page 29 GD32E51x User Manual CHLEN=1, CKPL=0) ........................936 Figure 22-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ........................936 Figure 22-51. Block diagram of I2S clock generator ..............936 Figure 22-52. I2S initialization sequence ..................939 Figure 22-53. I2S master reception disabling sequence ............941 Figure 23-1.
Page 30 GD32E51x User Manual Figure 25-10. Mode 2/B read access ....................1039 Figure 25-11. Mode 2 write access ....................1040 Figure 25-12. Mode B write access ....................1040 Figure 25-13. Mode C read access ....................1041 Figure 25-14. Mode C write access ....................1042 Figure 25-15.
Page 31 GD32E51x User Manual Figure 29-1. USBHS block diagram....................1237 Figure 29-2. Connection using internal embedded PHY with host or device mode ..1239 Figure 29-3. Connection using internal embedded PHY with OTG mode ......1240 Figure 29-4. Connection using external ULPI PHY ..............1240 Figure 29-5.
Page 32: List Of Tables
GD32E51x User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ......38 Table 1-2. Memory map of GD32E51x devices ................42 Table 1-3. Boot modes ........................... 46 Table 2-1. GD32E51x_HD and GD32E51x_CL base address and size for flash memory ..49 Table 2-2.
Page 33 GD32E51x User Manual Table 13-1. ADC internal input signals .................... 288 Table 13-2. ADC input pins definition ....................288 Table 13-3. External trigger source for ADC0 and ADC1 ............296 Table 13-4. External trigger source for ADC2 ................297 Table 13-5. t timings depending on resolution ..............
Page 34 GD32E51x User Manual Table 20-4. Description of USART important pins ............... 804 Table 20-5. Configuration of stop bits ..................... 805 Table 20-6. USART interrupt requests ..................... 821 Table 21-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) ...........................
Page 35 GD32E51x User Manual Table 24-21. Response R6 ........................989 Table 24-22. Response R7 ........................990 Table 24-23. Card status ........................992 Table 24-24. SD status ......................... 994 Table 24-25. Performance move field ....................996 Table 24-26. AU_SIZE field ......................... 996 Table 24-27.
Page 36 GD32E51x User Manual Table 28-2. Double-buffering buffer flag definition ..............1220 Table 28-3. Double buffer usage ..................... 1220 Table 28-4. Reception status encoding ..................1232 Table 28-5. Endpoint type encoding ....................1232 Table 28-6. Endpoint kind meaning ....................1232 Table 28-7. Transmission status encoding .................. 1233 Table 29-1.
Page 37: System And Memory Architecture
GD32E51x User Manual System and memory architecture The devices of GD32E51x series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M33 processor. The Arm Cortex -M33 processor includes two AHB buses ® ® known as Code and System buses. All memory accesses of the Arm Cortex -M33 processor are executed on these two buses according to the different purposes and the target memory...
Page 38: System Architecture
GD32E51x User Manual ® Figure 1-1. The structure of the Cortex -M33 processor Cortex-M33 processor Cortex-M33 core Nested Interrupts Vectored Floating Point Interrupt Unit(FPU) Controller (NVIC) DSP Extension Data Breakpoint Memory Watchpoint Unit Protection And Trace (BPU) Unit(MPU) (DWT) Serial-Wire Or JTAG Instrumentation Trace Port...
Page 39 GD32E51x User Manual CBUS SBUS DMA0 DMA1 ENET OTGHS APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including CBUS, SBUS, DMA0, DMA1, ENET and OTGHS. CBUS is the code bus of the Cortex®-M33 core, which is used for any instruction fetch and data access to the Code region.
Page 40: Figure 1-2. High Density Devices System Architecture
GD32E51x User Manual Figure 1-2. High density devices system architecture SW/JTAG TPIU POR/ PDR Flash Flash ARM Cortex-M33 Memory Memory Cbus Processor Controller Fmax:180MHz : 180MHz NVIC Master FMC SQPI TMU CRC SDIO 1.1V GP DMA 12 chs Slave AHB Peripherals Master 8MHz SRAM...
Page 41: Memory Map
GD32E51x User Manual Figure 1-3. Connectivity line devices system architecture SW/JTAG TPIU POR/ PDR Flash Flash ARM Cortex-M33 Memory Memory Cbus Processor Controller Fmax:180MHz : 180MHz NVIC Master FMC SQPI TMU CRC SDIO 1.1V GP DMA 12 chs Slave AHB Peripherals Master 8MHz ENET...
Page 42: Table 1-2. Memory Map Of Gd32E51X Devices
GD32E51x User Manual ® Additionally, a pre-defined memory map is provided by the Cortex -M33 processor to reduce the software complexity of repeated implementation of different device vendors. In the map, ® ® some regions are used by the Arm Cortex -M33 system peripherals which can not be modified.
Page 43 GD32E51x User Manual Pre-defined Address Peripherals Regions 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved...
Page 44 GD32E51x User Manual Pre-defined Address Peripherals Regions 0x4000 C800 - 0x4000 CBFF 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF I2C2 0x4000 8C00 - 0x4000 BFFF Reserved 0x4000 8800 - 0x4000 8BFF CAN2SRAM 0x4000 8400 - 0x4000 87FF USBSRAM_B 0x4000 8000 - 0x4000 BFFF Reserved...
Page 45: On-Chip Sram Memory
GD32E51x User Manual Pre-defined Address Peripherals Regions 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved SRAM 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2000 0000 - 0x2001FFFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes...
Page 46: Boot Configuration
GD32E51x User Manual Kbytes are called High-density devices (GD32E51x_HD). GD32E517xx and GD32E518xx microcontrollers are called connectivity line devices (GD32E51x_CL). Refer to Flash memory controller (FMC) Chapter for more details. Boot configuration 1.4. The GD32E51x devices provide three kinds of boot sources which can be selected by the BOOT0 and BOOT1 pins.
Page 47: Memory Density Information
GD32E51x User Manual Memory density information 1.5.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes. Example: 0x0080 indicates 128 Kbytes.
Page 48: System Configuration Registers
GD32E51x User Manual Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID System configuration registers 1.6.
Page 49: Flash Memory Controller (Fmc)
GD32E51x User Manual Flash memory controller (FMC) Overview 2.1. The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 512K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 50: Error Checking And Correcting (Ecc)
GD32E51x User Manual Block Name Address range Size(bytes) GD32E51x_HD 0x1FFF E000- 0x1FFF F7FF Information Boot loader area block GD32E51x_CL 0x1FFF B000- 0x1FFF F7FF 18KB Option bytes block Option bytes 0x1FFF F800 - 0x1FFF F80F One-time program block OTP bytes 0x1FFF_7000~0x1FFF_77FF Note: The information block stores the boot loader.
Page 51: Read Operations
GD32E51x User Manual Read operations 2.3.3. The flash can be addressed directly as a common memory space. Any instruction fetch and the data access from the flash are through the AHB BUS from the CPU. Wait state added: The WSCNT bits in the FMC_WS register needs to be configured correctly depend on the AHB clock frequency when reading the flash memory.
Page 52: Unlock The Fmc_Ctl Register
GD32E51x User Manual buffer is only performed only when fetching instructions. In the case of sequential code, when CPU execute the current buffer data (128-bit), it takes at least 4 clocks for 32-bit operation and at least 8 clocks for 16-bit operation. In this case, pre-fetch the data of next double-word address from flash memory and store to pre-fetch buffer.
Page 53: Page Erase
GD32E51x User Manual Page erase 2.3.5. The FMC provides a page erase function which is used to initialize the contents of a main flash memory page to a high state. Each page can be erased independently without affecting the contents of other pages. The following steps show the access sequence of the registers for a page erase operation.
Page 54: Mass Erase
GD32E51x User Manual Figure 2-1. Process of page erase operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Mass erase...
Page 55: Main Flash Programming
GD32E51x User Manual When the operation is executed successfully, the ENDF bit in the FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Since all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or using the debugging tool that accesses the FMC registers directly.
Page 56 GD32E51x User Manual The following steps show the register access sequence of the programming operation.  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 57: Otp Programming
GD32E51x User Manual Figure 2-3. Process of word program operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish Note: Reading the flash should be avoided when a program/erase operation is ongoing in the same bank.
Page 58: Option Bytes Programming
GD32E51x User Manual  Unlock the option bytes operation bits in the FMC_CTL register if necessary.  Wait until the OBWEN bit is set in the FMC_CTL register.  Set the OBER bit in the FMC_CTL register.  Send the option bytes erase command to the FMC by setting the START bit in the FMC_CTL register.
Page 59: Table 2-3. Option Bytes
GD32E51x User Manual Table 2-3. Option bytes Address Name Description option bytes security protection value 0xA5 : no security protection 0x1fff f800 any value except 0xA5 or 0xCC : protection level low 0xCC : protection level high 0x1fff f801 SPC_N SPC complement value [7:6]: BOR_TH (Brown out reset threshold) 00: BOR Level 3, brownout threshold level 3...
Page 60: Page Erase / Program Protection
GD32E51x User Manual Page erase / program protection 2.3.12. The FMC provides page erase/program protection functions to prevent inadvertent operations on the flash memory. The page erase or program will not be accepted by the FMC on protected pages. If the page erase or program command is sent to the FMC on a protected page, the WPERR bit in the FMC_STAT register will be set by the FMC.
Page 61 GD32E51x User Manual Protection level high: when setting SPC byte to 0xCC, protection level high performed. When this level is programmed, debug mode, boot from SRAM or boot from boot loader mode are disabled. The main flash block is accessible by all operations from user code. The SPC byte cannot be reprogrammed.
Page 62: Register Definition
GD32E51x User Manual Register definition 2.4. FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0630 This register has to be accessed by word (32-bit). Reserved Reserved DCRST ICRST DCEN ICEN Reserved PFEN Reserved WSCNT[2:0] Bits...
Page 63: Unlock Key Register (Fmc_Key)
GD32E51x User Manual 001: 1 wait state added 010: 2 wait state added 011: 3 wait state added 100: 4 wait state added 101 ~111: reserved Unlock key register (FMC_KEY) 2.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). KEY[31:16] KEY[15:0] Bits...
Page 64: Status Register (Fmc_Stat)
GD32E51x User Manual Status register (FMC_STAT) 2.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ENDF WPERR PGAERR PGERR Reserved BUSY rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 65 GD32E51x User Manual Reserved ENDIE Reserved ERRIE OBWEN Reserved START OBER OBPG Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. ENDIE End of operation interrupt enable bit This bit is set or cleared by software 0: no interrupt generated by hardware. 1: end of operation interrupt enable Reserved Must be kept at reset value.
Page 66: Address Register (Fmc_Addr)
GD32E51x User Manual 1: main flash mass erase command Main flash page erase command bit This bit is set or clear by software 0: no effect 1: main flash page erase command Main flash program command bit This bit is set or clear by software 0: no effect 1: main flash program command Note: This register should be reset after the corresponding flash operation completed.
Page 67 GD32E51x User Manual Bits Field Descriptions 31:16 ECCADDR[15:0] The offset address of double word where an ECC error is detected. Error address = base address + ECCADDR[15:0] * 8, the base address can be the start address of main Flash, system area, option bytes and OTP. Main flash: 0 ~ 0x3FFF (128K/8 - 1) Option bytes: 0 ~ 0x01 (16/8 -1) OTP: 0 ~ 0x3F (512/8 -1)
Page 68: Option Byte Status Register (Fmc_Obstat)
GD32E51x User Manual by writing 1. 0: No ECC error is detected in system memory. 1: An ECC bit error is detected in system memory. ECCDET Two bits errors detect flag. This bit set when two bits errors is detected. This bit is cleared by writing 1.
Page 69: Product Id Register (Fmc_Pid)
GD32E51x User Manual This register has to be accessed by word(32-bit). WP[31:16] WP[15:0] Bits Fields Descriptions 31:0 WP[31:0] Store WP[31:0] of option bytes block after system reset Product ID register (FMC_PID) 2.4.10. Address offset: 0x100 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). PID[31:16] PID[15:0] Bits...
Page 70: Backup Registers (Bkp)
GD32E51x User Manual Backup registers (BKP) Overview 3.1. The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from Standby mode or system reset do not affect these registers.
Page 71 GD32E51x User Manual and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection configuration should be set before enable TAMPER pin.
Page 72: Register Definition
GD32E51x User Manual Register definition 3.4. BKP base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..41) 3.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). DATA [15:0] Bits Fields...
Page 73: Tamper Pin Control Register (Bkp_Tpctl)
GD32E51x User Manual 1: RTC second pulse is selected as the RTC output This bit is reset only by a Backup domain reset. ASOEN RTC alarm or second signal output enable 0: Disable RTC alarm or second output 1: Enable RTC alarm or second output When enable, the TAMPER pin will output the RTC output.
Page 74: Tamper Control And Status Register (Bkp_Tpcs)
GD32E51x User Manual Tamper control and status register (BKP_TPCS) 3.4.4. Address offset: 0x34 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved TPIE Bits Fields Descriptions 15:10 Reserved Must be kept at reset value. Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred...
Page 75: Power Management Unit (Pmu)
GD32E51x User Manual Power management unit (PMU) Overview 4.1. The power consumption is regarded as one of the most important issues for the devices of GD32E51x series. According to the Power management unit (PMU), provides five types of power saving modes, including Sleep, Deep-sleep, Deep-sleep 1, Deep-sleep 2 and Standby mode.
Page 76: Backup Domain
GD32E51x User Manual Figure 4-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD BREG PB15 WKUPN NRST WKUPF FWDGT SLEEPING Cortex-M33 SLEEPDEEP HXTAL AHB IPs APB IPs 1.1V Domain 1.1V Domain Domain IRC8M IRC40K 3.3V IRC48M...
Page 77: Vdd / V Dda
GD32E51x User Manual achieve the RTC alarm event. After entering the power saving mode for a certain amount of time, the RTC alarm will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the Real-time clock (RTC).
Page 78: Figure 4-3. Waveform Of The Por / Pdr
GD32E51x User Manual Figure 4-2. Waveform of the BOR 100mV hyst BOR Reset (Active Low) domain The POR / PDR circuit is implemented to detect V and generate the power reset signal which resets the whole chip except the Backup domain when the supply voltage is lower than the specified threshold.
Page 79: Power Domain
GD32E51x User Manual threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register(PMU_CS0), indicates if V is higher or lower than the LVD threshold. This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers.
Page 80: Power Saving Modes
GD32E51x User Manual for the Backup domain and the V domain, etc, are located in this power domain. Once the 1.1V is powered up, the POR will generate a reset sequence on the 1.1V power domain. If need to enter the expected power saving mode, the associated control bits must be configured.
Page 81 GD32E51x User Manual  Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.  Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits from the lowest priority ISR.
Page 82 GD32E51x User Manual Deep-sleep 1 mode The Deep-sleep 1 mode is based on the SLEEPDEEP mode of the Cortex ® -M33. In Deep- sleep 1 mode, all clocks in the 1.1V domain are off, and all of IRC8M, IRC48M, HXTAL and PLLs are disabled.
Page 83: Table 4-1. Power Saving Mode Summary
GD32E51x User Manual The low-driver mode in Deep-sleep 2 mode can be entered by configuring the LDEN, LDNP, LDLP, LDOLP bits in the PMU_CTL0 register. The low-driver mode provides lower drive capability, and the low-power mode take lower power. Note: When exiting from the Deep-sleep 2 mode, the Cortex ®...
Page 84 GD32E51x User Manual Mode Sleep Deep-sleep Deep-sleep 1 Deep-sleep 2 Standby Any event(or interrupt Any event(or interrupt Any event (or Any event(or interrupt WKUP when SEVONPEND is when SEVONPEND is interrupt when when SEVONPEND is pins 1) from EXTI for WFE 1) from EXTI for WFE SEVONPEND is 1) from EXTI for WFE...
Page 85: Register Definition
GD32E51x User Manual Register definition 4.4. PMU base address: 0x4000 7000 Control register 0 (PMU_CTL0) 4.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). LDEN[1:0] Reserved HDEN Reserved LDNP...
Page 86 GD32E51x User Manual 1: Low-driver mode enabled when LDEN is 11 and use normal power LDO LDLP Low-driver mode when use low power LDO. 0: normal driver when use low power LDO 1: Low-driver mode enabled when LDEN is 11 and use low power LDO Reserved Must be kept at reset value.
Page 87: Control And Status Register 0 (Pmu_Cs0)
GD32E51x User Manual Note: Some peripherals may work with the IRC8M clock in the Deep-sleep / Deep- sleep 1 / Deep-sleep 2 mode. In this case, the LDO automatically switches from the low power mode to the normal mode and remains in this mode until the peripheral stop working.
Page 88 GD32E51x User Manual Reserved Must be kept at reset value. WUPEN5 WKUP Pin5(PB5) Enable 0: Disable WKUP pin5 function 1: Enable WKUP pin5 function If WUPEN5 is set before entering the power saving mode, a rising edge on the WKUP pin5 wakes up the system from the power saving mode. As the WKUP pin5 is active high, the WKUP pin5 is internally configured to input pull down mode.
Page 89: Control Register 1 (Pmu_Ctl1)
GD32E51x User Manual is active high, the WKUP pin0 is internally configured to input pull down mode. And set this bit will trigger a wakup event when the input is aready high. WUPEN6 WKUP Pin6(PB15) Enable 0: Disable WKUP pin6 function 1: Enable WKUP pin6 function If WUPEN6 is set before entering the power saving mode, a rising edge on the WKUP pin6 wakes up the system from the power saving mode.
Page 90: Control And Status Register 1 (Pmu_Cs1)
GD32E51x User Manual 31:2 Reserved Must be kept at reset value. DPMOD2 Deep-sleep 2 mode enable 0: Not care 1:Go to Deep-sleep 2 mode when SLEEPDEEP bit is set and the STBMOD bit is clear DPMOD1 Deep-sleep 1 mode enable 0: Not care 1:Go to Deep-sleep 1 mode when the SLEEPDEEP bit is set and the STBMOD bit is clear and the DPMOD2 bit is clear...
Page 91: Reset And Clock Unit (Rcu)
GD32E51x User Manual Reset and clock unit (RCU) High density reset and clock control unit (RCU) Reset control unit (RCTL) 5.1. Overview 5.1.1. GD32E51x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 92: Clock Control Unit (Cctl)
GD32E51x User Manual A system reset resets the processor core and peripheral IP components except for the SW- DP controller and the backup domain. A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset).
Page 93: Figure 5-2. Clock Tree
GD32E51x User Manual Figure 5-2. Clock tree CK48MSEL USBD Presacaler CK_USBD /1,1.5,2,2.5 3,3.5,4 (to USBD) (to FMC) CK_IRC48M CK_CTC CK_FMC CK_PLLSRC 48 MHz IRC48M SCS[1:0] CK_I2S (to I2S1,2) I2S enable CK_IRC8M CK_AHB 8 MHz ×2,3,4 CK_SYS CK_EXMC CK_PLL IRC8M Prescaler 180 MHz max EXMC enable (to EXMC)
Page 94: Characteristics
GD32E51x User Manual The SDIO, EXMC are clocked by the clock of CK_AHB. The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1).
Page 95: Figure 5-3. Hxtal Clock Source
GD32E51x User Manual Figure 5-3. HXTAL clock source OSCIN OSCOUT Crystal The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL. The HXTALSTB flag in control register RCU_CTL indicates if the high- speed external crystal oscillator is stable.
Page 96 GD32E51x User Manual The frequency accuracy of the IRC8M can be calibrated by the manufacturer, but its operating frequency is still less accurate than HXTAL. The application requirements, environment and cost will determine which oscillator type is selected. If the HXTAL or PLL is the system clock source, to minimize the time required for the system to recover from the Deep-sleep Mode, the hardware forces the IRC8M clock to be the system clock when the system initially wakes-up.
Page 97 GD32E51x User Manual drives the OSC32IN pin. Internal 40K RC oscillator (IRC40K) The internal RC oscillator has a frequency of about 40 kHz and is a low power clock source for the real time clock circuit or the rree watchdog timer. The IRC40K offers a low cost clock source as no external components are required.
Page 98: Table 5-1. Clock Output 0 Source Select
GD32E51x User Manual Table 5-1. Clock output 0 source select Clock source 0 selection bits Clock source NO CLK CK_SYS CK_IRC8M CK_HXTAL CK_PLL/2 Voltage control The 1.1V domain voltage in Deep-sleep mode can be controlled by DSLPVS[2:0] bit in the Deep-sleep mode voltage register (RCU_DSV).
Page 99: Register Definition
GD32E51x User Manual Register definition 5.3. RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLLSTB Reserved CKMEN...
Page 100: Clock Configuration Register 0 (Rcu_Cfg0)
GD32E51x User Manual HXTALBPS High speed crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0. 0: Disable the HXTAL Bypass mode 1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock.
Page 101 GD32E51x User Manual USBDPS ADCPSC[ PLLMF[5] Reserved PLLMF[4] CKOUT0SEL[2:0] USBDPSC[1:0] PLLMF[3:0] PREDV0 PLLSEL C[2] ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions USBDPSC[2] Bit 2 of USBDPSC see bits 23:22 of RCU_CFG0 PLLMF[5] Bit 5 of PLLMF see bits 21:18 of RCU_CFG0 Reserved Must be kept at reset value.
Page 102 GD32E51x User Manual 000010: CK_SYS = CK_PLL x 4 000011: CK_SYS = CK_PLL x 5 000100: CK_SYS = CK_PLL x 6 000101: CK_SYS = CK_PLL x 7 000110: CK_SYS = CK_PLL x 8 000111: CK_SYS = CK_PLL x 9 001000: CK_SYS = CK_PLL x 10 001001: CK_SYS = CK_PLL x 11 001010: CK_SYS = CK_PLL x 12 001011: CK_SYS = CK_PLL x 13...
Page 103 GD32E51x User Manual clock of PLL 15:14 ADCPSC[1:0] ADC clock prescaler selection These bits, bit 28 of RCU_CFG0 and bit 29 of RCU_CFG1 are written by software to define the ADC prescaler factor.Set and cleared by software. 0000: (CK_APB2 / 2) selected 0001: (CK_APB2 / 4) selected 0010: (CK_APB2 / 6) selected 0011: (CK_APB2 / 8) selected...
Page 104: Clock Interrupt Register (Rcu_Int)
GD32E51x User Manual SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock. 00: Select CK_IRC8M as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_PLL as the CK_SYS source 11: Reserved SCS[1:0] System clock switch...
Page 105 GD32E51x User Manual 1: Reset PLLSTBIF flag HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by software to reset the HXTALSTBIF flag. 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC IRC8M stabilization interrupt clear Write 1 by software to reset the IRC8MSTBIF flag. 0: Not reset IRC8MSTBIF flag 1: Reset IRC8MSTBIF flag LXTALSTBIC...
Page 106: Apb2 Reset Register (Rcu_Apb2Rst)
GD32E51x User Manual CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck. Reset when setting the CKMIC bit by software. 0: Clock operating normally 1: HXTAL clock stuck Reserved Must be kept at reset value. PLLSTBIF PLL stabilization interrupt flag Set by hardware when the PLL is stable and the PLLSTBIE bit is set.
Page 107 GD32E51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SHRTIME USART5 TIMER16 TIMER15 TIMER14 TIMER10 TIMER9 TIMER8 CMPEN Reserved Reserved Reserved Reserved ADC2RS USART0 TIMER7R TIMER0R ADC1RS ADC0RS SPI0RST PGRST PFRST PERST PDRST PCRST PBRST PARST Reserved AFRST Bits...
Page 108 GD32E51x User Manual This bit is set and reset by software. 0: No reset 1: Reset the TIMER10 TIMER9RST Timer 9 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER9 TIMER8RST Timer 8 reset This bit is set and reset by software.
Page 109: Apb1 Reset Register (Rcu_Apb1Rst)
GD32E51x User Manual 1: Reset the ADC0 PGRST GPIO port G reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port G PFRST GPIO port F reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port F PERST...
Page 110 GD32E51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). DAC1RS DAC0RS CAN1RS CAN0RS USBDRS UART4R UART3R USART2 USART1 Reserved PMURST BKPIRST I2C2RST I2C1RST I2C0RST Reserved WWDGT TIMER13 TIMER12 TIMER11 TIMER6R TIMER5R TIMER4R TIMER3R TIMER2R TIMER1R SPI2RST SPI1RST Reserved Reserved Bits...
Page 111 GD32E51x User Manual 1: Reset the I2C2 USBDRST USBD reset This bit is set and reset by software. 0: No reset 1: Reset the USBD I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C1 I2C0RST I2C0 reset This bit is set and reset by software.
Page 112 GD32E51x User Manual 13:12 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT 10:9 Reserved Must be kept at reset value. TIMER13RST TIMER13 reset This bit is set and reset by software.
Page 113: Ahb Enable Register (Rcu_Ahben)
GD32E51x User Manual TIMER1RST TIMER1 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER1 AHB enable register (RCU_AHBEN) 5.3.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SQPIEN TMUEN Reserved...
Page 114: Apb2 Enable Register (Rcu_Apb2En)
GD32E51x User Manual This bit is set and reset by software. 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value. FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software to enable/disable FMC clock during Sleep mode.
Page 115 GD32E51x User Manual This bit is set and reset by software. 0: Disabled CMP clock 1: Enabled CMP clock Reserved Must be kept at reset value SHRTIMEREN SHRTIMER clock enable This bit is set and reset by software. 0: Disabled SHRTIMER clock 1: Enabled SHRTIMER clock USART5EN USART5 clock enable...
Page 116 GD32E51x User Manual 18:16 Reserved Must be kept at reset value. ADC2EN ADC2 clock enable This bit is set and reset by software. 0: Disabled ADC2 clock 1: Enabled ADC2 clock USART0EN USART0 clock enable This bit is set and reset by software. 0: Disabled USART0 clock 1: Enabled USART0 clock TIMER7EN...
Page 117: Apb1 Enable Register (Rcu_Apb1En)
GD32E51x User Manual 0: Disabled GPIO port E clock 1: Enabled GPIO port E clock PDEN GPIO port D clock enable This bit is set and reset by software. 0: Disabled GPIO port D clock 1: Enabled GPIO port D clock PCEN GPIO port C clock enable This bit is set and reset by software.
Page 118 GD32E51x User Manual Reserved Must be kept at reset value. DAC1EN DAC1 clock enable This bit is set and reset by software. 0: Disabled DAC1 clock 1: Enabled DAC1 clock DAC0EN DAC0 clock enable This bit is set and reset by software. 0: Disabled DAC0 clock 1: Enabled DAC0 clock PMUEN...
Page 119 GD32E51x User Manual 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software. 0: Disabled UART3 clock 1: Enabled UART3 clock USART2EN...
Page 120: Backup Domain Control Register (Rcu_Bdctl)
GD32E51x User Manual This bit is set and reset by software. 0: Disabled TIMER12 clock 1: Enabled TIMER12 clock TIMER11EN TIMER11 clock enable This bit is set and reset by software. 0: Disabled TIMER11 clock 1: Enabled TIMER11 clock TIMER6EN TIMER6 clock enable This bit is set and reset by software.
Page 121 GD32E51x User Manual modified only when the BKPWEN bit in the power control register 0 (PMU_CTL0) is set. Reserved BKPRST LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LXTALDRI[1:0] LXTALEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. BKPRST Backup domain reset This bit is set and reset by software.
Page 122: Reset Source/Clock Register (Rcu_Rstsck)
GD32E51x User Manual 1: Enable the LXTAL Bypass mode LXTALSTB Low speed crystal oscillator stabilization flag Set by hardware to indicate if the LXTAL output clock is stable and ready for use. 0: LXTAL is not stable 1: LXTAL is stable LXTALEN LXTAL enable Set and reset by software.
Page 123: Ahb Reset Register (Rcu_Ahbrst)
GD32E51x User Manual 1: free Watchdog timer reset generated SWRSTF Software reset flag Set by hardware when a software reset generated. Reset by writing 1 to the RSTFC bit. 0: No software reset generated 1: Software reset generated PORRSTF Power reset flag Set by hardware when a power reset generated.
Page 124: Clock Configuration Register 1 (Rcu_Cfg1)
GD32E51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SQPIRST TMURST Reserved Reserved Bits Fields Descriptions SQPIRST SQPI reset This bit is set and reset by software. 0: No reset 1: Reset the SQPI TMURST TMU reset This bit is set and reset by software.
Page 125: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32E51x User Manual 28:0 Reserved Must be kept at reset value. Deep-sleep mode voltage register (RCU_DSV) 5.3.13. Address offset: 0x34 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved DSLPVS[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value.
Page 126: Additional Clock Interrupt Register (Rcu_Addint)
GD32E51x User Manual 23:18 Reserved Must be kept at reset value. IRC48MSTB Internal 48MHz RC oscillator clock stabilization flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use. 0: IRC48M is not stable 1: IRC48M is stable IRC48MEN Internal 48MHz RC oscillator enable Set and reset by software.
Page 127: Pll Clock Spread Spectrum Control Register (Rcu_Pllssctl)
GD32E51x User Manual Set and reset by software to enable/disable the IRC48M stabilization interrupt 0: Disable the IRC48M stabilization interrupt 1: Enable the IRC48M stabilization interrupt 13:7 Reserved Must be kept at reset value. IRC48MSTBIF IRC48M stabilization interrupt flag Set by hardware when the Internal 48 MHz RC oscillator clock is stable and the IRC48MSTBIE bit is set.
Page 128: Clock Configuration Register 2 (Rcu_Cfg2)
GD32E51x User Manual 0: Center spread selected 1: Down spread selected 29:28 Reserved Must be kept at reset value. 27:13 MODSTEP[14:0] These bits configure PLL spread spectrum modulation profile amplitude and frequency. The following criteria must be met: MODSTEP*MODCNT≤2 12:0 MODCNT[12:0] These bits configure PLL spread spectrum modulation profile amplitude and frequency.
Page 129: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32E51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved Reserved Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. CTCRST CTC reset This bit is set and reset by software. 0: No reset 1: Reset CTC 26:0 Reserved...
Page 130: Connectivity Line Devices: Reset And Clock Control Unit (Rcu)
GD32E51x User Manual Connectivity line devices: reset and clock control unit (RCU) Reset control unit (RCTL) 5.4. Overview 5.4.1. GD32E51x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 131: Clock Control Unit (Cctl)
GD32E51x User Manual source (external or internal reset). Figure 5-5. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have previously been powered off).
Page 132: Figure 5-6. Clock Tree
GD32E51x User Manual Figure 5-6. Clock tree CK_PLLUSB USBHS PHY clock 24Mhz to 60Mhz (to USBHS in high-speed mode) PLLUSBPR CK48MSEL[1:0] ESEL PLLUSBMF USBHSDV PLLUSBPREDV 48 0M H z CK_IRC48M CK_PLL2 PHSEL × 16 , 17 m ax / 1, 2, 3 / 2, 4 48 MHz/ 12 7...
Page 133: Characteristics
GD32E51x User Manual The I2C2 is clocked by IRC8M clock or system clock or APB1 clock, which selected by I2C2SEL bits in configuration register 2 (RCU_CFG2). The SDIO, EXMC are clocked by the clock of CK_AHB. The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1).
Page 134: Function Overview
GD32E51x User Manual Function overview 5.5.3. High speed crystal oscillator (HXTAL) The high speed external crystal oscillator (HXTAL), which has a frequency from 4 to 32 MHz, produces a highly accurate clock source for use as the system clock. A crystal with a specific frequency must be connected and located close to the two HXTAL pins.
Page 135 GD32E51x User Manual source selection for the CPU when the device is powered up. The IRC8M oscillator provides a lower cost type clock source as no external components are required. The IRC8M RC oscillator can be switched on or off using the IRC8MEN bit in the control register RCU_CTL. The IRC8MSTB flag in the control register RCU_CTL is used to indicate if the internal 8M RC oscillator is stable.
Page 136 GD32E51x User Manual PLL2STB flag in the RCU_CTL register will indicate if the PLL2 clock is stable. An interrupt can be generated if the related interrupt enable bit, PLL2STBIE, in the RCU_INT register, is set as the PLL2 becomes stable. The PLLUSB can be switched on or off by using the PLLUSBEN bit in the RCU_ADDCTL Register.
Page 137: Table 5-3. Clock Output 0 Source Select
GD32E51x User Manual HXTAL clock monitor (CKM) The HXTAL clock monitor function is enabled by the HXTAL clock monitor rnable bit, CKMEN, in the control register (RCU_CTL). This function should be enabled after the HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is detected, the HXTAL will be automatically disabled.
Page 138: Table 5-4. 1.1V Domain Voltage Selected In Deep-Sleep Mode
GD32E51x User Manual Table 5-4. 1.1V domain voltage selected in deep-sleep mode DSLPVS[2:0] Deep-sleep mode voltage(V)
Page 139: Register Definition
GD32E51x User Manual Register definition 5.6. RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.6.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB Reserved...
Page 140 GD32E51x User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL is switched off 1: PLL is switched on 23:20...
Page 141: Clock Configuration Register 0 (Rcu_Cfg0)
GD32E51x User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M internal 8MHz RC oscillator stabilization flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable Set and reset by software.
Page 142 GD32E51x User Manual 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 1100: CK_IRC48M clock selected 1101: (CK_IRC48M / 8) clock selected 1110: (CK_PLLUSB / 32) clock selected 23:22 USBHSPSC[1:0] USBHS clock prescaler selection...
Page 143 GD32E51x User Manual 010111: (PLL source clock x 24) 011000: (PLL source clock x 25) 011001: (PLL source clock x 26) 011010: (PLL source clock x 27) 011011: (PLL source clock x 28) 011100: (PLL source clock x 29) 011101: (PLL source clock x 30) 011110: (PLL source clock x 31) 011111: (PLL source clock x 32) 100000: (PLL source clock x 33)
Page 144 GD32E51x User Manual 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0] APB1 prescaler selection Set and reset by software to control the APB1 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected...
Page 145: Clock Interrupt Register (Rcu_Int)
GD32E51x User Manual Clock interrupt register (RCU_INT) 5.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIC STBIC STBIC STBIC STBIC STBIC STBIC STBIC PLL2 PLL1 HXTAL...
Page 146 GD32E51x User Manual 1: Reset IRC8MSTBIF flag LXTALSTBIC LXTAL stabilization interrupt clear Write 1 by software to reset the LXTALSTBIF flag. 0: Not reset LXTALSTBIF flag 1: Reset LXTALSTBIF flag IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by software to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag Reserved...
Page 147 GD32E51x User Manual CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck. Reset when setting the CKMIC bit by software. 0: Clock operating normally 1: HXTAL clock stuck PLL2STBIF PLL2 stabilization interrupt flag Set by hardware when the PLL2 is stable and the PLL2STBIE bit is set. Reset when setting the PLL2STBIC bit by software.
Page 148: Apb2 Reset Register (Rcu_Apb2Rst)
GD32E51x User Manual IRC40KSTBIE bit is set. Reset when setting the IRC40KSTBIC bit by software. 0: No IRC40K stabilization clock ready interrupt generated 1: IRC40K stabilization interrupt generated APB2 reset register (RCU_APB2RST) 5.6.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 149 GD32E51x User Manual 0: No reset 1: Reset the TIMER15 TIMER14RST Timer 14 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER14 23:22 Reserved Must be kept at reset value. TIMER10RST Timer 10 reset This bit is set and reset by software.
Page 150 GD32E51x User Manual 0: No reset 1: Reset the TIMER0 ADC1RST ADC1 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC1 ADC0RST ADC0 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC0 PGRST GPIO port G reset...
Page 151: Apb1 Reset Register (Rcu_Apb1Rst)
GD32E51x User Manual Reserved Must be kept at reset value. AFRST Alternate function I/O reset This bit is set and reset by software. 0: No reset 1: Reset Alternate Function I/O APB1 reset register (RCU_APB1RST) 5.6.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 152 GD32E51x User Manual 0: No reset 1: Reset the CAN1 CAN0RST CAN0 reset This bit is set and reset by software. 0: No reset 1: Reset the CAN0 I2C2RST I2C2 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C2 Reserved Must be kept at reset value.
Page 153 GD32E51x User Manual 0: No reset 1: Reset the SPI2 SPI1RST SPI1 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI1 13:12 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT 10:9...
Page 154: Ahb Enable Register (Rcu_Ahben)
GD32E51x User Manual 0: No reset 1: Reset the TIMER3 TIMER2RST TIMER2 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER2 TIMER1RST TIMER1 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER1 AHB enable register (RCU_AHBEN) 5.6.6.
Page 155 GD32E51x User Manual This bit is set and reset by software. 0: Disabled Ethernet TX clock 1: Enabled Ethernet TX clock ENETEN Ethernet clock enable This bit is set and reset by software. 0: Disabled Ethernet clock 1: Enabled Ethernet clock ULPIEN ULPI clock enable This bit is set and reset by software.
Page 156: Apb2 Enable Register (Rcu_Apb2En)
GD32E51x User Manual This bit is set and reset by software to enable/disable SRAM interface clock during Sleep mode. 0: Disabled SRAM interface clock during Sleep mode. 1: Enabled SRAM interface clock during Sleep mode DMA1EN DMA1 clock enable This bit is set and reset by software. 0: Disabled DMA1 clock 1: Enabled DMA1 clock DMA0EN...
Page 157 GD32E51x User Manual 1: Enabled USART5 clock Reserved Must be kept at reset value. TIMER16EN TIMER16 clock enable This bit is set and reset by software. 0: Disabled TIMER16 clock 1: Enabled TIMER16 clock TIMER15EN TIMER15 clock enable This bit is set and reset by software. 0: Disabled TIMER15 clock 1: Enabled TIMER15 clock TIMER14EN...
Page 158 GD32E51x User Manual 0: Disabled TIMER7 clock 1: Enabled TIMER7 clock SPI0EN SPI0 clock enable This bit is set and reset by software. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER0EN TIMER0 clock enable This bit is set and reset by software. 0: Disabled TIMER0 clock 1: Enabled TIMER0 clock ADC1EN...
Page 159: Apb1 Enable Register (Rcu_Apb1En)
GD32E51x User Manual This bit is set and reset by software. 0: Disabled GPIO port B clock 1: Enabled GPIO port B clock PAEN GPIO port A clock enable This bit is set and reset by software. 0: Disabled GPIO port A clock 1: Enabled GPIO port A clock Reserved Must be kept at reset value.
Page 160 GD32E51x User Manual 1: Enabled PMU clock BKPIEN Backup interface clock enable This bit is set and reset by software. 0: Disabled backup interface clock 1: Enabled backup interface clock CAN1EN CAN1 clock enable This bit is set and reset by software. 0: Disabled CAN1 clock 1: Enabled CAN1 clock CAN0EN...
Page 161 GD32E51x User Manual USART1EN USART1 clock enable This bit is set and reset by software. 0: Disabled USART1 clock 1: Enabled USART1 clock Reserved Must be kept at reset value. SPI2EN SPI2 clock enable This bit is set and reset by software. 0: Disabled SPI2 clock 1: Enabled SPI2 clock SPI1EN...
Page 162: Backup Domain Control Register (Rcu_Bdctl)
GD32E51x User Manual 1: Enabled TIMER5 clock TIMER4EN TIMER4 clock enable This bit is set and reset by software. 0: Disabled TIMER4 clock 1: Enabled TIMER4 clock TIMER3EN TIMER3 clock enable This bit is set and reset by software. 0: Disabled TIMER3 clock 1: Enabled TIMER3 clock TIMER2EN TIMER2 clock enable...
Page 163: Reset Source/Clock Register (Rcu_Rstsck)
GD32E51x User Manual 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by software. 0: Disabled RTC clock 1: Enabled RTC clock 14:10 Reserved Must be kept at reset value. RTCSRC[1:0] RTC clock entry selection Set and reset by software to control the RTC clock source.
Page 164 GD32E51x User Manual reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). WWDGT FWDGT BORRST RSTFC Reserved RSTF RSTF RSTF RSTF RSTF RSTF IRC40K IRC40KE Reserved Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated. Reset by writing 1 to the RSTFC bit.
Page 165: Ahb Reset Register (Rcu_Ahbrst)
GD32E51x User Manual 0: No External PIN reset generated 1: External PIN reset generated BORRSTF BOR reset flag Set by hardware when a BOR reset generated. Reset by writing 1 to the RSTFC bit. 0: No BOR reset generated 1: BOR reset generated RSTFC Reset flag clear This bit is set by software to clear all reset flags.
Page 166: Clock Configuration Register 1 (Rcu_Cfg1)
GD32E51x User Manual This bit is set and reset by software. 0: No reset 1: Reset the TMU 29:15 Reserved Must be kept at reset value. ENETRST ENET reset This bit is set and reset by software. 0: No reset 1: Reset the ENET Reserved Must be kept at reset value.
Page 167 GD32E51x User Manual 27:20 Reserved Must be kept at reset value. SHRTIMERSEL SHRTIMER Clock Source Selection Set and reset by software to control the SHRTIMER clock source. 0: APB2 clock selected as SHRTIMER source clock 1: System clock selected as SHRTIMER source clock I2S2SEL I2S2 clock source selection Set and reset by software to control the I2S2 clock source.
Page 168 GD32E51x User Manual 11101: (PLL2 source clock x 31) 11110 :(PLL2 source clock x 32) 11111: (PLL2 source clock x 40) 100000: (PLL2 source clock x 34) … 111110 :(PLL2 source clock x 64) 111111: (PLL2 source clock x 80) 11:8 PLL1MF[3:0] The PLL1 clock multiplication factor...
Page 169: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32E51x User Manual Note: The bit 0 of PREDV0 is same as bit 17 of RCU_CFG0, so modifying bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1. 0000: PREDV0 input source clock not divided 0001: PREDV0 input source clock divided by 2 0010: PREDV0 input source clock divided by 3 0011: PREDV0 input source clock divided by 4 0100: PREDV0 input source clock divided by 5...
Page 170: Additional Clock Control Register (Rcu_Addctl)
GD32E51x User Manual Additional clock control register (RCU_ADDCTL) 5.6.14. Address offset: 0xC0 Reset value: 0x8000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC48MS IRC48ME IRC48MCALIB[7:0] Reserved PLLUSBS PLLUSBE USBSWE USBHSS Reserved USBHSDV[2:0] CK48MSEL[1:0] Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register...
Page 171: Additional Clock Configuration Register (Rcu_Addcfg)
GD32E51x User Manual USBHSDV[2:0] USBHS clock divider factor This bit is set and reset by software. 000: USBHSDV input source clock divided by 2 001: USBHSDV input source clock divided by 4 … 111: USBHSDV input source clock divided by 16 USBHSSEL USBHS clock source selection Set and reset by software to control the USBHS clock source.
Page 172: Additional Clock Interrupt Register (Rcu_Addint)
GD32E51x User Manual PLLUSBPREDVSEL PLLUSBPREDV input clock source selection Set and reset by software. 0: PLLUSBSRC output selected as PLLUSBPREDV input source clock 1: CK_PLL1 output clock selected as PLLUSBPREDV input source clock PLLUSBPRESEL PLLUSB clock source preselection Set and reset by software to control the PLLUSB clock source. 0: CK_ HXTAL selected as PLLUSB source clock 1: CK_IRC48M output clock selected as PLLUSB source clock 15:4...
Page 173: Pll Clock Spread Spectrum Control Register (Rcu_Pllssctl)
GD32E51x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. PLLUSBSTBIC PLLUSB stabilization interrupt clear Write 1 by software to reset the PLLUSBSTBIF flag. 0: Not reset PLLUSBSTBIF flag 1: Reset PLLUSBSTBIF flag IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization interrupt clear Write 1 by software to reset the IRC48MSTBIF flag.
Page 174: Clock Configuration Register 2 (Rcu_Cfg2)
GD32E51x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). The spread spectrum modulation is available only for the main PLL clock The RCU_PLLSSCTL register must be written when the main PLL is disabled. This register is used to configure the PLL spread spectrum clock generation according to the following formulas: MODCNT = round(f /4/f...
Page 175: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32E51x User Manual Reserved I2C2SEL[1:0] Reserved USART5SEL[1:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. I2C2SEL[1:0] I2C2 Clock Source Selection Set and reset by software to control the I2C2 clock source. 00: APB1 clock selected as I2C2 source clock 01: System clock selected as I2C2 source clock 1x: CK_IRC8M clock selected as I2C2 source clock Reserved...
Page 176: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32E51x User Manual 0: No reset 1: Reset CTC 26:0 Reserved Must be kept at reset value. APB1 additional enable register (RCU_ADDAPB1EN) 5.6.20. Address offset: 0xE4 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). CAN2EN Reserved Reserved...
Page 177: Clock Trim Controller (Ctc)
GD32E51x User Manual Clock trim controller (CTC) Overview 6.1. The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the frequency of the IRC48M based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 178: Ref Sync Pulse Generator
GD32E51x User Manual Figure 6-1. CTC overview PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 6.3.1.
Page 179: Frequency Evaluation And Automatically Trim Process
GD32E51x User Manual start down-counting again. If no REF sync pulse detected, the counter down-count to zero, and then up- counting to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 180: Software Program Guide
GD32E51x User Manual CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 181 GD32E51x User Manual CKLIM = ( F ÷ F ) × 0.12% ÷ 2 (6-2) clock The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 182: Register Definition
GD32E51x User Manual Register definition 6.4. CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE...
Page 183: Control Register 1 (Ctc_Ctl1)
GD32E51x User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim warning (CKWARNIF) interrupt enable...
Page 184: Status Register (Ctc_Stat)
GD32E51x User Manual 01: LXTAL clock selected 10: Reserved. 11: Reserved Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8 100: Reference signal divided by 16...
Page 185 GD32E51x User Manual REFDIR CTC trim counter direction when reference sync pulse When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register overflow...
Page 186: Interrupt Clear Register (Ctc_Intc)
GD32E51x User Manual 0 : No Error occur 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 187 GD32E51x User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect. CKOKIC CKOKIF interrupt clear bit This bit is written by software and read as 0.
Page 188: Interrupt/Event Controller (Exti)
GD32E51x User Manual Interrupt/event controller (EXTI) Overview 7.1. ® Cortex -M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. You can read the -M33 for more details about NVIC.
Page 189: Table 7-1. Nvic Exception Types In Cortex ® -M33
GD32E51x User Manual ® Table 7-1. NVIC exception types in Cortex -M33 Vector Exception type priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable...
Page 190 GD32E51x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector address number number interrupt description interrupt description interrupt interrupt DMA0 channel4 global DMA0 channel4 global IRQ 15 0x0000_007C interrupt interrupt DMA0 channel5 global DMA0 channel5 global IRQ 16 0x0000_0080 interrupt interrupt DMA0 channel6 global DMA0 channel6 global...
Page 191 GD32E51x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector address number number interrupt description interrupt description IRQ 40 EXTI line[15:10] interrupts EXTI line[15:10] interrupts 0x0000_00E0 RTC alarm from EXTI IRQ 41 RTC alarm from EXTI interrupt 0x0000_00E4 interrupt USBD wakeup from EXTI USBHS wakeup from EXTI IRQ 42 0x0000_00E8...
Page 192 GD32E51x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector address number number interrupt description interrupt description IRQ66 CAN1 EWMC interrupt CAN1 EWMC interrupt 0x0000_0148 IRQ67 reserved USBHS global interrupt 0x0000_014C IRQ68 reserved reserved 0x0000_0150 IRQ69 SHRTIMER_IRQ2 interrupt SHRTIMER_IRQ2 interrupt 0x0000_0154 IRQ70 SHRTIMER_IRQ3 interrupt...
Page 193: External Interrupt And Event (Exti) Block Diagram
GD32E51x User Manual External interrupt and event (EXTI) block diagram 7.4. Figure 7-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~21 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External Interrupt and event function overview 7.5.
Page 194: Hardware Trigger
GD32E51x User Manual Hardware trigger 7.5.1. Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in AFIO module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 195 GD32E51x User Manual EXTI Line Source Number RTC Alarm USB wakeup Ethernet wakeup I2C2 wakeup USART5 wakeup...
Page 196: Exti Register
GD32E51x User Manual EXTI Register 7.6. EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 197: Rising Edge Trigger Enable Register (Exti_Rten)
GD32E51x User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5...
Page 198: Pending Register (Exti_Pd)
GD32E51x User Manual This register has to be accessed by word(32-bit). Reserved SWIEV21 SWIEV20 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. Interrupt / Event software trigger x (x = 0…21) 21: 0 SWIEVx...
Page 199: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32E51x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 8.1. There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions.
Page 200: Gpio Pin Configuration
GD32E51x User Manual Table 8-1. GPIO configuration table Configuration mode CTL[1:0] SPDy: MD[1:0] OCTL don’t care Analog don’t care Input floating Input x 00 Input pull-down Input pull-up x 00: Reserved Push-pull 0 or 1 General purpose x 01: Speed up to 10MHz Output (GPIO) Open-drain 0 or 1...
Page 201: External Interrupt/Event Lines
GD32E51x User Manual PB4: NJTRST in PU mode. PB3: JTDO in Floating mode. The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen.
Page 202: Output Configuration
GD32E51x User Manual Figure 8-2. Basic structure of Input configuration Alternate Function Input protect I / O pin Input driver Input Read Status Register Output configuration 8.3.5. When GPIO pin is configured as output:  The schmitt trigger input is enabled. ...
Page 203: Alternate Function (Af) Configuration
GD32E51x User Manual  The port input status register of this I/O port bit is “0”. Figure 8-4. Basic structure of Analog configuration shows the analog configuration. Figure 8-4. Basic structure of Analog configuration protection Analog ( Input / Output ) I/O pin Alternate function (AF) configuration 8.3.7.
Page 204: Gpio Locking Function
GD32E51x User Manual GPIO Each IO pin can be used for GPIO input function by configuring MDy bits to 0b00 in GPIOx_CTL0 / GPIOx_CTL1 registers. And set output function by configuring MDy bits to 0b01, 0b10, or 0b11 and configuring CTLy bits of corresponding port in GPIOx_CTL0 / GPIOx_CTL1 register to 0b00 (for GPIO push-pull output) or 0b01 (for GPIO open-drain output).
Page 205: Main Features
GD32E51x User Manual peripheral IO remapping function. Additionally, various GPIO pins can be selected to be the EXTI interrupt line by setting the relevant EXTI Source Selection Register (AFIO_EXTISSx) to trigger an interrupt or event. Main features 8.4.2.  APB slave interface for register access. ...
Page 206: Adc Af Remapping
GD32E51x User Manual ADC AF remapping 8.4.4. Refer to AFIO Port Configuration Register 0 (AFIO_ PCF0). Table 8-4. ADC0/1 external trigger routine conversion AF remapping function Register ADC0 ADC1 ADC0 externa signal trigger ADC0_ETRGRT_REMAP routine conversion is connected to EXTI11 ADC0 external signal trigger ADC0_ETRGRT_REMAP routine conversion is connected...
Page 207: Table 8-6. Timer4 Alternate Function Remapping
GD32E51x User Manual TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 3，8，9，10， function 12，13) “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER1_CH0/T PA15 PA15 IMER1_ETI TIMER1_CH1 TIMER1_CH2 PB10 TIMER1_CH3 PB11 TIMER2_CH0 TIMER2_CH1 TIMER2_CH2 TIMER2_CH3 TIMER3_CH0 PD12 TIMER3_CH1 PD13 TIMER3_CH2...
Page 208: Usart Af Remapping
GD32E51x User Manual USART AF remapping 8.4.6. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-7. USART0/1/2 alternate function remapping Register USART0 USART1 USART2 PA9(USART0_TX) USART0_REMAP = 0 PA10(USART0_RX) PB6(USART0_TX) USART0_REMAP = 1 PB7(USART0_RX) PA0(USART1_CTS) PA1(USART1_RTS) USART1_REMAP = 0 PA2(USART1_TX) PA3(USART1_RX) PA4(USART1_CK)
Page 209: Spi0/Spi2/I2S Af Remapping
GD32E51x User Manual Table 8-8. I2C0 alternate function remapping Register I2C0_SCL I2C0_SDA I2C0_REMAP = 0 I2C0_REMAP = 1 SPI0/SPI2/I2S AF remapping 8.4.8. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-9. SPI0/SPI2/I2S alternate function remapping Register SPI0 SPI2/I2S PA4(SPI0_NSS) PA5(SPI0_SCK) SPI0_REMAP = 0 PA6(SPI0_MISO)
Page 210: Ethernet Af Remapping
GD32E51x User Manual Register CAN0 CAN1 PB6(CAN1_TX) CAN0_RX and CAN0_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single CAN interface. Ethernet AF remapping 8.4.10. Table 8-11. ENET alternate function remapping Register ENET PA7(RX_DV-CRS_DV) PC4(RXD0) ENET_REMAP = “0” PC5(RXD1) PB0(RXD2) PB1(RXD3)
Page 211: Table 8-13. Osc32 Pins Configuration
GD32E51x User Manual Table 8-13. OSC32 pins configuration Alternate function LXTAL= ON LXTAL= OFF PC14 OSC32_IN PC14 PC15 OSC32_OUT PC15 The HXTAL oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1. Table 8-14. OSC pins configuration Alternate function HXTAL= ON HXTAL = OFF OSC_IN OSC_OUT...
Page 212: Register Definition
GD32E51x User Manual Register definition 8.5. GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..G) 8.5.1.
Page 213 GD32E51x User Manual These bits are set and cleared by software refer to CTL0[1:0]description 21:20 MD5[1:0] Port 5 mode bits These bits are set and cleared by software refer to MD0[1:0]description 19:18 CTL4[1:0] Port 4 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD4[1:0]...
Page 214: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32E51x User Manual 01: GPIO output with open-drain 10: AFIO output with push-pull 11: AFIO output with open-drain MD0[1:0] Port 0 mode bits These bits are set and cleared by software 00: Input mode (reset state) 01: Output mode(10MHz) 10: Output mode(2MHz) 11: Output mode(50MHz) Port control register 1 (GPIOx_CTL1, x=A..G) 8.5.2.
Page 215: Port Input Status Register (Gpiox_Istat, X=A
GD32E51x User Manual refer to MD0[1:0]description 19:18 CTL12[1:0] Port 12 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD12[1:0] Port 12 mode bits These bits are set and cleared by software refer to MD0[1:0]description 15:14 CTL11[1:0] Port 11 configuration bits...
Page 216: Port Output Control Register (Gpiox_Octl, X=A
GD32E51x User Manual Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT 0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 ISTATy Port input status(y=0..15)
Page 217: Port Bit Clear Register (Gpiox_Bc, X=A
GD32E51x User Manual BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by software 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy...
Page 218: Port Bit Speed Register (Gpiox_ Spd, X=A
GD32E51x User Manual LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can always be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset..
Page 219: Event Control Register (Afio_Ec)
GD32E51x User Manual Event control register (AFIO_EC) 8.5.9. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PORT[2:0] PIN[3:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Event output enable ®...
Page 220 GD32E51x User Manual ADC1_ET ADC0_ET TIMER4C SPI2_RE CAN1_R Reserved Reserved SWJ_CFG[2:0] Reserved Reserved RGRT_R Reserved RGRT_R Reserved H3_IREM EMAP EMAP EMAP PD01_RE TIMER3_ TIMER2_REMAP[1:0 TIMER1_REMAP[1:0 TIMER0_REMAP[1:0 USART2_REMAP[1: USART1_ USART0_ I2C0_RE SPI0_RE CAN0_REMAP[1:0] REMAP REMAP REMAP Bits Fields Descriptions 31:29 Reserved Must be kept at reset value SPI2_REMAP SPI2/I2S2 remapping...
Page 221 GD32E51x User Manual 1: Connect the ADC0 external signal trigger routine conversion to TIM7_TRGO. Reserved Must be kept at reset value. TIMER4CH3_IREMA TIMER4 channel3 internal remapping This bit is set and reset by software. 0: ConnectTIMER4_CH3 to PA3. 1: Connect the IRC40K internal clock to TIMER4_CH3 input in order to calibration. PD01_REMAP Port D0/Port D1 mapping to OSC_IN/OSC_OUT This bit is set and cleared by software.
Page 222 GD32E51x User Manual TIMER0_REMAP TIMER0 remapping [1:0] These bits are set and reset by software 00: Disable the remapping function(TIMER0_ETI / PA12, TIMER0_CH0 / PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11, TIMER0_BKIN / PB12, TIMER0_CH0_ON / PB13, TIMER0_CH1_ON / PB14, TIMER0_CH2_ON / PB15) 01: Enable the remapping function partially(TIMER0_ETI / PA12, TIMER0_CH0 / PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11,...
Page 223 GD32E51x User Manual /PA6,SPI0_MOSI /PA7) 1: Enable the remapping function (SPI0_NSS/PA15, SPI0_SCK /PB3, SPI0_MISO /PB4,SPI0_MOSI /PB5) Memory map and bit definitions for connectivity devices: TIMER1I TIMER4C PTP_PPS SPI2_RE ENET_P CAN1_R ENET_R Reserved TI1_REM Reserved SWJ_CFG[2:0] Reserved H3_IREM _REMAP HY_SEL EMAP EMAP PD01_RE TIMER3_...
Page 224 GD32E51x User Manual 1: Select an RMII PHY CAN1_REMAP CAN1 I/O remapping 0: Disable the remapping function (CAN1_RX/PB12,CAN_TX/PB13) 1: Enable the remapping function (CAN1_RX/PB5,CAN_TX/PB6) ENET_REMAP Ethernet MAC I/O remapping 0: Disable the remapping function (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 1: Enable the remapping function (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) 20:17 Reserved...
Page 225 GD32E51x User Manual 10: Enable the remapping function partially 1 (TIMER1_CH0-TIMER1_ETI/PA0, TIMER1_CH1/PA1, TIMER1_CH2/PB10, TIMER1_CH3/PB11) 11: Enable the remapping function fully (TIMER1_CH0-TIMER1_ETI/PA15, TIMER1_CH1/PB3, TIMER1_CH2/PB10, TIMER1_CH3/PB11) TIMER0_REMAP[1:0 TIMER0 remapping 00: Disable the remapping function (TIMER0_ETI / PA12, TIMER0_CH0 / PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11, TIMER0_BKIN / PB12, TIMER0_CH0_ON / PB13, TIMER0_CH1_ON / PB14, TIMER0_CH2_ON / PB15) 01: Enable the remapping function partially (TIMER0_ETI / PA12, TIMER0_CH0 /...
Page 226: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32E51x User Manual /PB4, SPI0_MOSI /PB5) EXTI sources selection register 0 (AFIO_EXTISS0) 8.5.11. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI3_SS[3:0] EXTI2_SS[3:0] EXTI1_SS[3:0] EXTI0_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI3_SS [3:0] EXTI 3 sources selection...
Page 227: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32E51x User Manual 0110: PG1 pin Other configurations are reserved. EXTI0_SS [3:0] EXTI 0 sources selection 0000: PA0 pin 0001: PB0 pin 0010: PC0 pin 0011: PD0 pin 0100: PE0 pin 0101: PF0 pin 0110: PG0 pin Other configurations are reserved. EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.12.
Page 228: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32E51x User Manual 0101: PF6 pin 0110: PG6 pin Other configurations are reserved. EXTI5_SS [3:0] EXTI 5 sources selection 0000: PA5 pin 0001: PB5 pin 0010: PC5 pin 0011: PD5 pin 0100: PE5 pin 0101: PF5 pin 0110: PG5 pin Other configurations are reserved.
Page 229: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32E51x User Manual 0100: PE11 pin 0101: PF11 pin 0110: PG11 pin Other configurations are reserved. 11:8 EXTI10_SS [3:0] EXTI 10 sources selection 0000: PA10 pin 0001: PB10 pin 0010: PC10 pin 0011: PD10 pin 0100: PE10 pin 0101: PF10 pin 0110: PG10 pin Other configurations are reserved.
Page 230 GD32E51x User Manual EXTI15_SS[3:0] EXTI14_SS[3:0] EXTI13_SS[3:0] EXTI12_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI15_SS [3:0] EXTI 15 sources selection 0000: PA15 pin 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin Other configurations are reserved.
Page 231: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32E51x User Manual AFIO port configuration register 1 (AFIO_PCF1) 8.5.15. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXMC_N TIMER13 IMER12_ TIMER10 TIMER9_ TIMER8_ Reserved CTC_REMAP[1:0] Reserved _REMAP REMAP _REMAP REMAP REMAP Bits Fields...
Page 232: Io Compensation Control Register (Afio_Cpsctl)
GD32E51x User Manual 0: Disable the remapping function (PB9) 1: Enable the remapping function (PF7) TIMER9_REMAP TIMER9 remapping This bit is set and cleared by software, it controls the mapping of the TIMER9_CH0 alternate function onto the GPIO ports 0: Disable the remapping function (PB8) 1: Enable the remapping function (PF6) TIMER8_REMAP TIMER8 remapping...
Page 233: Afio Port Configuration Register A (Afio_Pcfa)
GD32E51x User Manual 1: I/O compensation cell is enable AFIO port configuration register A (AFIO_PCFA) 8.5.17. Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). PA15_AF PA10_AF PA9_AFC PA13_AF PA10_ AFCFG [1:0] PA9_ AFCFG[1:0] PA8_ AFCFG [1:0] Reserved PA12_AFCFG [2:0]...
Page 234 GD32E51x User Manual These bits are set and cleared by software. 00: Do not configure PA11 alternate function to enable SHRTIMER/USART5 01: Configure PA11 alternate function to USART5 10/11: Configure PA11 alternate function to SHRTIMER 21:20 PA10_AFCFG[1:0] PA10 AF function configuration bits Bit 29 of AFIO_PCFA and these bits are written by software to define the function configuration.
Page 235: Afio Port Configuration Register B (Afio_Pcfb)
GD32E51x User Manual This bit is set and cleared by software. 0: Do not configure PA5 alternate function to USBHS 1: Configure PA5 alternate function to USBHS Reserved Must be kept at reset value. PA3_AFCFG[1:0] PA3 AF function configuration bit These bits are set and cleared by software.
Page 236 GD32E51x User Manual 01: Configure PB15 alternate function to SHRTIMER 10: Configure PB15 alternate function to TIMER14_CH1 11: Configure PB15 alternate function to TIMER14_CH0_ON 29:28 PB14_AFCFG[1:0] PB14 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PB14 alternate function to SHRTIMER/I2S1/TIMER14 01: Configure PB14 alternate function to I2S1 10: Configure PB14 alternate function to SHRTIMER 11: Configure PB14 alternate function to TIMER14...
Page 237 GD32E51x User Manual These bits are set and cleared by software. 00: Do not configure PB8 alternate function to SHRTIMER/I2C2/TIMER15 01: Configure PB8 Alternate function to I2C2 10: Configure PB8 alternate function to SHRTIMER 11: Configure PB8 alternate function to TIMER15 15:14 PB7_AFCFG[1:0] PB7 AF function configuration bit...
Page 238: Afio Port Configuration Register C (Afio_Pcfc)
GD32E51x User Manual This bit is set and cleared by software. 0: Do not configure PB3 alternate function to SHRTIMER 1: Configure PB3 alternate function to SHRTIMER PB2_AFCFG[1:0] PB2 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PB2 alternate function to SHRTIMER/USBHS 10: Configure PB2 alternate function to USBHS 01/11: Configure PB2 alternate function to SHRTIMER...
Page 239 GD32E51x User Manual 1: Configure PC12 alternate function to SHRTIMER 23:22 PC11_AFCFG[1:0] PC11 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PC11 alternate to SHRTIMER/I2S2 01/11: Configure PC11 alternate function to SHRTIMER 10: Configure PC11 alternate function to I2S2 Reserved Must be kept at reset value...
Page 240: Afio Port Configuration Register D (Afio_Pcfd)
GD32E51x User Manual 0: Do not configure PC3 alternate function to USBHS 1: Configure PC3 alternate function to USBHS PC2_AFCFG[1:0] PC2 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PC2 alternate function to USBHS/I2S1 01/11: Configure PC2 alternate function to I2S1 10: Configure PC2 alternate function to USBHS Reserved...
Page 241: Afio Port Configuration Register E (Afio_Pcfe)
GD32E51x User Manual AFIO port configuration register E (AFIO_PCFE) 8.5.21. Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). PE13_AF PE12_AF PE11_AF PE10_AF PE9_AFC PE8_AFC Reserved Reserved Reserved Reserved Reserved Reserved Reserved PE1_AFCFG[1:0] PE0_AFCFG[1:0] Bits Fields...
Page 242: Afio Port Configuration Register G (Afio_Pcfg)
GD32E51x User Manual 1: Configure PE9 alternate function to CMP3 Reserved Must be kept at reset value PE8_AFCFG PE8 AF function configuration bit This bit is set and cleared by software. 0: Do not configure PE8 alternate function to CMP1 1: Configure PE8 alternate function to CMP1 15:4 Reserved...
Page 243 GD32E51x User Manual 1: Configure PG14 alternate function to USART5 Reserved Must be kept at reset value. PG13_AFCFG PG13 AF function configuration bit This bit is set and cleared by software. 0: Do not configure PG13 alternate function to SHRTIMER 1: Configure PG13 alternate function to SHRTIMER Reserved Must be kept at reset value.
Page 244 GD32E51x User Manual 1: Configure PG6 alternate function to SHRTIMER 11:0 Reserved Must be kept at reset value.
Page 245: Cyclic Redundancy Checks Management Unit (Crc)
GD32E51x User Manual Cyclic redundancy checks management unit (CRC) Overview 9.1. A cyclic redundancy check management (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial.
Page 246: Function Overview
GD32E51x User Manual Figure 9-1. Block diagram of CRC management unit Data Input Input Data Register (32 bit) CRC Management Unit configurable polynomial Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) Function overview 9.3.
Page 247 GD32E51x User Manual 1) byte reverse: 32-bit data is divided into 4 groups and reverse implement in group inside. Reversed data: 0x2C6AB3F7 2) half-word reverse: 32-bit data is divided into 2 groups and reverse implement in group inside. Reversed data: 0x6A2CF7B3 3) word reverse: 32-bit data is divided into 1 groups and reverse implement in group inside.
Page 248: Register Definition
GD32E51x User Manual Register definition 9.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 9.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 249: Control Register (Crc_Ctl)
GD32E51x User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control register (CRC_CTL) 9.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O REV_I[1:0] PS[1:0] Reserved...
Page 250: Polynomial Register (Crc_Poly)
GD32E51x User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. Polynomial register (CRC_POLY) 9.4.5.
Page 251: Trigonometric Math Unit (Tmu)
GD32E51x User Manual Trigonometric Math Unit (TMU) Overview 10.1. The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. The TMU calculation unit can be used to calculate total 9 kinds of operations. The operation data must meet IEEE 32-Bit Single Precision Floating-Point Format.
Page 252: Data Format
GD32E51x User Manual Figure 10-1. Block diagram of Trigonometric Math Unit pre_process signals Interface data0 result_data Arithmetic Post error_data AHB Bus Θ_i Θ_o data1 Process Core Process Data and Control registers ctrl signals Data format 10.3.2. The operation data and calculation result data format is given in Table 10-2.
Page 253: Mode 0 Description
GD32E51x User Manual returned. If a TMU operation generates an overflow condition, then the latched overflow flag (OVRF) is set to 1. The OVRF flag will remain latched until the next new operation is started. Rounding: There are various rounding formats supported by the IEEE standard. Rounding has no meaning for TMU operations (rounding is inherent in the implementation).
Page 254: Mode 2 Description
GD32E51x User Manual Mode 2 description 10.3.5. This operation is equivalent as R0 = √ x. x is the input operation data, R0 is the calculation result. This mode only has OVRF flag and UDRF =0. The OVRF condition is as below: /* Check if input is negative */ If( x <...
Page 255: Mode 4 Description
GD32E51x User Manual This mode has no neither UDRF nor OVRF. If the result is too small, the result will return 0. Mode 4 description 10.3.7. This mode performs the following equivalent operation: 1. Make PerUnit equal to the fraction of x, PerUnit = fraction(x). 2.
Page 256 GD32E51x User Manual The algorithm for this mode is as follows: if ( ( fabs(Y) == 0.0 ) & ( fabs(X) == 0.0 ) ) { R1( Quadrant ) = 0.0; R0( Ratio ) = 0.0; }else if ( fabs(Y) < = fabs(X) ) { R0( Ratio ) = Y / X;...
Page 257: Mode 7 Description
GD32E51x User Manual Figure 10-2. Calculation of R1 (Quadrant) and R0 (Ratio) Based on Y and X Values If( (|Y| > |X|) & (Y >= 0) ) { Quadrant = 0.25; Ratio = -X/Y; } 0.125 (PU) = π/4 0.375 (PU) = 3*π/4 0.25 (PU) = π/2 If( (|Y| <= |X|) &...
Page 258: Mode 8 Description
GD32E51x User Manual Mode 8 description 10.3.11. This operation is equivalent as R0 = √x . x and y is the input operation data, R0 is the calculation result. This mode only has OVRF flag and UDRF =0. The OVRF condition is as below: If R0 result is too big for floating-point number (E >...
Page 259: Figure 10-3. Tmu Program Guidline
GD32E51x User Manual Figure 10-3. TMU program guidline Write TMU_IDATA0 Mode==6 or Mode == 7 or Mode ==8 Write TMU_IDATA1 Configure mode and interrupt enable Write 1 into TMUEN bit Interrupt enabled? Polling and Wait Step into interrupt TMUEN==0 routine Read TMU_DATA0 Mode == 6 Read TMU_DATA1...
Page 260: Tmu Register
GD32E51x User Manual TMU register 10.5. TMU base address: 0x4008 0000 Input data0 register (TMU_IDATA0) 10.5.1. Address offset: 0x00 Reset value: 0x3F80 0000 This register has to be accessed by word (32-bit). IDATA0[31:16] IDATA0[15:0] Bits Fields Descriptions 31:0 IDATA0[31:0] The value of input data Mode0~5: IDATA0 is the only operation data Mode6: IDATA0 is the X value Mode7: IDATA0 is the dividend...
Page 261: Control Register (Tmu_Ctl)
GD32E51x User Manual mode8: IDATA1 is the X value or Y value IDATA1 must meet IEEE 32-Bit Single Precision Floating-Point Format. Control register (TMU_CTL) 10.5.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CFIF...
Page 262: Data0 Register (Tmu_Data0)
GD32E51x User Manual Data0 register (TMU_DATA0) 10.5.4. Address offset: 0x0C Reset value: 0x3400 0000 This register has to be accessed by word (32-bit). DATA0[31:16] DATA0[15:0] Bits Fields Descriptions 31:0 DATA0[31:0] The result of calculation Mode 0~5,7,8: TMU_DATA0 is the only result value Mode6: TMU_DATA0=Ratio of X and Y TMU_DATA0 must meet IEEE 32-Bit Single Precision Floating-Point Format.
Page 263 GD32E51x User Manual Reserved Reserve UDRF OVRF Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. UDRF The flag of underflow 0: No underflow 1: Underflow This bit is set and cleared by hardware. when the next TMU calculation is started, this bit is cleared by hardware.
Page 264: Direct Memory Access Controller (Dma)
GD32E51x User Manual Direct memory access controller (DMA) Overview 11.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 265: Block Diagram
GD32E51x User Manual Block diagram 11.3. Figure 11-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 266: Table 11-1. Dma Transfer Operation
GD32E51x User Manual Table 11-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 267: Peripheral Handshake
GD32E51x User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 268: Address Generation
GD32E51x User Manual  Software priority: Four levels, including low, medium, high and ultra high by configuring the PRIO bits in the DMA_CHxCTL register.  For channels with equal software priority level, priority is given to the channel with lower channel number.
Page 269: Interrupt
GD32E51x User Manual Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register. Configure the DMA_CHxPADDR register for setting the peripheral base address.
Page 270: Figure 11-4. Dma0 Request Mapping
GD32E51x User Manual mapping Figure 11-5. DMA1 request mapping. The request of each peripheral can be independently enabled or disabled by programming the registers of the corresponding peripheral. The user has to ensure that only one request is enabled at a time on one channel. Table 11-3.
Page 271 GD32E51x User Manual Hardware priority ADC0 high TIMER1_CH2 TIMER3_CH0 Channel 0 TIMER16_CH0 TIMER16_UP SPI0_RX USART2_TX TIMER0_CH0 TIMER1_UP Channel 1 TIMER2_CH2 SHRTIMER_M SPI0_TX USART2_RX TIMER0_CH1 TIMER2_CH3 TIMER2_UP Channel 2 SHRTIMER_0 TIMER15_CH0 TIMER15_UP SPI1/I2S1_RX USART0_TX I2C1_TX I2C2_TX Channel 3 TIMER0_CH3 TIMER0_TG TIMER0_CMT TIMER3_CH1 SHRTIMER_1 SPI1/I2S1_TX...
Page 272 GD32E51x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER1_CH3 TIMER2_CH3 TIMER2_CH0 ● ● ● ● TIMER2 TIMER2_CH2 TIMER2_UP TIMER2_TG ● ● ● TIMER3 TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_UP ● ● ● ●...
Page 273: Figure 11-5. Dma1 Request Mapping
GD32E51x User Manual Figure 11-5. DMA1 request mapping Hardware priority SPI2/I2S2_RX TIMER4_CH3 TIMER4_TG high Channel 0 TIMER7_CH2 TIMER7_UP SPI2/I2S2_TX TIMER4_CH2 TIMER4_UP TIMER7_CH3 Channel 1 TIMER7_TG TIMER7_CMT I2S2ADD_RX UART3_RX USART5_RX TIMER5_UP Channel 2 DAC0_ OUT0 TIMER7_CH0 I2S2ADD_TX SDIO TIMER4_CH1 Channel 3 TIMER6_UP DAC0_OUT1 ADC2...
Page 274: Register Definition
GD32E51x User Manual Register definition 11.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 11.5.1.
Page 275: Interrupt Flag Clear Register (Dma_Intc)
GD32E51x User Manual Interrupt flag clear register (DMA_INTC) 11.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2...
Page 276 GD32E51x User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 277: Channel X Counter Register (Dma_Chxcnt)
GD32E51x User Manual CMEN Circular mode enable Software set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’.
Page 278: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer.
Page 279 GD32E51x User Manual MADDR[15:0] Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 280: Debug (Dbg)
GD32E51x User Manual Debug (DBG) Introduction 12.1. The GD32E51x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSightTM module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm ®...
Page 281: Jtag Daisy Chained Structure
GD32E51x User Manual The pin assignment are: PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions (NJTRST tied to 1 by hardware).
Page 282: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32E51x User Manual can debug in deep-sleep mode. When SLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN 12.3.2.
Page 283: Dbg Registers
GD32E51x User Manual DBG registers 12.4. DEBUG base address: 0xE0044000 ID code register (DBG_ID) 12.4.1. Address offset: 0x00 Read only This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software.
Page 284 GD32E51x User Manual 1: Hold the TIMER10 counter for debug when core halted. TIMER9_HOLD TIMER9 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER9 counter for debug when core halted. TIMER8_HOLD TIMER8 hold bit This bit is set and reset by software.
Page 285 GD32E51x User Manual 0: no effect 1: Hold the TIMER6 counter for debug when core halted. TIMER5_HOLD TIMER5 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER5 counter for debug when core halted. TIMER4_HOLD TIMER4 hold bit This bit is set and reset by software.
Page 286 GD32E51x User Manual This bit is set and reset by software. 0: no effect 1: Hold the TIMER0 counter for debug when core halted. WWDGT_HOLD WWDGT hold bit This bit is set and reset by software. 0: no effect 1: Hold the WWDGT counter clock for debug when core halted. FWDGT_HOLD FWDGT hold bit This bit is set and reset by software.
Page 287: Analog-To-Digital Converter (Adc)
GD32E51x User Manual Analog-to-digital converter (ADC) Introduction 13.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment(LSB) or the most significant bit alignment(MSB).
Page 288: Pins And Internal Signals
GD32E51x User Manual  Module supply requirements: the typical power supply voltage is 3.3V: – 1.62V to 2.4V, with ADC maximum frequency is 14MHz. – 2.4V to 3.6V, with ADC maximum frequency is 35MHz.  ≤V ≤V Channel input range: V REF- REF+.
Page 289: Functional Overview
GD32E51x User Manual Functional overview 13.4. Figure 13-1. ADC module block diagram (for ADC0 and ADC1) watchdog event 0/1/2 SHRTIMER Analog watchdog watchdog 0/1/2 Trig select event 0/1/2 Interrupt Routine channels Channel Management ADC_IN0 ADC_IN1 GPIO Over Routine data registers ADC_IN15 SAR ADC （16 bits）...
Page 290: Foreground Calibration Function
GD32E51x User Manual Figure 13-2. ADC module block diagram (for ADC2) Trig select Routine channels Interrupt Interrupt Channel Management generator watchdog Analog event watchdog 0/1/2 0/1/2 ADC_IN0 ADC_IN8 GPIO ADC_IN10 Routine data registers Over SAR ADC ADC_IN13 （16 bits） sampler SENSE REFINT TOVS...
Page 291: Adc Clock
GD32E51x User Manual Delay 14 CK_ADC to wait for ADC stability. Set CALNUM. Set RSTCLB (optional). Set CLB=1. Wait until CLB=0. ADC clock 13.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller.
Page 292: Routine Sequence
GD32E51x User Manual Routine sequence 13.4.5. The channel management circuit can organize the sampling conversion channels into a sequence: routine sequence. The routine sequence supports up to 16 channels, and each channel is called routine channel. The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length. The ADC_RSQ0~ADC_RSQ2 registers specify the selected channels of the routine sequence.
Page 293: Figure 13-4. Continuous Operation Mode
GD32E51x User Manual the corresponding software trigger or external trigger is active. The conversion data will be stored in the ADC_RDATA register. Figure 13-4. Continuous operation mode Sample Routine trigger Convert Software procedure for continuous conversion on a routine channel: Set the CTN bit in the ADC_CTL1 register.
Page 294: Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable
GD32E51x User Manual Figure 13-5. Scan operation mode, continuous operation mode disable Software procedure for scan conversion on a routine sequence: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure ADC_RSQx and ADC_SAMPTx registers. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 295: Conversion Result Threshold Monitor
GD32E51x User Manual Software procedure for discontinuous conversion on a routine sequence: Set the DISRC bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure DISNUM[2:0] bits in the ADC_CTL0 register. Configure ADC_RSQx and ADC_SAMPTx registers. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 296: Sample Time Configuration
GD32E51x User Manual Figure 13-8. 12-bit data storage mode 6-bit resolution data alignment is different from 12-bit/10-bit/8-bit resolution data alignment, shown as Figure 13-9. 6-bit data storage mode Figure 13-9. 6-bit data storage mode Routine sequence data DAL=0 Routine sequence data DAL=1 Sample time configuration 13.4.9.
Page 297: Dma Request
GD32E51x User Manual ETSRC[3:0] Trigger Source Trigger Type 0111 Software trigger SWRCST 1000 SHRTIMER_ADCTRIG0 Hardware trigger 1001 SHRTIMER_ADCTRIG2 1010~1111 reserved Table 13-4. External trigger source for ADC2 ETSRC[3:0] Trigger Source Trigger Type 0000 TIMER2_CH0 0001 TIMER1_CH2 0010 TIMER0_CH2 0011 TIMER7_CH0 Hardware trigger 0100 TIMER7_TRGO...
Page 298: Programmable Resolution (Dres)
GD32E51x User Manual Configure the conversion sequence (ADC_IN16) and the sampling time(ts_temp µs) for the channel. Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by external trigger. Read the temperature data(V ) in the ADC data register, and get the temperature temperature...
Page 299: Figure 13-10. 20-Bit To 16-Bit Result Truncation
GD32E51x User Manual bit right shifting up to 8-bit. It is configured through the OVSS[3:0] bits in the ADC_OVSAMPCTL register. Summation units can produce up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the data register.
Page 300: Adc Sync Mode
GD32E51x User Manual indicates truncation) 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Oversa shift shift shift shift shift shift shift shift shift mpling OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= ratio data 0000 0001 0010 0011 0100 0101 0110 0111...
Page 301: Free Mode
GD32E51x User Manual Figure 13-12. ADC sync block diagram Routine Routine data registers （16 bits ） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO Routine Routine data registers ADC_IN15 （16 bits ） channels SENSE Syncl mode control EXTI_11 Routine trigger mux ADC0 (master) Free mode 13.5.1.
Page 302: Routine Follow-Up Fast Mode
GD32E51x User Manual sampling time. Figure 13-13. Routine parallel mode on 10 channels Routine follow-up fast mode 13.5.3. The follow-up fast mode is applicable to sample the same channel of two ADCs. The source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register).
Page 303: Adc Interrupts
GD32E51x User Manual source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register). When the trigger occurs, ADC1 runs immediately, ADC0 runs after 14 ADC clock cycles, after the second 14 ADC clock cycles the ADC1 runs again. Continuous operation mode can’t be used in this mode, because it continuously converts the routine channel.
Page 304: Adc Registers
GD32E51x User Manual ADC registers 13.7. ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 3C00 Status register (ADC_STAT) 13.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). WDE2 WDE1 Reserved...
Page 305: Control Register 0 (Adc_Ctl0)
GD32E51x User Manual Set by hardware at the end of a routine sequence conversion. Cleared by software writing 0 to it or by reading the ADC_RDATA register. WDE0 Analog watchdog 0 event flag 0: Analog watchdog 0 event is not happened 1: Analog watchdog 0 event is happening Set by hardware when the converted voltage crosses the values programmed in the ADC_WDLT0 and ADC_WDHT0 registers.
Page 306 GD32E51x User Manual any configuration change. 15:13 DISNUM[2:0] Number of conversions in discontinuous mode The number of channels to be converted after a trigger will be DISNUM+1 in routine sequence. Reserved Must be kept at reset value. DISRC Discontinuous mode on routine channels 0: Discontinuous operation mode on routine channels disable 1: Discontinuous operation mode on routine channels enable Reserved...
Page 307: Control Register 1 (Adc_Ctl1)
GD32E51x User Manual 10000: ADC channel16 10001: ADC channel17 Other values are reserved. Note: ADC0 analog inputs Channel16 and Channel17 are internally connected to the temperature sensor, and to V inputs. ADC1 analog inputs Channel16, and REFINT Channel17 are internally connected to V .
Page 308 GD32E51x User Manual 0100: TIMER2_TRGO 0101: TIMER3_CH3 0110: EXTI Line11/ TIMER7_TRGO 0111: SWRCST 1000: SHRTIMER_ADCTRG0 1001: SHRTIMER_ADCTRG2 Others: Reserved For ADC2: 0000: TIMER2_CH0 0001: TIMER1_CH2 0010: TIMER0_CH2 0011: TIMER7_CH0 0100: TIMER7_TRGO 0101: TIMER4_CH0 0110: TIMER4_CH2 0111: SWRCST 1xxx: Reserved 16:12 Reserved Must be kept at reset value.
Page 309: Sample Time Register 0 (Adc_Sampt0)
GD32E51x User Manual ADC calibration 0: Calibration done 1: Calibration start Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC will be wake up when this bit is changed from low to high and take a stabilization time.
Page 310: Sample Time Register 1 (Adc_Sampt1)
GD32E51x User Manual 100: Channel sampling time is 41.5 cycles 101: Channel sampling time is 55.5 cycles 110: Channel sampling time is 71.5 cycles 111: Channel sampling time is 239.5 cycles Sample time register 1 (ADC_SAMPT1) 13.7.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 311: Watchdog High Threshold Register 0 (Adc_Wdht0)
GD32E51x User Manual Watchdog high threshold register 0 (ADC_WDHT0) 13.7.6. Address offset: 0x24 Reset value: 0x0000 0FFF This register has to be accessed by word(32-bit). Reserved Reserved WDHT0[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 WDHT0[11:0] High threshold for analog watchdog 0 These bits define the high threshold for the analog watchdog 0.
Page 312: Routine Sequence Register 1 (Adc_Rsq1)
GD32E51x User Manual Reserved RL[3:0] RSQ15[4:1] RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 RL[3:0] Routine sequence length. The total number of conversion in routine sequence equals to RL[3:0]+1. 19:15 RSQ15[4:0] refer to RSQ0[4:0] description 14:10 RSQ14[4:0] refer to RSQ0[4:0] description...
Page 313: Routine Sequence Register 2 (Adc_Rsq2)
GD32E51x User Manual Routine sequence register 2 (ADC_RSQ2) 13.7.10. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RSQ5[4:0] RSQ4[4:0] RSQ3[4:1] RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ5[4:0] refer to RSQ0[4:0] description...
Page 314: Oversample Control Register (Adc_Ovsampctl)
GD32E51x User Manual These bits contain the conversion result from routine channel, which is read only. Oversample control register (ADC_OVSAMPCTL) 13.7.12. Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved DRES[1:0] Reserved TOVS OVSS[3:0] OVSR[2:0]...
Page 315: Watchdog 1 Channel Selection Register (Adc_Wd1Sr)
GD32E51x User Manual Note: The software allows this bit to be written only when ADCON=0 (this ensures that no conversion is in progress). OVSR[2:0] Oversampling ratio This bit filed defines the number of oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x...
Page 316: Watchdog 2 Channel Selection Register (Adc_Wd2Sr)
GD32E51x User Manual AWD1CS[n] = 1: ADC analog input channel n is monitored by analog watchdog 1 When AWD1CH[17:0] = 000..0, the analog watchdog 1 is disabled. Note: The channels selected by AWD1CS must be also selected into the ADC_RSQn or ADC_ISQ registers.
Page 317: Watchdog Threshold Register 2 (Adc_Wdt2)
GD32E51x User Manual Reserved WDLT1[7:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:16 WDHT1[7:0] High threshold for analog watchdog 1 These bits define the high threshold for the analog watchdog 1. Note: Software is allowed to write these bits only when the ADC is disabled (ADCON =0).
Page 318: Differential Mode Control Register (Adc_Difctl)
GD32E51x User Manual (ADCON =0). Differential mode control register (ADC_DIFCTL) 13.7.17. Address offset: 0xB0 Reset value: 0x00000000 This register has to be accessed by word(32-bit). Reserved DIFCTL[17:16] DIFCTL DIFCTL[14:0] [15] Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. 17:15 DIFCTL[17:15] Differential mode for channel 17..15.
Page 319: Digital-To-Analog Converter (Dac)
GD32E51x User Manual Digital-to-analog converter (DAC) Overview 14.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 320: Table 14-1. Dac I/O Description
GD32E51x User Manual Figure 14-1. DAC block diagram DAC control register DBOFFx EXTI_9 TIMERx_ TRGO SHRTIMER_ DACTRIGx SWTRx DAC_ENx OUTx_DH buff Control logic Wave FIFO OUTx_DO (optional) 12-bit 12-bit 12-bit 12-bit Table 14-1. DAC I/O description Name Description Signal type Analog power supply Input, analog supply Ground for analog power supply...
Page 321: Function Overview
GD32E51x User Manual DAC0 DAC1 SHRTIMER_DACTRIG0 DAC trigger signals SHRTIMER_DACTRIG1 from SHRTIMER SHRTIMER_DACTRIG2 Note: The GPIO pins should be configured to analog mode before enable the DAC module. Function overview 14.3. DAC enable 14.3.1. The DAC can be turned on by setting the DENx bit in the DAC_CTL0 register. A t time WAKEUP is needed to startup the analog DAC submodule.
Page 322: Dac Conversion
GD32E51x User Manual DTSELx[3:0] Trigger Source Trigger Type 4b’0011 TIMER4_TRGO 4b’0100 TIMER1_TRGO 4b’0101 TIMER3_TRGO 4b’0110 EXTI_9 4b’0111 SWTR Software trigger 4b’1000 SHRTIMER_DACTRIG0 4b’1001 SHRTIMER_DACTRIG1 Hardware trigger 4b’1010 SHRTIMER_DACTRIG2 4b’1011 TIMER14_TRGO 4b’1100~1111 Reserved Reserved The TIMERx_TRGO signals are generated from the timers, the SHRTIMER_DACTRIGx signals are generated from the SHRTIMER, while the software trigger can be generated by setting the SWTRx bits in the DAC_SWT register.
Page 323: Dac Output Voltage
GD32E51x User Manual Figure 14-2. DAC LFSR algorithm Triangle noise mode: a triangle signal is added to the OUTx_DH value, and then the result is stored into the DAC_OUTx_DO register. The minimum value of the triangle signal is 0, while the maximum value of the triangle signal is (2 <<...
Page 324: Dac Concurrent Conversion
GD32E51x User Manual If the second external trigger arrives before confirming the previous request, the new request will not be serviced, and an underrun error event occurs. The DDUDRx bit in the DAC_STAT0 register is set, an interrupt will be generated if the DDUDRIEx bit in the DAC_CTL0 register is set.
Page 325: Dacx Control Register 0 (Dac_Ctl0)
GD32E51x User Manual DACx control register 0 (DAC_CTL0) 14.4.1. Address offset: 0x00 Reset value: 0x0000 0000 The bits-field [31:16] of this register is only available in DAC0, and must be kept at reset value in DAC1. This register has to be accessed by word (32-bit). DTSEL1 DDUDR DDMA...
Page 326 GD32E51x User Manual 0111: The bit width of the wave signal is 8 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 23:22 DWM1[1:0]...
Page 327 GD32E51x User Manual DACx_OUT0 output buffer turns off (DBOFF0=1). Otherwise DACx_OUT0 is connected to the external pin and on chip peripherals (CMP). DTSEL0[3] DACx_OUT0 trigger selection bit 3, refer to DTSEL0[2:0] DDUDRIE0 DACx_OUT0 DMA underrun interrupt enable 0: DACx_OUT0 DMA underrun interrupt disabled 1: DACx_OUT0 DMA underrun interrupt enabled DDMAEN0 DACx_OUT0 DMA enable...
Page 328: Dacx Software Trigger Register (Dac_Swt)
GD32E51x User Manual 0110: EXTI line 9 0111: Software trigger 1000: SHRTIMER_DACTRIG0 1001: SHRTIMER_DACTRIG1 1010: SHRTIMER_DACTRIG2 1011: TIMER14 TRGO 1100~1111: Reserved. DTEN0 DACx_OUT0 trigger enable 0: DACx_OUT0 trigger disabled 1: DACx_OUT0 trigger enabled DBOFF0 DACx_OUT0 output buffer turn off 0: DACx_OUT0 output buffer turns on to reduce the output impedance and improve the driving capability 1: DACx_OUT0 output buffer turns off DEN0...
Page 329: Dacx_Out0 12-Bit Right-Aligned Data Holding Register (Dac_Out0_R12Dh)
GD32E51x User Manual DACx_OUT0 12-bit right-aligned data holding register 14.4.3. (DAC_OUT0_R12DH) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT0_DH[11:0] DACx_OUT0 12-bit right-aligned data.
Page 330: Dacx_Out0 8-Bit Right-Aligned Data Holding Register (Dac_Out0_R8Dh)
GD32E51x User Manual DACx_OUT0 8-bit right-aligned data holding register (DAC_OUT0_R8DH) 14.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. OUT0_DH[7:0] DACx_OUT0 8-bit right-aligned data.
Page 331: Dacx_Out1 12-Bit Left-Aligned Data Holding Register (Dac_Out1_L12Dh)
GD32E51x User Manual DACx_OUT1 12-bit left-aligned data holding register 14.4.7. (DAC_OUT1_L12DH) Address offset: 0x18 Reset value: 0x0000 0000 This register is only available in DAC0. This register has to be accessed by word(32-bit). Reserved OUT1_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 332: Dacx Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32E51x User Manual DACx concurrent mode 12-bit right-aligned data holding register 14.4.9. (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register is only available in DAC0. This register has to be accessed by word(32-bit). Reserved OUT1_DH[11:0] Reserved OUT0_DH[11:0] Bits Fields Descriptions 31:28...
Page 333: Dacx Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32E51x User Manual These bits specify the data that is to be converted by DACx_OUT1. 19:16 Reserved Must be kept at reset value. 15:4 OUT0_DH[11:0] DACx_OUT0 12-bit left-aligned data These bits specify the data that is to be converted by DACx_OUT0. Reserved Must be kept at reset value.
Page 334: Dacx_Out1 Data Output Register (Dac_Out1_Do)
GD32E51x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT0_DO [11:0] DACx_OUT0 12-bit output data These bits, which are read only, storage the data that is being converted by DACx_OUT0. DACx_OUT1 data output register (DAC_OUT1_DO) 14.4.13.
Page 335: Dacx Control Register 1 (Dac_Ctl1)
GD32E51x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DDUDR1 DACx_OUT1 DMA underrun flag. This bit is set by hardware and cleared by software (by writing it to 1). 0: No underrun occurred. 1: Underrun occurred (Speed of DAC trigger is higher than the DMA transfer). 28:14 Reserved Must be kept at reset value.
Page 336: Dacx Status Register 1 (Dac_Stat1)
GD32E51x User Manual set. 0: DACx_OUT1 data FIFO disable. 1: DACx_OUT1 data FIFO enable. 15:3 Reserved Must be kept at reset value. FIFOUDRIE0 DACx_OUT0 FIFO underflow interrupt enable. 0: DACx_OUT0 FIFO underflow interrupt disabled. 1: DACx_OUT0 FIFO underflow interrupt enabled. FIFOOVRIE0 DACx_OUT0 FIFO overflow interrupt enable.
Page 337 GD32E51x User Manual 101~111: Reserved FIFOUDR1 DACx_OUT1 FIFO underflow flag 0: DACx_OUT1 FIFO is not underflow. 1: DACx_OUT1 FIFO is underflow. FIFOOVR1 DACx_OUT1 FIFO overflow flag 0: DACx_OUT1 FIFO is not overflow. 1: DACx_OUT1 FIFO is overflow. FIFOE1 DACx_OUT1 FIFO empty flag 0: DACx_OUT1 FIFO is not empty.
Page 338: Comparator (Cmp)
GD32E51x User Manual Comparator (CMP) Overview 15.1. The general purpose comparator CMP, can work either standalone (all terminal are available on I/Os) or together with the timers. It can be used to provide a trigger source when an analog signal is in a certain condition. Characteristics 15.2.
Page 339: Cmp Clock
GD32E51x User Manual Figure 15-1. CMP block diagram 0111 CMP1BLK[2:0] 1000 1001 0100 0101 0110 Polarity Selection 0000 CMP1PL 0001 0010 0011 CMP1MSEL[2:0] 0110 CMP3BLK[2:0] 1000 1001 0100 0101 0111 Polarity Selection CMP3PL 0000 0001 0010 0011 CMP3MSEL[2:0] 0110 CMP5BLK[2:0] 1000 1001 0100...
Page 340: Cmp Register Write Protection
GD32E51x User Manual corresponding alternate I / Os. The CMP output can be redirected internally and externally simultaneously. CMP output internally connect to the TIMER and the connections between them are as follows:  CMP output to the TIMER input channel. ...
Page 341: Cmp Output Blanking
GD32E51x User Manual CMPxLK bit to 1. The CMPx_CS register, including the CMPxLK bit will be read-only, and can only be reset by the MCU reset. CMP output blanking 15.3.4. CMP output blanking function can be used to avoid interference of short pulses in the input signal to CMP output signal.
Page 342: Register Definition
GD32E51x User Manual 15.4. Register definition CMP base address：0x4001 7C00 CMP1 Control / status register (CMP1_CS) 15.4.1. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1MS CMP1LK CMP1O Reserved Reserved CMP1BLK[2:0] Reserved EL[3] CMP1PL Reserved CMP1OSEL[3:0]...
Page 343 GD32E51x User Manual CMP1PL Polarity of CMP1 output This bit is used to select the polarity of CMP1 output. 0: Output is not inverted 1: Output is inverted Reserved Must be kept at reset value 13:10 CMP1OSEL[3:0] CMP1 output selection These bits are used to select the destination of the CMP1 output.
Page 344: Cmp3 Control / Status Register (Cmp3_Cs)
GD32E51x User Manual CMP3 Control / status register (CMP3_CS) 15.4.2. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP3MS CMP3LK CMP3O Reserved Reserved CMP3BLK[2:0] Reserved EL[3] CMP3PL Reserved CMP3OSEL[3:0] Reserved CMP3MSEL[2:0] Reserved CMP3EN Bits Fields...
Page 345: Cmp5 Control / Status Register (Cmp5_Cs)
GD32E51x User Manual 13:10 CMP3OSEL[3:0] CMP3 output selection These bits are used to select the destination of the CMP3 output. 0000: no selection 0001: TIMER0 break input 0010~0101: Reserved 0110: TIMER2 CH2 input capture 0111: Reserved 1000: TIMER14 channel1 input capture 1001~1111: Reserved Note: It is recommended to enable CMP first, and then configure the timer channel, when using TIMER to capture the output signal of the comparator.
Page 346 GD32E51x User Manual CMP5PL Reserved CMP5OSEL[3:0] Reserved CMP5MSEL[2:0] Reserved CMP5EN Bits Fields Descriptions CMP5LK CMP5 lock This bit allows to have all control bits of CMP5 as read-only. It can only be set once by software and cleared by a system reset. 0: CMP5_CS bits are read-write 1: CMP5_CS bits are read-only CMP5O...
Page 347 GD32E51x User Manual Note: It is recommended to enable CMP first, and then configure the timer channel, when using TIMER to capture the output signal of the comparator. Reserved Must be kept at reset value CMP5MSEL[2:0] CMP5_IM input selection These bits, together with bit 22, are used to select the source connected to the CMP5_IM input of the CMP5.
Page 348: Watchdog Timer (Wdgt)
GD32E51x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 349: Figure 16-1. Free Watchdog Block Diagram
GD32E51x User Manual Figure 16-1. Free watchdog block diagram Status: PUD 12-Bit Reset IRC40K Prescaler DownCounter /4/8 256 Reload Control register Reload Status: RUD register The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value (0x000), there will be a reset.
Page 350 GD32E51x User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 64 0.025 6552.025 1 / 128 0.025 13104.025 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: When after the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 351: Register Definition
GD32E51x User Manual Register definition 16.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 352 GD32E51x User Manual 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 353 GD32E51x User Manual This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
Page 354: Window Watchdog Timer (Wwdgt)
GD32E51x User Manual Window watchdog timer (WWDGT) 16.2. Overview 16.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 355: Figure 16-3. Window Watchdog Timing Diagram
GD32E51x User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set).
Page 356: Table 16-2. Min/Max Timeout Value At 100 Mhz (F Pclk1 )
GD32E51x User Manual Table 16-2. Min/max timeout value at 100 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0]=0x40 CNT[6:0]=0x7F 40.96 μs 1 / 1 2.62 ms 81.92 μs 1 / 2 5.24 ms 163.84 μs 1 / 4 10.49 ms 327.68 μs...
Page 357: Register Definition
GD32E51x User Manual Register definition 16.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 358 GD32E51x User Manual reaches 0x40. It can be cleared by a hardware reset or software reset by setting the WWDGTRST bit of the RCU module. A write operation of ‘0’ has no effect. PSC[1:0] Prescaler. The time base of the watchdog timer counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4...
Page 359: Real-Time Clock (Rtc)
GD32E51x User Manual Real-time clock (RTC) Overview 17.1. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register.
Page 360: Rtc Reset
GD32E51x User Manual (stored in the RTC_ALRMH/L register). Figure 17-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK LXTAL RTC_DIV RTC_CNT OVIF NVIC OVIE interrupt IRC40K RTC_Alarm Reload controler COMPARE ALRMIF RTC_PSC ALRMIE...
Page 361: Rtc Flag Assertion
GD32E51x User Manual registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete.
Page 362: Figure 17-3. Rtc Second And Overflow Waveform Example (Rtc_Psc= 3)
GD32E51x User Manual Figure 17-3. RTC second and overflow waveform example (RTC_PSC= 3)
Page 363: Rtc Register
GD32E51x User Manual RTC Register 17.4. RTC base address: 0x4000 2800 RTC interrupt enable register (RTC_INTEN) 17.4.1. Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions 31:3...
Page 364: Rtc Prescaler High Register (Rtc_Psch)
GD32E51x User Manual 31:6 Reserved Must be kept at reset value. LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode. 1: Enter configuration mode.
Page 365: Rtc Prescaler Low Register (Rtc_Pscl)
GD32E51x User Manual PSC[19:16] RTC prescaler value high RTC prescaler low register (RTC_PSCL) 17.4.4. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] RTC prescaler value low...
Page 366: Rtc Counter High Register (Rtc_Cnth)
GD32E51x User Manual DIV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated. RTC counter high register (RTC_CNTH) 17.4.7.
Page 367: Rtc Alarm High Register (Rtc_Alrmh)
GD32E51x User Manual 15:0 CNT[15:0] RTC counter value low RTC alarm high register (RTC_ALRMH) 17.4.9. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 ALRM[31:16] RTC alarm value high...
Page 368: Timer (Timerx)
GD32E51x User Manual Timer (TIMERx) Table 18-1. Timers (TIMERx) are divided into seven sorts TIMER8/ TIMER9/10 TIMER15/1 TIMER TIMER0/7 TIMER1~4 TIMER14 TIMER5/6 /12/13 General- TYPE Advanced General-L0 General-L2 General-L3 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit bit(TIMER1 Counter 16-bit 16-bit...
Page 369: Advanced Timer (Timerx, X=0, 7)
GD32E51x User Manual ITI1: ITI2: ITI3: TIMER3 ITI0: TIMER0_TRGO TIMER1_TRGO TIMER2_TRGO TIMER7_TRGO ITI1: ITI2: ITI3: TIMER4 ITI0: TIMER1_TRGO TIMER2_TRGO TIMER3_TRGO TIMER7_TRGO ITI1: ITI2: ITI3: TIMER10_ TIMER8 ITI0: TIMER1_TRGO TIMER2_TRGO TIMER9_TRGO TRGO ITI1: ITI2: ITI3: TIMER13_ TIMER11 ITI0: TIMER3_TRGO TIMER4_TRGO TIMER12_TRGO TRGO ITI1: ITI2:...
Page 370 GD32E51x User Manual position.  Hall sensor: for 3-phase motor control.  Programmable prescaler: 16 bit. The factor can be changed on the go.  Each channel is user-configurable: input capture mode, output compare mode, programmable PWM mode, single pulse mode ...
Page 371: Block Diagram
GD32E51x User Manual Block diagram 18.1.3. Figure 18-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 18-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2...
Page 372: Figure 18-2. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual Figure 18-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 373: Figure 18-3. Timing Chart Of Psc Value Change From 0 To 2
GD32E51x User Manual Figure 18-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 374 GD32E51x User Manual Figure 18-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 375: Figure 18-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-5. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 376: Figure 18-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32E51x User Manual Figure 18-6. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 377: Figure 18-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 378: Figure 18-8. Timing Chart Of Center-Aligned Counting Mode
GD32E51x User Manual Figure 18-8. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 379: Figure 18-9. Repetition Timechart For Center-Aligned Counter
GD32E51x User Manual The new written CREP value will not take effect until the next update event. When the value of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow.
Page 380: Figure 18-11. Repetition Timechart For Down-Counter
GD32E51x User Manual Figure 18-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 381: Figure 18-12. Channel Input Capture Principle
GD32E51x User Manual Figure 18-12. Channel Input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 382: Figure 18-13. Channel Output Compare Principle (With Complementary Output, X=0,1,2)
GD32E51x User Manual and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 383: Figure 18-15. Output-Compare In Three Modes
GD32E51x User Manual 1) Configure CHxP=0 (the active level of CHx_O is high, the same as OxCPRE), CHxEN=1 (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNEN=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;...
Page 384 GD32E51x User Manual Figure 18-15. Output-compare in three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 385: Figure 18-16. Timing Chart Of Eapwm
GD32E51x User Manual Figure 18-16. Timing chart of EAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Figure 18-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF...
Page 386 GD32E51x User Manual set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 387: Table 18-2. Complementary Outputs Controlled By Parameters
GD32E51x User Manual Table 18-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 388: Figure 18-18. Complementary Output With Dead-Time Insertion
GD32E51x User Manual (4) ⊕: Xor calculate. (5) (!OxCPRE)：the complementary output of the OxCPRE signal. Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 389: Figure 18-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32E51x User Manual in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register.
Page 390: Figure 18-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32E51x User Manual Table 18-3. Counting direction in different quadrature decoder direction is shown in mode. The quadrature decoder can be regarded as an external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-period value.
Page 391: Figure 18-21. Counter Behavior With Ci0Fe0 Polarity Inverted In Mode 2
GD32E51x User Manual Figure 18-21. Counter behavior with CI0FE0 polarity inverted in mode 2 Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 18-22. Hall sensor is used to BLDC motor show how to connect.
Page 392: Figure 18-23. Hall Sensor Timing Between Two Timers
GD32E51x User Manual Figure 18-22. Hall sensor is used to BLDC motor Hall Sensor Rotor Position signals TIMER_in Input capture Driver Motor GPIO Core TIMER_out BLDC Motor Output compare PWM output Figure 18-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT...
Page 393: Figure 18-24. Restart Mode
GD32E51x User Manual Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register. The trigger input of these modes can be selected by the TRGS [2:0] in the TIMERx_SMCFG register.
Page 394: Figure 18-25. Pause Mode
GD32E51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Pause mode TI0S=0 (Non-xor) The counter will be [CH0NP=0, CH0P=0] paused when the TRGS[2:0]=3’b101 CI0FE0 does not Filter is bypassed in trigger input is low, CI0FE0 is selected. invert.
Page 395: Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
GD32E51x User Manual Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the trigger signals edge or by setting the CEN bit to 1 using software.
Page 396 GD32E51x User Manual Figure 18-28. Timer0 master/slave mode example TIMER 14 TIMER0 TRGS Master ITI0 TRGO mode Prescaler Counter control TIMER 1 Master ITI1 TRGO mode Prescaler Counter control TIMER 2 Trigger Master ITI2 selection TRGO mode Prescaler Counter control CI0F_ED CI0FE0 CI1FE1...
Page 397: Figure 18-29. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32E51x User Manual Configure TIMER2 in master/slave mode by writing MSM=1 (TIMER2_SMCFG register). Select input trigger source (TRGS=3’b010 TIMER2 TIMER0 TIMERx_SMCFG register). Configure TIMER0 in event mode (SMC=3’b110 in the TIMER0_SMCFG register). When the CI0 signal of TIMER2 generates a rising edge, two timer counters start counting synchronously with the internal clock and both TRGIF flags are set.
Page 398 GD32E51x User Manual If one more DMA request event occurs, TIMERx will repeat the process above. Timer debug mode When the Cortex®-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register is set to 1, the TIMERx counter stops.
Page 399: Timerx Registers(X=0, 7)
GD32E51x User Manual TIMERx registers(x=0, 7) 18.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS...
Page 400 GD32E51x User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or quadrature decode mode, this bit is read only.
Page 401 GD32E51x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 402 GD32E51x User Manual counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 403 GD32E51x User Manual SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 404 GD32E51x User Manual 4’b0010 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 405 GD32E51x User Manual 100: Restart mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low.
Page 406 GD32E51x User Manual UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE...
Page 407 GD32E51x User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag Refer to CH0OF description CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag...
Page 408 GD32E51x User Manual Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs.
Page 409 GD32E51x User Manual CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1). 0: No affect 1: Generate channel’s c/c control update event Channel 3’s capture or compare event generation CH3G Refer to CH0G description Channel 2’s capture or compare event generation CH2G Refer to CH0G description Channel 1’s capture or compare event generation...
Page 410 GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL description CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description CH1COMFEN Channel 1 output compare fast enable...
Page 411 GD32E51x User Manual than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise. 111: PWM mode1. When counting up, O0CPRE is low when the counter is smaller than TIMERx_CH0CV, and high otherwise. When counting down, O0CPRE is high when the counter is larger than TIMERx_CH0CV, and low otherwise.
Page 412 GD32E51x User Manual 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability.
Page 413 GD32E51x User Manual Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions...
Page 414 GD32E51x User Manual This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits. 000: Timing mode.
Page 415 GD32E51x User Manual CH2MS[1:0] Channel 2 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH2EN bit in TIMERx_CHCTL2 register is reset).). 00: Channel 2 is programmed as output mode 01: Channel 2 is programmed as input mode, IS2 is connected to CI2FE2 10: Channel 2 is programmed as input mode, IS2 is connected to CI3FE2...
Page 416 GD32E51x User Manual 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 417 GD32E51x User Manual CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable Refer to CH0NEN description CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable Refer to CH0EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary...
Page 418 GD32E51x User Manual in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 419 GD32E51x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 420 GD32E51x User Manual Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 421 GD32E51x User Manual Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 422 GD32E51x User Manual Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input (asynchronous).
Page 423 GD32E51x User Manual channel is output disabled. 1: “off-state” enabled. If the CHxEN or CHxNEN bit is reset, the corresponding channel is “off-state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state”...
Page 424 GD32E51x User Manual DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DMATC[4:0] Reserved DMATA[4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n =...
Page 425 GD32E51x User Manual The transfer Timer is calculated by hardware, and ranges from 0 to DMATC. Input remap register (TIMERx_IRMP) (x=0) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ITI3_RMP ITI0_RMP Bits Fields Descriptions...
Page 426 GD32E51x User Manual 0: No effect OUTSEL The output value selection This bit-field set and reset by software 1: If POEN and IOS is 0, the output disabled 0: No effect...
Page 427: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32E51x User Manual General level0 timer (TIMERx, x=1, 2, 3, 4) 18.2. Overview 18.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 428: Function Overview
GD32E51x User Manual Figure 18-30. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection TIMER_CK DMA REQ/ACK ETIFP Trigger Selector&Counter...
Page 429: Figure 18-31. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual Figure 18-31. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111(external clock mode 0). External input pin source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 430: Figure 18-32. Timing Chart Of Psc Value Change From 0 To 2
GD32E51x User Manual Figure 18-32. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 431 GD32E51x User Manual Figure 18-33. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 432: Figure 18-34. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-34. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 433: Figure 18-35. Timing Chart Of Down Counting Mode,Psc=0/2
GD32E51x User Manual Figure 18-35. Timing chart of down counting mode,PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 434: Figure 18-36. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-36. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 435: Figure 18-37. Timing Chart Of Center-Aligned Counting Mode
GD32E51x User Manual Figure 18-37. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-37. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 436: Figure 18-38. Channel Input Capture Principle
GD32E51x User Manual TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by CHxIE = 1. Figure 18-38. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK...
Page 437: Figure 18-39. Channel Output Compare Principle (X=0,1,2,3)
GD32E51x User Manual Step5: Capture enables. (CHxEN in TIMERx_CHCTL2) Result: When you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by...
Page 438: Figure 18-40. Output-Compare In Three Modes
GD32E51x User Manual register, the CHxIF bit is set and the channel (n) interrupt is generated if CHxIE = 1. And the DMA request will be assert, if CxCDE=1. So the process can be divided to several steps as below: Step1: Clock configuration.
Page 439: Figure 18-41. Timing Chart Of Eapwm
GD32E51x User Manual Based on the counter mode, we have can also divide PWM into EAPWM (Edge aligned PWM) and CAPWM (Centre aligned PWM). The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 18-41. Timing chart of EAPWM shows the EAPWM output and interrupts waveform.
Page 440 GD32E51x User Manual Figure 18-42. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal (x=0,1,2,3), when the As is shown in Figure 18-39.
Page 441: Table 18-5. Examples Of Slave Mode
GD32E51x User Manual The OxCPRE signal can be forced to 0 when the ETIFE signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register.
Page 442: Figure 18-43. Restart Mode
GD32E51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-43. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Pause mode TI0S=0 (Non-xor) The counter will be [CH0NP=0, CH0P=0] paused when the TRGS[2:0]=3’b101 CI0FE0 does not Filter is bypassed in trigger input is low, CI0FE0 is selected.
Page 443: Figure 18-45. Event Mode
GD32E51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-45. Event mode Single pulse mode Single pulse mode. Refer to Timers interconnection Timers interconnection. Refer to Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB;...
Page 444: Timerx Registers(X=1, 2, 3, 4)
GD32E51x User Manual TIMERx registers(x=1, 2, 3, 4) 18.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 445 GD32E51x User Manual 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down...
Page 446 GD32E51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 447 GD32E51x User Manual Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved...
Page 448 GD32E51x User Manual filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 449 GD32E51x User Manual Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 450 GD32E51x User Manual 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled...
Page 451 GD32E51x User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 452 GD32E51x User Manual 0: No Channel 0 interrupt occurred 1: Channel 0 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000...
Page 453 GD32E51x User Manual TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high. 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
Page 454 GD32E51x User Manual 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 455 GD32E51x User Manual PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison. 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable.
Page 456 GD32E51x User Manual 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 457 GD32E51x User Manual Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH3EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 3 is programmed as output mode 01: Channel 3 is programmed as input mode, IS3 is connected to CI3FE3 10: Channel 3 is programmed as input mode, IS3 is connected to CI2FE3...
Page 458 GD32E51x User Manual at each update event will be enabled. 0: Channel 2 output compare shadow disable 1: Channel 2 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the...
Page 459 GD32E51x User Manual CH2CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear.
Page 460 GD32E51x User Manual CH3NP Channel 3 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP Channel 2 complementary output polarity Refer to CH0NP description...
Page 461 GD32E51x User Manual trigger operation in slave mode. And CIxFE0 will be inverted. [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode. And CIxFE0 will be not inverted. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal...
Page 462 GD32E51x User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock...
Page 463 GD32E51x User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) (x=1) Address offset: 0x34 Reset value: 0x0000 0000 0000 This register has to be accessed by word(32-bit) CH0VAL[31:16]...
Page 464 GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 465 GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 466 GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 467 GD32E51x User Manual 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 468 GD32E51x User Manual DMATB[15:0] Bits Fields Descriptions 31:0 DMATB[31:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC. DMA transfer buffer register (TIMERx_DMATB)(x=2,3,4) Address offset: 0x4C Reset value: 0x0000 0000...
Page 469 GD32E51x User Manual 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved Must be kept at reset value.
Page 470: General Level1 Timer (Timerx, X=8, 11)
GD32E51x User Manual General level1 timer (TIMERx, x=8, 11) 18.3. Overview 18.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 471: Function Overview
GD32E51x User Manual Figure 18-46. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter Trigger processor TIMERx_TRGO PSC_CLK TIMER_CK Trigger Selector&Counter Quadrate Decoder Output Logic CH0_O generation of outputs signals in compare, PWM,and mixed modes according to initialization, software CH1_O...
Page 472: Figure 18-47. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual Figure 18-47. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 473: Figure 18-48. Timing Chart Of Psc Value Change From 0 To 2
GD32E51x User Manual Figure 18-48. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 474 GD32E51x User Manual Figure 18-49. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 475: Figure 18-50. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-50. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 476: Figure 18-51. Channel Input Capture Principle
GD32E51x User Manual Figure 18-51. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 477: Figure 18-52. Channel Output Compare Principle (X=0,1)
GD32E51x User Manual CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 478: Figure 18-53. Output-Compare Under Three Modes
GD32E51x User Manual Step2: Compare mode configuration.  Set the shadow enable mode by CHxCOMSEN  Set the output mode (Set/Clear/Toggle) by CHxCOMCTL.  Select the active high polarity by CHxP/CHxNP  Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV.
Page 479: Figure 18-54. Pwm Mode Timechart
GD32E51x User Manual And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM mode0 (CHxCOMCTL==3’b110). Figure 18-54. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Channel output prepare signal Figure 18-52.
Page 480: Figure 18-55. Restart Mode
GD32E51x User Manual [2:0] in the TIMERx_SMCFG register. Table 18-6. Examples of slave mode Mode Selection Source Selection Polarity Selection Filter and Prescaler TRGS[2:0] For the ITIx, no filter 000: ITI0 If CI0FE0 or CI1FE1 is and prescaler can be 001: ITI1 SMC[2:0] selected as the trigger...
Page 481: Figure 18-56. Pause Mode
GD32E51x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-56. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode CH0P=0, The counter will start CI0FE0 does not TRGS[2:0]=3’b101 Filter is bypassed in to count when a rising invert.
Page 482: Figure 18-58. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32E51x User Manual counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0 register. After a trigger rising occurs in the single pulse mode, the OxCPRE signal will immediately be forced to the state which the OxCPRE signal will change to, as the compare match event occurs without taking the comparison result into account.
Page 483: Timerx Registers(X=8, 11)
GD32E51x User Manual TIMERx registers(x=8, 11) 18.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS...
Page 484 GD32E51x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 485 GD32E51x User Manual 000: ITI0 001: ITI1 010: ITI2 011: ITI3 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode.
Page 486 GD32E51x User Manual Reserved Must be kept at reset value. CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 487 GD32E51x User Manual 1: Trigger interrupt occurred. Reserved Must be kept at reset value. Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
Page 488 GD32E51x User Manual Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 489 GD32E51x User Manual 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 490 GD32E51x User Manual 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 491 GD32E51x User Manual 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 492 GD32E51x User Manual define the polarity of CI0. Reserved Must be kept at reset value. CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 493 GD32E51x User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 494 GD32E51x User Manual Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 495 GD32E51x User Manual Reserved Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 496: General Level2 Timer (Timerx, X=9, 10, 12, 13)
GD32E51x User Manual General level2 timer (TIMERx, x=9, 10, 12, 13) 18.4. Overview 18.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 497: Function Overview
GD32E51x User Manual Figure 18-59. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector...
Page 498: Figure 18-60. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual Figure 18-60. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 499: Figure 18-62. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E51x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 500: Figure 18-63. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-63. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 501: Figure 18-64. Channel Input Capture Principle
GD32E51x User Manual Figure 18-64. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling Capture Clock Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal First, the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 502: Figure 18-65. Channel Output Compare Principle
GD32E51x User Manual Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 503: Figure 18-66. Output-Compare Under Three Modes
GD32E51x User Manual * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. About the CHxVAL, you can change it on the go to meet the waveform you expected.
Page 504 GD32E51x User Manual value and the TIMERx_CHxCV content. With regard to a more detail description refer to the relative bit definition. Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values.
Page 505: Timerx Registers(X=9, 10, 12, 13)
GD32E51x User Manual TIMERx registers(x=9, 10, 12, 13) 18.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 506 GD32E51x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 507 GD32E51x User Manual The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 508 GD32E51x User Manual Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 509 GD32E51x User Manual This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 510 GD32E51x User Manual 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise. 111: PWM mode1. When counting up, O0CPRE is low when the counter is smaller than TIMERx_CH0CV, and high otherwise.
Page 511 GD32E51x User Manual the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH0CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010...
Page 512 GD32E51x User Manual 31:4 Reserved Must be kept at reset value. CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 513 GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 514 GD32E51x User Manual This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 515 GD32E51x User Manual 0: No effect Reserved Must be kept at reset value.
Page 516: General Level3 Timer (Timerx, X=14)
GD32E51x User Manual General level3 timer (TIMERx, x=14) 18.5. Overview 18.5.1. The general level3 timer module (TIMER14) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 517: Function Overview
GD32E51x User Manual Figure 18-67. General level3 timer block diagram Function overview 18.5.4. Clock source configuration The clock source of the advanced timer can be either the CK_TIMER or an alternate clock source controlled by SMC bits (TIMERx_SMCFG bit[2:0]).  SMC [2:0] == 3’b000.
Page 518: Figure 18-68. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual The default clock source is the CK_TIMER for driving the counter prescaler when the SMC [2:0] == 3’b000. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. In this mode, the TIMER_CK, which drives counter’s prescaler to count, is equal to CK_TIMER which is from RCU.
Page 519: Figure 18-69. Timing Chart Of Psc Value Change From 0 To 2
GD32E51x User Manual Figure 18-69. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 520 GD32E51x User Manual counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Figure 18-70. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear...
Page 521: Figure 18-71. Timing Chart Of Up Counting, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-71. Timing chart of up counting, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 522: Figure 18-72. Repetition Counter Timing Chart Of Up Counting Mode
GD32E51x User Manual Figure 18-72. Repetition counter timing chart of up counting mode TIMER_CK PSC_CLK 97 98 99 0 98 99 0 98 99 CNT_REG 98 99 0 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2...
Page 523: Figure 18-73. Channel Input Capture Principle
GD32E51x User Manual Figure 18-73. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 524: Figure 18-74. Channel Output Compare Principle (With Complementary Output, X=0)
GD32E51x User Manual and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 525: Figure 18-76. Output-Compare In Three Modes
GD32E51x User Manual configure CHxP=0 (the active level of CHx_O is high, the same as OxCPRE), CHxE=1 (the output of CHx_O is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;...
Page 526 GD32E51x User Manual Figure 18-76. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR register and TIMERx_CHxCV register.
Page 527: Figure 18-77. Pwm Mode Timechart
GD32E51x User Manual Figure 18-77. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 528: Table 18-7. Complementary Outputs Controlled By Parameters
GD32E51x User Manual the TIMERx_CHCTL2 register. Table 18-7. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 529: Figure 18-78. Complementary Output With Dead-Time Insertion
GD32E51x User Manual (!OxCPRE)：the complementary output of the OxCPRE signal. Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 0.
Page 530: Figure 18-79. Output Behavior In Response To A Break(The Break High Active)
GD32E51x User Manual in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register.
Page 531: Figure 18-80. Restart Mode
GD32E51x User Manual Table 18-8. Slave mode example table Source Mode Selection Polarity Selection Filter and Prescaler Selection TRGS[2:0] SMC[2:0] 000: ITI0 3'b100 (restart 001: ITI1 If you choose the CI0FE0 For the ITIx no filter and mode) 010: ITI2 or CI1FE1, configure the prescaler can be used.
Page 532: Figure 18-81. Pause Mode
GD32E51x User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 18-81. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode TRGS[2:0]=3’b1 The counter will TI0S=0(Non-xor) Filter is bypass in this start to count [CH0NP==0, CH0P==0] CI0FE0 is the example.
Page 533: Figure 18-83. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32E51x User Manual In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0 register.
Page 534 GD32E51x User Manual Timer debug mode ® When the Cortex -M23 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1, the TIMERx counter stops.
Page 535: Timerx Registers(X=14)
GD32E51x User Manual TIMERx registers(x=14) 18.5.5. TIMER14 base address: 0x4001 4000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 536 GD32E51x User Manual This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event.
Page 537 GD32E51x User Manual Reserved Must be kept at reset value MMC[2:0] Master mode control These bits control the selection of TRGO signal, which is sent in master mode to slave timers for synchronization function. 000: When a counter reset event occurs, a TRGO trigger signal is output. The counter resert source: Master timer generate a reset the UPG bit in the TIMERx_SWEVG register is set...
Page 538 GD32E51x User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 539 GD32E51x User Manual 101: Pause Mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low. 110: Event Mode. A rising edge of the trigger input enables the counter. 111: External Clock Mode 0. The counter counts on the rising edges of the selected trigger.
Page 540 GD32E51x User Manual 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled...
Page 541 GD32E51x User Manual 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag When the break input is inactive, the bit is set by hardware. When the break input is inactive, the bit can be cleared by software. 0: No active level break has been detected.
Page 542 GD32E51x User Manual Reserved Reserved BRKG TRGG CMTG Reserved CH1G CH0G Bits Fields Descriptions 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 543 GD32E51x User Manual This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value. The prescaler counter is cleared at the same time.
Page 544 GD32E51x User Manual CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits. 000: Timing mode.
Page 545 GD32E51x User Manual CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).). 00: Channel 0 is programmed as output mode 01: Channel 0 is programmed as input mode, IS0 is connected to CI0FE0 10: Channel 0 is programmed as input mode, IS0 is connected to CI1FE0...
Page 546 GD32E51x User Manual 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 547 GD32E51x User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10. CH0NEN Channel 0 complementary output enable When channel 0 is configured in output mode, setting this bit enables the complementary output in channel0. 0: Channel 0 complementary output disabled 1: Channel 0 complementary output enabled CH0P...
Page 548 GD32E51x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved...
Page 549 GD32E51x User Manual Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved...
Page 550 GD32E51x User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH1VAL[15:0] Bits...
Page 551 GD32E51x User Manual The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input (asynchronous). When one of channels is configured in output mode, setting this bit enables the channel outputs (CHx_O and CHx_ON) if the corresponding enable bits (CHxEN, CHxNEN in TIMERx_CHCTL2 register) have been set.
Page 552 GD32E51x User Manual state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. PROT[1:0] Complementary register protect control This bit-filed specifies the write protection property of registers. 00: protect disable. No write protection. 01: PROT mode 0.The ISOx/ISOxN bits in TIMERx_CTL1 register and the BRKEN/BRKP/OAEN/DTCFG bits in TIMERx_CCHP register are writing protected.
Page 553 GD32E51x User Manual 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value.
Page 554 GD32E51x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 0: No effect. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored.
Page 555: General Level4 Timer (Timerx, X=15, 16)
GD32E51x User Manual General level4 timer (TIMERx, x=15, 16) 18.6. Overview 18.6.1. The general level4 timer module (TIMER15, TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 556: Function Overview
GD32E51x User Manual Figure 18-84. General level4 timer block diagram Function overview 18.6.4. Clock source configuration The general level4 TIMER can only being clocked by the CK_TIMER.  Internal timer clock CK_TIMER which is from module RCU The general level4 TIMER has only one clock source which is the internal CK_TIMER, used...
Page 557: Figure 18-85. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER which is from Figure 18-85. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG)
Page 558: Figure 18-86. Timing Chart Of Psc Value Change From 0 To 2
GD32E51x User Manual Figure 18-86. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 559 GD32E51x User Manual Figure 18-87. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 560: Figure 18-88. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-88. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 561: Figure 18-89. Repetition Counter Timing Chart Of Up Counting Mode
GD32E51x User Manual Figure 18-89. Repetition counter timing chart of up counting mode TIMER_CK PSC_CLK 97 98 99 0 98 99 0 98 99 CNT_REG 98 99 0 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2...
Page 562: Figure 18-90. Channel Input Capture Principle
GD32E51x User Manual Figure 18-90. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 563: Figure 18-91. Channel Output Compare Principle (With Complementary Output, X=0)
GD32E51x User Manual value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly.
Page 564 GD32E51x User Manual In channel output compare function, the TIMERx can generate timed pulses with programmable position, polarity, duration and frequency. When the counter matches the value in the CHxVAL register of an output compare channel, the channel (n) output can be set, cleared, or toggled based on CHxCOMCTL.
Page 565: Figure 18-92. Output-Compare Under Three Modes
GD32E51x User Manual Figure 18-92. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR register and TIMERx_CHxCV register.
Page 566: Figure 18-93. Pwm Mode Timechart
GD32E51x User Manual Figure 18-93. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 567: Table 18-9. Complementary Outputs Controlled By Parameters
GD32E51x User Manual the TIMERx_CHCTL2 register. Table 18-9. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 568: Figure 18-94. Complementary Output With Dead-Time Insertion
GD32E51x User Manual (!OxCPRE)：the complementary output of the OxCPRE signal. Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 1.
Page 569: Figure 18-95. Output Behavior In Response To A Break(The Break High Active)
GD32E51x User Manual in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register.
Page 570: Figure 18-96. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32E51x User Manual to 1 can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software. If the CEN bit is cleared to 0 using software, the counter will be stopped and its value held.
Page 571 GD32E51x User Manual Timer debug mode ® When the Cortex -M23 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1, the TIMERx counter stops.
Page 572: Timerx Registers(X=15, 16)
GD32E51x User Manual TIMERx registers(x=15, 16) 18.6.5. TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits...
Page 573 GD32E51x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 574 GD32E51x User Manual Reserved Must be kept at reset value DMAS DMA request source selection 0: DMA request of channel x is sent when capture/compare event occurs. 1: DMA request of channel x is sent when update event occurs. CCUC Commutation control shadow register update control When the commutation control shadow enable (for CHxEN, CHxNEN and CHxCOMCTL bits) are set (CCSE=1), these shadow registers update are controlled...
Page 575 GD32E51x User Manual 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE...
Page 576 GD32E51x User Manual When the break input is inactive, the bit can be cleared by software. 0: No active level break has been detected. 1: An active level has been detected. Reserved Must be kept at reset value CMTIF Channel commutation interrupt flag This flag is set by hardware when channel’s commutation event occurs, and cleared by software 0: No channel commutation interrupt occurred...
Page 577 GD32E51x User Manual 1: Generate a break event Reserved Must be kept at reset value CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 578 GD32E51x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 579 GD32E51x User Manual 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 580 GD32E51x User Manual is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection...
Page 581 GD32E51x User Manual When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0. [CH0NP==0, CH0P==0]: CIxFE0’s rising edge is the active signal for capture or trigger operation in slave mode.
Page 582 GD32E51x User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 583 GD32E51x User Manual Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
Page 584 GD32E51x User Manual POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input (asynchronous).
Page 585 GD32E51x User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. Idle mode “off-state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off-state” for Table 18-9.
Page 586 GD32E51x User Manual This register has to be accessed by word(32-bit) Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1).
Page 587 GD32E51x User Manual Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CHVSEL OUTSEL Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 588: Basic Timer (Timerx, X=5, 6)
GD32E51x User Manual Basic timer (TIMERx, x=5, 6) 18.7. Overview 18.7.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 589: Figure 18-98. Timing Chart Of Internal Clock Divided By 1
GD32E51x User Manual generate PSC_CLK. Figure 18-98. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 590: Figure 18-99. Timing Chart Of Psc Value Change From 0 To 2
GD32E51x User Manual Figure 18-99. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 591: Figure 18-100. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E51x User Manual Figure 18-100. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 592: Figure 18-101. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E51x User Manual Figure 18-101. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 593: Timerx Registers(X=5, 6)
GD32E51x User Manual TIMERx registers(x=5, 6) 18.7.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS Bits...
Page 594 GD32E51x User Manual The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 595 GD32E51x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled...
Page 596 GD32E51x User Manual Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared.
Page 597 GD32E51x User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 598: Super High-Resolution Timer (Shrtimer)
GD32E51x User Manual Super High-Resolution Timer (SHRTIMER) Overview 19.1. SHRTIMER has a super high-resolution counting clock and can be used for high-precision timing. It can generate 10 super high resolution and flexible digital signals to control motor or be used for power management applications. The 10 digital signals can be output independently or coupled into 5 pairs of complementary signals.
Page 599: Function Overview
GD32E51x User Manual Figure 19-1. SHRTIMER block diagram Master_TIMER Master_TIMER Interrupt request repetition repetition counter auto Synchronization counter auto DMA mode DMA mode register DMA request DMA request reload register register reload register control output/input control ADC trigger Counter Compare Counter Compare DAC trigger...
Page 600: Table 19-1. The Limitations Of Auto-Reload And Compare Y (Y=0..3) Register
GD32E51x User Manual Figure 19-2. Master_TIMER diagram Slave_TIMERx(x=0..4) CREP Counter Synchronization repetition Start counter input Reset Counter SHRTIMER_PSCCK Half SHRTIMER_HPCK CMP0 mode 64 * f SHRTIMER_CK SHRTIMER_CK CMP1 (from RCU) SHRTIMER_CK CMP2 CMP3 The auto-reload register and compare y (y=0..3) register have the following limitations: ...
Page 601: Figure 19-3. Counter Clock When Divided By 32
GD32E51x User Manual in SHRTIMER_MTCTL0 register. The frequency relationship between them can be expressed below: CNTCKDIV[2:0]+1 SHRTIMER_PSCCK SHRTIMER_HPCK When the CNTCKDIV[3] bit in SHRTIMER_MTACTL register is ‘1’, the CNTCKDIV[2:0] bit-filed can only be configured with ‘3’b000’ and the frequency relationship between SHRTIMER_PSCCK and SHRTIMER_HPCK can be expressed below: SHRTIMER_PSCCK SHRTIMER_HPCK...
Page 602: Figure 19-4. Counter Behavior In Single Pulse Mode
GD32E51x User Manual SHRTIMER_MTCTL0 register). In single pulse mode, after setting the bit MTCEN in SHRTIMER_MTCTL0 register, the first reset event will start the counter. When counting up to the counter-reload value, the counter stops and generates a period event. Then the other reset event will reset and restart the counter.
Page 603: Figure 19-6. Repetition Counter Behavior In Continuous Mode
GD32E51x User Manual Repetition counter When MTCEN bit in SHRTIMER_MTCTL0 register is set to 1, the repetition counter load the value of SHRTIMER_MTCREP register. The repetition counter is decremented when the counter is cleared due to either a roll-over event in continuous mode or a reset event. When the repetition counter has reached zero, the coming roll-over event in continuous mode or reset event will generate a repetition event and reload the value of SHRTIMER_MTCREP register.
Page 604: Figure 19-8. Repetition Counter Behavior In Single Pulse Mode With Cntrstm = 1
GD32E51x User Manual Figure 19-8. Repetition counter behavior in single pulse mode with CNTRSTM = 1 shows repetition counter operation diagram in single pulse mode with CNTRSTM = 1. Figure 19-8. Repetition counter behavior in single pulse mode with CNTRSTM = 1 MTCEN or STxCEN(x=0..4) Reset event...
Page 605 GD32E51x User Manual Compare The Master_TIMER unit has four compare registers: SHRTIMER_MTCMPxV(x=0..3). When the counter value matches the compare registers value, a coincident compare event is generated. The compare event will set the corresponding compare interrupt flag to 1 (CMPxIF bit in SHRTIMER_MTINTF where x=0..3), and a compare interrupt or DMA request is issued if enabled (CMPxIE = 1 or CMPxDEN = 1 bits in SHRTIMER_MTDMAINTEN register where x=0..3).
Page 606: Table 19-3. Master_Timer Shadow Registers And Update Event
GD32E51x User Manual Note: Update event occurs only when SHWEN=1. Table 19-3. Master_TIMER shadow registers and update event lists the registers containing shadow registers and the relevant event. Table 19-3. Master_TIMER shadow registers and update event Registers Shadow registers Update event. that contain shadow registers enable bit SHRTIMER_MTDMAINTEN...
Page 607: Slave_Timerx(X=0
GD32E51x User Manual trigger request. SHRTIMER_DACTRIGOy(y=0..2) is the internal signal connected from Master_TIMER to the DAC module. Refer to Trigger to DAC for more information. Slave_TIMERx(x=0..4) unit 19.4.2. The SHRTIMER has 5 slave timers with similar structure: Slave_TIMERx(x=0..4). Each unit is built around the following components: ...
Page 608: Table 19-4. The Limitations Of Counter And Capture Y(Y=0,1) Value Registers
GD32E51x User Manual  The maximum value must be less than or equal to 0xFFFF – (1 t SHRTIMER_CK Refer to Table 19-1. The limitations of auto-reload and compare y (y=0..3) register. The counter and capture y(y=0,1) value registers also have the following limitations: for counter clock division below 64 (CNTCKDIV[3:0] <...
Page 609 GD32E51x User Manual Up counting mode The counter counts up continuously from 0 to the counter-reload value, which is defined in the SHRTIMER_STxCAR register. There are two counter operating modes: single pulse mode (CTNM = 0 in SHRTIMER_STxCTL0 register) and continuous mode (CTNM = 1 in SHRTIMER_STxCTL0 register).
Page 610 GD32E51x User Manual 2. Synchronization input start/reset counter. 3. Events configured in SHRTIMER_STxCNTRST register. All these sources are logical ORed, they can be valid simultaneously. If multiple reset events occur in the same t cycle, only the last one is valid. The counter reset requests are SHRTIMER_CK taken into account only once the related Slave_TIMERx are enabled Note: If the external events is configured with level sensitivity, only one external events can...
Page 611: Figure 19-11. Capture 0 Triggered By Exev0 And Exev1
GD32E51x User Manual The capture 0 trigger events are defined in SHRTIMER_STxCAP0TRG register and the capture 1 trigger events are defined in SHRTIMER_STxCAP1TRG register. All the trigger events are logical ORed and they are all valid when multiple trigger events are selected. Note: If the external events is configured with level sensitivity, only one external events can be enabled in the SHRTIMER_STxCAPyTRG(y=0,1) register.
Page 612: Figure 19-12．Compare 1 Behavior With Stxcar=0X8, Stxcmp1V=0X02
GD32E51x User Manual Figure 19-12．Compare 1 behavior with STxCAR=0x8, STxCMP1V=0x02 Cleared by CMP1IFC Cleared by CMP1IFC Half mode When HALFM bit in SHRTIMER_STxCTL0 is set to 1, the half mode is enabled. This mode forces the value of compare 0 active register to be half of the counter-reload value, but the value of SHRTIMER_STxCMP0V register is not updated with the SHRTIMER_MTCAR/2 value.
Page 613: Figure 19-14. Compare 1 Delayed Mode 0
GD32E51x User Manual generated. Once the relative capture is triggered, the value in compare y active register is summed with the relative SHRTIMER_STxCAP0V/ SHRTIMER_STxCAP1V, and it is compared to the counter. Compare 1 is associated with capture 0 and compare 0/2, while compare 3 is associated with capture 1 and compare 0/2.
Page 614: Figure 19-15. Compare 1 Delayed Mode 1
GD32E51x User Manual Compare 1 event occurs as soon as the counter value is equal to the recomputed compare 1 value. If capture 0 trigger occurs first, the later compare 0 event is ignored. If compare 0 event occurs first, the capture 0 trigger after the compare 1 event is ignored. Refer to Figure 19-15.
Page 615: Figure 19-16. Compare Delayed Mode With Shwen = 0
GD32E51x User Manual Figure 19-16. Compare delayed mode with SHWEN = 0 MTCEN or STxCEN(x=0..4) previous+ C1 C2+ C1 update event Counter when CTNM = 1 Preload=previous Active=previous + C1 Capture event C a p t u r e C a p t u r e previous register register...
Page 616: Figure 19-18. O0Pre Wave: Set On Cmp0, Reset On Cmp1
GD32E51x User Manual Only one of them can be chosen. Output prepare signal Slave_TIMERx has a set/reset output module. The module can generate two output prepare signals: O0PRE and O1PRE. O0PRE is controlled by SHRTIMER_STxCH0SET and SHRTIMER_STxCH0RST registers. O1PRE is controlled by SHRTIMER_STxCH1SET and SHRTIMER_STxCH1RST registers.
Page 617: Table 19-5. Slave_Timer Interconnection Event
GD32E51x User Manual  Master_TIMER: period event and compare y(y=0..3) event.  Slave_TIMERx interconnection event: there are 9 interconnect events from other Slave_TIMERy (for instance x=1, then y=0, 2..4). Refer to Table 19-5. Slave_TIMER interconnection event  External event y(y=0..9): EXEVy conditioned by external event filter in Slave_TIMERx ...
Page 618: Figure 19-19. Arbitration Mechanism During Each T
GD32E51x User Manual mechanism during each tSHRTMER_CK period Figure 19-19. Arbitration mechanism during each t period SHRTMER_CK Arbiter0: Arbiter0: STx interconnection Arbiter1: only one event Arbiter1: CMP3> Arbiter2: Arbiter2: CMP3> event y(y=0..8) delay and request delay reset> CMP2> CMP2> reset> smaller, smaller, CMP1>...
Page 619: Figure 19-20． Arbitration Mechanism Example
GD32E51x User Manual From Slave_TIMER0 itself: compare 3 event, period event. Interconnection event to Slave_TIMER0: interconnection event 7 (Slave_TIMER4 compare 2 event), interconnection event 8 (Slave_TIMER4 compare 3 event). Low-precision events: external event 2(EXEV2), external event 3(EXEV3)  The delay: Slave_TIMER4 compare 3 < Slave_TIMER0 compare 3 If the selected events above occur during one t period, the arbitration process and HPTMER_CK...
Page 620: Figure 19-23. Super High-Resolution Oxpre Wave
GD32E51x User Manual Figure 19-21. A pulse of 1 t period SHRTMER_CK SHRTIMER_CK SHRTIMER_CK OxPRE postponed super high- resolution SHRTIMER_CK OxPRE super high- anticipated resolution super high- OxPRE postponed resolution SHRTIMER_CK super high- OxPRE SHRTIMER_CK resolution anticipated Legend: set request reset request If the “set and reset requests”...
Page 621: Figure 19-24. Oxpre Wave With Cntckdiv[3:0] = 4'B0110
GD32E51x User Manual next active edge of the SHRTIMER_PSCCK, even if the arbitration is still performed every cycle. SHRTIMER_CK When “set and reset requests” from different event sources simultaneously occur in a tSHRTIMER_CK cycle, the “reset request” has the highest priority. In SHRTIMER_PSCCK cycle, subsequent requests override previous requests, and only the last request of that cycle Figure 19-24.
Page 622 GD32E51x User Manual  SHRTIMER_STxCH0RST = 0x0000 0010: compare 1 event produces “reset request” and O0PRE will be set to low level.  SHRTIMER_STxCMP0V = 0x0060  SHRTIMER_STxCMP1V = 0x00E0 Figure 19-25. C0OPRE wave in regular mode SHRTIMER_CK 0x00 0x20 0x40 0x60 0x80...
Page 623: Figure 19-26. C0Opre And C1Opre Complementary Wave With Dead-Time
GD32E51x User Manual CH0ONADEN = 1 bit in SHRTIMER_STxDMAINTEN register). The CH0ONAIF interrupt flag can be cleared by writing 1 to CH0ONAIFC bit in SHRTIMER_STxINTFC. The channel 1 is similar to channel 0. Figure 19-26. C0OPRE and C1OPRE complementary wave with dead-time shows C0OPRE and C1OPRE wave with O0PRE pulse width greater than the dead-time.
Page 624: Figure 19-28. Structure Chart In Balanced Mode
GD32E51x User Manual Figure 19-27. Complementary wave with pulse width less than dead-time O0PRE O0PRE DTRCFG[15:0] DTRCFG[15:0] DTRCFG[15:0] Skip dead-time C0OPRE C0OPRE following rising DTRS = 0 DTRS = 0 DTFS = 0 DTFCFG[15:0] DTFS = 0 DTFCFG[15:0] DTFCFG[15:0] Skip dead-time C1OPRE following falling C1OPRE...
Page 625: Figure 19-29. C0Opre And C1Opre Wave In Balanced Mode
GD32E51x User Manual inactive level (low level). When the output of toggle logic module is 0(low level), C1OPRE is connected to O1PRE and C0OPRE is set to inactive level (low level). It is advised to make SHRTIMER_STxCH0SET = SHRTIMER_STxCH1SET and SHRTIMER_STxCH0RST = SHRTIMER_STxCH1RST, in order to achieve a balanced operation with identical waveforms.
Page 626: Table 19-6. Crossbar And Idle Control Stage Work Together
GD32E51x User Manual Figure 19-29. C0OPRE and C1OPRE wave in balanced mode SHRTIMER_CK 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 Counter Compare 0 previous Preload=0x0080/Active=0x0080 register...
Page 627: Table 19-7. Request To Enter In Idle And Exit Idle State
GD32E51x User Manual CHyOPRE (y=0,1) to enter IDLE state. It is associated with ISOy/CHyP(y=0,1) in Table 19-7. Request to enter in IDLE and exit SHRTIMER_STxCHOCTL register. Refer to IDLE state. ISOy define the CHyOPRE level in IDLE state. The IDLE mode is permanently maintained but the counter continues to run, until the output is re-enabled to exit delayed IDLE.
Page 628: Figure 19-30. Iso0 = 0 And Chop = 0 In Delayed Idle
GD32E51x User Manual Figure 19-30. ISO0 = 0 and CHOP = 0 in delayed IDLE SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 0 CH0P = 0 CH0OPRE RUN State RUN State IDLE State re-enable EXEV6 ISO0 = 0 CH0P = 0 CH0OPRE...
Page 629: Figure 19-32. Iso0 = 0 And Chop = 1 In Delayed Idle
GD32E51x User Manual Figure 19-32. ISO0 = 0 and CHOP = 1 in delayed IDLE SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 0 CH0P = 1 CH0OPRE RUN State RUN State IDLE State re-enable EXEV6 ISO0 = 0 CH0P = 1 CH0OPRE...
Page 630: Figure 19-34. Balanced Idel With Iso0 = 0 And Iso1 = 0
GD32E51x User Manual When the selected event arrives, the CHyOPRE (y=0,1) enters IDLE state and takes the level defined by ISOy bits in the SHRTIMER_STxCHOCTL register. Meanwhile the DLYIIF in SHRTIMER_STxINTF register is set to 1.The selected external event triggers a capture of the counter value into the compare 3 active register (this value is not user-accessible).
Page 631: Table 19-8. Output During Idel State Controlled By Bunch Mode
GD32E51x User Manual  BMSTx bit must be reset (counter clock(SHRTIMER_PSCCK) is maintained and the counter operates normally)  No balanced IDLE are triggered while the outputs are in IDLE state controlled by bunch mode. IDLE controlled by bunch mode In bunch mode, the IDLE state is controlled by bunch controller.
Page 632: Figure 19-35. Stxchy_O Wave With Chyp=0 Or Chyp=1
GD32E51x User Manual Note: “×” means “0/1”. Writing 1 to STxCHyDIS in SHRTIMER_CHOUTDIS register will disable output and make output stage enters the Idle state. The priority order of the three states is: Idle state > Fault state > Run state. The output polarity is programmed using CHyP bits in SHRTIMER_STxCHOCTL register.
Page 633: Figure 19-36. Carrier-Signal Structure Diagram
GD32E51x User Manual Figure 19-36. Carrier-signal structure diagram Carrier-signal generator 0 CH0CSEN Carrier-signal generator 1 O0PRE CH1CSEN SHRTIMER_CSGCK O1PRE prescaler: CH1CSEN/ CH0CSEN SHRTIMER_CK IDLE CH0OPRE CH1OPRE In carrier-signal mode, it is possible to define a specific pulse width before the beginning of the carrier-signal.
Page 634: Figure 19-37. Shrtimer Output With Carrier-Signal Mode Enabled
GD32E51x User Manual Figure 19-37. SHRTIMER output even if the current carrier period is not completed. Refer to with carrier-signal mode enabled. Figure 19-37. SHRTIMER output with carrier-signal mode enabled Compare 1 active value Slave_TIMER0 Slave_TIMER0 OyPRE OyPRE Carrier-signal Carrier-signal Carrier signal Carrier signal duty...
Page 635: Table 19-10. Slave_Timerx Shadow Registers And Update Event
GD32E51x User Manual Note: Update event occurs only when SHWEN=1. Table 19-10. Slave_TIMERx shadow registers and update event lists the registers that contain shadow registers and corresponding update events. Table 19-10. Slave_TIMERx shadow registers and update event Registers Shadow registers Update event.
Page 636: Figure 19-38. Blanking Mode And Windowing Mode
GD32E51x User Manual account. Figure 19-38. Blanking mode and windowing mode Refer to Figure 19-38. Blanking mode and windowing mode EXEVyC EXEVyC EXEVy EXEVy Blanking mode Windowing mode Windowing signal Blanking signal EXEVyC EXEVyC Blanking signal Windowing signal EXEVy EXEVy EXEV0MEEN = 0 EXEV0MEEN = 0 EXEVy...
Page 637: Table 19-13. Filtering Signals Mapping In Windowing Mode
GD32E51x User Manual Slave_TIMER Slave_TIMER Slave_TIMER Slave_TIMER Slave_TIMER From STBLKSRC4 Slave_TIMER2 Slave_TIMER2 Slave_TIMER3 Slave_TIMER2 Slave_TIMER2 compare 3 compare 1 compare 0 CH1OPRE CH1OPRE STBLKSRC5 Slave_TIMER2 Slave_TIMER2 Slave_TIMER3 Slave_TIMER4 Slave_TIMER3 CH1OPRE CH1OPRE compare 3 compare 0 compare 0 STBLKSRC6 Slave_TIMER3 Slave_TIMER3 Slave_TIMER3 Slave_TIMER4 Slave_TIMER3...
Page 638: Dll Calibrate
GD32E51x User Manual SHRTIMER_DACTRIGOy(y=0..3). If DACTRGS[1:0] = 2’b00 in SHRTIMER_STxCTL0 register, Slave_TIMERx won’t generate trigger request. SHRTIMER_DACTRIGOy(y=0..3) is the internal signal connected from Slave_TIMERx to the DAC module. Refer to Trigger to DAC for more information. DLL calibrate 19.4.3. The DLL can produce and calibrate a super high resolution clock SHRTIMER_HPCK = 64 *f ).
Page 639: Figure 19-39. Bunch Mode Timing Chart
GD32E51x User Manual Bunch mode timing The BM-counter can be clocked by several sources, selected with BMCLKS[3:0] bits in the SHRTIMER_BMCTL register. When the rising edge of the selected clock source signal arrives, BM-counter increments by 1. When BMCLKS[3:0]=4’b1010, the clock source of BM-counter is the f prescaled SHRTIMER_CK by a factor defined with BMPSC[3:0] bit-field in SHRTIMER_BMCTL register.
Page 640: Figure 19-40. Regular Entry For Bunch Mode
GD32E51x User Manual events are divided into seven categories: 1. Events from Master_TIMER: repetition event, reset/roll-over event, compare 0 to 3 event 2. Events from Slave_TIMERx: repetition event, reset/roll-over event, compare 0 and 1 event 3. External event: EXEV6 and EXEV7 4.
Page 641 GD32E51x User Manual Figure 19-40. Regular entry for bunch mode Compare 1 active value Slave_TIMER0 OyPRE(y=0,1) EXEV Bunch mode termination. CHyOPRE(y=0,1) IDLE in bunch mode RUN in bunch mode ISOy=0 RUN state Bunch mode operation RUN state EXEV Bunch mode termination.
Page 642: Figure 19-41. Delayed Entry For Bunch Mode
GD32E51x User Manual Figure 19-41. Delayed entry for bunch mode Compare 1 active value Slave_TIMER0 Slave_TIMER0 O0PRE O0PRE Bunch mode EXEV termination. RUN in bunch mode Rrising Rrising Rrising dead-time dead-time IDLE in bunch mode Rrising dead-time dead-time CH0OPRE CH0OPRE ISO0 = 0 Entry arrives not during ISO0 = 0...
Page 643: Synchronization Input/Output
GD32E51x User Manual  Period event is used to produce “set request”.  Write two 32-bit data to the SHRTIMER_STxCMP0CP register consecutively using DMA (upon repetition event), as below: SHRTIMER_STxCMP0CP = {CREP[7:0] = (RUN number of periods - 1); CMP0VAL[15:0] = duty cycle} SHRTIMER_STxCMP0CP = {CREP[7:0] = (IDLE number of periods - 1);...
Page 644: External Event
GD32E51x User Manual which occurs during the counting with CTNM or CNTRSTM bits set to 1.  2’b01: Master_TIMER compare 0 event 2’b10: Slave_TIMER0 reset and start event. It is similar to Master_TIMER start event,  except for the following: counter roll-over in continuous mode, discarded reset request in single pulse mode with CNTRSTM=0.
Page 645: Figure 19-43. Extern Event Y(Y=0..4) Processed Diagram
GD32E51x User Manual SHRTIMER_EXEVDFCTL registers. The process by which external event y(y=0..4) are processed is shown in Figure 19-43. Extern event y(y=0..4) processed diagram. Figure 19-43. Extern event y(y=0..4) processed diagram Active/inactive Active/inactive crossbar crossbar Slave_TIMERx(x=0..4) Slave_TIMERx(x=0..4) External event filter: External event filter: EXEVyC EXEVy...
Page 646: Fault Input
GD32E51x User Manual SHRTIMER_EXEVDFCTL register. These external events sources EXEVySRCz(y=0..9,z=0..4) can come from comparators, digital input pins, ADC’s analog watchdogs and TIMER_TRGO. Refer to Table 19-15. External events mapping. Table 19-15. External events mapping External event EXEVySRC0 EXEVySRC1 EXEVySRC2 EXEVySRC3 External event 0 PC12 Comparator 1...
Page 647: Table 19-16. Fault Channel Mapping
GD32E51x User Manual Figure 19-45. Fault input diagram Fault channel Fault channel FLTyINEN Digital chip external pin Digital Filter Filter comparator FLTyINP FLTyINP FLTyINSRC FLTyINSRC FLTyINFC[3:0] FLTyINFC[3:0] FLTyEN SystemFault Channel output stage Channel output stage STxCH0_O Idle STxCH1_O CH0P/ CH0P/ CH1P Fault output state CH1P...
Page 648: Trigger To Adc
GD32E51x User Manual Fault channel FLTyINSRC = 0 (input pin) FLTyINSRC = 1(comparator) Fault channel 3 PB11 Fault channel 4 PC7/PG10 Note: “×” means not available. The polarity of the signal can be configured by the FLTyINP polarity bit in SHRTIMER_FLTINCFG0 and SHRTIMER_FLTINCFG1 registers.
Page 649: Trigger To Dac
GD32E51x User Manual Figure 19-46. Trigger to ADC selection overview SHRTIMER SHRTIMER_ADCTRIG0 SHRTIMER_ADCTRIGS0 SHRTIMER_ADCTRIGS1 SHRTIMER_ADCTRIG1 SHRTIMER_ADCTRIG2 SHRTIMER_ADCTRIGS2 SHRTIMER_ADCTRIGS3 SHRTIMER_ADCTRIG3 There are up to 32 events which can be combined (ORed) for each trigger output. They are defined in SHRTIMER_ADCTRIGSy(y=0..3) registers. SHRTIMER_ADCTRIGSy(y=0..3) registers are preloaded and can be updated synchronously with the timer they are related to.
Page 650: Interrupt
GD32E51x User Manual Figure 19-47. Trigger to DAC selection overview. Figure 19-47. Trigger to DAC selection overview Master_TIMER No trigger Update event SHRTIMER_DACTRIG0 DACTRGS[1:0] in SHRTIMER_MTCTL0 SHRTIMER_DACTRIG1 Slave_TIMERx No trigger SHRTIMER_DACTRIG2 Update event DACTRGS[1:0] in SHRTIMER_STxCTL0 Interrupt 19.4.10. Most events can generate interrupt requests. All interrupt requests are grouped in 7 vectors (SHRTIMER_IRQy,y=0..6).Refer to Table 19-17.
Page 651: Dma Request
GD32E51x User Manual Interrupt Number Event Control bit SHRTIMER_IRQ4 Update event UPIE in SHRTIMER_STxDMAINTEN Repetition event REPIE in SHRTIMER_STxDMAINTEN Slave_TIMER4: Compare 3 event CMP3IE in SHRTIMER_STxDMAINTEN SHRTIMER_IRQ5 Compare 2 event CMP2IE in SHRTIMER_STxDMAINTEN Compare 1 event CMP1IE in SHRTIMER_STxDMAINTEN Compare 0 event CMP0IE in SHRTIMER_STxDMAINTEN Bunch mode period event BMPERIE in SHRTIMER_INTEN...
Page 652: Dma Mode
GD32E51x User Manual DMA mode 19.4.12. Timer’s DMA mode is the function that configures SHRTIMER’s multiple registers by DMA module with a single DMA request. The relative registers (7 registers in total) are as follows:  SHRTIMER_DMAUPMTR: Defines which registers in the Master_TIMER are updated. Most of Master_TIMER control and data registers are associated with a selection bit.
Page 653: Debug Mode
GD32E51x User Manual Figure 19-48. DMA mode operation flowchart The DMA request to write SHRTIMER_DMATB Parse SHRTIMER_DMAUPSTyR(y=1..4) register and The process is similar to Parse SHRTIMER_DMAUPST0R register Data is transferred to Data is transferred to MTCTL0 bit SHRTIMER_MTCTL0 ST0CTL0bit SHRTIMER_ST0CTL0 is 1? and trigger a new DMA is 1?
Page 654: Master_Timer Registers
GD32E51x User Manual The registers can be segmented for ease of addressing： SHRTIMER Master_TIMER registers base address: 0x4001 7400 SHRTIMER Slave_TIMER0 registers base address: 0x4001 7480 SHRTIMER Slave_TIMER1 registers base address: 0x4001 7500 SHRTIMER Slave_TIMER2 registers base address: 0x4001 7580 SHRTIMER Slave_TIMER3 registers base address: 0x4001 7600 SHRTIMER Slave_TIMER4 registers base address: 0x4001 7680 SHRTIMER Common registers base address: 0x4001 7780...
Page 655 GD32E51x User Manual Note: UPREP can be set only if UPSEL[1:0] = 2’b00 or 2’b01. Reserved Must be kept at reset value SHWEN Shadow registers enable 0: The shadow registers are disabled 1: The shadow registers are enabled 26:25 DACTRGS[1:0] Trigger source to DAC The timer can also generate a DAC trigger event when an update event occurs.
Page 656 GD32E51x User Manual This bit-field specifies the event to be sent to the synchronization output pad SHRTIMER_SCOUT. 00: Master_TIMER start event. 01: Master_TIMER compare 0 event 10: Slave_TIMER0 reset and start event 11: Slave_TIMER0 compare 0 event 13:12 SYNOPLS[1:0] Synchronization output pulse This bit-field specifies...
Page 657 GD32E51x User Manual 1: The counter can be reset at any time (running or stopped). CTNM Continuous mode 0: Single pulse mode. The counter stops by hardware when it reaches the SHRTIMER_MTCAR value. 1: Continuous mode. The counter rolls over to zero and count continuously when it reaches the SHRTIMER_MTCAR value CNTCKDIV[2:0] Counter clock division...
Page 658 GD32E51x User Manual 0: No update interrupt occurred 1: Update interrupt occurred SYNIIF Synchronization input interrupt flag This flag is set by hardware when synchronization input occurs. 0: No synchronization input interrupt occurred 1: Synchronization input interrupt occurred REPIF Repetition interrupt flag This flag is set by hardware when a repetition event occurs.
Page 659 GD32E51x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value UPIFC Clear update interrupt flag 0: No effect 1: Clear update interrupt flag SYNIIFC Clear synchronization input interrupt flag 0: No effect 1: Clear synchronization input interrupt flag REPIFC Clear repetition interrupt flag 0: No effect...
Page 660 GD32E51x User Manual Bits Fields Descriptions 31:23 Reserved Must be kept at reset value UPDEN Update DMA request enable 0: disabled 1: enabled SYNIDEN Synchronization input DMA request enable 0: disabled 1: enabled REPDEN Repetition DMA request enable 0: disabled 1: enabled CMP3DEN Compare 3 DMA request enable...
Page 661 GD32E51x User Manual 0: disabled 1: enabled CMP1IE Compare 1 interrupt enable 0: disabled 1: enabled CMP0IE Compare 0 interrupt enable 0: disabled 1: enabled SHRTIMER Master_TIMER counter register (SHRTIMER_MTCNT) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0] Bits...
Page 662 GD32E51x User Manual CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 663 GD32E51x User Manual SHRTIMER Master_TIMER compare 0 value register (SHRTIMER_MTCMP0V) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CMP0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP0VAL[15:0] Compare 0 value This bit-field contains value to be compared to the counter.
Page 664 GD32E51x User Manual 0), it holds the content of the active register; otherwise, it holds the content of the shadow register. Note: (1) The minimum value must be greater than or equal to 3 t . For example: SHRTIMER_CK CARL[15:0] >= 0x60 when CNTCKDIV[3:0] = 4’b0000. (2) The maximum value must be less than or equal to 0xFFFF –...
Page 665 GD32E51x User Manual CMP3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP3VAL[15:0] Compare 3 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 666: Slave_Timerx Registers(X=0
GD32E51x User Manual Slave_TIMERx registers(x=0..4) 19.5.2. SHRTIMER Slave_TIMER0 registers base address: 0x4001 7480 SHRTIMER Slave_TIMER1 registers base address: 0x4001 7500 SHRTIMER Slave_TIMER2 registers base address: 0x4001 7580 SHRTIMER Slave_TIMER3 registers base address: 0x4001 7600 SHRTIMER Slave_TIMER4 registers base address: 0x4001 7680 SHRTIMER Slave_TIMERx control register 0 (SHRTIMER_STxCTL0) Address offset: 0x00 Reset value: 0x0000 0000...
Page 667 GD32E51x User Manual (2) When UPSEL[3:0] = 4’b0001, 4’b0011, 4’b0100, 4’b0101, it is possible to have multiple concurrent update source. For instance, update by Master_TIMER (UPBMT = 1) and DMA mode. SHWEN Shadow registers enable 0: The shadow registers are disabled 1: The shadow registers are enabled 26:25 DACTRGS[1:0]...
Page 668 GD32E51x User Manual UPBST1 Update by Slave_TIMER1 update event When the bit is set, the Slave_TIMERx(x=0,2,3,4) update event are synchronized with Slave_TIMER1 update event and the active registers of them are updated by the Slave_TIMER1 update event 0: The active registers is not update by Slave_TIMER1. 1: The active registers is update by Slave_TIMER1.
Page 669 GD32E51x User Manual in SHRTIMER_MTCTL0 register). 13:12 DELCMP1M[1:0] Compare 1 delayed mode 00: Compare 1 delayed mode disable. Compare match occurs as soon as the counter equals the value of compare 1 active register. 01: Compare 1 delayed mode 0. After a capture 0 event, the recalculated value of compare 1 is: (compare 1 active register value + capture 0 value).
Page 670 GD32E51x User Manual 0: The counter can be reset only if it stops (period elapsed) 1: The counter can be reset at any time (running or stopped). CTNM Continuous mode. 0: Single pulse mode. The counter stops by hardware when it reaches the SHRTIMER_STxCAR value.
Page 671 GD32E51x User Manual 31:22 Reserved Must be kept at reset value CH1F Channel 1 output flag This bit indicates the output level state of channel 1. 0: Channel 1 outputs inactive level. 1: Channel 1 outputs active level. CH0F Channel 0 output flag This bit indicates the output level state of channel 0.
Page 672 GD32E51x User Manual to inactive) occurs. 0: No channel 0 output inactive interrupt occurred 1: Channel 0 output inactive interrupt occurred CH0OAIF Channel 0 output active interrupt flag This flag is set by hardware when channel 0 output active (C1OPRE from inactive to active) occurs.
Page 673 GD32E51x User Manual 0: No compare 0 interrupt occurred 1: Compare 0 interrupt occurred SHRTIMER Slave_TIMERx interrupt flag clear register (SHRTIMER_STxINTC) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH1ONAI CH1OAIF CH0ONAI CH0OAIF Reserved DLYIIFC RSTIFC...
Page 674 GD32E51x User Manual CAP1IFC Clear capture 1 interrupt flag 0: No effect 1: Clear capture 1 interrupt flag (CAP1IF in SHRTIMER_STxINTF register) CAP0IFC Clear capture 0 interrupt flag 0: No effect 1: Clear capture 0 interrupt flag (CAP0IF in SHRTIMER_STxINTF register) UPIFC Clear update interrupt flag 0: No effect...
Page 675 GD32E51x User Manual CH1ONAI CH0ONAI Reserved DLYIIE RSTIE CH1OAIE CH0OAIE CAP1IE CAP0IE UPIE Reserved REPIE CMP3IE CMP2IE CMP1IE CMP0IE Bits Fields Descriptions Reserved Must be kept at reset value DLYIDEN Delayed IDLE mode entry DMA request enable 0: disabled 1: enabled RSTDEN Counter reset DMA request enable 0: disabled...
Page 676 GD32E51x User Manual 1: enabled CMP2DEN Compare 2 DMA request enable 0: disabled 1: enabled CMP1DEN Compare 1 DMA request enable 0: disabled 1: enabled CMP0DEN Compare 0 DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value DLYIIE Delayed IDLE mode entry interrupt enable 0: disabled...
Page 677 GD32E51x User Manual Reserved Must be kept at reset value REPIE Repetition interrupt enable 0: disabled 1: enabled CMP3IE Compare 3 interrupt enable 0: disabled 1: enabled CMP2IE Compare 2 interrupt enable 0: disabled 1: enabled CMP1IE Compare 1 interrupt enable 0: disabled 1: enabled CMP0IE...
Page 678 GD32E51x User Manual SHRTIMER Slave_TIMERx counter auto reload register (SHRTIMER_STxCAR) Address offset: 0x14 Reset value: 0x0000 FFDF This register has to be accessed by word(32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter.
Page 679 GD32E51x User Manual This bit-field specifies the repetition event generation rate. When the repetition counter had count down to zero, the coming roll-over event in continuous mode or reset event will generate a repetition event. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 680 GD32E51x User Manual CMP0VAL[15:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:16 CREP[7:0] Counter repetition value This bit-field is an alias from the CREP[7:0] in the SHRTIMER_STxCREP 15:0 CMP0VAL[15:0] Compare 0 value This bit-field is an alias from the CMP0VAL[15:0] in the SHRTIMER_STxCMP0V register SHRTIMER Slave_TIMERx compare 1 value register (SHRTIMER_STxCMP1V) Address offset: 0x24...
Page 681 GD32E51x User Manual This register has to be accessed by word(32-bit) Reserved CMP2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP2VAL[15:0] Compare 2 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 682 GD32E51x User Manual (1) The minimum value must be greater than or equal to 3 t . For example: SHRTIMER_CK CARL[15:0] >= 0x60 when CNTCKDIV[3:0] = 4’b0000. (2) The maximum value must be less than or equal to 0xFFFF – (1 t ).
Page 683 GD32E51x User Manual This bit-field indicates the counter value corresponding to the last capture event. And this bit-field is read-only. Note: For counter clock division below 32 (CNTCKDIV[2:0] < 5), the least significant bits of the counter are not significant. They cannot be written and read 0. SHRTIMER Slave_TIMERx dead-time control register (SHRTIMER_STxDTCTL) Address offset: 0x38 Reset value: 0x0000 0000...
Page 684 GD32E51x User Manual This bit-field controls the dead-time value of the following a falling edge of output prepare signal (OyPRE,y=0,1). DTFvalue = DTFCFG[15:0]x t = 1/ f SHRTIMER_DTGCK SHRTIMER_DTGCK SHRTIMER_DTGCK Writing this bit-field can change the low 9-bits of DTFCFG[15:0]. Note: (1) The bit-field DTFCFG[15:9] is in SHRTIMER_STxACTL register.
Page 685 GD32E51x User Manual 1: The sign of rising edge dead-time value is negative. Note: This bit cannot be modified when DTRSPROT or DTRSVPROT bit in SHRTIMER_STxDTCTL register is set. DTRCFG[8:0] Rising edge dead-time value This bit-field controls the dead-time value of the following a rising edge of output prepare signal (OyPRE,y=0,1).
Page 686 GD32E51x User Manual External event 6 generates channel 0 “set request” CH0SEXEV6 Refer to CH0SEXEV0 description. External event 5 generates channel 0 “set request” CH0SEXEV5 Refer to CH0SEXEV0 description. External event 4 generates channel 0 “set request” CH0SEXEV4 Refer to CH0SEXEV0 description. External event 3 generates channel 0 “set request”...
Page 687 GD32E51x User Manual 1: The event can generate “set request”. Master_TIMER compare 3 event generates channel 0 “set request” CH0SMTCMP3 When this bit is set, Master_TIMER compare 3 event can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”.
Page 688 GD32E51x User Manual Slave_TIMERx period event generates channel 0 “set request” CH0SPER When this bit is set, Slave_TIMERx period event can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”. Slave_TIMERx reset event generates channel 0 “set request” CH0SRST When this bit is set, Slave_TIMERx reset event from synchronous input and software can generate channel 0 “set request”.
Page 689 GD32E51x User Manual Refer to CH0RSEXEV0 description. External event 7 generates channel 0 “reset request” CH0RSEXEV7 Refer to CH0RSEXEV0 description. External event 6 generates channel 0 “reset request” CH0RSEXEV6 Refer to CH0RSEXEV0 description. External event 5 generates channel 0 “reset request” CH0RSEXEV5 Refer to CH0RSEXEV0 description.
Page 690 GD32E51x User Manual Slave_TIMERx interconnection event 0 generates channel 0 “reset request” CH0RSSTEV0 When this bit is set, Slave_TIMERx interconnection event 0 can generate channel “reset request”. Refer to Table 19-5. Slave_TIMER interconnection event. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”.
Page 691 GD32E51x User Manual 1: The event can generate “reset request”. Slave_TIMERx compare 1 event generates channel 0 “reset request” CH0RSCMP1 When this bit is set, Slave_TIMERx compare 1 event can generate channel “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”.
Page 692 GD32E51x User Manual CH1SST CH1SST CH1SST CH1SST CH1SMT CH1SMT CH1SMT CH1SMT CH1SMT CH1SCM CH1SCM CH1SCM CH1SCM CH1SPE CH1SRS CH1SSE CMP3 CMP2 CMP1 CMP0 Bits Fields Descriptions Update event generates channel 1 “set request” CH1SUP When this bit is set, update event can generate “set request”. 0: The event cannot generate “set request”.
Page 693 GD32E51x User Manual Refer to CH1SSTEV0 description. Slave_TIMERx interconnection event 5 generates channel 1 “set request” CH1SSTEV5 Refer to CH1SSTEV0 description. Slave_TIMERx interconnection event 4 generates channel 1 “set request” CH1SSTEV4 Refer to CH1SSTEV0 description. Slave_TIMERx interconnection event 3 generates channel 1 “set request” CH1SSTEV3 Refer to CH1SSTEV0 description.
Page 694 GD32E51x User Manual Slave_TIMERx compare 3 event generates channel 1 “set request” CH1SCMP3 When this bit is set, Slave_TIMERx compare 3 event can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”. Slave_TIMERx compare 2 event generates channel 1 “set request”...
Page 695 GD32E51x User Manual CH1RSU CH1RSE CH1RSE CH1RSE CH1RSE CH1RSE CH1RSE CH1RSE CH1RSE CH1RSE CH1RSE CH1RSS CH1RSS CH1RSS CH1RSS CH1RSS XEV9 XEV8 XEV7 XEV6 XEV5 XEV4 XEV3 XEV2 XEV1 XEV0 TEV8 TEV7 TEV6 TEV5 TEV4 CH1RSS CH1RSS CH1RSS CH1RSS CH1RSM CH1RSM CH1RSM CH1RSM CH1RSM...
Page 696 GD32E51x User Manual Refer to CH1RSSTEV0 description. Slave_TIMERx interconnection event 7 generates channel 1 “reset request” CH1RSSTEV7 Refer to CH1RSSTEV0 description. Slave_TIMERx interconnection event 6 generates channel 1 “reset request” CH1RSSTEV6 Refer to CH1RSSTEV0 description. Slave_TIMERx interconnection event 5 generates channel 1 “reset request” CH1RSSTEV5 Refer to CH1RSSTEV0 description.
Page 697 GD32E51x User Manual 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Master_TIMER period event generates channel 1 “reset request” CH1RSMTPER In continuous mode, the Master_TIMER counter roll-over event can generate channel “reset request”. In single pulse mode, the Master_TIMER reset event can generate channel “reset request”.
Page 698 GD32E51x User Manual This bit is set by software and cleared by hardware automatically. When this bit is set, it will generate “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Note: This bit is not preloaded SHRTIMER Slave_TIMERx external event filter configuration register 0 (SHRTIMER_STxEXEVFCFG0) Address offset: 0x4C...
Page 699 GD32E51x User Manual Reserved Must be kept at reset value 10:7 EXEV1FM[3:0] External event 1 filter mode Refer to EXEV0FM[3:0] description. EXEV1MEEN External event 1 memorized enable Refer to EXEV0MEEN description. Reserved Must be kept at reset value EXEV0FM[3:0] External event 0 filter mode In blanking mode, the external event is ignored if it occurs during a blank.
Page 700 GD32E51x User Manual 0: External event memory disable. 1: External event memory enable. The memorized event is generated as soon as the blanking period or windowing period is completed. Note: (1) This bit-field must not be modified once the counter is enabled (STxCEN bit set) (2) When this bit is set, a timeout event can be generated in window mode.
Page 701 GD32E51x User Manual Reserved Must be kept at reset value 10:7 EXEV6FM[3:0] External event 6 filter mode Refer to EXEV0FM[3:0] in SHRTIMER_STxEXEVFCFG0 description. EXEV6MEEN External event 6 memorized enable Refer to EXEV0MEEN in SHRTIMER_STxEXEVFCFG0 description. Reserved Must be kept at reset value EXEV5FM[3:0] External event 5 filter mode Refer to EXEV0FM[3:0] in SHRTIMER_STxEXEVFCFG0 description.
Page 702 GD32E51x User Manual Refer to ST3CMP0RST description. ST3CMP1RST Slave_TIMER3 compare 1 event resets counter Refer to ST3CMP0RST description. ST3CMP0RST Slave_TIMER3 compare 0 event resets counter This bit specifies whether the Slave_TIMER3 compare 0 event can reset the counter. 0: Slave_TIMER3 compare 0 event do not reset counter 1: Slave_TIMER3 compare 0 event resets counter ST2CMP3RST Slave_TIMER2 compare 3 event resets counter...
Page 703 GD32E51x User Manual EXEV4RST External event 4 resets counter Refer to EXEV0RST description. EXEV3RST External event 3 resets counter Refer to EXEV0RST description. EXEV2RST External event 2 resets counter Refer to EXEV0RST description. EXEV1RST External event 1 resets counter Refer to EXEV0RST description. EXEV0RST External event 0 resets counter This bit specifies whether the External event 0 can reset the counter.
Page 704 GD32E51x User Manual Reserved Must be kept at reset value For Slave_TIMER1 ST4CMP ST4CMP ST4CMP ST3CMP ST3CMP ST3CMP ST2CMP ST2CMP ST2CMP ST0CMP ST0CMP ST0CMP EXEV9R EXEV8R EXEV7R Reserved 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST EXEV6R EXEV5R EXEV4R...
Page 705 GD32E51x User Manual This bit specifies whether the Slave_TIMER2 compare 0 event can reset the counter. 0: Slave_TIMER2 compare 0 event do not reset counter 1: Slave_TIMER2 compare 0 event resets counter ST0CMP3RST Slave_TIMER0 compare 3 event resets counter Refer to ST0CMP0RST description. ST0CMP1RST Slave_TIMER0 compare 1 event resets counter Refer to ST0CMP0RST description.
Page 706 GD32E51x User Manual Refer to MTCMP0RST description MTCMP2RST Master_TIMER compare 2 event resets counter Refer to MTCMP0RST description MTCMP1RST Master_TIMER compare 1 event resets counter Refer to MTCMP0RST description MTCMP0RST Master_TIMER compare 0 event resets counter This bit specifies whether the Master_TIMER compare 0 event can reset the counter.
Page 707 GD32E51x User Manual Reserved Must be kept at reset value ST4CMP3RST Slave_TIMER4 compare 3 event resets counter Refer to ST4CMP0RST description. ST4CMP1RST Slave_TIMER4 compare 1 event resets counter Refer to ST4CMP0RST description. ST4CMP0RST Slave_TIMER4 compare 0 event resets counter This bit specifies whether the Slave_TIMER4 compare 0 event can reset the counter.
Page 708 GD32E51x User Manual EXEV9RST External event 9 resets counter Refer to EXEV0RST description. EXEV8RST External event 8 resets counter Refer to EXEV0RST description. EXEV7RST External event 7 resets counter Refer to EXEV0RST description. EXEV6RST External event 6 resets counter Refer to EXEV0RST description. EXEV5RST External event 5 resets counter Refer to EXEV0RST description.
Page 709 GD32E51x User Manual 1: Master_TIMER period event resets counter CMP3RST Slave_TIMER2 compare 3 event resets counter Refer to CMP1RST description CMP1RST Slave_TIMER2 compare 1 event resets counter This bit specifies whether the compare 1 event can reset the counter. 0: Compare 1 event do not reset counter 1: Compare 1 event resets counter UPRST Slave_TIMER2 update event resets counter...
Page 710 GD32E51x User Manual Refer to ST2CMP0RST description. ST2CMP0RST Slave_TIMER2 compare 0 event resets counter This bit specifies whether the Slave_TIMER2 compare 0 event can reset the counter. 0: Slave_TIMER2 compare 0 event do not reset counter 1: Slave_TIMER2 compare 0 event resets counter ST1CMP3RST Slave_TIMER1 compare 3 event resets counter Refer to ST1CMP0RST description.
Page 711 GD32E51x User Manual EXEV3RST External event 3 resets counter Refer to EXEV0RST description. EXEV2RST External event 2 resets counter Refer to EXEV0RST description. EXEV1RST External event 1 resets counter Refer to EXEV0RST description. EXEV0RST External event 0 resets counter This bit specifies whether the External event 0 can reset the counter. 0: External event 0 do not reset counter.
Page 712 GD32E51x User Manual For Slave_TIMER4 ST3CMP ST3CMP ST3CMP ST2CMP ST2CMP ST2CMP ST1CMP ST1CMP ST1CMP ST0CMP ST0CMP ST0CMP EXEV9R EXEV8R EXEV7R Reserved 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST EXEV6R EXEV5R EXEV4R EXEV3R EXEV2R EXEV1R EXEV0R MTCMP3 MTCMP2 MTCMP1...
Page 713 GD32E51x User Manual 1: Slave_TIMER1 compare 0 event resets counter ST0CMP3RST Slave_TIMER0 compare 3 event resets counter Refer to ST0CMP0RST description. ST0CMP1RST Slave_TIMER0 compare 1 event resets counter Refer to ST0CMP0RST description. ST0CMP0RST Slave_TIMER0 compare 0 event resets counter This bit specifies whether the Slave_TIMER0 compare 0 event can reset the counter.
Page 714 GD32E51x User Manual MTCMP1RST Master_TIMER compare 1 event resets counter Refer to MTCMP0RST description MTCMP0RST Master_TIMER compare 0 event resets counter This bit specifies whether the Master_TIMER compare 0 event can reset the counter. 0: Master_TIMER compare 0 event do not reset counter 1: Master_TIMER compare 0 event resets counter MTPERRST Master_TIMER period event resets counter...
Page 715 GD32E51x User Manual 10:7 CSFSTPW[3:0] First carrier-signal pulse width This bit-field defines the first carrier-signal pulse width following a rising edge on channel output prepare signal(CHxOPRE). = (CSFSTPW[3:0]+1) x t =16 x t CSFSTPW SHRTIMER_CSGCK SHRTIMER_CSGCK SHRTIMER_CK 0000: t CSFSTPW SHRTIMER_CSGCK 0001: t = 2*t...
Page 716 GD32E51x User Manual Bits Fields Descriptions CP0BST4CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER4 This bit reserved only in Slave_TIMER4. Refer to CP0BST0CMP1 description. CP0BST4CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER4 This bit reserved only in Slave_TIMER4. Refer to CP0BST0CMP0 description.
Page 717 GD32E51x User Manual This bit reserved only in Slave_TIMER1. Refer to CP0BST0CMP1 description. CP0BST1CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER1 This bit reserved only in Slave_TIMER1. Refer to CP0BST0CMP0 description. CP0BST1NA Capture 0 triggered by ST1CH0_O output active to inactive transition This bit reserved only in Slave_TIMER1.
Page 718 GD32E51x User Manual Refer to CP0BEXEV0 description. CP0BEXEV5 Capture 0 triggered by external event 5 Refer to CP0BEXEV0 description. CP0BEXEV4 Capture 0 triggered by external event 4 Refer to CP0BEXEV0 description. CP0BEXEV3 Capture 0 triggered by external event 3 Refer to CP0BEXEV0 description. CP0BEXEV2 Capture 0 triggered by external event 2 Refer to CP0BEXEV0 description.
Page 719 GD32E51x User Manual Bits Fields Descriptions CP1BST4CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER4 This bit reserved only in Slave_TIMER4. Refer to CP1BST0CMP1 description. CP1BST4CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER4 This bit reserved only in Slave_TIMER4. Refer to CP1BST0CMP0 description.
Page 720 GD32E51x User Manual CP1BST1CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER1 This bit reserved only in Slave_TIMER1. Refer to CP1BST0CMP1 description. CP1BST1CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER1 This bit reserved only in Slave_TIMER1. Refer to CP1BST0CMP0 description. CP1BST1NA Capture 1 triggered by ST1CH0_O output active to inactive transition This bit reserved only in Slave_TIMER1.
Page 721 GD32E51x User Manual CP1BEXEV6 Capture 1 triggered by external event 6 Refer to CP1BEXEV0 description. CP1BEXEV5 Capture 1 triggered by external event 5 Refer to CP1BEXEV0 description. CP1BEXEV4 Capture 1 triggered by external event 4 Refer to CP1BEXEV0 description. CP1BEXEV3 Capture 1 triggered by external event 3 Refer to CP1BEXEV0 description.
Page 722 GD32E51x User Manual DLYISME BMCH1D CH0CSE BMCH0IE Reserved DLYISCH[2:0] DTEN CH0FLTOS[1:0] ISO0 CH0P Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value BMCH1DTI Channel 1 dead-time insert in bunch mode In bunch mode, a dead-time can be inserted before output entering the IDLE state. 0: The output enter IDLE immediately.
Page 723 GD32E51x User Manual This bit specifies the channel 1 output signal polarity. 0: Channel 1 active high 1: Channel 1 active low Note: This bit must not be modified once the counter is enabled (STxCEN bit is set) 16:13 Reserved Must be kept at reset value 12:10 DLYISCH[2:0]...
Page 724 GD32E51x User Manual set) or its outputs are enabled and controlled by another timer. BMCH0DTI Channel 0 dead-time insert in bunch mode In bunch mode, a dead-time can be inserted before output entering the IDLE state. 0: The output enter IDLE immediately. 1: Dead-time is inserted before entering the IDLE state.
Page 725 GD32E51x User Manual SHRTIMER Slave_TIMERx fault control register (SHRTIMER_STxFLTCTL) Address offset: 0x68 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) FLTENP Reserved Reserved FLT4EN FLT3EN FLT2EN FLT1EN FLT0EN Bits Fields Descriptions FLTENPROT Protect fault enable This bit-field specifies whether the write protection function is enable or not. This bit is write-once.
Page 726 GD32E51x User Manual SHRTIMER Slave_TIMERx additional control register (SHRTIMER_STxACTL) Address offset: 0x7C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DTFCFG[15:9] Reserved CNTCKDI DTRCFG[15:9] Reserved Reserved V[3] Bits Fields Descriptions 31:25 DTFCFG[15:9] Falling edge dead-time value configure This bit-field controls the value of the dead-time following a falling edge of output prepare signal (OyPRE,y=0,1): DTFvalue = DTFCFG[15:0]x t SHRTIMER_DTGCK...
Page 727: Common Registers
GD32E51x User Manual Note: The CNTCKDIV[3:0] bit-field cannot be modified once the timer is enabled Reserved Must be kept at reset value Common registers 19.5.3. SHRTIMER Master_TIMER registers base address: 0x4001 7780 SHRTIMER control register 0 (SHRTIMER_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved...
Page 728 GD32E51x User Manual 101: Slaver_TIMER4 update event Other values are reserved 21:19 ADTG1USRC[2:0] SHRTIMER_ADCTRIG1 update source This bit-field can be configured by software to specify the the source to update the SHRTIMER_ADCTRIGS1 register. 000: Master_TIMER update event 001: Slaver_TIMER0 update event 010: Slaver_TIMER1 update event 011: Slaver_TIMER2 update event 100: Slaver_TIMER3 update event...
Page 729 GD32E51x User Manual This bit is used to enable or disable the update event generation. 0: Update event enable. 1: Update event disable. MTUPDIS Master_TIMER update disable This bit is used to enable or disable the update event generation. 0: Update event enable. 1: Update event disable.
Page 730 GD32E51x User Manual 0: No effect. 1: The counter is reset. ST0SRST Slave_TIMER0 software reset This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is reset. 0: No effect. 1: The counter is reset. MTSRST Master_TIMER software reset This bit can be set by software, and cleared by hardware automatically.
Page 731 GD32E51x User Manual pending update request is cancelled. 0: No effect. 1: update generated. MTSUP Master_TIMER software update This bit can be set by software, and cleared by hardware automatically. When this bit is set, the content of shadow register is transferred to the active register and any pending update request is cancelled.
Page 732 GD32E51x User Manual 0: No system fault interrupt occurred 1: System fault completed interrupt occurred FLT4IF Fault 4 interrupt flag Refer to FLT0IF description. FLT3IF Fault 3 interrupt flag Refer to FLT0IF description. FLT2IF Fault 2 interrupt flag Refer to FLT0IF description. FLT1IF Fault 1 interrupt flag Refer to FLT0IF description.
Page 733 GD32E51x User Manual 1: Clear DLL calibration completed interrupt flag 15:6 Reserved Must be kept at reset value SYSFLTIFC Clear system fault interrupt flag Writing 1 to this bit clears the SYSFLTIF in SHRTIMER_INTF register. 0: No effect 1: Clear system fault completed interrupt flag FLT4IFC Clear fault 4 interrupt flag Writing 1 to this bit clears the FLT4IF in SHRTIMER_INTF register.
Page 734 GD32E51x User Manual 31:18 Reserved Must be kept at reset value BMPERIE Bunch mode period interrupt enable 0: Disabled 1: Enabled DLLCALIE DLL calibration completed interrupt enable 0: disabled 1: enabled 15:6 Reserved Must be kept at reset value SYSFLTIE System fault interrupt enable 0: disabled 1: enabled...
Page 735 GD32E51x User Manual Note: The disable status corresponds to both Idle and Fault states which is given by ST3CH1DISF bit in the SHRTIMER_CHOUTDISF register. ST3CH0EN Slave_TIMER3 channel 0 output (ST3CH0_O) enable Refer to ST0CH0EN description. Note: The disable status corresponds to both Idle and Fault states which is given by ST3CH0DISF bit in the SHRTIMER_CHOUTDISF register.
Page 736 GD32E51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved ST4CH1D ST4CH0 ST3CH1 ST3CH0D ST2CH1 ST2CH0 ST1CH1D ST1CH0 ST0CH1 ST0CH0D Reserved Bits Fields Descriptions 31:10 Reserved Must be kept at reset value ST4CH1DIS Slave_TIMER4 channel 1 output (ST4CH1_O) disable. Refer to ST0CH0DIS description.
Page 737 GD32E51x User Manual SHRTIMER channel output disable flag register (SHRTIMER_CHOUTDISF) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved ST4CH1D ST4CH0 ST3CH1 ST3CH0D ST2CH1 ST2CH0 ST1CH1D ST1CH0 ST0CH1 ST0CH0D Reserved DISF DISF DISF DISF DISF DISF...
Page 738 GD32E51x User Manual SHRTIMER bunch mode control register (SHRTIMER_BMCTL) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) BMOPTF Reserved BMST4 BMST3 BMST2 BMST1 BMST0 BMMT rc_w0 Reserved BMSE BMPSC[3:0] BMCLKS[3:0] BMCTN BMEN Bits Fields Descriptions BMOPTF...
Page 739 GD32E51x User Manual 1: Slave_TIMER2 counter clock(SHRTIMER_PSCCK) is stopped and the counter is reset Note: (1) This bit cannot be changed while the bunch mode is enabled. (2) This bit must not be set when the balanced IDLE mode is active (DLYISCH[2:0] = 3’bx11 in SHRTIMER_STxCHOCTL register).
Page 740 GD32E51x User Manual BMPSC[3:0] SHRTIMER_BMCNTCK SHRTIMER_CK 0000: f SHRTIMER_BMCNTCK SHRTIMER_CK 0001: f SHRTIMER_BMCNTCK SHRTIMER_CK 0010: f SHRTIMER_BMCNTCK SHRTIMER_CK 0011: f SHRTIMER_BMCNTCK SHRTIMER_CK 0100: f SHRTIMER_BMCNTCK SHRTIMER_CK 0101: f SHRTIMER_BMCNTCK SHRTIMER_CK 0110: f SHRTIMER_BMCNTCK SHRTIMER_CK 0111: f /128 SHRTIMER_BMCNTCK SHRTIMER_CK 1000: f /256 SHRTIMER_BMCNTCK SHRTIMER_CK...
Page 741 GD32E51x User Manual the bit is set. Writing this bit to 0 will terminate bunch mode. 0: Bunch mode disable. 1: Bunch mode enable. SHRTIMER bunch mode start trigger register (SHRTIMER_BMSTRG) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) ST3EXEV ST0EXEV ST4CMP...
Page 742 GD32E51x User Manual operation. 0：No effect on bunch mode operation. 1：Slave_TIMER0 period event following external event 6 is starting bunch mode operation. ST4CMP1 Slave_TIMER4 compare 1 event triggers bunch mode operation Refer to MTCMP1 description. ST4CMP0 Slave_TIMER4 compare 0 event triggers bunch mode operation Refer to MTCMP0 description.
Page 743 GD32E51x User Manual Refer to MTRST description. ST0CMP1 Slave_TIMER0 compare 1 event triggers bunch mode operation Refer to MTCMP1 description. ST0CMP0 Slave_TIMER0 compare 0 event triggers bunch mode operation Refer to MTCMP0 description. ST0REP Slave_TIMER0 repetition event triggers bunch mode operation Refer to MTREP description.
Page 744 GD32E51x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved BMCMPVAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 BMCMPVAL[15:0] Bunch mode compare value This bit-field contains value to be compared to the BM-counter and defines the duration of the IDLE.
Page 745 GD32E51x User Manual SHRTIMER external event configuration register 0 (SHRTIMER_EXEVCFG0) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEV2E Reserved EXEV4EG[1:0] EXEV4P EXEV4SRC[1:0] Reserved EXEV3EG[1:0] EXEV3P EXEV3SRC[1:0] Reserved G[1] EXEV2E EXEV2P EXEV2SRC[1:0] Reserved EXEV1EG[1:0] EXEV1P EXEV1SRC[1:0]...
Page 746 GD32E51x User Manual 10:9 EXEV1EG[1:0] External event 1 edge sensitivity Refer to EXEV0EG[1:0] description. EXEV1P External event 1 polarity Refer to EXEV0P description. EXEV1SRC[1:0] External event 1 source Refer to EXEV0SRC[1:0] description. Reserved Must be kept at reset value EXEV0EG[1:0] External event 0 edge sensitivity This bit-field specifies the polarity of external event 0.
Page 747 GD32E51x User Manual Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:27 EXEV9EG[1:0] External event 9 edge sensitivity Refer to EXEV0EG[1:0] in SHRTIMER_EXEVCFG0 register description. EXEV9P External event 9 polarity Refer to EXEV0P in SHRTIMER_EXEVCFG0 register description. 25:24 EXEV9SRC[1:0] External event 9 source...
Page 748 GD32E51x User Manual EXEV5SRC[1:0] External event 5 source Refer to EXEV0SRC[1:0] in SHRTIMER_EXEVCFG0 register description. SHRTIMER external event digital filter control register (SHRTIMER_EXEVDFCTL) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEVFDIV[2:0] Reserved EXEV9FC[3:0] Reserved EXEV8FC[3:0]...
Page 749 GD32E51x User Manual Refer to EXEV5FC[3:0] description. Reserved Must be kept at reset value EXEV5FC[3:0] External event 5 filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency (f ) used to sample SAMP external event and the length of the digital filter applied to external event.
Page 750 GD32E51x User Manual 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 period event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER4 period event. TRG0ST4C3 SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 3 event Refer to TRG0ST4C1 description. TRG0ST4C2 SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 2 event Refer to TRG0ST4C1 description.
Page 751 GD32E51x User Manual This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER2 compare 1 event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER2 compare 1 event. TRG0ST1RST SHRTIMER_ADCTRIG0 on Slave_TIMER1 reset The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG0.
Page 752 GD32E51x User Manual The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG0. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER0 compare 1 event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER0 compare 1 event. TRG0EXEV4 SHRTIMER_ADCTRIG0 on external event 4 Refer to TRG0EXEV0 description.
Page 753 GD32E51x User Manual SHRTIMER trigger source 1 to ADC register (SHRTIMER_ADCTRIGS1) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) TRG1ST4 TRG1ST4 TRG1ST4 TRG1ST4 TRG1ST3 TRG1ST3 TRG1ST3 TRG1ST3 TRG1ST3 TRG1ST2 TRG1ST2 TRG1ST2 TRG1ST2 TRG1ST2 TRG1ST1 TRG1ST1...
Page 754 GD32E51x User Manual TRG1ST3C3 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event Refer to TRG1ST3C1 description. TRG1ST3C2 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 2 event Refer to TRG1ST3C1 description. TRG1ST3C1 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG1. This bit specifies whether the event can generate the ADC trigger event.
Page 755 GD32E51x User Manual Refer to TRG1ST1C1 description. TRG1ST1C1 SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG1. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event.
Page 756 GD32E51x User Manual 0: No ADC trigger event generated on SHRTIMER Master_TIMER period event. 1: ADC trigger event generated on SHRTIMER Master_TIMER period event. TRG1MTC3 SHRTIMER_ADCTRIG1 on Master_TIMER compare 3 event Refer to TRG1MTC0 description. TRG1MTC2 SHRTIMER_ADCTRIG1 on Master_TIMER compare 2 event Refer to TRG1MTC0 description.
Page 757 GD32E51x User Manual Refer to TRG2ST4C1 description. TRG2ST4C1 SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG2. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 compare 1 event.
Page 758 GD32E51x User Manual This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 reset . 1: ADC trigger event generated on SHRTIMER Slave_TIMER1 reset. TRG2ST1PER SHRTIMER_ADCTRIG2 on Slave_TIMER1 period event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG2.
Page 759 GD32E51x User Manual Refer to TRG2EXEV0 description. TRG2EXEV3 SHRTIMER_ADCTRIG2 on external event 3 Refer to TRG2EXEV0 description. TRG2EXEV2 SHRTIMER_ADCTRIG2 on external event 2 Refer to TRG2EXEV0 description. TRG2EXEV1 SHRTIMER_ADCTRIG2 on external event 1 Refer to TRG2EXEV0 description. TRG2EXEV0 SHRTIMER_ADCTRIG2 on external event 0 The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG2.
Page 760 GD32E51x User Manual TRG3ST1 TRG3ST1 TRG3ST0 TRG3ST0 TRG3ST0 TRG3ST0 TRG3EX TRG3EX TRG3EX TRG3EX TRG3EX TRG3MT TRG3MT TRG3MT TRG3MT TRG3MT Bits Fields Descriptions TRG3ST4RST SHRTIMER_ADCTRG3 on Slave_TIMER4 reset The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRG3. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 reset .
Page 761 GD32E51x User Manual 0: No ADC trigger event generated on SHRTIMER Slave_TIMER3 compare 1 event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER3 compare 1 event. TRG3ST2RST SHRTIMER_ADCTRG3 on Slave_TIMER2 reset The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRG3. This bit specifies whether the event can generate the ADC trigger event.
Page 762 GD32E51x User Manual The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRG3. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER0 period event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER0 period event. TRG3ST0C3 SHRTIMER_ADCTRG3 on Slave_TIMER0 compare 3 event Refer to TRG3ST0C1 description.
Page 763 GD32E51x User Manual Refer to TRG3MTC0 description. TRG3MTC0 SHRTIMER_ADCTRG3 on Master_TIMER compare 0 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG3. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Master_TIMER compare 1 event.
Page 764 GD32E51x User Manual Note: CLBPEREN bit and CLBSTRT bit must not be set simultaneously. SHRTIMER fault input configuration register 0 (SHRTIMER_FLTINCFG0) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) FLT3INP FLT3INS FLT3INE FLT2INP FLT2INS FLT2INE...
Page 765 GD32E51x User Manual FLT1INPROT Protect fault 1 input configuration Refer to FLT0INPROT description. 14:11 FLT1INFC[3:0] Fault 1 input filter control Refer to FLT0INFC[3:0] description. FLT1INSRC Fault 1 input source Refer to FLT0INSRC description. FLT1INP Fault 1 input polarity Refer to FLT0INP description. FLT1INEN Fault 1 input enable Refer to FLT0INEN description.
Page 766 GD32E51x User Manual (2) This bit-field cannot be modified when FLT0INPROT has been programmed. FLT0INSRC Fault 0 input source 0: The source of fault 0 input is chip external pin. 1: The source of fault 0 input is chip internal signal(for example comparator) Note: This bit can be written only when FLT0INEN bit is reset.
Page 767 GD32E51x User Manual Note: This bit must be configured before setting any FLTyINEN(y=0..4). 23:8 Reserved Must be kept at reset value FLT4INPROT Protect fault 4 input configuration Refer to FLT0INPROT in SHRTIMER_FLTINCFG0 register description. FLT4INFC[3:0] Fault 4 input filter control Refer to FLT0INFC[3:0] in SHRTIMER_FLTINCFG0 register description.
Page 768 GD32E51x User Manual Refer to MTCTL0 description. MTCREP SHRTIMER_MTCREP update by DMA mode Refer to MTCTL0 description. MTCAR SHRTIMER_MTCAR update by DMA mode Refer to MTCTL0 description. MTCNT SHRTIMER_MTCNT update by DMA mode Refer to MTCTL0 description. MTDMAINTEN SHRTIMER_MTDMAINTEN update by DMA mode Refer to MTCTL0 description.
Page 769 GD32E51x User Manual STxCHOCTL SHRTIMER_STxCHOCTL update by DMA mode Refer to STxCTL0 bit description. STxCSCTL SHRTIMER_STxCSCTL update by DMA mode Refer to STxCTL0 bit description. STxCNTRST SHRTIMER_STxCNTRST update by DMA mode Refer to STxCTL0 bit description. STxEXEVFCFG1 SHRTIMER_STxEXEVFCFG1update by DMA mode Refer to STxCTL0 bit description.
Page 770 GD32E51x User Manual Refer to STxCTL0 bit description. STxINTC SHRTIMER_STxINTC update by DMA mode Refer to STxCTL0 bit description. STxCTL0 SHRTIMER_STxCTL0 update by DMA mode This bit defines if the SHRTIMER_STxCTL0 register is updated by the DMA mode. 0: SHRTIMER_STxCTL0 register is not updated by DMA mode. 1: SHRTIMER_STxCTL0 register is updated DMA mode.
Page 771: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32E51x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) Universal synchronous/asynchronous receiver /transmitter 20.1. (USARTx, x=0..4) Overview 20.1.1. The USART provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK(PCLK1 or PCLK2) to produce a dedicated baud rate clock for the USART transmitter and receiver.
Page 772: Function Overview
GD32E51x User Manual  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface. – Character mode (T=0). – Block mode (T=1). – Direct and inverse convention.  Multiprocessor communication. – Enter into mute mode if address match does not occur. –...
Page 773: Figure 20-1. Usart Module Block Diagram
GD32E51x User Manual Figure 20-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controler Flow nCTS Controler USART Control Registers USART Address Transmitter Transimit clock...
Page 774 GD32E51x User Manual STB[1:0] stop bit length (bit) usage description Smartcard mode for receiving Normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 775: Figure 20-3. Usart Transmit Procedure
GD32E51x User Manual can be output through the CK pin. After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_DATA when the TBE bit in the USART_STAT0 register is asserted.
Page 776: Figure 20-4. Receiving A Frame Bit By Oversampling Method
GD32E51x User Manual USART receiver After power on, the USART receiver can be enabled by the following procedure: Set the UEN bit in USART_CTL0 to enable the USART. Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1 to configure the number of stop bits.
Page 777 GD32E51x User Manual If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value. If they are not the same, the parity error (PERR) bit in USART_STAT0 register will be set.
Page 778: Figure 20-5. Configuration Step When Using Dma For Usart Transmission
GD32E51x User Manual Figure 20-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_DATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 779: Figure 20-6. Configuration Steps When Using Dma For Usart Reception
GD32E51x User Manual Figure 20-6. Configuration steps when using DMA for USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 780: Figure 20-8. Hardware Flow Control
GD32E51x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared by reading the USART_DATA register.
Page 781: Figure 20-9. Break Frame Occurs During Idle State
GD32E51x User Manual are the same as the ADDR[3:0] bits in the USART_CTL1 register, the hardware will clear the RWU bit and exits the mute mode. The RBNE bit will be set when the frame that wakes up the USART. The status bits are available in the USART_STAT0 register. If the LSB 4 bits of an address frame differ from the ADDR[3:0] bits in the USART_CTL1 register, the hardware sets the RWU bit and enters mute mode automatically.
Page 782: Figure 20-10. Break Frame Occurs During A Frame
GD32E51x User Manual Figure 20-10. Break frame occurs during a frame frame0 frame1 frame2 RX pin 1 frame time FERR data0 data1 data2 USART_DATA LBDF Synchronous mode The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1.
Page 783: Figure 20-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32E51x User Manual Figure 20-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 784: Figure 20-14. Irda Data Modulation
GD32E51x User Manual pulse if the pulse width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block.
Page 785: Figure 20-15. Iso7816-3 Frame Format
GD32E51x User Manual The smartcard mode is a half-duplex communication protocol. When connected to a smartcard, the TX pin must be configured as open drain mode, and an external pull-up resistor will be needed, which drives a bidirectional line that is also driven by the smartcard. The data frame consists of 1 start bit, 9 data bits (1 parity bit included) and 1.5 stop bits.
Page 786 GD32E51x User Manual Block (T=1) mode In block (T=1) mode, the NKEN bit in the USART_CTL2 register should be cleared to deactivate the NACK transmission. When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. This timeout period is expressed in baud time units.
Page 787: Table 20-3. Usart Interrupt Requests
GD32E51x User Manual USART interrupts The USART interrupt events and flags are listed in Table 20-3. USART interrupt requests. Table 20-3. USART interrupt requests Enable Interrupt event Event flag Control register Control bit Transmit data buffer empty USART_CTL0 TBEIE CTS toggled flag CTSF USART_CTL2 CTSIE...
Page 788: Figure 20-16. Usart Interrupt Mapping Diagram
GD32E51x User Manual Figure 20-16. USART interrupt mapping diagram IDLEF IDLEIE ORERR RBNEIE PERR PEIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT RBNE RBNEIE TCIE TBEIE CTSF CTSIE...
Page 789: Register Definition
GD32E51x User Manual Register definition 20.1.4. USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register 0 (USART_STAT0) Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 790 GD32E51x User Manual 0: Transmit data buffer is not empty. 1: Transmit data buffer is empty. Transmission complete This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
Page 791 GD32E51x User Manual Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one. 0: The USART does not detect a framing error. 1: The USART has detected a framing error. PERR Parity error flag This bit is set when the parity bit of a receive frame does not match the expected parity value.
Page 792 GD32E51x User Manual INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value. 15:4 INTDIV[11:0] Integer part of baud-rate divider. FRADIV[3:0] Fraction part of baud-rate divider. Control register 0 (USART_CTL0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 793 GD32E51x User Manual 0: Parity check function disabled. 1: Parity check function enabled. Parity mode 0: Even parity. 1: Odd parity. PERRIE Parity error interrupt enable. If this bit is set, an interrupt occurs when the PERR bit in USART_STAT0 is set. 0: Parity error interrupt is disabled.
Page 794 GD32E51x User Manual 0: Receiver in active mode. 1: Receiver in mute mode. SBKCMD Send break command Software can set this to send a break frame. Hardware resets this bit automatically when the break frame has been transmitted. 0: Do not transmit a break frame. 1: Transmit a break frame.
Page 795 GD32E51x User Manual CK phase This bit specifies the phase of the CK pin in synchronous mode. 0: The capture edge of the LSB bit is the first edge of CK pin. 1: The capture edge of the LSB bit is the second edge of CK pin. This bit is reserved for UART3/4.
Page 796 GD32E51x User Manual This bit selects the sample method. The noise detection flag (NF) is disabled when the one sample bit method is selected. 0: Three sample bit method. 1: One sample bit method. CTSIE CTS interrupt enable If this bit is set, an interrupt occurs when the CTSF bit in USART_STAT0 is set. 0: CTS interrupt is disabled.
Page 797 GD32E51x User Manual 1: Half duplex mode is enabled. IRLP IrDA low-power This bit selects low-power mode of IrDA mode. 0: Normal mode. 1: Low-power mode. IREN IrDA mode enable This bit enables the IrDA mode of USART. 0: IrDA disabled. 1: IrDA enabled.
Page 798 GD32E51x User Manual When the USART works in IrDA normal mode, these bits must be set to 00000001. When the USART smartcard mode is enabled, the PSC [4:0] bits specify the division factor that is used to divide the peripheral clock (APB1/APB2) to generate the smartcard clock (CK).
Page 799 GD32E51x User Manual RINV RX pin level inversion This bit specifies the polarity of the RX pin. 0: RX pin signal values are not inverted. 1: RX pin signal values are inverted. This bit field cannot be written when the USART is enabled (UEN=1). Reserved Must be kept the reset value.
Page 800 GD32E51x User Manual Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in Smartcard T=1 Reception. Its value equals to the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1. This value, which must be programmed only once per received block, can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field).
Page 801 GD32E51x User Manual This bit is set when the USART is receiving a data frame. 0: USART reception path is idle. 1: USART reception path is working. 15:13 Reserved Must be kept the reset value. End of block flag This bit is set when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4.
Page 802 GD32E51x User Manual 1: collision detected in halfduplex mode. Reserved Forced by hardware to 0. CDEN Collision detection enable 0: disable 1: enable Reserved Forced by hardware to 0.
Page 803: Universal Synchronous/Asynchronous Receiver /Transmitter (Usartx, X=5)
GD32E51x User Manual Universal synchronous/asynchronous receiver /transmitter 20.2. (USARTx, x=5) Overview 20.2.1. The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK2, CK_USART5) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 804: Function Overview
GD32E51x User Manual  LIN break generation and detection  IrDA support Synchronous mode and transmitter clock output for synchronous transmission   ISO 7816-3 compliant smartcard interface Character mode (T=0) – Block mode (T=1) – Direct and inverse convention –...
Page 805: Figure 20-17. Usart Module Block Diagram
GD32E51x User Manual Figure 20-17. USART module block diagram CPU/DMA Transmit Read Write Shift Buffer Buffer Register SW_RX IrDA Block Receive Shift Read FiFO Register USART Guard Time and Prescaler Register CK Controler USART Control Registers USART Address Transmitter Transimit clock Controler Receiver...
Page 806 GD32E51x User Manual STB[1:0] stop bit length (bit) usage description Smartcard mode for receiving Normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 807: Figure 20-19. Usart Transmit Procedure
GD32E51x User Manual can output through the CK pin. After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_TDATA when the TBE bit in the USART_STAT register is asserted.
Page 808 GD32E51x User Manual The break frame is sent when the SBKCMD bit is set, and SBKCMD bit is reset after the transmission. USART receiver After power on, the USART receiver can be enabled by the following procedure: Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1.
Page 809: Figure 20-20. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32E51x User Manual Figure 20-20. Oversampling method of a receive frame bit (OSB=0) If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value.
Page 810: Figure 20-21. Configuration Step When Using Dma For Usart Transmission
GD32E51x User Manual When DMA is used for USART transmission, DMA transfers data from internal SRAM to the transmit data buffer of the USART. The configuration step are shown in Figure 20-21. Configuration step when using DMA for USART transmission. Figure 20-21.
Page 811: Figure 20-22. Configuration Step When Using Dma For Usart Reception
GD32E51x User Manual Figure 20-22. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 812: Figure 20-24. Hardware Flow Control
GD32E51x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 813 GD32E51x User Manual is detected on the RX pin, the IDLEF bit in USART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 814: Figure 20-25. Break Frame Occurs During Idle State
GD32E51x User Manual Figure 20-25. Break frame occurs during idle state frame0 frame1 frame2 RX pin 1 frame time FERR data0 00000000 data2 data1 USART_RDATA LBDF As shown in Figure 20-26. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame.
Page 815: Figure 20-27. Example Of Usart In Synchronous Mode
GD32E51x User Manual Figure 20-27. Example of USART in synchronous mode Figure 20-28. 8-bit format USART synchronous waveform (CLEN=1) Idle frame data (8bit) Idle CK pin (CPL=0, CPH=0) CK pin(CPL=1, CPH=0) CK pin (CPL=0, CPH=1) CK pin (CPL=1, CPH=1) Start Master data output bit0 bit1...
Page 816: Figure 20-29. Irda Sir Endec Module
GD32E51x User Manual Figure 20-29. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 817: Figure 20-31. Iso7816-3 Frame Format
GD32E51x User Manual Half-duplex communication mode The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 818 GD32E51x User Manual current frame by pulling down the TX pin during the last 1 bit time of the stop bits. The USART can automatically resend data according to the protocol for SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame. At the end of the last repeated character the TC bit is set immediately without guard time.
Page 819 GD32E51x User Manual (0xFF) may be programmed. The real value will be programmed after the reception of the third character. The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set).
Page 820: Figure 20-32. Usart Receive Fifo Structure
GD32E51x User Manual Figure 20-32. USART Receive FIFO structure Rx Module Rx shift register Rx FIFO EN FIFO 0 Rx Buffer FIFO 1 FIFO 2 FIFO 3 If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out.
Page 821: Table 20-6. Usart Interrupt Requests
GD32E51x User Manual Table 20-6. USART interrupt requests Interrupt event Event flag Enable Control bit Transmit data register empty TBEIE Transmission complete TCIE Received data ready to be RBNE read RBNEIE Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE...
Page 822: Figure 20-33. Usart Interrupt Mapping Diagram
GD32E51x User Manual Figure 20-33. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ORERR ERRIE LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 823: Register Definition
GD32E51x User Manual Register definition 20.2.4. USAR5 base address: 0x4001 7000 Control register 0 (USART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE DEA[4:0] DED[4:0] OVSMOD AMIE PCEN PERRIE TBEIE TCIE RBNEIE...
Page 824 GD32E51x User Manual AMIE ADDR match interrupt enable 0: ADDR match interrupt is disabled 1: ADDR match interrupt is enabled Mute mode enable 0: Mute mode disabled 1: Mute mode enabled Word length 0: 8 Data bits 1: 9 Data bits This bit field cannot be written when the USART is enabled (UEN=1).
Page 825 GD32E51x User Manual 1: An interrupt will occur whenever the IDLEF bit is set in USART_STAT. Transmitter enable 0: Transmitter is disabled 1: Transmitter is enabled Receiver enable 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit UESM USART enable in Deep-sleep mode 0: USART not able to wake up the MCU from Deep-sleep mode.
Page 826 GD32E51x User Manual 1: Receiver timeout function enabled 22:20 Reserved Must be kept at reset value. MSBF Most significant bit first 0: Data is transmitted/received with the LSB first 1: Data is transmitted/received with the MSB first This bit field cannot be written when the USART is enabled (UEN=1). DINV Data bit level inversion 0: Data bit signal values are not inverted...
Page 827 GD32E51x User Manual This bit field cannot be written when the USART is enabled (UEN=1). Clock phase 0: The first clock transition is the first data capture edge in synchronous mode 1: The second clock transition is the first data capture edge in synchronous mode This bit field cannot be written when the USART is enabled (UEN=1).
Page 828 GD32E51x User Manual Bits Fields Descriptions 31:23 Reserved Must be kept at reset value WUIE Wakeup from deep-sleep mode interrupt enable 0: Wakeup from deep-sleep mode interrupt is disabled 1: Wakeup from deep-sleep mode interrupt is enabled 21:20 WUM[1:0] Wakeup mode from deep-sleep mode These bits are used to specify the event which activates the WUF (Wakeup from deep-sleep mode flag) in the USART_STAT register.
Page 829 GD32E51x User Manual error, but the corresponding error flag is set. This mode can be used in smartcard mode. 1: The DMA request is not asserted in case of reception error until the error flag is cleared. The RBNE flag and corresponding error flag will be set. The software must first disable the DMA request (DMAR = 0) or clear RBNE before clearing the error flag.
Page 830 GD32E51x User Manual 1: Low-power mode This bit field cannot be written when the USART is enabled (UEN=1). IREN IrDA mode enable 0: IrDA disabled 1: IrDA enabled This bit field cannot be written when the USART is enabled (UEN=1). ERRIE Error interrupt enable 0: Error interrupt disabled...
Page 831 GD32E51x User Manual GUAT[7:0] PSC[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:8 GUAT[7:0] Guard time value in smartcard mode This bit field cannot be written when the USART is enabled (UEN=1). PSC[7:0] Prescaler value for dividing the system clock In IrDA Low-power mode, the division factor is the prescaler value.
Page 832 GD32E51x User Manual the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1. This value, which must be programmed only once per received block, can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field).
Page 833 GD32E51x User Manual SBKCMD Send break command Writing 1 to this bit sets the SBKF flag and makes the USART send a BREAK frame, as soon as the transmit machine is idle. Reserved Must be kept at reset value Status register (USART_STAT) Address offset: 0x1C Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 834 GD32E51x User Manual It is cleared/set by hardware when a wakeup/mute sequence (address or IDLEIE) is recognized, which is selected by the WM bit in the USART_CTL0 register. This bit can only be set by writing 1 to the MMCMD bit in the USART_CMD register when wakeup on IDLEIE mode is selected.
Page 835 GD32E51x User Manual Set by hardware when the LIN break is detected. Cleared by writing 1 to LBDC bit in USART_INTC register. Transmit data register empty 0: Data is not transferred to the shift register 1: Data is transferred to the shift register. An interrupt will occur if the TBEIE bit is set in USART_CTL0 Set by hardware when the content of the USART_TDATA register has been transferred into the transmit shift register or writing 1 to TXFCMD bit of the...
Page 836 GD32E51x User Manual 0: No noise error is detected 1: Noise error is detected. In multibuffer communication, an interrupt will occur if the ERRIE bit is set in USART_CTL2. Set by hardware when noise error is detected on a received frame. Cleared by writing 1 to NEC bit in USART_INTC register.
Page 837 GD32E51x User Manual 16:13 Reserved Must be kept at reset value End of block clear Writing 1 to this bit clears the EBF bit in the USART_STAT register. Receiver timeout clear Writing 1 to this bit clears the RTF flag in the USART_STAT register. 10:9 Reserved Must be kept at reset value...
Page 838 GD32E51x User Manual RDATA[8:0] Receive data value The received data character is contained in these bits. The value read in the MSB (bit 7 or bit 8 depending on the data length) will be the received parity bit, if receiving with the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
Page 839 GD32E51x User Manual detected, which is before RBNE flag. This flag is cleared by writing 0. 0: No parity error is detected 1: Parity error is detected. Reserved Must be kept at reset value. USART receive FIFO control and status register (USART_RFCS) Address offset: 0xD0 Reset value: 0x0000 0400 This register has to be accessed by word (32-bit).
Page 840 GD32E51x User Manual 1:Early NACKenable when smartcard mode is selected...
Page 841: Inter-Integrated Circuit Interface (I2C)
GD32E51x User Manual Inter-integrated circuit interface (I2C) Inter-integrated circuit interface (I2Cx, x=0, 1) 21.1. Overview 21.1.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL.
Page 842: Table 21-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32E51x User Manual Figure 21-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 21-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Description Term...
Page 843: Figure 21-2. Data Validation
GD32E51x User Manual is set. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V Data validation The data on the SDA line must be stable during the HIGH period of the clock.
Page 844: Figure 21-4. Clock Synchronization
GD32E51x User Manual transition of this clock may not change the state of the SCL line. The SCL line is therefore held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time. Figure 21-4.
Page 845: Figure 21-6. I2C Communication Flow With 7-Bit Address
GD32E51x User Manual to the following command on I2C bus: transmitting or receiving the desired data. Additionally, if General Call is enabled by software, the I2C slave always responds to a General Call Address (0x00). The I2C block supports both 7-bit and 10-bit address modes. An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation.
Page 846 GD32E51x User Manual As is shown in Figure 21-9. Programming model for slave transmitting (10-bit address mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing.
Page 847: Figure 21-9. Programming Model For Slave Transmitting (10-Bit Address Mode)
GD32E51x User Manual Figure 21-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 848: Figure 21-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32E51x User Manual I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 21-10. Programming model for slave receiving (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE Master generates START 1) Software initialization condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge...
Page 849 GD32E51x User Manual to I2C bus as soon as the shift register is not empty. During the transmission of the first byte, software can write the second byte to I2C_DATA, and this time TBE is cleared because neither I2C_DATA nor shift register is empty. Any time TBE is set, software can write a byte to I2C_DATA as long as there is still data to be transmitted.
Page 850 GD32E51x User Manual First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus. Software sets START bit requesting I2C to generate a START signal on I2C bus.
Page 851: Figure 21-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32E51x User Manual Figure 21-12. Programming model for master receiving using Solution A (10-bit address mode) Hardware Action I2C Line State Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 852: Figure 21-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32E51x User Manual a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA. Then the header is sent out to I2C bus, and ADDSEND is set again. Software should again clear ADDSEND by reading I2C_STAT0 and then I2C_STAT1.
Page 853 GD32E51x User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 854 GD32E51x User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 855 GD32E51x User Manual  SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications.
Page 856: Table 21-2. Event Status Flags
GD32E51x User Manual The programming flow for SMBus is similar to normal I2C. In order to use SMBus mode, the application should configure several SMBus specific registers, respond to some SMBus specific flags and implement the upper protocols described in SMBus specification. Before communication, SMBEN bit in I2C_CTL0 should be set and SMBSEL and ARPEN bits should be configured to desired values.
Page 857 GD32E51x User Manual Error Name Description LOSTARB Arbitration lost OUERR Over-run or under-run when SCL stretch is disabled. AERR No acknowledge received CRC value doesn’t match PECERR SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert...
Page 858: Register Definition
GD32E51x User Manual Register definition 21.1.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved SALT POAP...
Page 859 GD32E51x User Manual 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent...
Page 860 GD32E51x User Manual 1: I2C is enabled Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[6:0] Bits Fields Descriptions 31:13 Reserved...
Page 861 GD32E51x User Manual 0000000 - 0000001: Not allowed 0000010 - 1011010: 2MHz~90MHz 1011011 - 1111111: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz. In I2C fast mode, the frequencies of APB1 must be equal or greater than 8MHz.
Page 862 GD32E51x User Manual Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) Address offset: 0x10 Reset value: 0x0000 0000...
Page 863 GD32E51x User Manual 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode) SMBTO...
Page 864 GD32E51x User Manual cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail). 0: I2C_DATA is not empty 1: I2C_DATA is empty, software can write RBNE I2C_DATA is not empty during receiving This bit is set by hardware after it moves a byte from shift register to I2C_DATA and...
Page 865 GD32E51x User Manual mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA. 0: No START signal sent 1: START signal sent Transfer status register 1 (I2C_STAT1) Address offset: 0x18...
Page 866 GD32E51x User Manual Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver. It is cleared by hardware after a STOP or a START signal or I2CEN=0 or LOSTARB=1. 0: Receiver 1: Transmitter I2CBSY...
Page 867 GD32E51x User Manual =CLKC*T =2*CLKC*T high PCLK1 PCLK1 In fast speed mode or fast mode plus, if DTCY=1: =9*CLKC*T =16*CLKC*T high PCLK1 PCLK1 Note: If DTCY is 0, when PCLK1 is an integral multiple of 3, the baud rate will be more accurate.
Page 868 GD32E51x User Manual Txframe rise flag, cleared by software by writing 0 Txframe fall flag, cleared by software by writing 0 11:10 Reserved Must be kept at reset value. Level of rxframe signal Level of txframe signal RFRIE Rxframe rise interrupt enable 0: Rxframe rise interrupt disabled 1: Rxframe rise interrupt enabled RFFIE...
Page 869 GD32E51x User Manual 31:16 Reserved Must be kept at reset value. 15:9 ADDM[6:0] Defines which bits of register ADDRESS[7:1] are compared with an incoming address byte, and which bits are ignored. Any bit set to 1 in ADDM[6:0] enables comparisons with the corresponding bit in ADDRESS[7:1]. Bits set to 0 are ignored (can be either 0 or 1 in the incoming address).
Page 870 GD32E51x User Manual STLOIE Interrupt enable for start lost 0: interrupt disable 1: interrupt enable Reserved Must be kept at reset value. STPSEND Stop condition sent out in master mode This bit is set by hardware and cleared by software write 0 0: No STOP condition sent 1: STOP condition sent STLO...
Page 871 GD32E51x User Manual ADD10SENDC ADD10SEND status clear When SRCEN bit is set to 1, software can clear the ADD10SEND bit of I2C_STAT0 by writing 1 to this bit BTCC BTC status clear When SRCEN bit is set to 1, software can clear the BTC bit of I2C_STAT0 by writing 1 to this bit ADDSENDC ADDSEND status clear...
Page 872: Inter-Integrated Circuit Interface (I2Cx, X=2)
GD32E51x User Manual Inter-integrated circuit interface (I2Cx, x=2) 21.2. Overview 21.2.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 873: Table 21-4. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32E51x User Manual Figure 21-14. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter...
Page 874: Figure 21-15. Data Validation
GD32E51x User Manual  <t I2CCLK HIGH with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 160ns. Digital filter delay is DNF[3:0]×t I2CCLK The period of PCLK clock t match the conditions as follows:...
Page 875: Figure 21-16. Start And Stop Signal
GD32E51x User Manual Figure 21-16. START and STOP signal START STOP Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device.
Page 876: Figure 21-18. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32E51x User Manual Figure 21-18. I2C communication flow with 7-bit address (Master Transmit) Figure 21-19. I2C communication flow with 7-bit address (Master Receive) Start Slave address …… DATAN R(1) DATA0 NACK Stop data transfer (N+1 bytes) From master to slave From slave to master In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent.
Page 877: Figure 21-22. Data Hold Time
GD32E51x User Manual Noise filter Analog noise filter and digital noise filter are integrated in I2C peripherals, the noise filters can be configured before the I2C peripheral is enabled according to the actual requirements. The analog noise filter is disabled by setting the ANOFF bit in I2C_CTL0 register and enabled when ANOFF is 0.
Page 878: Figure 21-23. Data Setup Time
GD32E51x User Manual Figure 21-23. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t =SDADELY*t where t = ( PSC+1 ) *t SDADELY I2CCLK I2CCLK effects total delay...
Page 879: Table 21-5. Data Setup Time And Data Hold Time
GD32E51x User Manual Table 21-5. Data setup time and data hold time Standard Fast mode Fast mode SMBus Symbol Parameter mode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000 1000 SCL and SDA...
Page 880: Figure 21-24. Data Transmission
GD32E51x User Manual Figure 21-24. Data transmission SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA  Data Reception When receiving data, the data will be received in the shift register first. If RBNE is 0, the data in the shift register will move into I2C_RDATA register.
Page 881 GD32E51x User Manual Working mode Action Slave receiver mode ACK control SMBus mode PEC generation/checking The number of bytes to be transferred is configured by BYTENUM[7:0] in I2C_CTL1 register. If BYTENUM is greater than 255, or in slave byte control mode, the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register.
Page 882 GD32E51x User Manual  The SCL is stretched when the ADDSEND bit is set, and released when the ADDSEND bit is cleared. In slave transmitting mode, after the ADDSEND bit is cleared, the SCL will be stretched  before the first data byte writing to the I2C_TDATA register. Or the SCL will be stretched before the new data is written to the I2C_TDATA register after the previous data transmission is completed.
Page 883: Figure 21-26. I2C Initialization In Slave Mode
GD32E51x User Manual 3. ADDSEND=1. Only when the ADDSEND=1, or TCR=1, the RELOAD bit can be modified. Figure 21-26. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1...
Page 884: Figure 21-27. Programming Model For Slave Transmitting When Ss=0
GD32E51x User Manual When SBCTL=1, the slave works in slave byte control mode, the BYTENUM[7:0] must be configured in the ADDSEND interrupt service routine. And the number of TI events is equal to the value of BYTENUM[7:0]. When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine.
Page 885: Figure 21-28. Programming Model For Slave Transmitting When Ss=1
GD32E51x User Manual Figure 21-28. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 886: Figure 21-29. Programming Model For Slave Receiving
GD32E51x User Manual Figure 21-29. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 887: Figure 21-30. I2C Initialization In Master Mode
GD32E51x User Manual mode, the HEAD10R bit must be configured to decide whether the complete address sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register. If the number of bytes to be transferred is equal to or greater than 255, BYTENUM[7:0] should be configured as 0xFF.
Page 888: Figure 21-31. Programming Model For Master Transmitting (N<=255)
GD32E51x User Manual bit in I2C_CTL1 can be set to generate a STOP signal automatically. When AUTOEND is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signal by setting the STOP bit in the I2C_CTL1 register. Or generate a RESTART signal to start a new transfer.
Page 889: Figure 21-32. Programming Model For Master Transmitting (N>255)
GD32E51x User Manual Figure 21-32. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 890: Figure 21-33. Programming Model For Master Receiving (N<=255)
GD32E51x User Manual Figure 21-33. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 891: Figure 21-34. Programming Model For Master Receiving (N>255)
GD32E51x User Manual Figure 21-34. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 892 GD32E51x User Manual  Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 893 GD32E51x User Manual of the SMBus peripheral is greater than (BUSTOB+1)*2048*t and within the timeout I2CCLK interval described in the bus idle detection section, the TIMEOUT bit in the I2C_STAT register will be set.  Packet error checking There is a CRC-8 calculator in I2C block to perform Packet Error Checking for I2C data. A PEC (packet error code) byte is appended at the end of each transfer.
Page 894: Figure 21-35. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32E51x User Manual  SMBus slave mode The SMBus receiver must be able to NACK each command or data it receives. For ACK control in slave mode, slave byte control mode can be enabled by setting SBCTL bit in I2C_CTL0 register. SMBus-specific addresses should be enabled when needed.
Page 895: Figure 21-36. Smbus Master Receiver And Slave Transmitter Communication Flow
GD32E51x User Manual  SMBus master receiver and slave transmitter  If the SMBus master is required to receive PEC at the end of bytes transfer, automatic end mode can be enabled. Before sending a START signal on the bus, PECTRANS bit must be set and slave addresses must be programmed.
Page 896: Table 21-7. I2C Error Flags
GD32E51x User Manual Use DMA for data transfer As is shown in I2C slave mode and I2C master mode, each time TI or RBNE is asserted, software should write or read a byte, this may cause CPU’s high overload. The DMA controller can be used to process TI and RBNE flag: each time TI or RBNE is asserted, DMA controller does a read or write operation automatically.
Page 897 GD32E51x User Manual I2C debug mode When the microcontroller enters the debug mode (Cortex®-M33 core halted), the SMBus timeout either continues to work normally or stops, depending on the I2Cx_HOLD configuration bits in the DBG module.
Page 898: Register Definition
GD32E51x User Manual Register definition 21.2.4. I2C2 base address: 0x4000 C000 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SMBALT SMBDAE SMBHAE Reserved PECEN GCEN WUEN SBCTL STPDETI DENR DENT Reserved...
Page 899 GD32E51x User Manual 1 mode and Deep-sleep 2 mode. 0: Wakeup from power saving mode disable. 1: Wakeup from power saving mode enable. Note: WUEN can be set only when DNF[3:0] = 0000 Whether to stretch SCL low when data is not ready in slave mode. This bit is set and cleared by software.
Page 900 GD32E51x User Manual 0: Stop detection (STPDET) interrupt is disabled 1: Stop detection (STPDET) interrupt is enabled NACKIE NACK received interrupt enable 0: NACK received interrupt is disabled 1: NACK received interrupt is enabled ADDMIE Address match interrupt enable in slave mode 0: Address matchinterrupt is disabled 1: Address matchnterrupt is enabled RBNEIE...
Page 901 GD32E51x User Manual 1: Transfer PEC Note: This bit has no effect when RELOAD=1, or SBCTL=0 in slave mode. AUTOEND Automatic end mode in master mode 0: TC bit is set when the transfer of BYTENUM[7:0] bytes is completed. 1: a STOP signal is sent automatically when the transfer of BYTENUM[7:0] bytes is completed.
Page 902 GD32E51x User Manual 1: The 10 bit master receive address sequence is RESTART + header of 10-bit address (read). Note: When the START bit is set, this bit can not be changed. ADD10EN 10-bit addressing mode enable in master mode 0: 7-bit addressing in master mode 1: 10-bit addressing in master mode Note: When the START bit is set, this bit can not be modified.
Page 903 GD32E51x User Manual 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address 1: 10-bit address Note: When ADDRESSEN is set, this bit should not be written. ADDRESS[9:8] Highest two bits of a 10-bit address Note: When ADDRESSEN is set, this bit should not be written.
Page 904 GD32E51x User Manual Note: When ADDRESS2EN is set, these bits should not be written. If ADDMSK2 is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if all the bits are matched. ADDRESS2[7:1] Second I2C address for the slave Note: When ADDRESS2EN is set, these bits should not be written.
Page 905 GD32E51x User Manual SCLL[7:0] SCL low period SCL low period can be generated by configuring these bits. =(SCLL+1)*t SCLL Note: These bits can only be used in master mode. Timeout register (I2C_TIMEOUT) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). EXTOEN Reserved BUSTOB[11:0]...
Page 906 GD32E51x User Manual Note: This bit can be written only when TOEN =0. 11:0 BUSTOA[11:0] Bus timeout A When TOIDLE = 0, t =(BUSTOA+1)*2048*t TIMEOUT I2CCLK When TOIDLE = 1, t =(BUSTOA+1)*4*t IDLE I2CCLK Note: These bits can be written only when TOEN =0. Status register (I2C_STAT) Address offset: 0x18 Reset value: 0x0000 0001...
Page 907 GD32E51x User Manual 1: SMBALERT event is detected on SMBA pin TIMEOUT TIMEOUT flag. When a timeout or extended clock timeout occurred, this bit will be set. It is cleared by software by setting the TIMEOUTC bit and cleared by hardware when I2CEN=0. 0: no timeout or extended clock timeout occur 1: a timeout or extended clock timeout occur PECERR...
Page 908 GD32E51x User Manual 0: Transfer of BYTENUM[7:0] bytes is not completed 1: Transfer of BYTENUM[7:0] bytes is completed STPDET STOP signal detected in slave mode This flag is set by hardware when a STOP signal is detected on the bus. It is cleared by software by setting STPDETC bit and cleared by hardware when I2CEN=0.
Page 909 GD32E51x User Manual This register has to be accessed by word (32-bit). Reserved SMBALT TIMEOUT PECERR LOSTAR STPDET ADDSEN Reserved OUERRC BERRC Reserved NACKC Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. SMBALTC SMBus alert flag clear. Software can clear the SMBALT bit of I2C_STAT by writing 1 to this bit.
Page 910 GD32E51x User Manual Reserved Reserved PECV[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PECV[7:0] Packet Error Checking Value that calculated by hardware when PEC is enabled. PECV is cleared by hardware when I2CEN = 0. Receive data register (I2C_RDATA) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 911 GD32E51x User Manual TDATA[7:0] Transmit data value...
Page 912: Serial Peripheral Interface/Inter-Ic Sound (Spi/I2S)
GD32E51x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 22.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 913: Figure 22-1. Block Diagram Of Spi
GD32E51x User Manual  Master clock (MCK) can be output.  Transmission and reception using DMA. SPI function overview 22.3. SPI block diagram 22.3.1. Figure 22-1. Block diagram of SPI SYSCLK Clock Generator Control Registers TxRx Control Logic MOSI TX Buffer MISO Shift Register RX Buffer...
Page 914: Table 22-2. Quad-Spi Signal Description
GD32E51x User Manual Pin name Direction Description Master in hardware NSS mode: when NSSDRV=1, it is NSS output, suitable for single master application; when NSSDRV=0, it is NSS input, suitable for multi-master application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave.
Page 915: Figure 22-2. Spi Timing Diagram In Normal Mode
GD32E51x User Manual Figure 22-2. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[2] D[4] D[0] D[1] D[5] D[6] D[7] LF=1 FF16=0 D[2] MISO D[1] D[5] D[6] D[7] D[0] D[3]...
Page 916: Table 22-3. Nss Function In Slave Mode
GD32E51x User Manual NSS function 22.3.4. Slave mode When slave mode is configured (MSTMOD=0), SPI gets NSS level from NSS pin in hardware NSS mode (SWNSSEN = 0) or from SWNSS bit in software NSS mode (SWNSSEN = 1) and transmits/receives data only when NSS level is low.
Page 917: Table 22-5. Spi Operation Modes
GD32E51x User Manual Mode Register configuration Description configuration error will occur and the CONFERR bit will be set to 1. Applicable to multi-master mode. Once MSTMOD = 1 SWNSS = 0, SPI will automatically SWNSSEN = 1 enter slave mode, and a master SWNSS = 0 configuration error will occur and the NSSDRV: Don’t care...
Page 918: Figure 22-4. A Typical Full-Duplex Connection
GD32E51x User Manual Mode Description Register configuration Data pin usage BDEN = 0 BDOEN: Don’t care MSTMOD = 0 Slave reception with RO = 1 MOSI: reception unidirectional connection BDEN = 0 MISO: not used BDOEN: Don’t care MSTMOD = 0 Slave transmission with RO = 0 MOSI: not used...
Page 919: Figure 22-6. A Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
GD32E51x User Manual Figure 22-6. A typical simplex connection (Master: transmit only, Slave: receive) Figure 22-7. A typical bidirectional connection Master Slave MTB/MRB SRB/STB MISO MISO MOSI MOSI Initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise,...
Page 920 GD32E51x User Manual Basic transmission and reception sequence Transmission sequence After the initialization sequence, the SPI is enabled and stays at idle state. In master mode, the transmission starts when the application writes a data into the transmission buffer. In slave mode the transmission starts when SCK clock signal begins to toggle at SCK pin and NSS level is low, so application should ensure that data is already written into transmission buffer before the transmission starts in slave mode.
Page 921: Figure 22-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32E51x User Manual similar to normal mode described above. The modes described above (MFD, MTU, MRU, MTB, MRB, SFD, STU, SRU, STB and SRB) are still supported in TI mode. While, in TI mode the CKPL and CKPH bits in SPI_CTL0 registers take no effect and the SCK sample edge is falling edge.
Page 922: Figure 22-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32E51x User Manual In slave TI mode, after the last rising edge of SCK in transfer, the slave begins to transmit the LSB bit of the last data byte, and after a half-bit time, the master begins to sample the line. To make sure that the master samples the right value, the slave should continue to drive this bit after the falling sample edge of SCK for a period of time before releasing the pin.
Page 923: Figure 22-12. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32E51x User Manual There are two operation modes in Quad-SPI mode: quad write and quad read, decided by QRD bit in SPI_QCTL register. Quad write operation SPI works in quad write mode when QMOD is set and QRD is cleared in SPI_QCTL register. In this mode, MOSI, MISO, IO2 and IO3 are all used as output pins.
Page 924: Figure 22-13. Timing Diagram Of Read Operation In Quad-Spi Mode
GD32E51x User Manual Set QMOD and QRD bits in SPI_QCTL register and then enable SPI by setting SPIEN in SPI_CTL0 register. Write an arbitrary byte (for example, 0xFF) to SPI_DATA register. Wait until the RBNE flag is set and read SPI_DATA to get the received byte. Write an arbitrary byte (for example, 0xFF) to SPI_DATA to receive the next byte.
Page 925 GD32E51x User Manual The disabling sequence of TI mode is the same as the sequences described above. NSS pulse mode The disabling sequence of NSSP mode is the same as the sequences described above. Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared.
Page 926 GD32E51x User Manual internal signal needs to be kept low between the data phase and CRC phase. SPI interrupts 22.3.8. Status flags  Transmission buffer empty flag (TBE) This bit is set when the transmission buffer is empty, the software can write the next data to the transmission buffer by writing the SPI_DATA register.
Page 927: Figure 22-14. Block Diagram Of I2S
GD32E51x User Manual register is compared with the received CRC value after the last data, the CRCERR is set when they are different. Table 22-6. SPI interrupt requests Interrupt Flag Description Clear method enable bit Transmission buffer empty Write SPI_DATA register. TBEIE RBNE Reception buffer not empty...
Page 928: Figure 22-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E51x User Manual I2S signal description 22.4.2. There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 929: Figure 22-16. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32E51x User Manual Figure 22-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame.
Page 930: Figure 22-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32E51x User Manual When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame. In transmission mode, if a 24- bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits: D[23:8], and the second one should be a 16-bit data.
Page 931: Figure 22-24. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32E51x User Manual Figure 22-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD Figure 22-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 932: Figure 22-30. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32E51x User Manual Figure 22-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD LSB justified standard For LSB justified standard, I2S_WS and I2S_SD are updated on the falling edge of I2S_CK. In the case that the channel length is equal to the data length, LSB justified standard and MSB justified standard are exactly the same.
Page 933: Figure 22-33. Lsb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32E51x User Manual Figure 22-33. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit 0 16-bit data I2S_SD Figure 22-34. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 934: Figure 22-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32E51x User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure 22-38. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK I2S_WS 32-bit data I2S_SD Figure 22-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 24-bit data...
Page 935: Figure 22-43. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E51x User Manual (DTLEN=00, CHLEN=1, CKPL=1) The timing diagrams for each configuration of the long frame synchronization mode are shown below. Figure 22-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=0) Figure22-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 frame 2...
Page 936: Figure 22-48. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32E51x User Manual (DTLEN=01, CHLEN=1, CKPL=0) Figure 22-48. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 22-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2...
Page 937: Table 22-7. I2S Bitrate Calculation Formulas
GD32E51x User Manual The block diagram of I2S clock generator is shown as Figure 22-51. Block diagram of I2S clock generator.The I2S interface clocks are configured by the DIV bits, the OF bit, the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register. The source clock is the system clock(CK_SYS) or PLL2*2.
Page 938 GD32E51x User Manual I2S_ADD Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD Slave transmission Input or NU Input Input Output Slave reception Input or NU Input Input Input output or Input or Full-duplex output or NU output output input output 1. NU means the pin is not used by I2S and can be used by other functions. 2.
Page 939: Figure 22-52. I2S Initialization Sequence
GD32E51x User Manual Figure 22-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 940 GD32E51x User Manual (TBE is high) and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmission buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 941: Figure 22-53. I2S Master Reception Disabling Sequence
GD32E51x User Manual Figure 22-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTD ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 942 GD32E51x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 943: Table 22-10. I2S Interrupt
GD32E51x User Manual  Transmission buffer empty flag (TBE) This bit is set when the transmission buffer is empty, the software can write the next data to the transmission buffer by writing the SPI_DATA register.  Reception buffer not empty flag (RBNE) This bit is set when reception buffer is not empty, which means that one data is received and stored in the reception buffer, and software can read the data by reading the SPI_DATA register.
Page 944 GD32E51x User Manual Interrupt Interrupt flag Description Clear method enable bit TXURERR Transmission underrun error Read SPI_STAT register Read SPI_DATA register and then RXORERR Reception overrun error ERRIE read SPI_STAT register. FERR I2S format error Read SPI_STAT register...
Page 945 GD32E51x User Manual Register definition 22.5. SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 I2S1_ADD base address: 0x4000 3400 I2S2_ADD base address: 0x4000 4000 Control register 0 (SPI_CTL0) 22.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 946 GD32E51x User Manual CRCNT CRC next transfer 0: Next transfer is data 1: Next transfer is CRC value When the transfer is managed by DMA, CRC value is transferred by hardware. This bit should be cleared. In full-duplex or transmit-only mode, set this bit after the last data is written to SPI_DATA register.
Page 947 GD32E51x User Manual PCLK means PCLK2 when using SPI0. PCLK means PCLK1 when using SPI1 and SPI2. MSTMOD Master mode enable 0: Slave mode 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle. 1: CLK pin is pulled high when SPI is idle.
Page 948 GD32E51x User Manual NSSP SPI NSS pulse mode enable. 0: Disable SPI NSS pulse mode 1: Enable SPI NSS pulse mode NSSDRV Drive NSS output 0: Disable master NSS output 1: Enable master NSS output DMATEN Transmit buffer DMA enable 0: Disable transmit buffer DMA 1: Enable transmit buffer DMA, when the TBE bit in SPI_STAT is set, it will be a DMA request on corresponding DMA channel.
Page 949 GD32E51x User Manual 1: SPI or I2S is currently transmitting and/or receiving a frame. This bit is set and cleared by hardware. RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register.
Page 950 GD32E51x User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register. the hardware has two buffers, including transmission buffer and reception buffer. Write data to SPI_DATA will save the data to transmission buffer and read data from SPI_DATA will get the data from reception buffer.
Page 951 GD32E51x User Manual RX CRC register (SPI_RCRC) 22.5.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value...
Page 952 GD32E51x User Manual of the transmitted bytes and saves them in TCRC register.If the data frame format is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value in TCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC[15:0].
Page 953 GD32E51x User Manual 0: Short frame synchronization 1: long frame synchronization This bit has a meaning only when PCM standard is used. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. Reserved Must be kept at reset value.
Page 954 GD32E51x User Manual Reserved MCKOEN DIV[7:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: Disable I2S_MCK output 1: Enable I2S_MCK output This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1...
Page 955 GD32E51x User Manual Quad-SPI mode read select. 0: SPI is in quad wire write mode. 1: SPI is in quad wire read mode. This bit can only be configured when the SPI is not busy (the TRANS bit is cleared). This bit is only available in SPI0.
Page 956: Table 23-1. Sqpi Controller Mode Definition
GD32E51x User Manual Serial/Quad Parallel Interface (SQPI) Overview 23.1. Serial/Quad Parallel Interface (SQPI) is a controller for external serial/dual/quad parallel interface memory peripheral. For example: SQPI-PSRAM and SQPI-FLASH. With this controller, users can use external SQPI interface memory as SRAM simply. The GD32EPRTxxA series chips are internally stacked with PSRAM, the SQPI pins connected to PSARM cannot be used for other purposes.
Page 957 GD32E51x User Manual Command Phase SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Address Phase SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Waitcycle Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout Data Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout...
Page 958: Figure 23-1. Sqpi_Pl Example
GD32E51x User Manual Figure 23-1. SQPI_PL Example SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Command Phase Address Phase Waitcycle Phase Data Phase Sample Time (SQPI_PL=0) Sample Time (SQPI_PL=1) SQPI controller special command 23.3.2. SQPI controller special command (SQPI_SC) function can send only command phase with no address, waitcycle, and data phase.
Page 959: Figure 23-3. Sqpi_Rdid Example (Sqpi_Idlen=00)
GD32E51x User Manual SQPI controller read ID command 23.3.3. For more than 32-bit ID data, SQPI_RDID function can supply help. To use this function, first you should set SQPI_IDLEN bit to 0x00(64bit,this is default), then set the SQPI_RDID bit to 1 and wait it cleared by hardware through polling this bit, and at last read the SQPI_IDL and SQPI_IDH registers.
Page 960: Figure 23-5. Sqpi Sss Mode Timing (Spi)
GD32E51x User Manual Read ID command flow 23.3.6. The first, user should configure SQPI_RCMD bits by Read ID command (e.g. 0x9F for SQPIPSRAM) and read waitcycle number in SQPI_RCMD register. The second user sets SQPI_RID bit to 1 and wait it reset to 0. The third, user can get ID value by read SQPI_IDL and SQPI_IDH registers.
Page 961: Figure 23-6. Sqpi Ssq Mode Timing
GD32E51x User Manual Figure 23-6. SQPI SSQ Mode Timing SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase Data Phase Figure 23-7. SQPI SQQ Mode Timing (SQPI) SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase...
Page 962: Figure 23-9. Sqpi Ssd Mode Timing
GD32E51x User Manual Figure 23-9. SQPI SSD Mode Timing SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase Figure 23-10. SQPI SDD Mode Timing SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase Register definition...
Page 963 GD32E51x User Manual 0: Sample data at rising edge(default) 1: Sample data at falling edge. 30:29 SQPI_IDLEN[1:0] SQPI controller external memory ID length. 00:64-bit 01:32-bit 10:16-bit 11:8-bit 28:24 SQPI_ADDRBIT[4:0] Bit number of SPI PSRAM address phase. Default：24 23:18 SQPI_CLKDIV[5:0] Clock divider for SQPI output clock. 0x0 is invalid.
Page 964 GD32E51x User Manual 001: SSS mode 010: SQQ mode 011: QQQ mode 100: SSD mode 101: SDD mode 19:16 SQPI_RWAITCYCLE SQPI read command waitcycle number after address phase [3:0] 15:0 SQPI_RCMD[15:0] SQPI read command for AHB read transfer SQPI_RCMD[3:0] are valid when SQPI_CMDBIT=00 SQPI_RCMD[7:0] are valid when SQPI_CMDBIT=01 SQPI_RCMD[15:0] are valid when SQPI_CMDBIT=10 Note: Before write 1 to SQPI_RID bit, you must ensure it is cleared and after set SQPI_RID...
Page 965 GD32E51x User Manual 15:0 SPI_WCMD[15:0] SQPI write command for AHB write transfer Note: Before write 1 to SQPI_SC bit, you must ensure it is cleared and after set SQPI_SC to 1, you must wait SQPI_SC cleared SQPI ID Low Register (SQPI_IDL) 23.4.4.
Page 966 GD32E51x User Manual Secure digital input/output interface (SDIO) Introduction 24.1. The secure digital input/output interface (SDIO) defines the SD, SD I/O, MMC and CE-ATA card host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC) and CE-ATA devices. The supported SD memory card and SD I/O card system specifications are defined in the SD card Association website at www.sdcard.org.
Page 967: Figure 24-1. Sdio "No Response" And "No Data" Operations
GD32E51x User Manual Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
Page 968: Figure 24-2. Sdio Multiple Blocks Read Operation
GD32E51x User Manual Figure 24-2. SDIO multiple blocks read operation Figure 24-3. SDIO multiple blocks write operation Data transfers to/from SD memory cards, SD I/O cards (both IO only card and combo card) and CE-ATA device are done in data blocks. Data transfers to/from MMC are done in data blocks or streams.
Page 969: Figure 24-6. Sdio Block Diagram
GD32E51x User Manual SDIO functional description 24.4. The following figure shows the SDIO structure. There have two main parts:  The SDIO adapter block consists of control unit which manage clock, command unit which manage command transfer, data unit which manage data transfer. ...
Page 970: Table 24-1. Sdio I/O Definitions
GD32E51x User Manual SDIO_DAT[7:0]: These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the card or the host is driving these signals at a time. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7 (just for MMC4.2), by the SDIO controller.
Page 971 GD32E51x User Manual 0b00/0b10. There are short response which have 48 bits or long response which have 136 bits. The response stores in SDIO_RESP0 - SDIO_RESP3 registers. The command unit also generates the command status flags defined in SDIO_STAT register. Command state machine CS_Idle After reset, ready to send command.
Page 972 GD32E51x User Manual → 3.Command CRC failed CS_Idle Data unit The data unit performs data transfers to and from cards. The data transfer uses SDIO_DAT[7:0] signals when 8-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b10), use SDIO_DAT[3:0] signals when 4-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b01), or SDIO_DAT[0] signal when 1-bit data width (BUSMODE bits in SDIO_CLKCTL register is 0b00).
Page 973 GD32E51x User Manual → 1.Data receive ended DS_Idle → 2.DSM disabled DS_Idle → 3.Data timeout reached DS_Idle → 4.Receives a start bit before timeout DS_Receive Note: The command timeout programmed in the data timer register (SDIO_DATATO). DS_Receive Receive data from the card and write it to the data FIFO. →...
Page 974 GD32E51x User Manual Program the SDIO command control register (SDIO_CMDCTL): CMDIDX with 24, CMDRESP with 1 (SDIO card host waits for a short response); CSMEN with ‘1’ (enable to send a command). Other fields are their reset value. When the CMDRECV flag is set, program the SDIO data control register (SDIO_DATACTL): DATAEN with ‘1’...
Page 975 GD32E51x User Manual CID register: The Card Identification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual Read/Write (RW) card shall have a unique identification number. The host can use CMD2 and CMD10 to get the content of this register.
Page 976: Figure 24-7. Command Token Format
GD32E51x User Manual  Broadcast commands with response (bcr) response from all cards simultaneously.  Addressed (point-to-point) commands (ac) no data transfer on DAT. Addressed (point-to-point) data transfer commands (adtc) data transfer on DAT.  Command format All commands have a fixed code length of 48 bits, as show in Figure 24-7.
Page 977: Table 24-3. Card Command Classes (Cccs)
GD32E51x User Manual For CE-ATA device, the device shall support the MMC commands required to achieve the transfer state during device initialization. Other interface configuration settings, such as bus width, may require additional MMC commands also be supported. See the MMC reference. CE-ATA makes use of the following MMC commands: CMD0 - GO_IDLE_STATE, CMD12 - STOP_TRANSMISSION, CMD39 - FAST_IO, CMD60 - RW_MULTIPLE_REGISTER, CMD61 - RW_MULTIPLE_BLOCK.
Page 978 GD32E51x User Manual CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC.CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card.
Page 979: Table 24-4. Basic Commands (Class 0)
GD32E51x User Manual Table 24-4. Basic commands (class 0) Response type argument Abbreviation Description index format CMD0 [31:0] stuff bits GO_IDLE_STATE Resets all cards to idle state Asks the card, in idle state, to send [31:0] its Operating Conditions Register CMD1 SEND_OP_COND without busy...
Page 980: Table 24-5. Block-Oriented Read Commands (Class 2)
GD32E51x User Manual For MMC only. The card sends its CMD8 adtc [31:0] stuff bits SEND_EXT_CSD EXT_CSD register as a block of data. Addressed card sends its card- [31:16] RCA CMD9 SEND_CSD specific data (CSD) on the CMD [15:0] stuff bits line.
Page 981: Table 24-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32E51x User Manual address SD and MMC, this command reads a block of the size selected by the SET_BLOCKLEN command. In the case of a High Capacity Card, block length is fixed 512 Bytes regardless of the SET_BLOCKLEN command. Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION [31:0] data...
Page 982: Table 24-8. Erase Commands (Class 5)
GD32E51x User Manual Response type argument Abbreviation Description index format In the case of a Standard Capacity SD, this command writes a block of size selected [31:0] data CMD24 adtc WRITE_BLOCK SET_BLOCKLEN command. In the address case of a SDHC, block length is fixed 512 Bytes regardless of the SET_BLOCKLEN command.
Page 983: Table 24-9. Block Oriented Write Protection Commands (Class 6)
GD32E51x User Manual be selected for erase.(MMC) Erases all previously selected write CMD38 [31:0] stuff bits ERASE blocks. Note: 1.CMD34 and CMD37 are reserved in order to maintain backwards compatibility with older versions of the MMC. 2. Data address is in byte units in a Standard Capacity SD Memory Card and in block (512 Byte) units in a High Capacity SD Memory Card.
Page 984: Table 24-11. Application-Specific Commands (Class 8)
GD32E51x User Manual Table 24-11. Application-specific commands (class 8) Response Cmd index type argument Abbreviation Description format Sends host capacity support information (HCS) and asks the [31]reserved bit accessed card to send its [30]HCS operating condition SD_SEND_OP_C ACMD41 [29:24]reserved bits register(OCR) content in the [23:0]V Voltage...
Page 985: Table 24-12. I/O Mode Commands (Class 9)
GD32E51x User Manual Table 24-12. I/O mode commands (class 9) Response type argument Abbreviation Description index format Used to write and read 8 bit (register) data fields. command addresses a card and a [31:16] RCA register and provides the data for [15] register write flag writing if the write flag is set.
Page 986: Table 24-13. Switch Function Commands (Class 10)
GD32E51x User Manual Table 24-13. Switch function commands (class 10) Response type argument Abbreviation Description index format [31] Mode 0:Check function 1:Switch function [30:24] reserved [23:20] reserved for function group 6 (0h or Fh) Only for SD memory and [19:16] reserved for function SD I/O.
Page 987: Figure 24-8. Response Token Format
GD32E51x User Manual Responses format Responses have two formats, as show in Figure 24-8. Response Token Format, all responses are sent on the CMD line. The code length depends on the response type. Except R2 is 136 bits length, others are all 48 bits length. Figure 24-8.
Page 988: Table 24-15. Response R2
GD32E51x User Manual CMD9. Only the bits [127..1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. Table 24-15. Response R2 Bit position [133:128] [127:1] Width ‘0’...
Page 989: Table 24-19. Response R5 For Mmc
GD32E51x User Manual 1’ Number start transmissio Reserve Memory Stuff Reserve description S18A I/O OCR n bit Present Bits functions R5 (Interrupt request) For MMC only. Code length is 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0.
Page 990: Figure 24-9. 1-Bit Data Bus Width
GD32E51x User Manual the response of CMD8. Bits 19-16 indicate the voltage range that the card supports. The card that accepted the supplied voltage returns R7 response. In the response, the card echoes back both the voltage range and check pattern set in the argument. Table 24-22.
Page 991: Figure 24-11. 8-Bit Data Bus Width
GD32E51x User Manual 8-bit data packet format Figure 24-11. 8-bit data bus width Two status fields of the card 24.5.5. The SD Memory supports two status fields and others just support the first one: Card Status: Error and state information of a executed command, indicated in the response SD Status: Extended status field of 512 bits that supports special features of the SD Memory Card and future Application-Specific features.
Page 992: Table 24-23. Card Status
GD32E51x User Manual •X: Exceptions are detected by the card during command execution phase (Execution Mode). Clear condition •A: According to current state of the card. •B: Always related to the previous command. Reception of a valid command will clear it (with a delay of one command).
Page 993 GD32E51x User Manual ’1’= error occurred during the operation. ’0’= no error UNDERRUN Only for MMC. The card could not ’1’= error sustain data transfer in stream read mode. ’0’= no error OVERRUN Only for MMC. The card could not ’1’= error sustain data programming in stream write mode.
Page 994: Table 24-24. Sd Status
GD32E51x User Manual ’0’= enabled APP_CMD The card will expect ACMD, or an ’1’= disabled indication that the command has been interpreted as ACMD. Reserved ’0’= no error AKE_SEQ_ERROR Only for SD memory. Error in the ’1’= error sequence of the authentication process.
Page 995 GD32E51x User Manual Bits Identifier Type Value Description Clear Condition [479:44 SIZE_OF_PROTECT Size protected (See below) ED_AREA area [447:44 SPEED_CLASS Speed class of the (See below) card [439:43 PERFORMANCE_M Performance (See below) move indicated by 1 [MB/s] step. [431:42 AU_SIZE Size of AU (See below) [427:42...
Page 996: Table 24-25. Performance Move Field
GD32E51x User Manual 02h: Class 4 03h: Class 6 04h: Class 10 05h–FFh: Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm and the value can be set by 1 [MB/sec] step. If the card does not move useing RUs, Pm should be considered as infinity. Setting to FFh means infinity. The minimum value of Pm is defined in Table 24-25.
Page 997: Table 24-28. Erase Size Field
GD32E51x User Manual than or equal to the maximum AU size. The card should set smaller AU size as possible. Table 24-27. Maximum AU size Card Capacity up to 64MB up to 256MB up to 512MB up to 32GB up to 2TB Maximum 512 KB 1 MB...
Page 998: Table 24-30. Erase Offset Field
GD32E51x User Manual meaningless if ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 24-30. Erase offset field ERASE_OFFSET Value Definition 0 [sec] 1 [sec] 2 [sec] 3 [sec] Programming sequence 24.6. Card identification 24.6.1. The host will be in card identification mode after reset and while it is looking for new cards on the bus.
Page 999 GD32E51x User Manual this command. If the card cannot perform data transfer in the specified range it must discard itself from further bus operations and go into Inactive State. Otherwise, the card shall respond sending back its V range. If the card can operate on the supplied voltage, the response echoes back the supply voltage and the check pattern that were set in the command argument.
Page 1000 GD32E51x User Manual RW_MULTIPLE_REGISTER (CMD60) commands will succeed and the returned data will be the CE-ATA reset signature. No data commands 24.6.2. To send any non-data command, the software needs to program the SDIO_CMDCTL register and the SDIO_CMDAGMT register with appropriate parameters. Using these two registers, the host forms the command and sends it to the command bus.

This manual is also suitable for:

Gd32e513 series Gd32e517 series Gd32e518 series Gd32eprt a series

GigaDevice Semiconductor GD32E51 Series User Manual

Quick Links

Chapters

Need help?

Questions and answers

Related Manuals for GigaDevice Semiconductor GD32E51 Series

Summary of Contents for GigaDevice Semiconductor GD32E51 Series