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GigaDevice Semiconductor GD32F1 0 Series User Manual

GigaDevice Semiconductor GD32F1 0 Series User Manual

Arm cortex-m3 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32F1x0

Arm

Cortex

-M3 32-bit MCU

®

®

For GD32F130xx,GD32F150xx

User Manual

Revision 3.7

(Jun. 2023)

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Page 1 GigaDevice Semiconductor Inc. GD32F1x0 Cortex -M3 32-bit MCU ® ® For GD32F130xx,GD32F150xx User Manual Revision 3.7 (Jun. 2023)
Page 2: Table Of Contents
GD32F1x0 User Manual Table of Contents Table of Contents......................... 2 List of Figures ........................15 List of Tables ........................21 1. System and me mory architecture ................23 ARM Cortex-M3 processor..................23 1.1. System architecture ....................24 1.2. Memory map......................25 1.3.
Page 3 GD32F1x0 User Manual 2.3.11. Security protection ....................49 Register definition....................50 2.4. 2.4.1. Wait state register (FMC_WS) ..................50 2.4.2. Unlock key register (FMC_KEY) ................50 2.4.3. Option bytes unlock key register (FMC_OBKEY)............51 2.4.4. Status register (FMC_STAT) ..................51 2.4.5. Control register (FMC_CTL)..................52 2.4.6. Address register (FMC_ADDR) ................53 2.4.7.
Page 4 GD32F1x0 User Manual 4.3.8. APB1 enable register (RCU_APB1EN) ..............88 4.3.9. Backup domain control register (RCU_BDCTL)............90 4.3.10. Reset source /clock register (RCU_RSTSCK).............92 4.3.11. AHB reset register (RCU_AHBRST)................93 4.3.12. Configuration register 1 (RCU_CFG1) ...............94 4.3.13. Configuration register 2 (RCU_CFG2) ...............95 4.3.14. Control register 1 (RCU_CTL1) ................96 4.3.15.
Page 5 GD32F1x0 User Manual 6.4.1. Port control register (GPIOx_CTL, x=A..D,F) ............116 6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ..........117 6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F)..........119 6.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F) ........... 121 6.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F) ........... 122 6.4.6.
Page 6 GD32F1x0 User Manual 8.5.6. Channel x memory base address register (DMA_CHxMADDR) ........147 9. Debug (DBG) ......................149 Overview........................ 149 9.1. Serial Wire Debug port overview ................149 9.2. 9.2.1. Pin assignment ....................149 9.2.2. JEDEC-106 ID code ..................... 149 Debug hold function overview ................
Page 7 GD32F1x0 User Manual 10.5.9. Routine sequence register 1 (ADC_RSQ1) .............. 172 10.5.10. Routine sequence register 2 (ADC_RSQ2) ............172 10.5.11. Routine data register (ADC_RDATA)..............173 Digital-to-analog converter (DAC) ............... 173 11.1. Overview ......................173 11.2. Characteristic..................... 174 11.3. Function overview ..................... 175 11.3.1.
Page 8 GD32F1x0 User Manual 13.2. Window watchdog timer (WWDGT) ..............196 13.2.1. Overview ......................196 13.2.2. Characteristics..................... 196 13.2.3. Function overview ....................196 13.2.4. Register definition ....................199 Real-time clock(RTC)..................... 201 14.1. Overview ......................201 14.2. Characteristics ....................201 14.3. Function overview ..................... 202 14.3.1.
Page 9 GD32F1x0 User Manual Timer (TIMERx) ....................... 229 Advanced timer (TIMERx,x=0) ................230 15.1. 15.1.1. Overview ......................230 15.1.2. Characteristics..................... 230 15.1.3. Block diagram...................... 231 15.1.4. Function overview ....................231 15.1.5. TIMERx registers(x=0) ..................258 General level0 timer (TIMERx, x=1, 2)..............285 15.2.
Page 10 GD32F1x0 User Manual Function overview ..................... 420 16.3. Universal synchronous asynchronous receiver transmitter (USART)..422 17.1. Overview ......................422 Characteristics ....................422 17.2. Function overview ..................... 423 17.3. 17.3.1. USART frame format .................... 424 17.3.2. Baud rate generation .................... 425 17.3.3.
Page 11 GD32F1x0 User Manual 18.3.5. Arbitration ......................460 18.3.6. I2C communication flow ..................460 18.3.7. Programming model ................... 461 18.3.8. SCL line stretching ..................... 470 18.3.9. Use DMA for data transfer ................... 471 18.3.10. Packet error checking ..................471 18.3.11. SMBus support ....................471 18.3.12.
Page 12 GD32F1x0 User Manual 19.5.1. Control register 0 (SPI_CTL0) ................510 19.5.2. Control register 1 (SPI_CTL1) ................512 19.5.3. Status register (SPI_STAT) ..................513 19.5.4. Data register (SPI_DATA) ..................514 19.5.5. CRC polynomial register (SPI_CRCPOLY) ............... 515 19.5.6. RX CRC register (SPI_RCRC) ................515 19.5.7.
Page 13 GD32F1x0 User Manual 21.3.10. TSI GPIOs ....................... 543 Registers definition.................... 545 21.4. 21.4.1. Control register (TSI_CTL)..................545 21.4.2. Interrupt enable register (TSI_INTEN) ..............547 21.4.3. Interrupt flag clear register (TSI_INTC) ..............547 21.4.4. Interrupt flag register (TSI_INTF) ................548 21.4.5. Pin hysteresis mode register (TSI_PHM) ..............549 21.4.6.
Page 14 GD32F1x0 User Manual Revision history ..................... 575...
Page 15: List Of Figures
GD32F1x0 User Manual List of Figures ® -M3 processor ..............24 Figure 1-1. The structure of the Cortex Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices ....25 Figure 2-1. Process of page erase operation ................... 43 Figure 2-2. Process of the mass erase operation .................. 44 Figure 2-3.
Page 16 GD32F1x0 User Manual Figure 15-2. Timing chart of internal clock divided by 1..............232 Figure 15-3. Timing chart of PSC value change from 0 to 2 ............233 Figure 15-4. Timing chart of up counting mode, PSC=0/2 ...............234 Figure 15-5. Timing chart of up counting mode , change TIMERx_CAR on the go....234 Figure 15-6.
Page 17 GD32F1x0 User Manual Figure 15-45. Timing chart of internal clock divided by 1 ..............326 Figure 15-46. Timing chart of PSC value change from 0 to 2 ............326 Figure 15-47. Timing chart of up counting mode, PSC=0/2 .............327 Figure 15-48. Timing chart of up counting mode, change TIMERx_CAR on the go .....328 Figure 15-49.
Page 18 GD32F1x0 User Manual Figure 16-3. IFRP output timechart 3 ......................421 Figure 17-1. USART module block diagram....................424 Figure 17-2. USART character frame (8 bits data and 1 stop bit) ..........425 Figure 17-3. USART transmit procedure ....................427 Figure 17-4. Oversampling method of a receive frame bit (OSB=0) ..........428 Figure 17-5.
Page 19 GD32F1x0 User Manual Figure 19-13. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ..496 Figure 19-14. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ..496 Figure 19-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ..497 Figure 19-16. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ..497 Figure 19-17.
Page 20 GD32F1x0 User Manual CHLEN=1, CKPL=0) ..........................502 Figure 19-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ..........................502 Figure 19-44. Block diagram of I2S clock generator................503 Figure 19-45. I2S initialization sequence ....................505 Figure 19-46. I2S master reception disabling sequence ..............507 Figure 20-1.
Page 21: List Of Tables
GD32F1x0 User Manual List of Tables Table 1-1. Memory map of GD32F130xx and GD32F150xx devices ..........26 Table 1-2. Flash module organization ......................29 Table 1-3. Boot modes ............................29 Table 2-1. Base address and size for flash memory ................41 Table 2-2.
Page 22 GD32F1x0 User Manual Table 18-2. Event status flags ........................473 Table 18-3. Error flags ............................473 Table 19-1. SPI signal description ......................485 Table 19-2. NSS function in slave mode....................486 Table 19-3. NSS function in master mode ....................487 Table 19-4. SPI operation modes.........................487 Table 19-5.
Page 23: System And Memory Architecture
GD32F1x0 User Manual System and memory architecture ® The GD32F1x0 series are 32-bit general-purpose microcontrollers based on the ARM ® ® Cortex -M3 processor. The Cortex -M3 processor includes three AHB buses known as I- ® Code, D-Code and System buses. All memory accesses of the Cortex -M3 processor are executed on the three buses according to the different purposes and the target memory spaces.
Page 24: System Architecture
GD32F1x0 User Manual ® Figure 1-1. The structure of the Cortex -M3 processor Cortex-M3 processor Interrupts and Nested power control Vectored Interrupt Cortex-M3 core Controller (NVIC) Data Flash Patch Trace Port Watchpoint Breakpoint Interface Unit And Trace (FPB) (TPIU) (DWT) Serial-Wire Or JTAG Instrumentation...
Page 25: Memory Map
GD32F1x0 User Manual Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices 1.2V TPIU GPIO Ports AHB2: Fma x = 72MHz POR/PDR A, B, C, D, F ARM Cortex-M3 Processor SRAM SRAM : 72MHz Controller IBus Flash : 72MHz Touch Flash Memory...
Page 26: Table 1-1. Memory Map Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual processor to reduce the software complexity of repeated implementation of different device ® ® vendors. However, some regions are used by the ARM Cortex -M3 system peripherals. The following figure shows the memory map of GD32F1x0 series, including Code, SRAM, peripheral, and other pre-defined regions.
Page 27 GD32F1x0 User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 0000 - 0x4001 03FF SYSCFG+CMP 0x4000 C400 - 0x4000 FFFF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6400 - 0x4000 6FFF...
Page 28: Bit-Banding
GD32F1x0 User Manual Bit-banding 1.3.1. ® In order to reduce the time of read-modify-write operations, the Cortex -M3 processor provides a bit-banding function to perform a single atomic bit operation. The memory map includes two bit-band regions. These occupy the SRAM and Peripherals respectively. These bit-band regions map each word in an alias region of memory to a bit in a bit-band region of memory.
Page 29: On-Chip Flash Memory
GD32F1x0 User Manual when reading non-initialized locations. On-chip Flash memory 1.3.3. The devices provide up to 64 KB of on-chip flash memory. The flash memory consists of up to 64 KB main flash organized into 64 pages with 1 KB capacity per page and a 3 KB information block for the boot loader.
Page 30 GD32F1x0 User Manual According to the selected boot source, either the main flash memory (original memory space beginning at 0x0800 0000) or the system memory (original memory space beginning at 0x1FFF EC00) is aliased in the boot memory space which begins at the address 0x0000 0000. When the on-chip SRAM whose memory space is beginning at 0x2000 0000 is selected as the boot source, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.
Page 31: System Configuration Registers (Syscfg)
GD32F1x0 User Manual 1.5. System configuration registers (SYSCFG) SYSCFG base address: 0x4001 0000 System configuration register 0 (SYSCFG_CFG0) 1.5.1. Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the BOOT1_n option bit after reset) This register has to be accessed by word(32-bit).
Page 32: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32F1x0 User Manual USART0_TX_DMA_ USART0_TX DMA request remapping enable 0: Not remap (USART0_TX DMA requests are mapped on DMA channel 1) 1: Remap (USART0_TX DMA requests are mapped on DMA channel 3) ADC_DMA_RMP ADC DMA request remapping enable 0: Not remap (ADC DMA requests are mapped on DMA channel 0) 1: Remap (ADC DMA requests are mapped on DMA channel 1) Reserved Must be kept at reset value...
Page 33: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32F1x0 User Manual X010: PC2 pin X011: PD2 pin X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI1_SS[3:0] EXTI 1 sources selection X000: PA1 pin X001: PB1 pin X010: PC1 pin X011: Reserved X100: Reserved X101: PF1 pin X110: Reserved X111: Reserved EXTI0_SS[3:0] EXTI 0 sources selection...
Page 34: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32F1x0 User Manual X010: PC7 pin X011: Reserved X100: Reserved X101: PF7 pin X110: Reserved X111: Reserved 11:8 EXTI6_SS[3:0] EXTI 6 sources selection X000: PA6 pin X001: PB6 pin X010: PC6 pin X011: Reserved X100: Reserved X101: PF6 pin X110: Reserved X111: Reserved EXTI5_SS[3:0] EXTI 5 sources selection...
Page 35 GD32F1x0 User Manual EXTI11_SS [3:0] EXTI10_SS [3:0] EXTI9_SS [3:0] EXTI8_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI11_SS[3:0] EXTI 11 sources selection X000: PA11 pin X001: PB11 pin X010: PC11 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved...
Page 36: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32F1x0 User Manual X111: Reserved EXTI sources selection register 3 (SYSCFG_EXTISS3) 1.5.5. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 37: System Configuration Register 2 (Syscfg_Cfg2)
GD32F1x0 User Manual X110: Reserved X111: Reserved EXTI12_SS[3:0] EXTI 12 sources selection X000: PA12 pin X001: PB12 pin X010: PC12 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved System configuration register 2 (SYSCFG_CFG2) 1.5.6. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 38: Device Electronic Signature
GD32F1x0 User Manual SRAM_PARITY_ SRAM parity check error lock ERROR_LOCK This bit is set by softw are and cleared by a system reset. 0: The SRAM parity check error is disconnected from the break input of TIMER0/14/15/16 1: The SRAM parity check error is connected from the break input of TIMER0/14/15/16 ®...
Page 39: Unique Device Id (96 Bits)
GD32F1x0 User Manual Unique device ID (96 bits) 1.6.2. Base address: 0x1FFF F7AC The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). UNIQUE_ID[31:16] UNIQUE_ID[15:0] Bits Fields Descriptions 31:0 UNIQUE_ID[31:0] Unique device ID Base address: 0x1FFF F7B0 The value is factory programmed and can never be altered by user.
Page 40 GD32F1x0 User Manual 31:0 UNIQUE_ID[95:64] Unique device ID...
Page 41: Flash Memory Controller (Fmc)
GD32F1x0 User Manual Flash memory controller (FMC) 2.1. Overview The Flash Memory Controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time within 32K bytes while CPU executes instruction. It also provides page erase, mass erase, and word/half word program for flash memory. 2.2.
Page 42: Read Operations
GD32F1x0 User Manual The Information Block stores the bootloader - this block cannot be programmed or Note: erased by user. Read operations 2.3.2. The flash can be addressed directly as a common memory space. Any instruction fetch and the data access from the flash are through the IBUS or DBUS from the CPU. Unlock the FMC_CTL register 2.3.3.
Page 43: Mass Erase
GD32F1x0 User Manual ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. If the target erasing page is being used for fetching codes or accessing data, the software may run out of control. The FMC will not provide any notification when this occurs. Additionally, the page erase operation will be ignored on protected pages.
Page 44: Figure 2-2. Process Of The Mass Erase Operation
GD32F1x0 User Manual  Write the mass erase command by setting MER bit in FMC_CTL register.  Send the mass erase command to the FMC by setting the START bit in FMC_CTL register.  Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_STAT register.
Page 45: Main Flash Programming
GD32F1x0 User Manual Main flash programming 2.3.6. The FMC provides a 32-bit word/16-bit half word programming function which is used to modify the main flash memory contents. The following steps show the word programming operation register access sequence.  Unlock the FMC_CTL register if necessary. ...
Page 46: Option Bytes Erase
GD32F1x0 User Manual Figure 2-3. Process of the word programming operation Start Is the LK bit 0 Unlock the FMC_CTL Is the BUSY bit 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit 0 Finish Option bytes erase 2.3.7.
Page 47: Option Bytes Programming
GD32F1x0 User Manual When the operation is executed successfully, an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. The end of this operation is indicated by the ENDF bit in the FMC_STAT register. Option bytes programming 2.3.8.
Page 48: Page Erase/Program Protection
GD32F1x0 User Manual Address Name Description [6]: SRAM_PARITY_CHECK 0: Enable sram parity check 1: Disable sram parity check [5]: VDDA_VISOR 0: Disable V monitor 1: Enable V monitor [4]: BOOT1_n 0: BOOT1 bit is 1 1: BOOT1 bit is 0 [3]: Reserved [2]: nRST_STDBY 0: Generate a reset instead of entering standby mode...
Page 49: Security Protection
GD32F1x0 User Manual by set OB_WP [15:0]. Table 2-3. OB_WP bit for pages protected OB_WP bit pages protected OB_WP[0] page 0 ~ page 3 OB_WP[1] page 4 ~ page 7 OB_WP[2] page 8 ~ page 11 OB_WP[14] page 56 ~ page 59 OB_WP[15] page 60 ~ page 63 Security protection...
Page 50: Register Definition
GD32F1x0 User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. WSCNT[2:0] Wait state counter register These bits set and reset by softw are.
Page 51: Option Bytes Unlock Key Register (Fmc_Obkey)
GD32F1x0 User Manual Write KEY[31:0] w ith key to unlock FMC_CTL register. Option bytes unlock key register (FMC_OBKEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_CTL option bytes operation unlock registers These bits are only be w ritten by softw are...
Page 52: Control Register (Fmc_Ctl)
GD32F1x0 User Manual softw are can clear it by w riting 1. Reserved Must be kept at reset value. PGERR Program error flag bit When programming to the flash w hile it is not 0xFFFF, this bit is set by hardw are. The softw are can clear it by w riting 1.
Page 53: Address Register (Fmc_Addr)
GD32F1x0 User Manual This bit is set by hardw are w hen right sequence w ritten to FMC_OBKEY register. This bit can be cleared by softw are. Reserved Must be kept at reset value. FMC_CTL lock bit This bit is cleared by hardw are w hen right sequent w ritten to FMC_KEY register. This bit can be set by softw are.
Page 54: Option Bytes Status Register (Fmc_Obstat)
GD32F1x0 User Manual ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash command address bits These bits are set by softw are. ADDR bits are the address of flash erase command Option bytes status register (FMC_OBSTAT) 2.4.7. Address offset: 0x1C Reset value: 0xXXXX XX0X This register has to be accessed by word(32-bit).
Page 55: Wait State Enable Register (Fmc_Wsen)
GD32F1x0 User Manual Reserved OB_WP[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 OB_WP[15:0] Store OB_WP[15:0] of option bytes block after system reset 0: Protection active 1: Unprotected Wait state enable register (FMC_WSEN) 2.4.9. Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 56 GD32F1x0 User Manual PID[31:16] PID[15:0] Bits Fields Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by softw are. These bits are unchanged constantly after pow er on. These bits are one time programmed w hen the chip product.
Page 57: Power Management Unit (Pmu)
GD32F1x0 User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32F1x0 series. The Power management unit (PMU), provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting Figure 3-1.
Page 58 GD32F1x0 User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP0 WKUPR BKP PAD WKUP1 PC13 WKUPN NRST WKUPF SLEEPING FWDGT Cortex-M3 SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V IRC14M...
Page 59: Backup Domain
GD32F1x0 User Manual Backup domain 3.3.1. The Backup domain is powered by the V or the battery power source (V ) selected by the internal power switch, and the V pin which drives Backup Domain, power supply for RTC unit, LXTAL oscillator, BPOR, and three pads, including PC13 to PC15. In order to keeping the content of the Backup domain registers and the RTC supply, when V supply is shut down, V...
Page 60: Vdd Domain
GD32F1x0 User Manual domain includes ADC / DAC (AD / DA Converter), IRC8M (Internal 8MHz RC oscillator), IRC14M (Internal 14MHz RC oscillator at 14MHz frequency), IRC40K (Internal 40KHz RC oscillator), PLLs (Phase Locking Loop), LVD (Low Voltage Detector), etc. domain 3.3.3.
Page 61: 1.2V Power Domain
GD32F1x0 User Manual domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register (PMU_CS), indicates if V is higher or lower than the LVD threshold.
Page 62: Power Saving Modes
GD32F1x0 User Manual Power saving modes 3.3.5. After a system reset or a power reset, the GD32F1x0 MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, PCLK2) or gating the clocks of the unused peripherals.
Page 63: Table 3-1. Power Saving Mode Summary
GD32F1x0 User Manual source If not, the program will skip the entry process of Deep-sleep mode to continue to execute the following procedure. Standby Mode ® The Standby mode is based on the SLEEPDEEP mode of the Cortex -M3, too. In Standby mode, the whole 1.2V domain for GD32F130/150xx devices, the LDO is shut down, and all of IRC8M, IRC14M for GD32F130/150xx devices, HXTAL and PLLs are disabled.
Page 64: Register Definition
GD32F1x0 User Manual when configured for RTC function, PC14 and PC15 pins when used as LXTAL crystal oscillator pins, and WKUP pin if enabled. 3.4. Register definition PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit).
Page 65: Power Control/Status Register (Pmu_Cs)
GD32F1x0 User Manual 0: No effect 1: Reset the standby flag This bit is alw ays read as 0. WURST Wakeup Flag Reset 0: No effect 1: Reset the w akeup flag This bit is alw ays read as 0. STBMOD Standby Mode ®...
Page 66 GD32F1x0 User Manual 1: Enable WKUP0 pin function If WUPEN0 is set before entering the Standby mode, a rising edge on the WKUP0 pin w akes up the system from the Standby mode. As the WKUP0 pin is active high, the WKUP0 pin is internally configured to input pull dow n mode.
Page 67: Reset And Clock Unit (Rcu)
GD32F1x0 User Manual Reset and clock unit (RCU) 4.1. Reset control unit (RCTL) Overview 4.1.1. GD32F1x0 reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, res ets the full system except the backup domain during a power up.
Page 68: Clock Control Unit (Cctl)
GD32F1x0 User Manual source (external or internal reset). Figure 4-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have previously been powered off).
Page 69: Figure 4-2. Clock Tree
GD32F1x0 User Manual Figure 4-2. Clock tree CK_ LXTAL CK_CEC (to CEC) ÷ 244 CECSEL USBD CK_USB Prescaler (to USB) ÷ 1,1.5,2,2.5 CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable (to FMC) (by hardware) HCLK CK_IRC8M AHB enable (to AHB bus,Cortex-M3,SRAM,DMA) 8 MHz CK_CST ×2,3,4...
Page 70: Characteristics
GD32F1x0 User Manual Characteristics 4.2.2.  3 to 25 MHz high speed crystal oscillator (HXTAL).  Internal 8 MHz RC oscillator (IRC8M).  Internal 14 MHz RC oscillator (IRC14M).  32,768 Hz Low speed crystal oscillator (LXTAL).  Internal 40KHz RC oscillator (IRC40K). ...
Page 71 GD32F1x0 User Manual Internal 8 MHz RC oscillator (IRC8M) The internal 8 MHz RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up. The IRC8M oscillator provides a lower cost type clock source as no external components are required.
Page 72 GD32F1x0 User Manual LXTAL becomes stable. Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the backup domain control register (RCU_BDCTL). The CK_LXTAL is equal to the external clock which drives the OSC32IN pin. Internal 40KHz RC oscillator (IRC40K) The internal 40KHz RC oscillator has a frequency of about 40 kHz and is a low power clock source for the real time clock circuit or the free watchdog timer.
Page 73: Table 4-1. Clock Source Select
GD32F1x0 User Manual Table 4-1. Clock source select Clock Source Selection bits Clock Source No Clock CK_IRC14M CK_IRC40K CK_LXTAL CK_SYS CK_IRC8M CK_HXTAL CK_PLL or CK_PLL/2 The CK_OUT frequency can be reduced by a configurable binary divider, controlled by the CKOUTDIV[2:0] bits , in the Configuration register 0 (RCU_CFG0). Deep-sleep mode clock control When the MCU is in deep-sleep mode, the HDMI CEC or USART0 can wake up the MCU, when their clock is provided by LXTAL clock and LXTAL clock is enable.
Page 74: Register Definition
GD32F1x0 User Manual 4.3. Register definition RCU base address: 0x4002 1000 Control register 0 (RCU_CTL0) 4.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLLSTB PLLEN...
Page 75: Configuration Register 0 (Rcu_Cfg0)
GD32F1x0 User Manual HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be w ritten only if the HXTALEN is 0. 0: Disable the HXTAL bypass mode. 1: Enable the HXTAL bypass mode in w hich the HXTAL output clock is equal to the input clock.
Page 76 GD32F1x0 User Manual PLLPRE PLLDV CKOUTDIV[2:0] PLLMF[4] CKOUTSEL[2:0] USBDPSC[1:0] PLLMF[3:0] PLLSEL ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions PLLDV The CK_PLL divide by 1 or 2 for CK_OUT 0: CK_PLL divide by 2 for CK_OUT 1: CK_PLL divide by 1 for CK_OUT 30:28 CKOUTDIV[2:0] The CK_OUT divider w hich the CK_OUT frequency can be reduced...
Page 77 GD32F1x0 User Manual These bits and bit 27 of RCU_CFG0 are w ritten by softw are to define the PLL multiplication factor. 00000: (PLL source clock x 2) 00001: (PLL source clock x 3) 00010: (PLL source clock x 4) 00011: (PLL source clock x 5) 00100: (PLL source clock x 6) 00101: (PLL source clock x 7)
Page 78 GD32F1x0 User Manual Set and reset by softw are to control the PLL clock source. 0: (CK_IRC8M / 2) selected as PLL source clock 1: HXTAL selected as PLL source clock 15:14 ADCPSC[1:0] ADC clock prescaler selection Set and cleared by softw are. 00: (CK_APB2 / 2) selected 01: (CK_ APB2 / 4) selected 10: (CK_ APB2 / 6) selected...
Page 79: Interrupt Register (Rcu_Int)
GD32F1x0 User Manual Set by softw are to select the CK_SYS source. Because the change of CK_SYS has inherent latency, softw are should read SCSS to confirm w hether the sw itching is complete or not. The sw itch w ill be forced to IRC8M w hen leaving Deep-sleep and Standby mode or by HXTAL clock monitor w hen the HXTAL failure is detected and the HXTAL is selected as the clock source of CK_SYS or PLL.
Page 80 GD32F1x0 User Manual 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC IRC8M stabilization interrupt clear Write 1 by softw are to reset the IRC8MSTBIF flag. 0: Not reset IRC8MSTBIF flag 1: Reset IRC8MSTBIF flag LXTALSTBIC LXTAL stabilization interrupt clear Write 1 by softw are to reset the LXTALSTBIF flag.
Page 81 GD32F1x0 User Manual 1: Enable the IRC40K stabilization interrupt CKMIF HXTAL clock stuck interrupt flag Set by hardw are w hen the HXTAL clock is stuck. Reset by softw are when setting the CKMIC bit. 0: Clock operating normally 1: HXTAL clock stuck Reserved Must be kept at reset value.
Page 82: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F1x0 User Manual 1: IRC40K stabilization interrupt generated APB2 reset register (RCU_APB2RST) 4.3.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). TIMER16 TIMER15 TIMER14 Reserved USART0 TIMER0 CFGCMP Reserved Reserved. SPI0RST Reserved ADCRST Reserved Bits...
Page 83: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F1x0 User Manual TIMER0RST TIMER0 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER0 Reserved Must be kept at reset value. ADCRST ADC reset This bit is set and reset by softw are. 0: No reset 1: Reset the ADC Reserved...
Page 84 GD32F1x0 User Manual 1: Reset DAC unit PMURST Pow er control reset This bit is set and reset by softw are. 0: No reset 1: Reset pow er control unit 27:24 Reserved Must be kept at reset value. USBDRST USBD reset This bit is set and reset by softw are.
Page 85: Ahb Enable Register (Rcu_Ahben)
GD32F1x0 User Manual 10:9 Reserved Must be kept at reset value. TIMER13RST TIMER13 timer reset This bit is set and reset by softw are. 0: No reset 1: Reset TIMER13 Timer Reserved Must be kept at reset value. TIMER5RST TIMER5 timer reset This bit is set and reset by softw are.
Page 86 GD32F1x0 User Manual 1: Enabled TSI clock Reserved Must be kept at reset value. PFEN GPIO port F clock enable This bit is set and reset by softw are 0: Disabled GPIO port F clock 1: Enabled GPIO port F clock Reserved Must be kept at reset value.
Page 87: Apb2 Enable Register (Rcu_Apb2En)
GD32F1x0 User Manual 0: Disabled SRAM interface clock during Sleep mode 1: Enabled SRAM interface clock during Sleep mode Reserved Must be kept at reset value. DMAEN DMA clock enable This bit is set and reset by softw are. 0: Disabled DMA clock 1: Enabled DMA clock APB2 enable register (RCU_APB2EN) 4.3.7.
Page 88: Apb1 Enable Register (Rcu_Apb1En)
GD32F1x0 User Manual 0: Disabled USART0 clock 1: Enabled USART0 clock Reserved Must be kept at reset value. SPI0EN SPI0 clock enable This bit is set and reset by softw are. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER0EN TIMER0 timer clock enable This bit is set and reset by softw are.
Page 89 GD32F1x0 User Manual This bit is set and reset by softw are. 0: Disabled HDMI CEC interface clock 1: Enabled HDMI CEC interface clock DACEN DAC interface clock enable This bit is set and reset by softw are. 0: Disabled DAC interface clock 1: Enabled DAC interface clock PMUEN Pow er interface clock enable...
Page 90: Backup Domain Control Register (Rcu_Bdctl)
GD32F1x0 User Manual 13:12 Reserved Must be kept at reset value. WWDGTEN Window w atchdog timer clock enable This bit is set and reset by softw are. 0: Disabled Window w atchdog timer clock 1: Enabled Window w atchdog timer clock 10:9 Reserved Must be kept at reset value.
Page 91 GD32F1x0 User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. BKPRST Backup domain reset This bit is set and reset by softw are. 0: No reset 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by softw are. 0: Disabled RTC clock 1: Enabled RTC clock 14:10...
Page 92: Reset Source /Clock Register (Rcu_Rstsck)
GD32F1x0 User Manual Reset source /clock register (RCU_RSTSCK) 4.3.10. Address offset: 0x24 Reset value: 0x0C00 0000, reset flags reset by power Reset only, other reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). WWDGT FWDGT PORRST OBLRST LPRSTF...
Page 93: Ahb Reset Register (Rcu_Ahbrst)
GD32F1x0 User Manual 0: No pow er reset generated 1: Pow er reset generated EPRSTF External PIN reset flag Set by hardw are w hen an External PIN generated. Reset by w riting 1 to the RSTFC bit. 0: No external PIN reset generated 1: External PIN reset generated OBLRSTF Option byte loader reset flag...
Page 94: Configuration Register 1 (Rcu_Cfg1)
GD32F1x0 User Manual Reserved. Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. TSIRST TSI unit reset This bit is set and reset by softw are. 0: No reset TSI unit 1: Reset TSI unit Reserved Must be kept at reset value. PFRST GPIO port F reset This bit is set and reset by softw are.
Page 95: Configuration Register 2 (Rcu_Cfg2)
GD32F1x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved HXTALPREDV[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. HXTALPREDV[3:0] CK_HXTAL divider previous PLL This bit is set and reset by softw are. These bits can be w ritten w hen PLL is disable Note: The bit 0 of HXTALPREDV is same as bit 17 of RCU_CFG0, so modifying bit 17 of RCU_CFG0 aslo modifies bit 0 of RCU_CFG2.
Page 96: Control Register 1 (Rcu_Ctl1)
GD32F1x0 User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. ADCSEL CK_ADC clock source selection This bit is set and reset by softw are. 0: CK_ADC select CK_IRC14M 1: CK_ADC select CK_APB2 w hich is divided by 2/4/6/8. Reserved Must be kept at reset value.
Page 97: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F1x0 User Manual MHz ± 1%. Reserved Must be kept at reset value. IRC14MSTB IRC14M internal 14M RC oscillator stabilization flag Set by hardw are to indicate if the IRC14M oscillator is stable and ready for use. 0: IRC14M oscillator is not stable 1: IRC14M oscillator is stable IRC14MEN IRC14M Internal 14M RC oscillator enable...
Page 98: Voltage Key Register (Rcu_Vkey)
GD32F1x0 User Manual Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. I2C2RST I2C2 unit reset This bit is set and reset by softw are 0: Not reset I2C2 unit 1: Reset I2C2 unit Voltage key register (RCU_VKEY) 4.3.17.
Page 99: Power Down Voltage Select Register (Rcu_Pdvsel)
GD32F1x0 User Manual DSLPVS[2:0] Deep-sleep mode voltage select These bits is set and reset by softw are 000 : The core voltage is 1.2V in Deep-sleep mode 001 : The core voltage is 1.1V in Deep-sleep mode 010 : The core voltage is 1.0V in Deep-sleep mode 011 : The core voltage is 0.9V in Deep-sleep mode 100~111 : Reserved Power down voltage select register (RCU_PDVSEL)
Page 100: Interrupt / Event Controller (Exti)
GD32F1x0 User Manual Interrupt / event controller (EXTI) Overview 5.1. Cortex -M3 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception ® and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processor core. You can read the Technical Reference Manual of Cortex -M3 for more details about NVIC.
Page 101: Table 5-2. Nvic Exception Types In Cotrex
GD32F1x0 User Manual Table 5-1. NVIC exception types in Cotrex ® Vector Exception type Priority (a) Vector address Description num ber 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable...
Page 102 GD32F1x0 User Manual Interrupt Vector Peripheral interrupt description Vector address num ber num ber IRQ 17 TIMER5 and DAC global interrupts 0x0000_0084 IRQ 18 Reserved 0x0000_0088 IRQ 19 TIMER13 global interrupt 0x0000_008C IRQ 20 TIMER14 global interrupt 0x0000_0090 IRQ 21 TIMER15 global interrupt 0x0000_0094 IRQ 22...
Page 103: External Interrupt And Event Block Diagram
GD32F1x0 User Manual External interrupt and event block diagram 5.4. Figure 5-1. Block diagram of EXTI. Polarity Software Control Trigger EXTI Line0~22 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External interrupt and event function overview 5.5.
Page 104: Table 5-4. Exti Source
GD32F1x0 User Manual Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in SYSCFG module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 105 GD32F1x0 User Manual EXTI line num ber Source RTC alarm USBD w akeup RTC tamper and timestamp Reserved CMP0 output CMP1 output Reserved Reserved USART0 w akeup Reserved CEC w akeup...
Page 106: Register Definition
GD32F1x0 User Manual Register definition 5.6. EXTI base address: 0x4001 0400 Interrupt Enable register (EXTI_INTEN) 5.6.1. Address offset: 0x00 Reset value: 0x0F90 0000 This register has to be accessed by word(32-bit). Reserved INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 107: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F1x0 User Manual Rising edge trigger enable register (EXTI_RTEN) 5.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN22 RTEN21 Reserved RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6...
Page 108: Software Interrupt Event Register (Exti_Swiev)
GD32F1x0 User Manual Bits Fields Descriptions 31: 23 Reserved Must be kept at reset value. 22: 21 FTENx Falling edge trigger enable (x = 21, 22) 0: Falling edge of linex is invalid 1: Falling edge of linex is valid as an interrupt / event request Reserved Must be kept at reset value.
Page 109: Pending Register (Exti_Pd)
GD32F1x0 User Manual 0: Deactivate the EXTIx softw are interrupt / event request 1: Activate the EXTIx softw are interrupt / event request Pending register (EXTI_PD) 5.6.6. Address offset: 0x14 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). Reserved PD22 PD21...
Page 110: General-Purpose I/Os (Gpio)
GD32F1x0 User Manual General-purpose I/Os (GPIO) Overview 6.1. There are up to 55 general purpose I/O pins, (GPIO), named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4 ~ PF7 for the device to implement logic input/output functions.
Page 111: Gpio Pin Configuration
GD32F1x0 User Manual Floating GPIO Pull-up INPUT Pull-dow n Floating Push-pull Pull-up GPIO Pull-dow n OUTPUT Floating Open-drain Pull-up Pull-dow n Floating AFIO Pull-up INPUT Pull-dow n Floating Push-pull Pull-up AFIO Pull-dow n OUTPUT Floating Open-drain Pull-up Pull-dow n ANALOG Figure 6-1.
Page 112: Alternate Functions (Af)
GD32F1x0 User Manual PA14: SWCLK in AF pull-down mode PA13: SWDIO in AF pull-up mode The GPIO pins can be configured as inputs or outputs. And all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen. When the GPIO pins are configured as input pins, the data on the external pads can be captured at every AHB clock cycle to the port input status register (GPIOx_ISTAT).
Page 113: Output Configuration
GD32F1x0 User Manual Figure 6-2. Basic structure of Input configuration Output configuration 6.3.5. When GPIO pin is configured as output:  The schmitt trigger input is activated.  The weak pull-up and pull-down resistors could be chosen.  The output buffer is enabled: –...
Page 114: Alternate Function (Af) Configuration
GD32F1x0 User Manual  The weak pull-up and pull-down resistors are disabled.  The output buffer is disabled.  The schmitt trigger input is de-activated.  Read access to the port input status register gets the value “0”. Figure 6-4. Basic structure of Analog configuration shows the high impedance-analog configuration.
Page 115: Gpio Locking Function
GD32F1x0 User Manual Figure 6-5. Basic structure of Alternate function configuration Output driver Alternate Function Output protect I / O pin Alternate Function Input Input driver GPIO locking function 6.3.8. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD, GPIOx_AFSELy(y=0,1).
Page 116: Register Definition
GD32F1x0 User Manual 6.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOF base address: 0x4800 1400 Port control register (GPIOx_CTL, x=A..D,F) 6.4.1. Address offset: 0x00 Reset value: 0x2800 0000 for port A;...
Page 117: Port Output Mode Register (Gpiox_Omode, X=A
GD32F1x0 User Manual 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by softw are. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by softw are. Refer to CTL0[1:0] description 15:14 CTL7[1:0] Pin 7 configuration bits...
Page 118 GD32F1x0 User Manual Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value OM15 Pin 15 output mode bit These bits are set and cleared by softw are. Refer to OM0 description OM14 Pin 14 output mode bit These bits are set and cleared by softw are.
Page 119: Port Output Speed Register (Gpiox_Ospd, X=A
GD32F1x0 User Manual Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by softw are. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by softw are. Refer to OM0 description Pin 3 output mode bit These bits are set and cleared by softw are.
Page 120 GD32F1x0 User Manual Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by softw are. Refer to OSPD0[1:0 ] description 25:24 OSPD12[1:0] Pin 12 output max speed bits These bits are set and cleared by softw are. Refer to OSPD0[1:0] description 23:22 OSPD11[1:0]...
Page 121: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32F1x0 User Manual OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by softw are. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits These bits are set and cleared by softw are. x0: Output max speed 2M (reset value) 01: Output max speed 10M 11: Output max speed 50M Port pull-up/down register (GPIOx_PUD, x=A..D,F)
Page 122: Port Input Status Register (Gpiox_Istat, X=A
GD32F1x0 User Manual Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-dow n bits These bits are set and cleared by softw are. Refer to PUD0[1:0] description 17:16 PUD8[1:0] Pin 8 pull-up or pull-dow n bits These bits are set and cleared by softw are. Refer to PUD0[1:0] description 15:14 PUD7[1:0]...
Page 123: Port Output Control Register (Gpiox_Octl, X=A
GD32F1x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3 ISTAT2 ISTAT1 ISTAT0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 ISTATy[15:0] Port input status (y=0..15)
Page 124: Port Configuration Lock Register (Gpiox_Lock, X=A, B)
GD32F1x0 User Manual CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by softw are. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit 15:0...
Page 125: Alternate Function Selected Register0 (Gpiox_Afsel0, X=A, B, C)
GD32F1x0 User Manual 0: Port configuration not locked 1: Port configuration locked Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C) 6.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SEL7[3:0] SEL6[3:0] SEL5[3:0] SEL4[3:0] SEL3[3:0]...
Page 126: Alternate Function Selected Register1 (Gpiox_Afsel1, X=A,B,C)
GD32F1x0 User Manual 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected 0100: AF4 selected (Port A,B only) 0101: AF5 selected (Port A,B only) 0110: AF6 selected (Port A,B only) 0111: AF7 selected (Port A,B only) 1000 ~ 1111: Reserved Alternate function selected register1 (GPIOx_AFSEL1, x=A,B,C) 6.4.10.
Page 127: Bit Clear Register (Gpiox_Bc, X=A
GD32F1x0 User Manual Refer to SEL8[3:0] description SEL9[3:0] Pin 9 alternate function selected These bits are set and cleared by softw are. Refer to SEL8[3:0] description SEL8[3:0] Pin 8 alternate function selected These bits are set and cleared by softw are. 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected...
Page 128: Cyclic Redundancy Checks Management Unit (Crc)
GD32F1x0 User Manual Cyclic redundancy checks management unit (CRC) 7.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32/16/8 bit CRC code within fixed polynomial.
Page 129: Function Overview
GD32F1x0 User Manual Figure 7-1. Block Diagram of CRC management unit Data Input Input Data Register (32 bit) CRC Management Unit Fixed polynomial 0x4C11DB7 Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) 7.3. Function overview ...
Page 130 GD32F1x0 User Manual 1) byte reverse: 32-bit data is divided into 4 groups and reverse implement in group inside. Reversed data: 0x2C6AB3F7 2)half-word reverse: 32-bit data is divided into 2 groups and reverse implement in group inside. Reversed data: 0x6A2CF7B3 3)word reverse: 32-bit data is divided into 1 groups and reverse implement in group inside.
Page 131: Register Definition
GD32F1x0 User Manual 7.4. Register definition CRC base address: 0x4002 3000 Data Register (CRC_DATA) 7.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word(32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Softw are w rite and read.
Page 132: Control Register (Crc_Ctl)
GD32F1x0 User Manual These bits are unrelated w ith CRC calculation. This byte can be used for any goals by any other peripheral. The CRC_CTL register w ill generate no effect to the byte. Control Register (CRC_CTL) 7.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 133 GD32F1x0 User Manual IDATA [15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA w ill be programmed to this value.
Page 134: Direct Memory Access Controller (Dma)
GD32F1x0 User Manual Direct memory access controller (DMA) 8.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 135: Block Diagram
GD32F1x0 User Manual 8.3. Block diagram Figure 8-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 136: Table 8-1. Dma Transfer Operation
GD32F1x0 User Manual Table 8-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 137: Peripheral Handshake
GD32F1x0 User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 138: Address Generation
GD32F1x0 User Manual – Software priority: Four levels, including low, medium, high and ultra-high by configuring the PRIO bits in the DMA_CHxCTL register. – For channels with equal software priority level, priority is given to the channel with lower channel number. Address generation 8.4.4.
Page 139: Interrupt
GD32F1x0 User Manual 4. Confi gure the PRIO bits in the DMA_CHxCTL register to set the channel software priority. 5. Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register. 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register.
Page 140: Dma Request Mapping
GD32F1x0 User Manual DMA request mapping 8.4.9. Several requests from peripherals may be mapped to one DMA channel. They are logically ORed before entering the DMA. For details, see the following Figure 8-4. DMA request mapping. The request of each peripheral can be independently enabled or disabled by programming the registers of the corresponding peripheral.
Page 141: Figure 8-4. Dma Request Mapping
GD32F1x0 User Manual Figure 8-4. DMA request mapping ADC(1) Hardware TIMER1_CH2 TIMER16_CH0(1) priority Channel 0 TIMER16_UP(1) ADC(2) SPI0_RX USART0_TX(1) I2C0_TX TIMER0_CH0 Channel 1 TIMER1_UP high TIMER2_CH2 TIMER16_CH0(2) TIMER16_UP(2) SPI0_TX USART0_RX(1) I2C0_RX TIMER0_CH1 TIMER1_CH1 TIMER2_CH3 Channel 2 TIMER2_UP TIMER5_UP DAC0 TIMER15_CH0(1) TIMER15_UP(1) SPI1_RX USART0_TX(2)
Page 142 GD32F1x0 User Manual Table 8-3. DMA requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● ● ● ADC(1) ADC(2) ● SPI/I2S SPI/I2S0_RX SPI/I2S0_TX SPI1_RX SPI1_TX SPI2_RX SPI2_TX USART0_TX(2) USART0_RX(2) ●...
Page 143: Register Definition
GD32F1x0 User Manual 8.5. Register definition DMA base address: 0x4002 0000 Interrupt flag register (DMA_INTF) 8.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved ERRIF6 HTFIF6 FTFIF6 GIF6 ERRIF5 HTFIF5 FTFIF5 GIF5 ERRIF4 HTFIF4 FTFIF4...
Page 144: Channel X Control Register (Dma_Chxctl)
GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0 Bits Fields Descriptions...
Page 145 GD32F1x0 User Manual Softw are set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be w ritten w hen CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Softw are set and cleared 00: Low 01: Medium 10: High...
Page 146: Channel X Counter Register (Dma_Chxcnt)
GD32F1x0 User Manual Transfer direction Softw are set and cleared 0: Read from peripheral and w rite to memory 1: Read from memory and w rite to peripheral This bit can not be w ritten w hen CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Softw are set and cleared...
Page 147: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F1x0 User Manual is read-only, and decreases after each DMA transfer. If the register is zero, no transaction can be issued w hether the channel is enabled or not. Once the transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode.
Page 148 GD32F1x0 User Manual 31:0 MADDR[31:0] Memory base address These bits can not be w ritten w hen CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half w ord address. When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the tw o LSBs of these bits are ignored.
Page 149: Debug (Dbg)
GD32F1x0 User Manual Debug (DBG) 9.1. Overview The GD32F1x0 series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M3.
Page 150: Debug Hold Function Overview
GD32F1x0 User Manual 9.3. Debug hold function overview Debug support for power saving mode 9.3.1. When STB_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in standby mode.
Page 151: Dbg Registers
GD32F1x0 User Manual 9.4. DBG registers DBG base address: 0xE004 2000 ID code register (DBG_ID) 9.4.1. Address: 0xE004 2000 This register has to be accessed by word(32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by softw are, These bits are unchanged constant. Control register 0(DBG_CTL0) 9.4.2.
Page 152 GD32F1x0 User Manual This bit is set and reset by softw are. 0: no effect 1: hold the TIMER5 counter for debug w hen core is halted Reserved Must be kept at reset value I2C2_HOLD I2C2 hold bit This bit is set and reset by softw are. 0: no effect 1: hold the I2C2 SMBUS timeout for debug w hen core is halted I2C1_HOLD...
Page 153: Control Register 1 (Dbg_Ctl1)
GD32F1x0 User Manual This bit is set and reset by softw are. 0: no effect 1: in the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, a system reset generated w hen exiting standby mode. DSLP_HOLD Deep-sleep mode hold bit This bit is set and reset by softw are.
Page 154 GD32F1x0 User Manual 1: hold the TIMER14 counter for debug w hen core is halted 15:11 Reserved Must be kept at reset value RTC_HOLD RTC hold bit This bit is set and reset by softw are. 0: no effect 1: hold the RTC counter for debug w hen core is halted Reserved Must be kept at reset value...
Page 155: Analog To Digital Converter (Adc)
GD32F1x0 User Manual Analog to digital converter (ADC) 10.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels, 2 internal channels and the battery voltage (V ) channel.
Page 156: Pins And Internal Signals
GD32F1x0 User Manual 10.3. Pins and internal signals Figure 10-1. ADC module block diagram show the ADC block diagram.Table 10-1. ADC give the ADC internal signals internal input signals, Table 10-2. ADC input pins definition and pins description. Table 10-1. ADC internal input signals Internal signal nam e Description Internal temperature sensor output voltage...
Page 157: Function Overview
GD32F1x0 User Manual 10.4. Function overview Figure 10-1. ADC module block diagram Trig select DMA request Routine channels Interrupt Interrupt Channel Mangement generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Routine data registers ADC_IN15 SAR ADC 12-bit （16 bits） BAT/2 SENSE REFINT self calibration...
Page 158: Dual Clock Domain Architecture
GD32F1x0 User Manual Dual clock domain architecture 10.4.2. The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock, which can be asynchronous and independent from the APB clock. Application can reduce PLCK frequency for low power operation while still keeping optimum ADC performance.
Page 159: Figure 10-3. Continuous Operation Mode
GD32F1x0 User Manual Configure RSQ0 with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if it is needed. Set the SWRCST bit, or generate an external trigger for the routine sequence. Wait the EOC flag to be set. Read the converted data result in the ADC_RDATA register.
Page 160: Figure 10-4. Scan Operation Mode, Continuous Disable
GD32F1x0 User Manual specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in routine sequence till the end of sequence, once the corresponding software trigger or external trigger is active. The conversion data will be stored in the ADC_RDATA register.
Page 161: Conversion Result Threshold Monitor Function
GD32F1x0 User Manual EOCIE bit is set. Figure 10-6. Discontinuous operation mode Software procedure for discontinuous operation mode on a routine sequence: Set the DISRC bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure DISNUM [2:0] bits in the ADC_CTL0 register. Configure ADC_RSQx and ADC_SAMPTx registers.
Page 162: Sample Time Configuration
GD32F1x0 User Manual Figure 10-7. Data storage mode of 12-bit resolution Figure 10-8. Data storage mode of 10-bit resolution Figure 10-9. Data storage mode of 8-bit resolution Figure 10-10. Data storage mode of 6-bit resolution Routine channel data DAL=0 DAL=1 Sample time configuration 10.4.8.
Page 163: External Trigger Configuration
GD32F1x0 User Manual External trigger configuration 10.4.9. The conversion of routine sequence can be triggered by rising edge of external trigger inputs. The external trigger source of routine sequence is controlled by the ETSRC [2:0] bits in the ADC_CTL1 register. Table 10-3.
Page 164: Battery Voltage Monitoring
GD32F1x0 User Manual the channel. Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the internal temperature sensor output voltage(V ), and get the temperature temperature with the following equation:...
Page 165: Register Definition
GD32F1x0 User Manual 10.5. Register definition ADC base address: 0x4001 2400 Status register (ADC_STAT) 10.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved STRC Reserved rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:5 Reserved...
Page 166 GD32F1x0 User Manual This register has to be accessed by word (32-bit). Reserved RWDEN Reserved DISNUM [2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. RWDEN Routine channel analog w atchdog enable 0: Analog w atchdog routine channel disable 1: Analog w atchdog routine channel enable 22:16...
Page 167: Control Register 1 (Adc_Ctl1)
GD32F1x0 User Manual 00001: ADC channel1 00010: ADC channel2 …… 01111: ADC channel15 10000: ADC channel16 10001: ADC channel17 10010: ADC channel18 Other values are reserved. Note: ADC analog inputs Channel16, Channel17 and Channel 18 are internally connected to the temperature sensor, to V and to V analog inputs.
Page 168: Sampling Time Register 0 (Adc_Sampt0)
GD32F1x0 User Manual 19:17 ETSRC[2:0] External trigger select for routine sequence 000: TIMER0 CH0 001: TIMER0 CH1 010: TIMER0 CH2 011: TIMER1 CH1 100: TIMER2 TRGO 101: TIMER14 CH0 110: EXTI line 11 111: SWRCST 16:12 Reserved Must be kept at reset value Data alignment 0: LSB alignment 1: MSB alignment...
Page 169: Sampling Time Register 1 (Adc_Sampt1)
GD32F1x0 User Manual This register has to be accessed by word (32-bit). Reserved SPT17[2:0] SPT16[2:0] SPT15[2:1] SPT15[0] SPT14[2:0] SPT13[2:0] SPT12[2:0] SPT11[2:0] SPT10[2:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:21 SPT17[2:0] Refer to SPT10[2:0] description 20:18 SPT16[2:0] Refer to SPT10[2:0] description 17:15...
Page 170: Watchdog High Threshold Register (Adc_Wdht)
GD32F1x0 User Manual SPT5[0] SPT4[2:0] SPT3[2:0] SPT2[2:0] SPT1[2:0] SPT0[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:27 SPT9[2:0] Refer to SPT0[2:0] description 26:24 SPT8[2:0] Refer to SPT0[2:0] description 23:21 SPT7[2:0] Refer to SPT0[2:0] description 20:18 SPT6[2:0] Refer to SPT0[2:0] description 17:15 SPT5[2:0]...
Page 171: Watchdog Low Threshold Register (Adc_Wdlt)
GD32F1x0 User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 WDHT[11:0] High threshold for analog w atchdog These bits define the high threshold for the analog w atchdog. Watchdog low threshold register (ADC_WDLT) 10.5.7. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 172: Routine Sequence Register 1 (Adc_Rsq1)
GD32F1x0 User Manual The total number of conversion in routine sequence equals to RL [3:0] +1. 19:15 RSQ15[4:0] Refer to RSQ0[4:0] description 14:10 RSQ14[4:0] Refer to RSQ0[4:0] description RSQ13[4:0] Refer to RSQ0[4:0] description RSQ12[4:0] Refer to RSQ0[4:0] description Routine sequence register 1 (ADC_RSQ1) 10.5.9.
Page 173: Routine Data Register (Adc_Rdata)
GD32F1x0 User Manual RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:25 RSQ5[4:0] Refer to RSQ0[4:0] description 24:20 RSQ4[4:0] Refer to RSQ0[4:0] description 19:15 RSQ3[4:0] Refer to RSQ0[4:0] description 14:10 RSQ2[4:0] Refer to RSQ0[4:0] description RSQ1[4:0] Refer to RSQ0[4:0] description RSQ0[4:0]...
Page 174: Characteristic
GD32F1x0 User Manual The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability. Characteristic 11.2.
Page 175: Function Overview
GD32F1x0 User Manual Function overview 11.3. DAC enable 11.3.1. The DAC can be powered on by setting the DENx bit in the DAC_CTL register. A t time WAKEUP is needed to startup the analog DAC submodule. DAC output buffer 11.3.2. For the concern of reducing output impedance, and driving external loads ,an output buffer is integrated inside each DAC module.
Page 176: Dac Workflow
GD32F1x0 User Manual DTSELx[2:0] Trigger Source Trigger Type 3b’110 EXTI_9 3b’111 SWTR Softw are trigger The TIMERx_TRGO signals are generated from the timers, while the software trigger can be generated by setting the SWTRx bit in the DAC_SWT register. DAC workflow 11.3.5.
Page 177: Register Definition
GD32F1x0 User Manual Register definition 11.4. DAC base address: 0x4000 7400 Control register (DAC_CTL) 11.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DDUDRIE DDMAEN Reserved Reserved DTSEL0[2:0] DTEN0 DBOFF0 DEN0 Bits Fields Descriptions...
Page 178: Software Trigger Register (Dac_Swt)
GD32F1x0 User Manual 0: DAC0 trigger disabled 1: DAC0 trigger enabled DBOFF0 DAC0 output buffer turn off This bit is set and cleared by softw are to enable/disable DAC0 output buffer. 0: DAC0 output buffer turns on to reduce the output impedance and improve the driving capability 1: DAC0 output buffer turn off DEN0...
Page 179: Dac0 12-Bit Left-Aligned Data Holding Register (Dac0_L12Dh)
GD32F1x0 User Manual Reserved DAC0_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC0_DH[11:0] DAC0 12-bit right-aligned data These bits specify the data that is to be converted by DAC0. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) 11.4.4.
Page 180: Dac0 Data Output Register (Dac0_Do)
GD32F1x0 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. DAC0_DH[7:0] DAC0 8-bit right-aligned data. These bits specify the data that is to be converted by DAC0. DAC0 data output register (DAC0_DO) 11.4.6. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 181 GD32F1x0 User Manual 0: No DMA underrun error condition occurred 1: DMA underrun error condition occurred (the frequency of the current selected trigger that is driving DAC conversion is higher than the DMA service capability rate) 12:0 Reserved Must be kept at reset value...
Page 182: Comparator (Cmp)
GD32F1x0 User Manual Comparator (CMP) Overview 12.1. The general purpose comparators, CMP0 and CMP1, can work either standalone (all terminal are available on I/Os) or together with the timers. Characteristics 12.2. Rail-to-rail comparators.  Configurable hysteresis.  Configurable speed and consumption. ...
Page 183: Cmp Clock And Reset
GD32F1x0 User Manual Figure 12-1. CMP block diagram Note: V is 1.2V. REFINT CMP clock and reset 12.3.1. The CMP clock is synchronous with the PCLK. The CMP share common reset and clock enable bits with SYSCFG. CMP I/O configure 12.3.2.
Page 184: Cmp Operating Mode
GD32F1x0 User Manual CMP operating mode 12.3.3. For a given application, there is a trade-off between the CMP power consumption versus propagation delay, which is adjusted by configuring bits CMPxM [1:0] in CMP_CS register. The CMP works fastest with highest power consumption when CMPxM = 2’b00, while works slowest with lowest power consumption when CMPxM = 2’b11.
Page 185: Register Definition
GD32F1x0 User Manual 12.4. Register definition CMP base address: 0x4001 001C Control/status register (CMP_CS) 12.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1LK CMP1O CMP1HST[1:0] CMP1PL CMP1OSEL[2:0] WNDEN CMP1MSEL[2:0] CMP1M Reserved CMP1EN rw/r rw/r rw/r...
Page 186 GD32F1x0 User Manual 010: TIMER 0 channel0 Input capture 011: TIMER 0 OCPRE_CLR input 100: TIMER1 channel3 input capture 101: TIMER1 OCPRE_CLR input 110: TIMER2 channel0 input capture 111: TIMER2 OCPRE_CLR input WNDEN Window mode enable This bit is used to disconnect the CMP1_IP input of CMP1 from P A3 and connect it to CMP0’s CMP0_IP input.
Page 187 GD32F1x0 User Manual 1: Non-inverting input above inverting input and the output is high 13:12 CMP0HST[1:0] CMP0 hysteresis These bits are used to control the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis CMP0PL Polarity of CMP0 output This bit is used to select the polarity of CMP0 output.
Page 188 GD32F1x0 User Manual This bit is used to closes a sw itch betw een CMP0 non-inverting input on P A0 and P A4 (DAC0) I/O. 0: Sw itch open 1: Sw itch closed CMP0EN CMP0 enable 0: CMP0 disabled 1: CMP0 enabled...
Page 189: Watchdog Timer (Wdgt)
GD32F1x0 User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 190: Figure 13-1. Free Watchdog Timer Block Diagram
GD32F1x0 User Manual Figure 13-1. Free watchdog timer block diagram Status: PUD Reset IRC40K Prescaler 12-Bit /4/8 /256 Downcounter Reload Reload Control register Status: RUD register The free watchdog timer is enabled by writing the value 0xCCCC in the control register (FWDGT_CTL), and the counter starts counting down.
Page 191: Table 13-1. Min / Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32F1x0 User Manual Table 13-1. Min / max FWDGT timeout period at 40 kHz (IRC40K) Min tim eout (m s) Max tim eout (m s) PSC[2:0] Prescaler divider RL[11:0]= RL[11:0]= bits 0x000 0xFFF 1 / 4 0.025 409.525 1 / 8 0.025 819.025 1 / 16...
Page 192: Register Definition
GD32F1x0 User Manual Register definition 13.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 193 GD32F1x0 User Manual bit in the FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to w ait until...
Page 194 GD32F1x0 User Manual Status register (FWDGT_STAT) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Watchdog counter w indow value update When a w rite operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 195 GD32F1x0 User Manual operation is performed w hile the counter is greater than the value stored in this register. The WUD bit in the FWDGT_STAT register must be reset in order to be able to change the reload value. These bits are w rite protected. Write 0x5555 in the FWDGT_CTL register before w riting these bits.
Page 196: Window Watchdog Timer (Wwdgt)
GD32F1x0 User Manual Window watchdog timer (WWDGT) 13.2. Overview 13.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions.After the window watchdog timer starts, the value of downcounter reduce progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared).
Page 197: Figure 13-2. Window Watchdog Timer Block Diagram
GD32F1x0 User Manual Figure 13-2. Window watchdog timer block diagram The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. Whenever window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F, it implies that the CNT[6] bit should be set.
Page 198: Figure 13-3. Window Watchdog Timer Timing Diagram
GD32F1x0 User Manual Figure 13-3. Window watchdog timer timing diagram Calculate the WWDGT timeout by using the formula below. ×4096 ×2 × ( CNT [ 5:0 ] +1 ) (ms) (13-1) WWDGT PCLK1 where: : WWDGT timeout WWDGT : APB1 clock period measured in ms PCLK1 Refer to the Table 13-2.
Page 199: Register Definition
GD32F1x0 User Manual Register definition 13.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 200 GD32F1x0 User Manual EWIE Early w akeup interrupt enable. If the bit is set, an interrupt occurs w hen the counter reaches 0x40. It can be cleared by a hardw are reset or softw are reset by setting the WWDGTRST bit of the RCU module. A w rite operation of 0 has no effect. PSC[1:0] Prescaler.
Page 201: Real-Time Clock(Rtc)
GD32F1x0 User Manual Real-time clock(RTC) Overview 14.1. The RTC provides a time which includes hour/minute/second/sub-second and a calendar including year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjustment for daylight saving time.
Page 202: Function Overview
GD32F1x0 User Manual Function overview 14.3. Block diagram 14.3.1. Figure 14-1. Block diagram of RTC ALARM 0 Alarm-0 Flag Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_spre (Default 1 Hz) IRC40K 7-bit 15-bit ck_apre Digital (Default 256 Hz) Synchronous Asynchronous HXTAL/2~31...
Page 203: Shadow Registers Introduction
GD32F1x0 User Manual In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. Asynchronous prescaler is mainly used for reducing power consumption.
Page 204: Rtc Initialization And Configuration
GD32F1x0 User Manual RTC initialization and configuration 14.3.5. RTC register write protection BKPWEN bit in the PMU_CTL register is cleared in default, so writing to RTC registers needs setting BKPWEN bit ahead of time. After power-on reset, most of RTC registers are write protected. Unlocking this protection is the first step before writing to them.
Page 205: Calendar Reading
GD32F1x0 User Manual next second comes. Alarm function operation process To avoid unexpected alarm assertion and metastable state, alarm function has an operation flow: Disable Alarm (by resetting ALRM0EN in RTC_CTL) Set the Alarm registers needed(RTC_ALRM0TD/RTC_ALRM0SS) Enable Alarm function (by setting ALRM0EN in the RTC_CTL) Calendar reading 14.3.6.
Page 206: Resetting The Rtc
GD32F1x0 User Manual Especially that software must clear RSYNF bit and wait it asserted before reading calendar register after wakeup from power saving mode. Reading calendar registers under BPSHAD=1 When BPSHAD=1, RSYNF is cleared and maintains as 0 by hardware so reading calendar registers does not care about RSYNF bit.
Page 207: Rtc Reference Clock Detection
GD32F1x0 User Manual an offset (in a fraction of a second) with the remote clock, RTC unit provides a function named shift function to remove this offset and thus make second precision higher. RTC_SS register indicates the fraction of a second in binary format and is down counting when RTC is running.
Page 208: Rtc Smooth Digital Calibration
GD32F1x0 User Manual When reference detection function is running while the external reference clock is removed (no reference clock edge found in 3 ck_apre window), the calendar updating still can be performed by LXTAL clock only. If the reference clock is recovered later, detection function will use 7 ck_apre window to identify the reference clock and use 3 ck_apre window to adjust the 1Hz clock (ck_spre) edge.
Page 209 GD32F1x0 User Manual FACTOR_A<3. When the FACTOR_A is less than 3, the FACTOR_S value should be set to a value less than the nominal value. Assuming that RTC clock frequency is nominal 32.768 KHz, the corresponding FACTOR_S should be set as following rule: FACTOR_A = 2: 2 less than nominal FACTOR_S (8189 with 32.768 KHz) FACTOR_A = 1: 4 less than nominal FACTOR_S (16379 with 32.768 KHz) FACTOR_A = 0: 8 less than nominal FACTOR_S (32759 with 32.768 KHz)
Page 210: Time-Stamp Function
GD32F1x0 User Manual Time-stamp function 14.3.11. Time-stamp function is performed on RTC_TS pin and is enabled by control bit TSEN. When a time-stamp event occurs on RTC_TS pin, the calendar value will be saved in time- stamp registers (RTC_DTS/RTC_TTS/RTC_SSTS) and the time-stamp flag (TSF) is set to 1 by hardware.
Page 211: Calibration Clock Output
GD32F1x0 User Manual Edge detection mode on tamper input detection When FLT bit is set to 0x0, the tamper detection is set to edge detection mode and TPxEG bit determines the rising edge or falling edge is the detecting edge. When tamper detection is under edge detection mode, the internal pull-up resistors on the tamper detection input pin are deactivated.
Page 212: Rtc Power Saving Mode Management
GD32F1x0 User Manual function will directly output the content of alarm flag in RTC_STAT. The OPOL bit in RTC_CTL can configure the polarity of the alarm output which means that the RTC_ALARM output is the opposite of the corresponding flag bit or not. RTC power saving mode management 14.3.15.
Page 213: Register Definition
GD32F1x0 User Manual Register definition 14.4. RTC base address: 0x4000 2800 Time register (RTC_TIME) 14.4.1. Address offset: 0x00 System reset: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state. This register has to be accessed by word(32-bit).
Page 214: Control Register (Rtc_Ctl)
GD32F1x0 User Manual This register is write protected and can only be written in initialization state. This register has to be accessed by word(32-bit). Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[2:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:20 YRT[3:0] Year tens in BCD code...
Page 215 GD32F1x0 User Manual 31:24 Reserved Must be kept at reset value COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output 0x2: Reserved 0x3: Reserved...
Page 216: Status Register (Rtc_Stat)
GD32F1x0 User Manual 1: Enable time-stamp function 10:9 Reserved Must be kept at reset value ALRM0EN Alarm-0 function enable 0: Disable alarm function 1: Enable alarm function Reserved Must be kept at reset value Clock System 0: 24-hour format 1: 12-hour format Note: Can only be w ritten in initialization state BPSHAD Shadow registers bypass control...
Page 217 GD32F1x0 User Manual 31:17 Reserved Must be kept at reset value SCPF Smooth calibration pending flag Set to 1 by hardw are w hen softw are w rites to RTC_HRFC w ithout entering initialization mode and set to 0 by hardw are w hen smooth calibration configuration is taken into account.
Page 218: Prescaler Register (Rtc_Psc)
GD32F1x0 User Manual 0:Shadow register are not yet synchronized 1:Shadow register are synchronized Year configuration mark Set by hardw are if the year field of calendar date register is not the default value 0. 0:Calendar has not been initialized 1:Calendar has been initialized SOPF Shift function operation pending flag 0:No shift operation is pending...
Page 219: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32F1x0 User Manual Alarm 0 time and date register (RTC_ALRM0TD) 14.4.6. Address offset: 0x1C System reset: not effect Backup domain reset: 0x0000 0000 This register is write protected and can only be written in initialization state. This register has to be accessed by word(32-bit). MSKD DOWS DAYT[1:0]...
Page 220: Write Protection Key Register (Rtc_Wpk)
GD32F1x0 User Manual 1:Mask second field SCT[2:0] Second tens in BCD code SCU[3:0] Second units in BCD code Write protection key register (RTC_WPK) 14.4.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved WPK[7:0] Bits...
Page 221: Shift Function Control Register (Rtc_Shiftctl)
GD32F1x0 User Manual Shift function control register (RTC_SHIFTCTL) 14.4.9. Address offset: 0x2C System reset: not effect Backup domain reset: 0x0000 0000 This register is writing protected and can only be wrote when SOPF=0. This register has to be accessed by word(32-bit). Reserved Reserved SFS[14:0]...
Page 222: Date Of Time Stamp Register (Rtc_Dts)
GD32F1x0 User Manual Reserved MNT[2:0] MNU[3:0] Reserved SCT[2:0] SCU[3:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value AM/PM mark 0:AM or 24-hour format 1:PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code Reserved Must be kept at reset value 14:12...
Page 223: Sub Second Of Time Stamp Register (Rtc_Ssts)
GD32F1x0 User Manual Reserved Must be kept at reset value DAYT[1:0] Day tens in BCD code DAYU[3:0] Day units in BCD code Sub second of time stamp register (RTC_SSTS) 14.4.12. Address offset: 0x38 Backup domain reset: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1.
Page 224: Tamper Register (Rtc_Tamp)
GD32F1x0 User Manual FREQI Increase RTC frequency by 488.5PPM 0: No effect 1: One RTCCLK pulse is inserted every 2 pulses. This bit should be used in conjunction w ith CMSK bit. If the input clock frequency is 32.768KHz, the number of RTCCLK pulses added during 32s calibration w indow i s (512 * FREQI) - CMSK CWND8 Frequency compensation w indow 8 second selected...
Page 225 GD32F1x0 User Manual Only valid w hen LXTAL is disabled and PC15MDE=1,PC15 output this bit data. PC14MDE PC14 Mode 0:No effect 1:Force PC14 to push-pull output if LXTAL is disable PC14VAL PC14 Value Only valid w hen LXTAL is disabled and PC14MDE=1,PC14 output this bit data. PC13MDE PC13 Mode 0:No effect...
Page 226: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32F1x0 User Manual 0x1: Sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) 0x2: Sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) 0x3: Sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) 0x4: Sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) 0x5: Sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) 0x6: Sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) 0x7: Sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) TPTS...
Page 227: Backup Registers (Rtc_Bkpx) (X=0
GD32F1x0 User Manual Backup domain reset: 0x0000 0000 System reset: no effect This register is write protected and can only be wrote when ALRM0EN=0 or INITM=1. This register has to be accessed by word(32-bit). Reserved MSKSSC[3:0] Reserved Reserved SSC[14:0] Bits Fields Descriptions 31:28...
Page 228 GD32F1x0 User Manual This register has to be accessed by word(32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be w rote or read by softw are. The content remains valid even in pow er saving mode because they can pow ered-on by V .
Page 229: Timer (Timerx)
GD32F1x0 User Manual Timer (TIMERx) Table 15-1. Timers (TIMERx) are devided into six sorts TIMER TIMER0 TIMER1/2 TIMER13 TIMER14 TIMER15/16 TIMER5 TYPE Advanced General-L0 General-L2 General-L3 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit(TIMER1) Counter 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit(TIMER2)
Page 230: Advanced Timer (Timerx,X=0)
GD32F1x0 User Manual 15.1. Advanced timer (TIMERx,x=0) Overview 15.1.1. The advanced timer module (TIMER0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The advanced timer has a 16-bit counter that can be used as an unsigned counter.
Page 231: Block Diagram
GD32F1x0 User Manual Block diagram 15.1.3. Figure 15-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 15-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2...
Page 232: Figure 15-2. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual [2:0] in the TIMERx_SMCFG register, details as follows. When the SMC [2:0] bits are set to 0x4, 0x5 or 0x6, the internal clock CK_TIMER is the counter prescaler driving clock source. Figure 15-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse...
Page 233: Figure 15-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual event. Figure 15-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 234: Figure 15-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Figure 15-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-5.
Page 235: Figure 15-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F1x0 User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated.
Page 236: Figure 15-7. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF)
Page 237 GD32F1x0 User Manual Figure 15-8. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register.
Page 238: Figure 15-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32F1x0 User Manual If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overflow.
Page 239: Figure 15-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32F1x0 User Manual Figure 15-11. Repetition counter timing chart of down counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 240: Figure 15-12. Channel Input Capture Principle
GD32F1x0 User Manual Figure 15-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 241: Figure 15-13. Channel Output Compare Principle (With Complementary Output, X=0, 1, 2)
GD32F1x0 User Manual and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: A DMA request or interrupt is generated by setting CHxG directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 242: Figure 15-15. Output-Compare Under Three Modes
GD32F1x0 User Manual If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled).
Page 243: Figure 15-16. Eapwm Timechart
GD32F1x0 User Manual Figure 15-15. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 244 GD32F1x0 User Manual Figure 15-16. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 15-17. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 245 GD32F1x0 User Manual The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 246: Table 15-2. Complementary Outputs Controlled By Parameters
GD32F1x0 User Manual Table 15-2. Complementary outputs controlled by parameters Com plem entary Param eters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off -state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 247: Figure 15-18. Channel Output Complementary Pwm With Dead-Time Insertion
GD32F1x0 User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 248: Figure 15-19. Output Behavior In Response To A Break(The Break High Active)
GD32F1x0 User Manual in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register.
Page 249: Figure 15-20. Example Of Counter Operation In Quadrature Decoder Interface Mode
GD32F1x0 User Manual external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-reload value. Therefore, users must configure the TIMERx_CAR register before the counter starts to count. Table 15-3. Counting direction versus quadrature decode signals CI0FE0 CI1FE1 Counting m ode...
Page 250: Figure 15-22. Hall Sensor I S Used To Bldc Motor
GD32F1x0 User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 15-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in(Advanced/GeneralL0 TIMER) should accept three Rotor Position signals from Motor.
Page 251: Figure 15-23. Hall Sensor Timing Between Two Timers
GD32F1x0 User Manual Figure 15-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_I N CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_O N CH1_O CH1_ON CH2_O CH2_O N Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode,...
Page 252: Figure 15-24. Restart Mode
GD32F1x0 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 110: CI1FE1 the trigger source, be used by configuring 111: ETIFP configure the ETP for ETFC and prescaler can polarity selection and be used by configuring inversion. ETPSC. Restart m ode The counter w ill be TRGS[2:0] =...
Page 253: Figure 15-26. Event Mode
GD32F1x0 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event m ode ETPSC = 1, ETI is The counter w ill TRGS[2:0] ETP = 0, the polarity of divided by 2. =3’b111 start to count w hen ETI does not change.
Page 254: Figure 15-27. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F1x0 User Manual Figure 15-27. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop CNT_REG O2CPRE Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt.
Page 255: Table 15-5. Input Trigger Of Timer0
GD32F1x0 User Manual Table 15-5. Input trigger of Timer0 shows the input trigger. Table 15-5. Input trigger of Timer0 Slave ITI0(TRGS = 000) ITI1(TRGS = 001) ITI2(TRGS = 010) ITI3(TRGS = 011) TIMER TIMER0 TIMER14 TIMER1 TIMER2 reserved Note: ‘-’ means no interconnection. Other interconnection examples: TIMER2 as prescaler for TIMER0 We configure TIMER2 as a prescaler for TIMER0.
Page 256: Figure 15-29. Triggering Timer0 With Enable Of Timer2
GD32F1x0 User Manual Figure 15-29. Triggering TIMER0 with Enable of TIMER2 TIMER_CK CNT_REG TRGIF CNT_REG Using an external trigger to start 2 timers synchronously We configure the start of TIMER0 is triggered by the enable of TIMER2, and TIMER2 is triggered by its CI0 input rises edge.
Page 257: Figure 15-30. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F1x0 User Manual Figure 15-30. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event.
Page 258: Timerx Registers(X=0)
GD32F1x0 User Manual TIMERx registers(x=0) 15.1.5. TIMER0 base address: 0x4001 2C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 259 GD32F1x0 User Manual After the counter is enabled, cannot be sw itched from 0x00 to non 0x00. Direction 0: Count up 1: Count dow n If the timer w ork in center-aligned mode or quadrature decoder mode, this bit is read only.
Page 260 GD32F1x0 User Manual Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit ISO2...
Page 261 GD32F1x0 User Manual CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 262 GD32F1x0 User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 263 GD32F1x0 User Manual 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 264 GD32F1x0 User Manual direction depends on CI1FE1 level. 011: Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1 edge, w hile the direction depends on each other. 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input.
Page 265 GD32F1x0 User Manual CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable...
Page 266 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved...
Page 267 GD32F1x0 User Manual 1: Channel commutation interrupt occurred Channel 3 ‘s capture/compare interrupt flag CH3IF Refer to CH0IF description Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardw are and cleared by softw are.
Page 268 GD32F1x0 User Manual This bit is set by softw are and cleared by hardw are automatically. When this bit is set, the TRGIF flag in TIMERx_INTF register is set, related interrupt or DMA transfer can occur if enabled. 0: No generate a trigger event 1: Generate a trigger event CMTG Channel commutation event generation...
Page 269 GD32F1x0 User Manual Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output com pare m ode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0]...
Page 270 GD32F1x0 User Manual 001: Set the channel output. O0CPRE signal is forced high w hen the counter is equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low w hen the counter is equals to the output compare register TIMERx_CH0CV.
Page 271 GD32F1x0 User Manual 10: Channel 0 is programmed as input mode, IS0 is connec ted to CI1FE0 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 272 GD32F1x0 User Manual is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection...
Page 273 GD32F1x0 User Manual 11: Channel 3 is programmed as input mode, IS3 is connected to ITS. Note: When CH3MS[1:0]=11, it is necessary to ensure that an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register. CH2COMCEN Channel 2 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal w ill be cleared.
Page 274 GD32F1x0 User Manual 11 and CH0MS bit-filed is 00. CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output w ill be accelerated if the channel is configured in PWM1 or PWM2 mode.
Page 275 GD32F1x0 User Manual 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset w hen CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 276 GD32F1x0 User Manual Refer to CH0EN description CH2NP Channel 2 complementary output polarity Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity...
Page 277 GD32F1x0 User Manual operation in slave mode. And CIxFE0 w ill not be inverted. [CH0NP==0, CH0P==1]: CIxFE0’s falling edge is the active signal for capture or trigger operation in slave mode. And CIxFE0 w ill be inverted. [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode.
Page 278 GD32F1x0 User Manual PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed w ill be loaded to the corresponding shadow register at every update event.
Page 279 GD32F1x0 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting dow n to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed w hen these shadow registers are enabled.
Page 280 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 281 GD32F1x0 User Manual CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 282 GD32F1x0 User Manual This bit can be modified only w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 00. BRKP Break polarity This bit specifies the polarity of the BRKIN input signal. 0: BRKIN input active low 1; BRKIN input active high BRKEN Break enable This bit can be set to enable the BRKIN and CCS clock failure event inputs.
Page 283 GD32F1x0 User Manual CHxCOMSEN bits in TIMERx_CHCTL0/1 registers (if the related channel is configured in output) are w riting protected. This bit-field can be w ritten only once after the reset. Once the TIMERx_CCHP register has been w ritten, this bit-field w ill be w riting protected. DTCFG[7:0] Dead time configure The relationship betw een DTVAL value and the duration of dead-time is as follow :...
Page 284 GD32F1x0 User Manual DMA transfer buffer register (TIMERx_DMATB) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) w ill be accessed.
Page 285: General Level0 Timer (Timerx, X=1, 2)
GD32F1x0 User Manual 15.2. General level0 timer (TIMERx, x=1, 2) Overview 15.2.1. The general level0 timer module (TIMER1, 2) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 286: Function Overview
GD32F1x0 User Manual Figure 15-31. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Trigger processor Input logic PSC_CLK Trigger Selector&Counter Polarity selection TIMER_CK Quadrate Decoder DMA REQ/ACK...
Page 287: Figure 15-32. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Figure 15-32. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111(external clock mode 0). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 288: Figure 15-33. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual Figure 15-33. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 289: Figure 15-34. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Figure 15-34. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-35.
Page 290: Figure 15-36. Timing Chart Of Down Counting Mode , Psc=0/2
GD32F1x0 User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow.
Page 291: Figure 15-37. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Figure 15-37. Timing chart of down counting mode, change TIMERx_CAR on the go. TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF)
Page 292 GD32F1x0 User Manual behavior for different clock frequencies when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-38. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear...
Page 293: Figure 15-39. Channel Input Capture Principle
GD32F1x0 User Manual Figure 15-39. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 294: Figure 15-40. Channel Output Compare Principle (X=0,1,2,3)
GD32F1x0 User Manual and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 295: Figure 15-41. Output-Compare Under Three Modes
GD32F1x0 User Manual  Set the shadow enable mode by CHxCOMSEN.  Set the output mode (set/clear/toggle) by CHxCOMCTL.  Select the active polarity by CHxP.  Enable the output by CHxEN. Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform.
Page 296: Figure 15-43. Timing Chart Of Capwm
GD32F1x0 User Manual The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV. Figure 15-43. Timing chart of CAPWM shows the CAPWM output and interrupts waveform. In up counting mode, if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR, the output will be always inactive in PWM mode 0 (CHxCOMCTL=3’b110).
Page 297: Table 15-6. Timerx(X=1,2) Interconnection
GD32F1x0 User Manual Channel output prepare signal As is shown in Figure 15-40. Channel output compare principle (x=0,1,2,3) when TIMERx is configured in compare match output mode,a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal. The OxCPRE signal type is defined by configuring the CHxCOMCTL bit.
Page 298 GD32F1x0 User Manual Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB; Of course, you have to enable a DMA request which will be asserted by some internal interrupt event. When the interrupt event was asserted, TIMERx will send a request to DMA, which is configured to M2P mode and PADDR is TIMERx_DMATB, then DMA will access the TIMERx_DMATB.
Page 299: Timerx Registers(X=1, 2)
GD32F1x0 User Manual TIMERx registers(x=1, 2) 15.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 300 GD32F1x0 User Manual can be set. After the counter is enabled, cannot be sw itched from 0x00 to non 0x00. Direction 0: Count up 1: Count dow n If the timer w ork in center-aligned mode or quadrature decoder mode, this bit is read only.
Page 301 GD32F1x0 User Manual Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 302 GD32F1x0 User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 303 GD32F1x0 User Manual After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level. The filtering capability configuration is as f ollow s: EXTFC[3:0] Tim es SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101...
Page 304 GD32F1x0 User Manual 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) w hen CEN bit is set high. 001: Quadrature decoder mode 0. The counter counts on CI0FE0 edge, w hile the direction depends on CI1FE1 level.
Page 305 GD32F1x0 User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 306 GD32F1x0 User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 307 GD32F1x0 User Manual mode, this flag is set w hen a compare event occurs. 0: No Channel 1 interrupt occurred 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardw are on an update event and cleared by softw are. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG)
Page 308 GD32F1x0 User Manual 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag w as already high. 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by softw are, and cleared by hardw are automatically.
Page 309 GD32F1x0 User Manual 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 310 GD32F1x0 User Manual pulse mode (w hen SPM=1) This bit cannot be modified w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output w ill be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 311 GD32F1x0 User Manual CH0CAPFLT [3:0] Tim es SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear.
Page 312 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable...
Page 313 GD32F1x0 User Manual 110: PWM mode 0. When counting up, O2CPRE is high w hen the counter is smaller than TIMERx_CH2CV, and low otherw ise. When counting dow n, O2CPRE is l o w w hen the counter is larger than TIMERx_CH2CV, and high otherw ise. 111: PWM mode 1.
Page 314 GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value 15:12 CH3CAPFLT[3:0] Channel 3 input capture filter control Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the...
Page 315 GD32F1x0 User Manual Same as output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved...
Page 316 GD32F1x0 User Manual Refer to CH0EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, together w ith CH0P, this bit is used to define the polarity of CI0.
Page 317 GD32F1x0 User Manual CNT[15:0] Bits Fields Descriptions 31:0 CNT[31:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Counter register (TIMERx_CNT) (x=2) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CNT[15:0] Bits...
Page 318 GD32F1x0 User Manual value of this bit-filed w ill be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) (x=1) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). CARL[31:16] CARL[15:0] Bits...
Page 319 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH0VAL[31:16] CH0VAL[15:0] Bits Fields Descriptions 31:0 CH0VAL[31:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 320 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH1VAL[31:16] CH1VAL[15:0] Bits Fields Descriptions 31:0 CH1VAL[31:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 321 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH2VAL[31:16] CH2VAL[15:0] Bits Fields Descriptions 31:0 CH2VAL[31:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 322 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH3VAL[31:16] CH3VAL[15:0] Bits Fields Descriptions 31:0 CH3VAL[31:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 323 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA w ill access(R/W) the register of TIMERx_DMA TB Reserved Must be kept at reset value.
Page 324: General Level2 Timer (Timerx, X=13)
GD32F1x0 User Manual 15.3. General level2 timer (TIMERx, x=13) Overview 15.3.1. The general level2 timer module (TIMER 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 325: Function Overview
GD32F1x0 User Manual configuration of the general level2 timer. Figure 15-44. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes...
Page 326: Figure 15-45. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Figure 15-45. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 327: Figure 15-47. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 328: Figure 15-48. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Figure 15-48. Timing chart of up counting mode , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE)
Page 329: Figure 15-49. Channel Input Capture Principle
GD32F1x0 User Manual Figure 15-49. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling Capture Clock Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal First, the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 330: Figure 15-50. Channel Output Compare Principle
GD32F1x0 User Manual and DMA request will be asserted or not based on the configuration of CHxIE in TIMERx_DMAINTEN. Direct generation: An interrupt is generated by setting CHxG directly. The channel input capture function can be also used for pulse period measurement from signals on the TIMERx_CHx pins.
Page 331: Figure 15-51. Output-Compare Under Three Modes
GD32F1x0 User Manual Step3: Interrupt/DMA-request enables configuration by CHxIE. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform. Step5: Start the counter by configuring CEN to 1. Figure 15-51. Output-compare under three modes show the three compare modes toggle/set/clear.
Page 332 GD32F1x0 User Manual Figure 15-52. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output prepare signal As is shown in Figure 15-50. Channel output compare principle when TIMERx is configured in compare match output mode,a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal.
Page 333: Timerx Registers(X=13)
GD32F1x0 User Manual TIMERx registers(x=13) 15.3.5. TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 334 GD32F1x0 User Manual registers are loaded w ith their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 335 GD32F1x0 User Manual Reserved Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardw are w hen a capture event occurs w hile CH0IF flag has already been set.
Page 336 GD32F1x0 User Manual 31:2 Reserved Must be kept at reset value. Channel 0’s capture or compare event generation CH0G This bit is set by softw are in order to generate a capture or compare event in channel 0, it is automatically cleared by hardw are. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 337 GD32F1x0 User Manual 011: Toggle on match. O0CPRE toggles w hen the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low . O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0.
Page 338 GD32F1x0 User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal.
Page 339 GD32F1x0 User Manual Reserved Reserved.. CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementar y output signal polarity.
Page 340 GD32F1x0 User Manual 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value.
Page 341 GD32F1x0 User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 342 GD32F1x0 User Manual Channel input remap register(TIMERx_IRMP) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CI0_RMP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER13_CH0) 01: Channel 0 input is connected to the RTCCLK 10: Channel 0 input is connected to HXTAL/32 clock...
Page 343: General Level3 Timer (Timerx, X=14)
GD32F1x0 User Manual 15.4. General level3 timer (TIMERx, x=14) Overview 15.4.1. The general level3 timer module (TIMER14) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 344: Function Overview
GD32F1x0 User Manual Figure 15-53. General level3 timer block diagram CH0_IN Input Logic Synchronizer&Filter Edge selector Prescaler CH1_IN &Edge Detector ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter Trigger processor TIMERx_TRGO PSC_CLK Trigger Selector&Counter TIMER_CK DMA REQ/ACK DMA controller TIMERx_CH0 TIMERx_CH1 TIMERx_TG TIMERx_UP req en/direct req set...
Page 345: Figure 15-54. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Figure 15-54. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 346: Figure 15-55. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual Figure 15-55. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 347: Figure 15-56. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Figure 15-56. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-57.
Page 348: Figure 15-58. Repetition Counter Timing Chart Of Up Counting Mode
GD32F1x0 User Manual Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register. Counter repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMERx_CREP register.
Page 349: Figure 15-59. Channel Input Capture Principle
GD32F1x0 User Manual Figure 15-59. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 350: Figure 15-60. Channel Output Compare Principle (With Complementary Output, X=0)
GD32F1x0 User Manual Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 351: Figure 15-62. Output-Compare Under Three Modes
GD32F1x0 User Manual output of CHx_ON is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(high) level. When CH0_O and CH0_ON are output at the same time, the specific outputs of CH0_O and CH0_ON are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the TIMERx_CCHP register.
Page 352: Figure 15-63. Pwm Mode Timechart
GD32F1x0 User Manual Figure 15-62. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 353 GD32F1x0 User Manual Figure 15-63. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 354: Table 15-7. Complementary Outputs Controlled By Parameters
GD32F1x0 User Manual Table 15-7. Complementary outputs controlled by parameters Com plem entary Param eters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off -state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 355: Figure 15-64. Complementary Output With Dead-Time Insertion
GD32F1x0 User Manual Dead time insertion The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 0. The detail about the delay time, refer to the register TIMERx_CCHP. The dead time delay insertion ensures that no two complementary signals drive the active state at the same time.
Page 356: Figure 15-65. Output Behavior In Response To A Break(The Break High Active)
GD32F1x0 User Manual setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 357: Figure 15-66. Restart Mode
GD32F1x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection mode) 001: ITI1 CHxP and CHxNP for the For the CIx, configure Filter 3'b101 (pause 010: ITI2 polarity selection and by CHxCAPFLT, no mode) 011: ITI3 inversion. prescaler can be used. 3'b110 (event 100: CI0F_ED mode)
Page 358: Figure 15-68. Event Mode
GD32F1x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection The counter w ill [CH0NP==0, CH0P==0] example. start to count CI0FE0 is the no inverted. w hen a rising selection. trigger input. Figure 15-68. Event mode TIMER_CK CI0FE0 CNT_REG TRGIF Single pulse mode...
Page 359: Table 15-9. Timerx(X=14) Interconnection
GD32F1x0 User Manual Figure 15-69. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 Timers interconnection Refer to Advanced timer (TIMERx, x=0). Table 15-9. TIMERx(x=14) interconnection ITI2(TRGS = ITI3(TRGS = Slave TIMER ITI0(TRGS = 000) ITI1(TRGS = 001) 010) 011) TIMER14 TIMER1 TIMER2 Reserved Reserved...
Page 360: Timerx Registers(X=14)
GD32F1x0 User Manual TIMERx registers(x=14) 15.4.5. TIMER14 base address: 0x4001 4000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 361 GD32F1x0 User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded w ith their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 362 GD32F1x0 User Manual The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only w hen PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value MMC[2:0] Master mode control These bits control the selection of TRGO signal, w hich is sent in master mode to slave timers for synchronization function.
Page 363 GD32F1x0 User Manual After these bits have been w ritten, they are updated based w hen commutation event coming. When a channel does not have a complementary output, this bit has no effect. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 364 GD32F1x0 User Manual 010: Reserved 011: Reserved 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode. The trigger input enables the counter clock w hen it is high and disables the counter clock w hen it is low .
Page 365 GD32F1x0 User Manual 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE...
Page 366 GD32F1x0 User Manual When channel 0 is configured in input mode, this flag is set by hardw are w hen a capture event occurs w hile CH0IF flag has already been set. This flag is cleared by softw are. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value.
Page 367 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved Reserved BRKG TRGG CMTG Reserved CH1G CH0G Bits Fields Descriptions 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by softw are and cleared by hardw are automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 368 GD32F1x0 User Manual 1: Generate a channel 1 capture or compare event Update event generation This bit can be set by softw are, and cleared by hardw are automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (dow n counting) it takes the auto-reload value.
Page 369 GD32F1x0 User Manual through TRGS bits in TIMERx_SMCFG register. Reserved Must be kept at reset value. CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 370 GD32F1x0 User Manual 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the w ork mode of the channel and the input signal selection. This bit-field is w ritable only w hen the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 371 GD32F1x0 User Manual 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 372 GD32F1x0 User Manual output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together w ith CH0P, this bit is used to define the polarity of CI0.
Page 373 GD32F1x0 User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 374 GD32F1x0 User Manual CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 375 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 376 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event.. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input...
Page 377 GD32F1x0 User Manual Idle mode “off -state” enable When POEN bit is reset (Idle mode), this bit can be set to enable the “off -state” for the channels w hich has been configured in output mode. 0: “off-state” disabled. If the CHxEN/CHx NEN bits are both reset, the channels are output disabled.
Page 378 GD32F1x0 User Manual Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA w ill access(R/W) the register of TIMERx_DMA TB Reserved Must be kept at reset value.
Page 379: General Level4 Timer (Timerx, X=15,16)
GD32F1x0 User Manual 15.5. General level4 timer (TIMERx, x=15,16) Overview 15.5.1. The general level4 timer module (TIMER15,TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level4 timer has a 16-bit counter that can be used as an unsigned counter.
Page 380: Function Overview
GD32F1x0 User Manual Figure 15-70. General level4 timer block diagram Input Logic Synchronizer&Filter CH0_IN Edge selector Prescaler &Edge Detector TIMERx_CHxCV CK_TIMER Counter PSC_CLK Counter Control TIMER_CK DMA REQ/ACK TIMERx_CH0 TIMERx_UP DMA controller req en/direct req set Register /Interrupt APB BUS Output Logic Interrupt CH0_O...
Page 381: Figure 15-71. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Figure 15-71. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 382 GD32F1x0 User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again and an overflow event will be generated.
Page 383: Figure 15-74. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Figure 15-74. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 384: Figure 15-75. Repetition Counter Timing Chart Of Up Counting Mode
GD32F1x0 User Manual Figure 15-75. Repetition counter timing chart of up counting mode TIMER_CK PSC_CLK 97 98 99 0 98 99 0 98 99 CNT_REG 98 99 0 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2...
Page 385: Figure 15-76. Channel Input Capture Principle
GD32F1x0 User Manual Figure 15-76. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 386: Figure 15-77. Output-Compare Under Three Modes
GD32F1x0 User Manual Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly.  Channel output compare function The channel input capture function, the TIMERx can generate timed pulses with programmable position, polarity, duration and frequency. When the counter matches the value in the CHxVAL register of an output compare channel, the channel (n) output can be set, cleared, or toggled based on CHxCOMCTL.
Page 387: Figure 15-78. Pwm Mode Timechart
GD32F1x0 User Manual Figure 15-77. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 388 GD32F1x0 User Manual Figure 15-78. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 389: Table 15-10. Complementary Outputs Controlled By Parameters
GD32F1x0 User Manual Table 15-10. Complementary outputs controlled by parameters Com plem entary Param eters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off -state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 390: Figure 15-79. Channel Output Complementary Pwm With Dead-Time Insertion
GD32F1x0 User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 1.
Page 391: Figure 15-80. Output Behavior In Response To A Break(The Break High Active)
GD32F1x0 User Manual HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, t he output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 392: Figure 15-81. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F1x0 User Manual the counter will be stopped and its value held. In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value.
Page 393 GD32F1x0 User Manual Timer debug mode When the Cortex -M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register ® set to 1, the TIMERx counter stops.
Page 394: Timerx Registers(X=15,16)
GD32F1x0 User Manual TIMERx registers(x=15,16) 15.5.5. TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields...
Page 395 GD32F1x0 User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded w ith their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 396 GD32F1x0 User Manual can be modified only w hen PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value DMAS DMA request source selection 0: DMA request of channel x is sent w hen capture/compare event occurs. 1: DMA request of channel x is sent w hen update event occurs.
Page 397 GD32F1x0 User Manual UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH0IE Channel 0 capture/compare interrupt enable 0: disabled...
Page 398 GD32F1x0 User Manual 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag When the break input is inactive, the bit is set by hardw are. When the break input is inactive, the bit can be cleared by softw are. 0: No active level break has been detected.
Page 399 GD32F1x0 User Manual 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by softw are and cleared by hardw are automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 400 GD32F1x0 User Manual CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output com pare m ode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
Page 401 GD32F1x0 User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output w ill be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 402 GD32F1x0 User Manual 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 403 GD32F1x0 User Manual complementary output in channel0. 0: Channel 0 complementary output disabled 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 404 GD32F1x0 User Manual 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved PSC[15:0] Bits...
Page 405 GD32F1x0 User Manual Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate.
Page 406 GD32F1x0 User Manual Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by:...
Page 407 GD32F1x0 User Manual is 00. Run mode “off -state” enable When POEN bit is set (Run mode), this bit can be set to enable the “off -state” for the channels w hich has been configured in output mode. 0: “off-state” disabled. If the CHxEN or CHxNEN bit is reset, the corresponding channel is output disabled.
Page 408 GD32F1x0 User Manual TIMERx_CTL0. 2. This bit can be modified only w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 00. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved DMATC[4:0]...
Page 409 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) w ill be accessed. The transfer Timer is calculated by hardw are, and ranges from 0 to DMATC.
Page 410: Basic Timer (Timerx, X=5)
GD32F1x0 User Manual 15.6. Basic timer (TIMERx, x=5) The basic timer is only available on GD32F150 series. Overview 15.6.1. The basic timer module (TIMER5) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 411: Figure 15-83. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 15-83. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG)
Page 412: Figure 15-84. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual Figure 15-84. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 413: Figure 15-73. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Figure 15-85. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-86.
Page 414 GD32F1x0 User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. Once the timer is set to operate in the single pulse mode, it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 415: Timerx Registers(X=5)
GD32F1x0 User Manual TIMERx registers(x=5) 15.6.5. TIMER5 base address: 0x4000 1000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8 Reserved Must be kept at reset value ARSE Auto-reload shadow enable...
Page 416 GD32F1x0 User Manual The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized. Counter enable 0: Counter disable 1: Counter enable...
Page 417 GD32F1x0 User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 418 GD32F1x0 User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by softw are, and cleared by hardw are automatically.
Page 419 GD32F1x0 User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 420: Infrared Ray Port (Ifrp)
GD32F1x0 User Manual Infrared ray port (IFRP) 16.1. Overview Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control. There is no register in this module, which is controlled by TIMER15 and TIMER16. You can improve the module's output to high current capacity by set the GPIO pin to Fast Mode.
Page 421: Figure 16-2. Ifrp Output Timechart 2
GD32F1x0 User Manual Note: IFRP_OUT has one APB clock delay from TIMER16_CH0. Figure 16-2. IFRP output timechart 2 Note: Carrier (TIMER15_CH0)’s duty cycle can be changed, and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high. Figure 16-3. IFRP output timechart 3 TIMER16_CH0 TIMER15_CH0 IFRP_OUT...
Page 422 GD32F1x0 User Manual Universal synchronous asynchronous receiver transmitter (USART) Overview 17.1. The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 423 GD32F1x0 User Manual – Checks parity of received data byte  LIN break generation and detection IrDA support   Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface – Character mode (T=0) – Block mode (T=1) –...
Page 424: Figure 17-1. Usart Module Block Diagram
GD32F1x0 User Manual Table 17-1. USART important pins description Type Description Input Receive Data Output I/O (single- Transmit Data. high level When enabled but w ire/smartcard mode) nothing to be transmitted Output Serial clock for synchronous communication nCTS Input Clear to send in Hardw are flow control mode nRTS Output Request to send in Hardw are flow control mode...
Page 425: Figure 17-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32F1x0 User Manual Figure 17-2. USART character frame (8 bits data and 1 stop bit) In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 17-2. Stop bits configuration STB[1:0] stop bit length (bit) usage description...
Page 426 GD32F1x0 User Manual For example, when oversampled by 16: Get USARTDIV by caculating the value of USART_BUAD: If USART_BUAD=0x21D, then INTDIV=33 (0x21), FRADIV=13 (0xD). USARTDIV=33+13/16=33.81. Get the value of USART_BUAD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, the nearest integer is 6, so FRADIV=6 (0x6).
Page 427: Figure 17-3. Usart Transmit Procedure
GD32F1x0 User Manual Figure 17-3. USART transmit procedure Write data0 to Write data1 to Write data2 to USART_TDATA by USART_TDATA by USART_TDATA by DMA or software DMA or software DMA or software set by set by set by hardware hardware hardware data1 data0...
Page 428: Figure 17-4. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32F1x0 User Manual (NERR) status will be generated for the frame. An interrupt is generated, If the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set. If the OSB bit in USART_CTL2 register is set, the receiver gets only one sample to evaluate a bit value. In this situation, no noisy error will be detected.
Page 429: Figure 17-5. Configuration Step When Using Dma For Usart Transmission
GD32F1x0 User Manual Figure 17-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 430: Figure 17-6. Configuration Step When Using Dma For Usart Reception
GD32F1x0 User Manual Figure 17-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 431: Figure 17-8. Hardware Flow Control
GD32F1x0 User Manual RTS flow control USART receiver can receive data only when the nRTS signal is low, and the signal does not go high until the data frame reception is finished. The next reception occurs when the nRTS signal goes low again. The signal keeps high when the receive register is full. CTS flow control If the TBE bit in USART_STAT is ‘0’...
Page 432: Figure 17-9. Break Frame Occurs During Idle State
GD32F1x0 User Manual RX pin, the hardware clears the RWU bit and exits the mute mode. When wake up at an idle frame, the IDLEF bit in USART_STAT is not set. When the WM bit of in USART_CTL0 register is set, the MSB bit of a frame is detected as the address flag.
Page 433: Figure 17-10. Break Frame Occurs During A Frame
GD32F1x0 User Manual Figure 17-10. Break frame occurs during a frame Synchronous mode 17.3.9. The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1. The LMEN bit in USART_CTL1 and SCEN, HDEN, IREN bits in USART_CTL2 should be reset in synchronous mode.
Page 434: Figure 17-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32F1x0 User Manual Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 17.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be reset in IrDA mode.
Page 435: Figure 17-14. Irda Data Modulation
GD32F1x0 User Manual greater than 1 but smaller than 2 times PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block. Figure 17-14.
Page 436: Figure 17-15. Iso7816-3 Frame Format
GD32F1x0 User Manual Figure 17-15. ISO7816-3 frame format ISO 7816-3 frame without parity error 0.5 bit 1 bit ISO 7816-3 frame with parity error T=0 mode Comparing to the time in normal operation, the transmission time from transmit shift register to the TX pin is delayed half baud clock, and the TC flag assertion time delayed a certain value wrote in the guard time register.
Page 437 GD32F1x0 User Manual characters, the USART_RT register must be programmed to the CWT (character wait time) - 11 value, which is expressed in baudtime units, after the reception of the first character (RBNE interrupt). The USART signals to the software through the RT flag and interrupt (when RTIE bit is set), if the smartcard doesn’t send a new character in less than the CWT period after the end of the previous character.
Page 438: Table 17-3. Usart Interrupt Requests
GD32F1x0 User Manual In the ModBus/ASCII mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function by programming the LF ASCII code in the ADDR field and activating the address match interrupt (AMIE=1).
Page 439: Figure 17-16. Usart Interrupt Mapping Diagram
GD32F1x0 User Manual Interrupt event Event flag Enable Control bit Character match AMIE Receiver timeout error RTIE End of block EBIE Wakeup from deep-sleep mode WUIE All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time.
Page 440 GD32F1x0 User Manual 17.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 Control register 0 (USART_CTL0) 17.4.1. Address offset: 0x00 Reset value: 0x0000_0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE DEA[4:0] DED[4:0] OVSMOD AMIE...
Page 441 GD32F1x0 User Manual 1: Oversampling by 8. This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). AMIE ADDR match interrupt enable. 0: ADDR match interrupt is disabled. 1: ADDR match interrupt is enabled.
Page 442 GD32F1x0 User Manual IDLEIE IDLE line detected interrupt enable. 0: IDLE line detected interrupt disabled. 1: An interrupt w ill occur w henever the IDLEF bit is set in USART_STAT. Transmitter enable. 0: Transmitter is disabled. 1: Transmitter is enabled. Receiver enable 0: Receiver is disabled.
Page 443 GD32F1x0 User Manual This bit field cannot be w ritten w hen both reception (REN=1) and USART (UEN=1) are enabled. RTEN Receiver timeout enable 0: Receiver timeout function disabled. 1: Receiver timeout function enabled. This bit is reserved in USART1. 22:20 Reserved Must be kept at reset value.
Page 444 GD32F1x0 User Manual 0: CK pin disabled 1: CK pin enabled This bit field cannot be w ritten w hen the USART is enabled (UEN=1). This bit is reserved in USART1. Clock polarity 0: Steady low value on CK pin outside transmission w indow in synchronous mode. 1: Steady high value on CK pin outside transmission w indow in synchronous mode .
Page 445 GD32F1x0 User Manual Control register 2 (USART_CTL2) 17.4.3. Address offset: 0x08 Reset value: 0x0000_0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields...
Page 446 GD32F1x0 User Manual Driver enable polarity mode 0: DE signal is active high 1: DE signal is active low This bit field cannot be w ritten w hen the USART is enabled (UEN=1). Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, w hich is output on the RTS pin.
Page 447 GD32F1x0 User Manual 1: RTS hardw are flow control enabled, data can be requested only w hen there is space in the receive buffer. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). DENT DMA enable for transmission 0: DMA mode is disabled for transmission.
Page 448 GD32F1x0 User Manual Baud rate generator register (USART_BAUD) 17.4.4. Address offset: 0x0C Reset value: 0x0000_0000 This register has to be accessed by word (32-bit). This register cannot be written when the USART is enabled (UEN=1). Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16...
Page 449 GD32F1x0 User Manual In IrDA Low -pow er mode, the division factor is the prescaler value. 00000000: Reserved - do not program this value. 00000001: divides the source clock by 1. 00000010: divides the source clock by 2. In IrDA normal mode, 00000001: can be set this value only.
Page 450 GD32F1x0 User Manual to 1, the block length counter is reset. 23:0 RT[23:0] Receiver timeout threshold These bits are used to specify receiver timeout value in terms of number of baud clocks. In standard mode, the RTF flag is set if no new start bit is detected for more than the RT value after the last received character.
Page 451 GD32F1x0 User Manual Status register (USART_STAT) 17.4.8. Address offset: 0x1C Reset value: 0x0000_00C0 This register has to be accessed by word (32-bit). Reserved Reserved CTSF LBDF RBNE IDLEF ORERR NERR FERR PERR Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknow ledge flag.
Page 452 GD32F1x0 User Manual w hen w akeup on IDLEIE mode is selected. Send break flag 0: No break character is transmitted. 1: Break character w ill be transmitted. This bit indicates that a send break character w as requested. Set by softw are, by w riting 1 to the SBKCMD bit in the USART_CMD register. Cleared by hardw are during the stop bit of break transmission.
Page 453 GD32F1x0 User Manual 1: A change occurred on the nCTS status line. An interrupt w ill occur if the CTSIE bit is set in USART_CTL2. Set by hardw are w hen the nCTS input toggles. Cleared by w riting 1 to CTSC bit in USART_INTC register. LBDF LIN break detected flag .
Page 454 GD32F1x0 User Manual 0: No overrun error is detected. 1: Overrun error is detected. An interrupt w ill occur if the RBNEIE bit is set in USART_CTL0. In multibuffer communication, an interrupt w ill occur if the ERRIE bit is set in USART_CTL2. Set by hardw are w hen the w ord in the receive shift register is ready to be transfer red into the USART_RDATA register w hile the RBNE bit is set.
Page 455 GD32F1x0 User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. Wakeup from deep-sleep mode clear. Writing 1 to this bit clears the WUF bit in the USART_STAT register. This bit is reserved in USART1. 19:18 Reserved Must be kept at reset value ADDR match clear Writing 1 to this bit clears the AMF bit in the USART_STAT register.
Page 456 GD32F1x0 User Manual Receive data register (USART_RDATA) 17.4.10. Offset: 0x24 Reset value: Undefined This register has to be accessed by word (32-bit). Reserved Reserved RDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. RDATA[8:0] Receive data value The received data character is contained in these bits.
Page 457: Figure 18-1. I2C Module Block Diagram
GD32F1x0 User Manual Inter-integrated circuit interface (I2C) 18.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard-mode and fast-mode as well as CRC calculation and checking, SMBus (system management bus) and PMBus (power management bus).
Page 458: Table 18-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32F1x0 User Manual Figure 18-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 18-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 459: Figure 18-2. Data Validation
GD32F1x0 User Manual devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V Data validation 18.3.2. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW (see Figure 18-2.
Page 460: Figure 18-4. Clock Synchronization
GD32F1x0 User Manual held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time. Figure 18-4. Clock synchronization Arbitration 18.3.5. Arbitration, like synchronization, is part of the protocol where more than one master is used in the system.
Page 461: Figure 18-6. I2C Communication Flow With 7-Bit Address
GD32F1x0 User Manual if General Call is enabled by software, the I2C slave always responds to a General Call Address (0x00). The I2C block supports both 7-bit and 10-bit address modes. An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation.
Page 462 GD32F1x0 User Manual mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus.
Page 463: Figure 18-9. Programming Model For Slave Transmitting (10-Bit Address Mode)
GD32F1x0 User Manual Figure 18-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 464: Figure 18-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32F1x0 User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 18-10.
Page 465 GD32F1x0 User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 466 GD32F1x0 User Manual Figure 18-11. Programming model for master transmitting (10-bit address mode) I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND...
Page 467 GD32F1x0 User Manual reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1. If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out.
Page 468: Figure 18-12. Programming Model For Master Receiving Using Solution A
GD32F1x0 User Manual Figure 18-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 469: Figure 18-13. Programming Model For Master Receiving Mode Using Solution B
GD32F1x0 User Manual If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 470 GD32F1x0 User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 471 GD32F1x0 User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 472 GD32F1x0 User Manual related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications.
Page 473: Table 18-2. Event Status Flags
GD32F1x0 User Manual a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data. SMBus programming flow The programming flow for SMBus is similar to normal I2C. In order to use SMBus mode, the application should configure several SMBus specific registers, respond to some SMBus specific flags and implement the upper protocols described in SMBus specification.
Page 474 GD32F1x0 User Manual 18.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved SALT...
Page 475 GD32F1x0 User Manual 1: ACKEN bit specifies w hether to send ACK or NACK for the next byte that is to be received, PECTRA NS bit indicates the next byte that is to be received is a PEC byte. ACKEN Whether or not to send an ACK This bit is set and cleared by softw are and cleared by hardw are w hen I2CEN=0.
Page 476 GD32F1x0 User Manual 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[6:0] Bits...
Page 477 GD32F1x0 User Manual I2CCLK[6:0] should be the frequency of input APB1 clock in MHz w hich is at least 0000000 - 0000001: Not allow ed 0000010 - 1001000: 2 MHz~72MHz 1001001 - 1111111: Not allow ed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 478 GD32F1x0 User Manual Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) 18.4.5.
Page 479 GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardw are and cleared by w riting 0. 0: SMBA pin not pulled dow n (device mode) or no Alert detected (host mode) 1: SMBA pin pulled dow n and Alert address received (device mode) or Alert detected (host mode) SMBTO...
Page 480 GD32F1x0 User Manual cleared by w riting a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, w riting I2C_DATA w on’t clear TBE (refer to Programming Model for detail). 0: I2C_DATA is not empty 1: I2C_DATA is empty, softw are can w rite RBNE I2C_DATA is not empty during receiving This bit is set by hardw are after it moves a byte from shift register to I2C_DATA and...
Page 481 GD32F1x0 User Manual mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardw are and cleared by reading I2C_STAT0 and w riting I2C_DATA. 0: No START signal sent 1: START signal sent Transfer status register 1 (I2C_STAT1) 18.4.7.
Page 482 GD32F1x0 User Manual Reserved Must be kept at reset value. Transmitter or receiver This bit indicates w hether the I2C is a transmitter or a receiver. It is cleared by hardw are after a STOP or a START signal or I2CEN=0 or LOSTARB=1. 0: Receiver 1: Transmitter I2CBSY...
Page 483 GD32F1x0 User Manual In fast speed mode if DTCY=0: =CLKC* T =2*CLKC* T high PCLK1 PCLK1 In fast speed mode if DTCY=1: =9*CLKC*T =16*CLKC* T high PCLK1 PCLK1 Note: If DTCY is 0, w hen PCLK1 is an integral multiple of 3, the baud rate w ill be more accurate.
Page 484: Figure 19-1. Block Diagram Of Spi
GD32F1x0 User Manual 19.2. Characteristics SPI characteristics 19.2.1.  Master or slave operation with full-duplex or half-duplex or simplex mode.  Separate transmission and reception buffer, 16 bits wide.  Data frame size can be 8 or 16 bits.  Bit order can be LSB or MSB.
Page 485: Table 19-1. Spi Signal Description
GD32F1x0 User Manual SPI signal description 19.3.2. Table 19-1. SPI signal description Pin nam e Direction Description Master: SPI clock output Slave: SPI clock input Master: data reception line Slave: data transmission line MISO Master w ith bidirectional mode: not used Slave w ith bidirectional mode: data transmission and reception line.
Page 486: Figure 19-2. Spi Timing Diagram In Normal Mode
GD32F1x0 User Manual Figure 19-2. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[0] D[2] D[4] D[5] D[1] D[6] D[7] LF=1 FF16=0 MISO D[2] D[6] D[1] D[5] D[7] D[0] D[3]...
Page 487: Table 19-3. Nss Function In Master Mode
GD32F1x0 User Manual software NSS mode) goes low, the SPI automatically enters slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). NSS goes low after SPI is enabled. The application may also use a general purpose IO as NSS pin to realize more flexible NSS.
Page 488: Figure 19-3. A Typical Full-Duplex Connection
GD32F1x0 User Manual Mode Description Register configuration Data pin usage MSTMOD = 1 Master reception w ith RO = 1 MOSI: not used unidirectional connection BDEN = 0 MISO: reception BDOEN: Don’t care MSTMOD = 1 Master transmission w ith RO = 0 MOSI: transmission bidirectional connection...
Page 489: Figure 19-4. A Typical Simplex Connection (Master: Receive, Slave: Transmit)
GD32F1x0 User Manual Figure 19-4. A typical simplex connection (Master: receive, Slave: transmit) Figure 19-5. A typical simplex connection (Master: transmit only, Slave: receive) Figure 19-6. A typical bidirectional connection SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate, otherwise, ignore this step.
Page 490 GD32F1x0 User Manual FF16=1, otherwise is 8 bits. Data order is configured by LF bit in SPI_CTL0 register, and SPI will first send the LSB if LF=1, or the MSB if LF=0. NSS function section. Configure MSTMOD, RO, BDEN and BDOEN depending on the operation modes described in Table 19-4.
Page 491 GD32F1x0 User Manual duplex mode. In MRU or MRB mode, after SPI is enabled, the SPI continuously generates SCK until the SPI is disabled. So the application should ignore the TBE flag and read out reception buffer in time after the RBNE flag is set, otherwise a data overrun fault will occur. The slave reception mode (SRU or SRB) is similar to the reception sequence of full-duplex mode except that the TBE bit need to be ignored.
Page 492 GD32F1x0 User Manual CRC function 19.3.7. There are two CRC calculators in SPI: one for transmission and the other for reception. The CRC calculation uses the polynomial defined in SPI_CRCPOLY register. Application can enable the CRC function by setting CRCEN bit in SPI_CTL0 register. The CRC calculators calculate CRC for each bit transmitted and received on lines continuously, and the calculated CRC values can be read from SPI_TCRC and SPI_RCRC registers.
Page 493: Table 19-5. Spi Interrupt Requests
GD32F1x0 User Manual enabled, the CONFERR is set when the NSS pin is pulled low. In NSS software mode, the CONFERR is set when the SWNSS bit is 0. When the CONFERR is set, the SPIEN bit and the MSTMOD bit are cleared by hardware, the SPI is disabled and the device is forced into slave mode.
Page 494: Figure 19-7. Block Diagram Of I2S
GD32F1x0 User Manual 19.4. I2S function overview I2S block diagram 19.4.1. Figure 19-7. Block diagram of I2S SYSCLK I2S_MCK SPI_SCK / I2S_CK SPI_NSS / I2S_WS 16 bits TX Buffer SPI_MOSI / I2S_SD 16 bits RX Buffer There are five sub modules to support I2S function, including control registers, clock generator, master control logic, slave control logic and shift register.
Page 495: Figure 19-8. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F1x0 User Manual signal indicates the channel side. For PCM standard, the I2S_WS signal indicates frame synchronization information. The data length and the channel length are configured by the DTLEN bit and CHLEN bit in the SPI_I2SCTL register. Since the channel length must be greater than or equal to the data length, four packet types are available.
Page 496: Figure 19-11. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F1x0 User Manual Figure 19-11. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD When the packet type is 32-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame.
Page 497: Figure 19-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32F1x0 User Manual Figure 19-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame.
Page 498: Figure 19-20. Msb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F1x0 User Manual Figure 19-20. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 19-21. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 19-22. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 19-23.
Page 499: Figure 19-25. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32F1x0 User Manual Figure 19-25. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 8-bit 0 24-bit data I2S_SD When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame.
Page 500: Figure 19-29. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32F1x0 User Manual (DTLEN=00, CHLEN=0, CKPL=0) frame 1 frame 2 I2S_CK I2S_WS 16-bit data I2S_SD Figure 19-29. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 19-30. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2 32-bit data...
Page 501 GD32F1x0 User Manual Figure 19-34. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD Figure 19-35. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) The timing diagrams for each configuration of the long frame synchronization mode are shown below.
Page 502: Figure 19-36. Pcm Standard Long Frame Synchronization Mode Timing Diagram
GD32F1x0 User Manual (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 32 bits I2S_SD Figure 19-40. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-41. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2...
Page 503: Figure 19-44. Block Diagram Of I2S Clock Generator
GD32F1x0 User Manual I2S clock 19.4.4. Figure 19-44. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 19-44. Block diagram of I2S clock generator.The I2S interface clocks are configured by the DIV bits, the OF bit, the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register.
Page 504: Figure 19-45. I2S Initialization Sequence
GD32F1x0 User Manual are four available operation modes, including master transmission mode, master reception mode, slave transmission mode, and slave reception mode. The direction of I2S interface signals for each operation mode is shown in the Table 19-8. Direction of I2S interface signals for each operation mode.
Page 505 GD32F1x0 User Manual Figure 19-45. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 506 GD32F1x0 User Manual TBEIE bit in the SPI_CTL1 register is set. At the beginning, the transmission buffer is empty (TBE is high) and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmission buffer to the shift register (TBE goes high) immediately.
Page 507: Figure 19-46. I2S Master Reception Disabling Sequence
GD32F1x0 User Manual Figure 19-46. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTD ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 508 GD32F1x0 User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 509: Table 19-9. I2S Interrupt
GD32F1x0 User Manual Error conditions There are three error flags:  Transmission underrun error flag (TXURERR) This situation occurs when the transmission buffer is empty when the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the reception buffer is full and a newly incoming data has been completely received.
Page 510 GD32F1x0 User Manual 19.5. Register definition SPI0/I2S0 base address: 0x4001 3000 SPI1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 19.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 511 GD32F1x0 User Manual SPI_DATA register. In receive only mode, set this bit after the second last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN...
Page 512 GD32F1x0 User Manual CKPH Clock phase selection 0: Capture the first data at the first clock transition. 1: Capture the first data at the second clock transition. Control register 1 (SPI_CTL1) 19.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved Reserved TBEIE...
Page 513 GD32F1x0 User Manual DMA request on corresponding DMA channel. Status register (SPI_STAT) 19.5.3. Address offset: 0x08 Reset value: 0x0000 0002 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved FERR Reserved TRANS RXORERR CONFERR CRCERR TXURERR I2SCH...
Page 514 GD32F1x0 User Manual This bit is set by hardw are and is able to be cleared by w riting 0. This bit is not used in I2S mode. TXURERR Transmission underrun error bit 0: No transmission underrun error occurs. 1: Transmission underrun error occurs. This bit is set by hardw are and cleared by a read operation on the SPI_STA T register.
Page 515 GD32F1x0 User Manual If the Data frame format is set to 16-bit data, the SPI_DATA [15:0] is used for transmission and reception, transmission buffer and reception buffer are 16-bit. CRC polynomial register (SPI_CRCPOLY) 19.5.5. Address offset: 0x10 Reset value: 0x0000 0007 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 516 GD32F1x0 User Manual The hardw are computes the CRC value after each received bit, w hen the TRA NS is set, a read to this register could return an intermediate value. This register is reset w hen the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is set.
Page 517 GD32F1x0 User Manual PCMSMO Reserved I2SSEL I2SEN I2SOPMOD[1:0] Reserved I2SSTD[1:0] CKPL DTLEN[1:0] CHLEN Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. I2SSEL I2S mode selection 0: SPI mode 1: I2S mode This bit should be configured w hen SPI mode or I2S mode is disabled. I2SEN I2S enable 0: Disable I2S...
Page 518 GD32F1x0 User Manual DTLEN[1:0] Data length 00: 16 bits 01: 24 bits 10: 32 bits 11: Reserved These bits should be configured w hen I2S mode is disabled. These bits are not used in SPI mode. CHLEN Channel length 0: 16 bits 1: 32 bits The channel length must be equal to or greater than the data length.
Page 519 GD32F1x0 User Manual These bits should be configured w hen I2S mode is disabled. These bits are not used in SPI mode. HDMI-CEC controller(HDMI-CEC) 20.1. Overview The products of the GD32F150xx series integrate the HDMI-CEC controller inside to support the CEC protocol. Consumer Electronics Control (CEC) belongs to a part of HDMI (High- Definition Multimedia Interface) standard.
Page 520: Figure 20-1. Hdmi-Cec Controller Block Diagram
GD32F1x0 User Manual 20.3. Function overview CEC bus pin 20.3.1. The CEC device communicates with others by only one bidirectional line. When the CEC device is in the output state, in order to allow a wired-and connection, the CEC pin need to be configured in alternate function open drain mode, and an external 27kΩ...
Page 521: Figure 20-3. Start Bit Timing
GD32F1x0 User Manual 2) Data frame: The frames in the message followed the header frame. Data frame is optional. All frames are ten bits long and have the same basic structure as shown below: Table 20-1. Frame Structure Fram e Structure Information bits ENDOM The information bits are data, opcodes or addresses, dependent on context.
Page 522: Figure 20-5. The Process Of Cec Line Arbitration
GD32F1x0 User Manual Tim e (m s) The bit start event. transition. 0.8ms When indicating a logical 1, T2 as the latest time for a low - high transition. 0.85ms The earliest time it is safe to sample the signal line to determine its state. 1.25ms The latest time it is safe to sample the signal line to determine its state.
Page 523: Table 20-3. The Relationship Betwwen Signal Free Time And Precondition
GD32F1x0 User Manual below: Table 20-3. The relationship betwwen Signal Free Time and precondition Signal Free Tim e (nom inal data bit Precondition periods) Present Initiator w ants to send another message ≥7 immediately after its previous message ≥5 New Initiator w ants to send a message ≥3 Previous attempt to send message unsuccessful This means that there is an opportunity for other devices to gain access to the CEC line during...
Page 524: Figure 20-7. Erro Bit Period
GD32F1x0 User Manual Figure 20-7. Erro bit period Frame error CEC protocol defines that each frame of message need the acknowledgement to confirm the communication is successful. For broadcast(destination address=0xF), the ACK bit should be logic 1 and for singlecast(destination address<0xF), the ACK bit should be logic 0, otherwise the frame error occurs(TAERR/RAE flag asserted).
Page 525: Figure 20-8. The Timing Of Bit Period Long Error
GD32F1x0 User Manual expected. If BPLEIE=1, the CEC interrupt is generated after BPLE is set. When BPLE asserted, controller will stop receiving message and generate error bit if in one of the cases below: BPLEG=1 in both singlecast and broadcast BCNG=0 in broadcast Figure 20-8.
Page 526: Figure 20-9. Transmission Error Detection
GD32F1x0 User Manual Transmission error detection(TERR) The TERR is set when the initiator find low impedance on the CEC bus when it is transmitting high impedance. TERR will also generate CEC interrupt if TERRIE=1. When TERR asserted the transmission is aborted and the software can retry the transmission. TERR check window is depending on the different bit state of the frame shown as below: Figure 20-9.
Page 527: Table 20-6. Hdmi-Cec Interrupt
GD32F1x0 User Manual HDMI-CEC interrupt 20.3.7. There 13 interrupts in HDMI-CEC controller are made up of corresponding flag and interrupt enable bit: Table 20-6. HDMI-CEC Interrupt Interrupt event in HDMI-CEC Event flag Interrupt enable bit Arbitration fail ARBF ARBFIE TX Byte Request TBRIE Transmission end TEND...
Page 528 GD32F1x0 User Manual 20.4. Register definition HDMI-CEC base address: 0x4000 7800 Control register (CEC_CTL) 20.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved ENDOM STAOM CECEN Bits Fields Descriptions 31:3 Reserved Must be kept at reset value.
Page 529 GD32F1x0 User Manual Configuration register (CEC_CFG) 20.4.2. Address offset: 0x04 Reset value: 0x0000 0000 Note: This register can only be write when CECEN=0. This register has to be accessed by word(32-bit). LMEN OAD [14:0] Reserved SFTOPT BCNG BPLEG BREG BRES RTOL SFT[2:0] Bits...
Page 530 GD32F1x0 User Manual 0: Not generate an Error-bit on CEC line w hen detected BPLE in singlecast 1: Generate an Error-bit on CEC line w hen detected BPLE in singlecast BREG Generate an Error-bit w hen detected BRE in singlecast This bit is set and cleared by softw are.
Page 531 GD32F1x0 User Manual Reserved TDATA[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data register These bits are w rite only and contain the data byte to be transmit. Receive data register (CEC_RDATA) 20.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 532 GD32F1x0 User Manual 31:13 Reserved Must be kept at reset value. TAERR Transmit ACK Error flag. This bit is set by hardw are and cleared by softw are writing 1. The ACK bit is received 1 in singlecast and is received 0 in broadcast w ill assert the flag.
Page 533 GD32F1x0 User Manual in broadcast. BPSE Bit Period Short Error This bit is set by hardw are and cleared by softw are writing 1. BPSE is asserted if a data-bit period is less than the minimal period. Bit Rising Error This bit is set by hardw are and cleared by softw are writing 1.
Page 534 GD32F1x0 User Manual TERRIE TERR Interrupt Enable. This bit is set and cleared by softw are. 0: TERR interrupt disable 1: TERR interrupt enable TUIE TU Interrupt Enable. This bit is set and cleared by softw are. 0: TU interrupt disable 1: TU interrupt enable TENDIE TEND Interrupt Enable.
Page 535 GD32F1x0 User Manual 1: RO interrupt enable RENDIE REND Interrupt Enable. This bit is set and cleared by softw are. 0: REND interrupt disable 1: REND interrupt enable BRIE BR Interrupt Enable. This bit is set and cleared by softw are. 0: BR interrupt disable 1: BR interrupt enable...
Page 536: Figure 21-1. Block Diagram Of Tsi Module
GD32F1x0 User Manual Touch sensing interface (TSI) 21.1. Overview Touch Sensing Interface (TSI) provides a convenient solution for touch keys, sliders and capacitive proximity sensing applications. The controller builds on charge transfer method. Placing a finger near fringing electric fields adds capacitance to the system and TSI is able to measure this capacitance change using charge transfer method.
Page 537: Figure 21-2. Block Diagram Of Sample Pin And Channel Pin
GD32F1x0 User Manual etc. Detecting the change of a system is the key problem and goal in these technologies. The TSI module is designed to use charge transfer method which detects the capacitive change of an electrode when touched or close to it by a finger. In order to detect the capacitive change, TSI performs a charge transfer sequence including several charging, transfer steps until satisfying the termination condition.
Page 538: Table 21-1. Pin And Analog Switch State In A Charge-Transfer Sequence
GD32F1x0 User Manual sample pin and channel , i.e. PIN0 is channel pin and PIN1 is sample pin. Table 21-1. Pin and analog switch state in a charge-transfer sequence Step Nam e ASW_0 ASW_1 PIN0 PIN1 Discharge Close Close Input Floating Pull Dow n Buffer Time1 Open...
Page 539: Figure 21-3. Voltage Of A Sample Pin During Charge-Transfer Sequence
GD32F1x0 User Manual 7. Buffer Time3 Buffer time with ASW_0 and ASW_1 open, PIN0 and PIN1 are configured to input floating. 8. Compare ASW_0, ASW_1, PIN0 and PIN1 remain the configuration of step 7. At this step, the voltage of sample pin PIN1 is compared to a threshold called V .
Page 540: Figure 21-4. Fsm Flow Of A Charge-Transfer Sequence
GD32F1x0 User Manual Figure 21-4. FSM flow of a charge-transfer sequence IDLE(discharge) Started Buffer Time1 Extend charge Charge enabled Extend charge disabled Extend Charge Buffer Time2 Vs > Vth ！(Vs > Vth) or the cycle number and the cycle number reaches MCN Charge Transfer do not reach MCN...
Page 541: Table 21-2. Duration Time Of Extend Charge State In Each Cycle
GD32F1x0 User Manual cycles, V (the voltage of sample pin) reaches V (the threshold voltage). There is also a max cycle number defined by MCN in TSI_CTL register. When the cycle number reaches MCN, FSM returns to IDLE state and stops after Compare State, whether reaches V or not.
Page 542 GD32F1x0 User Manual PIN mode control of TSI 21.3.6. There are 4 pins in each group and each of these pins is able to be used as a sample pin or channel pin. Only one pin in a group should be configured as sample pin, and channel pins can be more than one.
Page 543: Table 21-3. Tsi Errors And Flags
GD32F1x0 User Manual If configured as software trigger mode (TRGMOD = 0), charging transfer sequence starts by setting TSIS bit. If configured as hardware trigger mode (TRGMOD = 1), charging transfer sequence is started by falling / rising edge on the trigger pin. Wait for the CTCF or MNERR flag in TSI_INTF register and clear these flags by setting CCTCF or CMNERR bit in TSI_INTC register.
Page 544 GD32F1x0 User Manual TSI group TSI pins GPIO pins PIN2 PB13 PIN3 PB14...
Page 545 GD32F1x0 User Manual 21.4. Registers definition TSI base address: 0x4002 4000 Control register (TSI_CTL) 21.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). CDT[3:0] CTDT[3:0] ECDT[6:0] ECEN ECDIV[0] CTCDIV[2:0] Reserved MCN[2:0] PINMOD EGSEL TRGMOD TSIS TSIEN...
Page 546 GD32F1x0 User Manual Note: Extend charge state is only present w hen ECEN bit in TSI_CTL register is set. ECEN Extend charge state enable. 0: Extend charge disabled 1: Extend charge enabled ECDIV[0] Extend charge clock (ECCLK) division factor. ECCLK is divided from HCLK and ECDIV defines the division factor. 000: f ECCLK HCLK...
Page 547 GD32F1x0 User Manual pin detected. TSIS TSI start This bit is set by softw are to start a charge-transfer sequence in softw are trigger mode and reset by hardw are w hen the sequence stops. After setting this bit, softw are can reset it to stop the started sequence manually. 0: TSI is not started 1: TSI is started.
Page 548 GD32F1x0 User Manual Reserved CMNERR CCTCF Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CMNERR Clear max cycle number error 0: Reserved 1: Clear MNERR CCTCF Clear charge-transfer complete flag 0: Reserved 1: Clear CTCF Interrupt flag register (TSI_INTF) 21.4.4.
Page 549 GD32F1x0 User Manual 1: Charge-transfer complete Pin hysteresis mode register (TSI_PHM) 21.4.5. Address offset: 0x10 Reset value: 0xFFFF FFFF This register can be accessed by word (32-bit). Reserved G5P3 G5P2 G5P1 G5P0 G4P3 G4P2 G4P1 G4P0 G3P3 G3P2 G3P1 G3P0 G2P3 G2P2 G2P1...
Page 550 GD32F1x0 User Manual Sample configuration register (TSI_SAMPCFG) 21.4.7. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved G5P3 G5P2 G5P1 G5P0 G4P3 G4P2 G4P1 G4P0 G3P3 G3P2 G3P1 G3P0 G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1P1...
Page 551 GD32F1x0 User Manual Group control register (TSI_GCTL) 21.4.9. Address offset: 0x30 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 21:16 Group complete This bit is set by hardw are w hen charge-transfer sequence for an enabled group is complete.
Page 552 GD32F1x0 User Manual 13:0 CYCN[13:0] Cycle number These bits reflect the cycle number for a group as soon as a charge-transfer sequence completes. They are cleared by hardw are w hen a new charge-transfer sequence starts.
Page 553: Figure 22-1. Usbd Block Diagram
GD32F1x0 User Manual Universal Serial Bus full-speed device interface (USBD) The USBD is only available on GD32F150 series. 22.1. Overview The Universal Serial Bus full-speed device interface (USBD) module provides a device solution for implementing a USB 2.0 full-speed compliant peripheral. It contains a full-speed internal USB PHY and no more external PHY chip is needed.
Page 554: Table 22-1. Usbd Signal Description
GD32F1x0 User Manual 22.4. Signal description Table 22-1. USBD signal description I/O port Type Description VBUS Input Bus pow er port Input/Output Differential D- Input/Output Differential D+ Note: As soon as the USBD is enabled, these pins are connected to the USBD internal transceiver automatically.
Page 555 GD32F1x0 User Manual Each endpoint supports:  Single/Double buffer (endpoint 0 can’t use double buffer). One endpoint buffer descriptor.   Programmable buffer starting address and buffer length.  Configurable response to a packet.  Control transfer (endpoint 0 only). Endpoint buffer The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus.
Page 556: Figure 22-2. An Example With Buffer Descriptor Table Usage (Usbd_Baddr = 0)
GD32F1x0 User Manual Figure 22-2. An example with buffer descriptor table usage (USBD_BADDR = 0) offset 0x1FF IN endpoint 1 double buffer 0 IN endpoint 1 double buffer 1 Endpoint 0 reception buffer Endpoint 0 transmission buffer COUNT1_TX1 ADDR1_TX1 COUNT1_TX0 Endpoint 1 buffer descriptor (double buffer) ADDR1_TX0 COUNT0_RX...
Page 557: Table 22-2. Double-Buffering Buffer Flag Definition
GD32F1x0 User Manual Table 22-2. Double-buffering buffer flag definition Buffer flag Tx endpoint Rx endpoint TX_DTG (USBD_EPx CS bit 6) RX_DTG (USBD_EPx CS bit 14) SW_BUF RX_DTG (USBD_EPx CS bit 14) TX_DTG (USBD_EPx CS bit 6) The DTG bit and the SW_BUF bit are responsible for the flow control. When a transfer completes, the USB peripheral toggle the DTG bit;...
Page 558 GD32F1x0 User Manual After the transaction process is completed, an endpoint-specific interrupt is generated. In the interrupt routine, the application can process it accordingly. Transaction formatting is performed by the hardware, including CRC generation and checking. Once the endpoint is enabled, endpoint control and status register, buffer address and COUNT filed should not be modified by the application software.
Page 559 GD32F1x0 User Manual length of data is greater than actually allocated length, the excess data are not copied. This is a buffer overrun situation. A STALL handshake is sent, and this transaction fails. If an addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the ACK, according to the endpoint status and no data is written to the endpoint data buffers.
Page 560 GD32F1x0 User Manual the data transmission or reception of data in another buffer. The DTOG bit indicates which buffer that the USB peripheral is currently using. The application software initializes the DTOG according to the first buffer to be used. At the end of each transaction, the RX_ST or TX_ST bit is set, depending on the enabled direction regardless of CRC errors or buffer-overrun conditions (if errors occur, the ERRIF bit will be set).
Page 561 GD32F1x0 User Manual  A device in the non-configured state should draw a maximum of 100mA from the USB bus.  A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor. The maximum value is 500mA. ...
Page 562 GD32F1x0 User Manual Endpoint initialization sequence 1. Program USBD_EPxTBADDR or USBD_EPxRBADDR registers with transmission or reception data buffer address. 2. Program the EP_CTL and EP_KCTL bits in USBD_EPxCS register to set endpoint type and buffer kind according to the endpoint usage. 3.
Page 563 GD32F1x0 User Manual programming USBD_EPxCS register. 3. Wait for successful transfer interrupt (STIF). 4. In the interrupt handler, application needs to update user buffer length and location pointer. Then application fill the endpoint buffer with user buffer data. Last application will configure the endpoint status to be VALID to start next transfer.
Page 564 GD32F1x0 User Manual 22.7. Register definition USBD base address: 0x4000 5C00 USBD control register (USBD_CTL) 22.7.1. Address offset: 0x40 Reset value: 0x0003 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE ESOFIE Reserved...
Page 565 GD32F1x0 User Manual 1: Interrupt generated w hen SOFIF bit in USBD_INTF register is set. ESOFIE Expected start of frame interrupt enable 0: Expected start of frame interrupt disabled 1: Interrupt generated w hen ESOFIF bit in USBD_INTF register is set. Reserved Must be kept at reset value RSREQ...
Page 566 GD32F1x0 User Manual rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value STIF Successful transfer interrupt flag This bit set by hardw are w hen a successful transaction completes PMOUIF Packet memory overrun/underrun interrupt flag This bit set by hardw are to indicate that the packet memory is inadequate to hold transfer data.
Page 567 GD32F1x0 User Manual This register can be accessed by half-word (16-bit) or word (32-bit). Reserved RX_DP RX_DM LOCK SOFLN[1:0] FCNT[10:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value RX_DP Receive data + line status Represent the status on the DP line RX_DM Receive data - line status Represent the status on the DM line...
Page 568 GD32F1x0 User Manual 0: The USB device disabled. No transactions handled. 1: The USB device enabled. USBDAR[6:0] USBD device address After bus reset, the address is reset to 0x00. If the enable bit is set, the device w ill respond on packets for function address DEV_ADDR USBD buffer address register (USBD_BADDR) 22.7.5.
Page 569: Table 22-4. Reception Status Encoding
GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value RX_ST Reception successful transferred Set by hardw are w hen a successful OUT/SETUP transaction complete Cleared by softw are by w riting 0 RX_DTG Reception data PID toggle This bit represent the toggle data bit (0=DATA0,1=DATA1)for non-isochronous endpoint Used to implement the flow control for double-buffered endpoint Used to sw ap buffer for isochronous endpoint 13:12...
Page 570: Table 22-5. Endpoint Type Encoding
GD32F1x0 User Manual Table 22-5. Endpoint type encoding EP_CTL[1:0] Meaning BULK: bulk endpoint CONTROL: control endpoint ISO: isochronous endpoint INTERRUPT: interrupt endpoint Table 22-6. Endpoint kind meaning EP_CTL[1:0] EP_KCTL Meaning BULK DBL_BUF CONTROL STATUS_OUT Table 22-7. Transmission status encoding TX_STA[1:0] Meaning DISABLED: ignore all transmission requests of this endpoint STALL: STALL handshake status...
Page 571 GD32F1x0 User Manual USBD endpoint transmission buffer byte count register 22.7.8. (USBD_EPxTBCNT), x=[0..7] Address offset: [USBD_BADDR] + x * 16 + 4 USB local Address: [USBD_BADDR] + x * 8 + 2 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved EPTXCNT[9:0]...
Page 572 GD32F1x0 User Manual EPRBAR[0] Must be set to 0 USBD endpoint reception buffer byte count register 22.7.10. (USBD_EPxRBCNT), x=[0..7] Address offset: [USBD_BADDR] + x * 16 + 12 USB local Address: [USBD_BADDR] + x * 8 + 6 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved BLKSIZ BLKNUM[4:0]...
Page 573: Table 23-1. List Of Abbreviations Used In Register
GD32F1x0 User Manual Appendix 23.1. List of abbreviations used in register Table 23-1. List of abbreviations used in register abbreviations for Descriptions registers read/w rite (rw ) Softw are can read and w rite to this bit. read-only (r) Softw are can only read this bit. w rite-only (w ) Softw are can only w rite to this bit.
Page 574 GD32F1x0 User Manual 23.3. Available peripherals For availability of peripherals and their number across all MCU series types, refer to the corresponding device data datasheet.
Page 575: Table 24-1. Revision History
GD32F1x0 User Manual Revision history Table 24-1. Revision history Revision No. Description Date Initial Release Mar.18, 2014 Add GD32F170/190 Products Jan.15, 2016 Adapt To New Name Convention Jun.24, 2016 3.0.1 Mar.30, 2017 Proofreading 3.1.0 Proofreading Jan.22, 2018 1. Modify the format according to the version specification. 2.
Page 576 GD32F1x0 User Manual Revision No. Description Date 9. Update Analog to digital converter (ADC) chapter. 10. Delete the SLCD, CAN, IVREF and OPA chapters. 1. Update Direct memory access controller (DM A) chapter. 2. Update Power management unit (PM U) chapter. 3.
Page 577 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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