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GD32E23 Series
GigaDevice Semiconductor GD32E23 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32E23 Series. We have
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GigaDevice Semiconductor GD32E23 Series manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32E23 Series User Manual (547 pages)
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 7 MB
Table of Contents
Table of Contents
2
List of Figures
13
List of Table
19
System and Memory Architecture
21
Arm ® Cortex ® -M23 Processor
21
System Architecture
22
Figure 1-1. the Structure of the Cortex
22
Memory Map
23
Figure 1-2. Series System Architecture of Gd32E23X Series
23
Table 1-1.Memory Map of Gd32E23X Series
24
On-Chip SRAM Memory
26
On-Chip Flash Memory
26
Table 1-2. Flash Module Organization
26
Boot Configuration
27
Table1-3. Boot Modes
27
System Configuration Registers (SYSCFG)
28
System Configuration Register 0 (SYSCFG_CFG0)
28
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
31
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
32
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
33
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
35
System Configuration Register 2 (SYSCFG_CFG2)
38
IRQ Latency Register (SYSCFG_CPU_IRQ_LAT)
39
Device Electronic Signature
39
Memory Density Information
40
Unique Device ID (96 Bits)
40
Flash Memory Controller (FMC)
42
Overview
42
Characteristics
42
Function Overview
42
Flash Memory Architecture
42
Table 2-1. Base Address and Size for Flash Memory
42
Read Operations
43
Table 2-2. the Relation between WSCNT and AHB Clock Frequency
43
Unlock the FMC_CTL Register
44
Page Erase
44
Mass Erase
46
Figure 2-1. Process of Page Erase Operation
46
Main Flash Programming
47
Figure 2-2. Process of the Mass Erase Operation
47
OTP Programming
49
Figure 2-3. Process of the Word Programming Operation
49
Option Byte Erase
50
Option Byte Programming
50
Option Byte Description
51
Table 2-3. Option Byte
51
Page Erase/Program Protection
52
Security Protection
52
Table 2-4. OB_WP Bit for Pages Protected
52
Register Definition
54
Wait State Register (FMC_WS)
54
Unlock Key Register (FMC_KEY)
54
Option Byte Unlock Key Register (FMC_OBKEY)
55
Status Register (FMC_STAT)
55
Control Register (FMC_CTL)
56
Address Register (FMC_ADDR)
58
Option Byte Status Register (FMC_OBSTAT)
58
Write Protection Register (FMC_WP)
59
Product ID Register (FMC_PID)
59
Power Management Unit (PMU)
60
Overview
60
Characteristics
60
Function Overview
60
Figure 3-1. Power Supply Overview
60
Backup Domain
61
VDD / V Dda
62
Figure 3-2. Waveform of the por / PDR
63
Figure 3-3. Waveform of the LVD Threshold
63
1.2V Power Domain
64
Power Saving Modes
64
Table 3-1. Power Saving Mode Summary
65
PMU Registers
67
Control Register (PMU_CTL)
67
Control and Status Register (PMU_CS)
68
Reset and Clock Unit (RCU)
72
Reset Control Unit (RCTL)
72
Overview
72
Function Overview
72
Clock Control Unit (CCTL)
73
Overview
73
Figure 4-1. the System Reset Circuit
73
Figure 4-2. Clock Tree
74
Characteristics
75
Function Overview
75
Figure 4-3. HXTAL Clock Source
75
Table 4-1. Clock Source Select
77
Table 4-2. Core Domain Voltage Selected in Deep-Sleep Mode
78
Register Definition
79
Control Register 0 (RCU_CTL0)
79
Configuration Register 0 (RCU_CFG0)
80
Interrupt Register (RCU_INT)
84
APB2 Reset Register (RCU_APB2RST)
87
APB1 Reset Register (RCU_APB1RST)
88
AHB Enable Register (RCU_AHBEN)
90
APB2 Enable Register (RCU_APB2EN)
91
APB1 Enable Register (RCU_APB1EN)
93
Backup Domain Control Register (RCU_BDCTL)
94
Reset Source /Clock Register (RCU_RSTSCK)
96
AHB Reset Register (RCU_AHBRST)
97
Configuration Register 1 (RCU_CFG1)
98
Configuration Register 2 (RCU_CFG2)
99
Control Register 1 (RCU_CTL1)
100
Voltage Key Register (RCU_VKEY)
101
Deep-Sleep Mode Voltage Register (RCU_DSV)
101
Interrupt/Event Controller (EXTI)
103
Overview
103
Characteristics
103
Interrupts Function Overview
103
Table 5-1. NVIC Exception Types in Cortex-M23
104
Table 5-2. Interrupt Vector Table
104
External Interrupt and Event (EXTI) Block Diagram
106
External Interrupt and Event Function Overview
106
Figure 5-1. Block Diagram of EXTI
106
Table 5-3. EXTI Source
106
Register Definition
109
Interrupt Enable Register (EXTI_INTEN)
109
Event Enable Register (EXTI_EVEN)
109
Rising Edge Trigger Enable Register (EXTI_RTEN)
110
Falling Edge Trigger Enable Register (EXTI_FTEN)
110
Software Interrupt Event Register (EXTI_SWIEV)
111
Pending Register (EXTI_PD)
112
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
113
Overview
113
Characteristics
113
Function Overview
113
GPIO Pin Configuration
114
Figure 6-1. Basic Structure of of a General-Pupose I/O
114
Table 6-1. GPIO Configuration Table
114
Alternate Functions (AF)
115
Additional Functions
115
Input Configuration
115
Output Configuration
116
Analog Configuration
116
Figure 6-2. Basic Structure of Input Configuration
116
Figure 6-3. Basic Structure of Output Configuration
116
Alternate Function (AF) Configuration
117
Figure 6-4. Basic Structure of Analog Configuration
117
Figure 6-5. Basic Structure of Alternate Function Configuration
117
GPIO Locking Function
118
GPIO Single Cycle Toggle Function
118
Register Definition
119
Port Control Register (Gpiox_Ctl, X=A
119
Port Output Mode Register (Gpiox_Omode, X=A
120
Port Output Speed Register (Gpiox_Ospd, X=A
122
Port Pull-Up/Down Register (Gpiox_Pud, X=A
124
Port Input Status Register (Gpiox_Istat, X=A
125
Port Output Control Register (Gpiox_Octl, X=A
126
Port Bit Operate Register (Gpiox_Bop, X=A
126
Port Configuration Lock Register (Gpiox_Lock, X=A,B)
127
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A,B,C)
128
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A,B,C)
129
Bit Clear Register (Gpiox_Bc, X=A
130
Port Bit Toggle Register (Gpiox_Tg, X=A
130
Cyclic Redundancy Checks Management Unit (CRC)
132
Overview
132
Characteristics
132
Figure 7-1. Block Diagram of CRC Calculation Unit
132
Function Overview
133
Register Definition
135
Data Register (CRC_DATA)
135
Free Data Register (CRC_FDATA)
135
Control Register (CRC_CTL)
136
Initialization Data Register (CRC_IDATA)
137
Polynomial Register (CRC_POLY)
137
Direct Memory Access Controller (DMA)
138
Overview
138
Characteristics
138
Block Diagram
139
Function Overview
139
DMA Operation
139
Figure 8-1. Block Diagram of DMA
139
Table 8-1. DMA Transfer Operation
140
Peripheral Handshake
141
Figure 8-2. Handshake Mechanism
141
Arbitration
142
Address Generation
142
Circular Mode
142
Memory to Memory Mode
142
Channel Configuration
143
Interrupt
143
Table 8-2. Interrupt Events
143
DMA Request Mapping
144
Figure 8-3. DMA Interrupt Logic
144
Table 8-3. DMA Requests for each Channel
144
Figure 8-4. DMA Request Mapping
145
Register Definition
147
Interrupt Flag Register (DMA_INTF)
147
Interrupt Flag Clear Register (DMA_INTC)
147
Channel X Control Register (Dma_Chxctl)
148
Channel X Counter Register (Dma_Chxcnt)
150
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
151
Channel X Memory Base Address Register (Dma_Chxmaddr)
151
Debug (DBG)
153
Overview
153
SW Function Overview
153
Pin Assignment
153
Debug Hold Function Overview
153
Debug Support for Power Saving Mode
153
Debug Support for TIMER, I2C, RTC, WWDGT and FWDGT
154
Register Definition
155
ID Code Register (DBG_ID)
155
Control Register 0 (DBG_CTL0)
155
Control Register 1 (DBG_CTL1)
157
Analog to Digital Converter (ADC)
159
Overview
159
Characteristics
159
Pins and Internal Signals
160
Figure 10-1. ADC Module Block Diagram
160
Table 10-1. ADC Internal Input Signals
160
Table 10-2. ADC Input Pins Definition
160
Function Overview
161
Foreground Calibration Function
161
Dual Clock Domain Architecture
162
ADC Enable
162
Routine Sequence
162
Operation Mode
162
Figure 10-2. Single Operation Mode
162
Figure 10-3. Continuous Operation Mode
163
Figure 10-4. Scan Operation Mode, Continuous Disable
164
Figure 10-5. Scan Operation Mode, Continuous Enable
164
Conversion Result Threshold Monitor Function
165
Data Storage Mode
165
Figure 10-6. Discontinuous Operation Mode
165
Figure 10-7. Data Storage Mode of 12-Bit Resolution
166
Figure 10-8. Data Storage Mode of 10-Bit Resolution
166
Figure 10-9. Data Storage Mode of 8-Bit Resolution
166
Figure 10-10. Data Storage Mode of 6-Bit Resolution
166
Sample Time Configuration
167
External Trigger Configuration
167
DMA Request
167
ADC Internal Channels
167
Table 10-3. External Trigger Source for ADC
167
Programmable Resolution (DRES) - Fast Conversion Mode
168
On-Chip Hardware Oversampling
168
Table 10-4. T CONV Timings Depending on Resolution
168
Figure 10-11. 20-Bit to 16-Bit Result Truncation
169
Figure 10-12. a Numerical Example with 5-Bit Shifting and Rounding
169
Table 10-5. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)
170
ADC Interrupts
171
Register Definition
172
Status Register (ADC_STAT)
172
Control Register 0 (ADC_CTL0)
172
Control Register 1 (ADC_CTL1)
174
Sample Time Register 0 (ADC_SAMPT0)
175
Sample Time Register 1 (ADC_SAMPT1)
176
Watchdog Low Threshold Register (ADC_WDLT)
177
Routine Sequence Register 0 (ADC_RSQ0)
177
Routine Sequence Register 1 (ADC_RSQ1)
178
Routine Sequence Register 2 (ADC_RSQ2)
179
Routine Data Register (ADC_RDATA)
179
Oversampling Control Register (ADC_OVSAMPCTL)
180
Comparator (CMP)
182
Introduction
182
Main Features
182
Function Description
182
CMP Clock and Reset
183
CMP I/O Configuration
183
CMP Operating Mode
183
Figure 11-1. CMP Block Diagram
183
CMP Hysteresis
184
CMP Register Write Protection
184
Figure 11-2. CMP Hysteresis
184
CMP Registers
185
Control/Status Register (CMP_CS)
185
Watchdog Timer (WDGT)
187
Free Watchdog Timer (FWDGT)
187
Overview
187
Characteristics
187
Function Overview
187
Figure 12-1. Free Watchdog Block Diagram
188
Table 12-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
189
Register Definition
190
Window Watchdog Timer (WWDGT)
194
Overview
194
Characteristics
194
Function Overview
194
Figure 12-2. Window Watchdog Timer Block Diagram
195
Figure 12-3. Window Watchdog Timing Diagram
196
Table 12-2. Min-Max Timeout Value at 72 Mhz
196
Register Definition
197
Real-Time Clock(RTC)
199
Overview
199
Characteristics
199
Function Overview
200
Block Diagram
200
Figure 13-1. Block Diagram of RTC
200
Clock Source and Prescalers
201
Shadow Registers Introduction
201
Configurable and Field Maskable Alarm
201
RTC Initialization and Configuration
202
Calendar Reading
203
Resetting the RTC
204
RTC Shift Function
205
RTC Reference Clock Detection
205
RTC Smooth Digital Calibration
206
Time-Stamp Function (Only for Gd32E230Xx Devices)
208
Tamper Detection
208
Calibration Clock Output
209
Alarm Output
209
RTC Power Saving Mode Management
210
RTC Interrupts
210
Table 13-1. RTC Power Saving Mode Management
210
Table 13-2. RTC Interrupts Control
210
Register Definition
212
Time Register (RTC_TIME)
212
Date Register (RTC_DATE)
212
Control Register (RTC_CTL)
213
Status Register (RTC_STAT)
217
Prescaler Register (RTC_PSC)
220
Alarm 0 Time and Date Register (RTC_ALRM0TD)
220
Write Protection Key Register (RTC_WPK)
221
Sub Second Register (RTC_SS)
222
Shift Function Control Register (RTC_SHIFTCTL)
222
Time of Time Stamp Register (RTC_TTS)
223
Date of Time Stamp Register (RTC_DTS)
224
Sub Second of Time Stamp Register (RTC_SSTS)
224
High Resolution Frequency Compensation Register (RTC_HRFC)
225
Tamper Register (RTC_TAMP)
226
Alarm 0 Sub Second Register (RTC_ALRM0SS)
230
Backup Registers (Rtc_Bkpx) (X=0
231
Timer (Timerx)
232
Table 14-1. Timers (Timerx) Are Devided into Six Sorts
232
Advanced Timer (Timerx, X=0)
233
Overview
233
Characteristics
233
Block Diagram
234
Figure 14-1. Advanced Timer Block Diagram
234
Function Overview
235
Figure 14-2. Timing Chart of Internal Clock Divided by 1
235
Figure 14-3. Timing Chart of PSC Value Change from 0 to 2
236
Figure 14-4. Timing Chart of up Counting Mode, PSC=0/2
237
Figure 14-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
238
Figure 14-6. Timing Chart of down Counting Mode, PSC=0/2
239
Figure 14-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
239
Figure 14-8. Timing Chart of Center-Aligned Counting Mode
241
Figure 14-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
242
Figure 14-10. Repetition Counter Timing Chart of up Counting Mode
242
Figure 14-11. Repetition Counter Timing Chart of down Counting Mode
243
Figure 14-12. Channel Input Capture Principle
244
Figure 14-13. Channel Output Compare Principle (with Complementary Output, X=0,1,2)
245
Figure 14-14. Channel Output Compare Principle (CH3_O)
245
Figure 14-15. Output-Compare in Three Modes
246
Figure 14-16. Timing Chart of EAPWM
247
Figure 14-17. Timing Chart of CAPWM
247
Table 14-2. Complementary Outputs Controlled by Parameters
249
Figure 14-18. Complementary Output with Dead Time Insertion
251
Figure 14-19. Output Behavior of the Channel in Response to a Break (the Break High Active)
252
Table 14-3. Counting Direction in Different Quadrature Decoder Mode
252
Figure 14-20. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
253
Figure 14-21. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
253
Figure 14-22. Hall Sensor Is Used to BLDC Motor
253
Figure 14-23. Hall Sensor Timing between Two Timers
255
Table 14-4. Examples of Slave Mode
255
Figure 14-24. Restart Mode
256
Figure 14-25. Pause Mode
256
Figure 14-26. Event Mode
257
Figure 14-27. Single Pulse Mode Timerx_Chxcv=4, Timerx_Car=99
257
Figure 14-28. TIMER0 Master/Slave Mode Timer Example
258
Figure 14-29. Triggering TIMER0 with Enable Signal of TIMER2
260
Figure 14-30. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
261
Timerx Registers(X=0)
262
General Level0 Timer (Timerx, X=2)
290
Overview
290
Characteristics
290
Block Diagram
290
Figure 14-31. General Level 0 Timer Block Diagram
290
Function Overview
291
Figure 14-32. Timing Chart of Internal Clock Divided by 1
292
Figure 14-33. Timing Chart of PSC Value Change from 0 to 2
293
Figure 14-34. Timing Chart of up Counting Mode, PSC=0/2
294
Figure 14-35. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
295
Figure 14-36. Timing Chart of down Counting Mode, PSC=0/2
295
Figure 14-37. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
296
Figure 14-38. Timing Chart of Center-Aligned Counting Mode
297
Figure 14-39. Channel Input Capture Principle
299
Figure 14-40. Channel Output Compare Principle (X=0,1,2,3)
300
Figure 14-41. Output-Compare under Three Modes
301
Figure 14-42. Timing Chart of EAPWM
302
Figure 14-43. Timing Chart of CAPWM
302
Timerx Registers(X=2)
305
General Level2 Timer (Timerx, X=13)
328
Overview
328
Characteristics
328
Block Diagram
328
Figure 14-44. General Level2 Timer Block Diagram
328
Function Overview
330
Figure 14-45. Timing Chart of Internal Clock Divided by 1
330
Figure 14-46. Timing Chart of PSC Value Change from 0 to 2
331
Figure 14-47. Timing Chart of up Counting Mode, PSC=0/2
332
Figure 14-48. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
332
Figure 14-49. Channel Input Capture Principle
333
Figure 14-50. Channel Output Compare Principle
334
Figure 14-51. Output-Compare in Three Modes
335
Figure 14-52. PWM Mode Timechart
336
Timerx Registers(X=13)
338
Figure 14-53. General Level3 Timer Block Diagram
348
Figure 14-54. Timing Chart of Internal Clock Divided by 1
350
Figure 14-55. Timing Chart of PSC Value Change from 0 to 2
351
Figure 14-56. Timing Chart of up Counting Mode, PSC=0/2
352
Figure 14-57. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
352
Figure 14-58. Repetition Counter Timing Chart of up Counting Mode
353
Figure 14-59. Channel Input Capture Principle
354
Figure 14-60. Channel Output Compare Principle (with Complementary Output, X=0)
355
Figure 14-61. Channel Output Compare Principle (CH1_O)
355
Figure 14-62. Output-Compare in Three Modes
356
Figure 14-63. PWM Mode Timechart
357
Table 14-5. Complementary Outputs Controlled by Parameters
359
Figure 14-64. Complementary Output with Dead-Time Insertion
360
Figure 14-65. Output Behavior in Response to a Break(the Break High Active)
361
Figure 14-66. Restart Mode
362
Table 14-6. Slave Mode Example Table
362
Figure 14-67. Pause Mode
363
Figure 14-68. Event Mode
363
Figure 14-69. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
364
Figure 14-70. General Level4 Timer Block Diagram
386
Figure 14-71. Timing Chart of Internal Clock Divided by 1
388
Figure 14-72. Timing Chart of PSC Value Change from 0 to 2
389
Figure 14-73. Timing Chart of up Counting Mode, PSC=0/2
390
Figure 14-74. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
390
Figure 14-75. Repetition Counter Timing Chart of up Counting Mode
391
Figure 14-76. Channel Input Capture Principle
392
Figure 14-77. Channel Output Compare Principle (with Complementary Output, X=0)
393
Figure 14-78. Output-Compare under Three Modes
394
Figure 14-79. PWM Mode Timechart
395
Table 14-7. Complementary Outputs Controlled by Parameters
396
Figure 14-80. Complementary Output with Dead-Time Insertion
398
Figure 14-81. Output Behavior in Response to a Break(the Break High Active)
399
Figure 14-82. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
399
Figure 14-83. Basic Timer Block Diagram
417
Figure 14-84. Timing Chart of Internal Clock Divided by 1
418
Figure 14-85. Timing Chart of PSC Value Change from 0 to 2
419
Figure 14-86. Timing Chart of up Counting Mode, PSC=0/2
420
Figure 14-87. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
420
Figure 15-1. IFRP Output Timechart 1
427
Figure 15-2. IFRP Output Timechart 2
428
Figure 15-3. IFRP Output Timechart 3
428
Figure 16-1. USART Module Block Diagram
431
Table 16-1. Description of USART Important Pins
431
Figure 16-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
432
Table 16-2. Configuration of Stop Bits
432
Figure 16-3.USART Transmit Procedure
434
Figure 16-4.Oversampling Method of a Receive Frame Bit (OSB=0)
435
Figure 16-5. Configuration Step When Using DMA for USART Transmission
436
Figure 16-6. Configuration Step When Using DMA for USART Reception
437
Figure 16-7. Hardware Flow Control between Two Usarts
437
Figure16-8. Hardware Flow Control
438
Figure 16-9. Break Frame Occurs During Idle State
439
Figure 16-10. Break Frame Occurs During a Frame
440
Figure 16-11. Example of USART in Synchronous Mode
440
Figure 16-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
441
Figure 16-13. Irda SIR ENDEC Module
441
Figure 16-14. Irda Data Modulation
442
Figure 16-15. ISO7816-3 Frame Format
443
Figure 16-16. USART Receive FIFO Structure
445
Table 16-3. USART Interrupt Requests
446
Figure 16-17. USART Interrupt Mapping Diagram
447
Figure 17-1. I2C Module Block Diagram
467
Table 17-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
468
Figure 17-2. Data Validation
469
Figure 17-3. START and STOP Signal
469
Figure 17-4. Clock Synchronization
470
Figure 17-5. SDA Line Arbitration
470
Figure 17-6. I2C Communication Flow with 7-Bit Address
471
Figure 17-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
471
Figure 17-8. I2C Communication Flow with 10-Bit Address (Master Receive)
471
Figure 17-9. Programming Model for Slave Transmitting (10-Bit Address Mode)
471
Figure 17-10. Programming Model for Slave Receiving (10-Bit Address Mode)
474
Figure 17-11. Programming Model for Master Transmitting (10-Bit Address Mode)
475
Figure 17-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)
477
Figure 17-13. Programming Model for Master Receiving Mode Using Solution B (10-Bit Address Mode)
479
Table 17-2. Event Status Flags
482
Table 17-3. Error Flags
483
Figure 18-1. Block Diagram of SPI
497
Table 18-1. SPI Signal Description
497
Figure 18-2. SPI0 Timing Diagram in Normal Mode
498
Table 18-2. Quad-SPI Signal Description
498
Figure 18-3. SPI1 Timing Diagram in Normal Mode
499
Figure 18-4. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
499
Figure 18-5. SPI1 Data Frame Right-Aligned Diagram
500
Figure 18-6. Transmission and Reception FIFO
500
Table 18-3. NSS Function in Slave Mode
501
Table 18-4. NSS Function in Master Mode
502
Table 18-5. SPI Operation Modes
502
Figure 18-7. a Typical Full-Duplex Connection
504
Figure 18-8. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
504
Figure 18-9. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
504
Figure 18-10. a Typical Bidirectional Connection
504
Figure 18-11. Timing Diagram of TI Master Mode with Discontinuous Transfer
507
Figure 18-12. Timing Diagram of TI Master Mode with Continuous Transfer
507
Figure 18-13. Timing Diagram of TI Slave Mode
508
Figure 18-14. Timing Diagram of NSS Pulse with Continuous Transmit
509
Figure 18-15. Timing Diagram of Write Operation in Quad-SPI Mode
510
Figure 18-16. Timing Diagram of Read Operation in Quad-SPI Mode
511
Figure 18-17. Block Diagram of I2S
515
Table 18-6. SPI Interrupt Requests
515
Figure 18-18. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
516
Figure 18-19. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
517
Figure 18-20. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
517
Figure 18-21. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
517
Figure 18-22. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
517
Figure 18-23. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
517
Figure 18-24. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
518
Figure 18-25. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
518
Figure 18-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
518
Figure 18-27. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
518
Figure 18-28. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
519
Figure 18-29. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
519
Figure 18-30. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
519
Figure 18-31. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
519
Figure 18-32. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
519
Figure 18-33. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
519
Figure 18-34. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
520
Figure 18-35. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
520
Figure 18-36. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
520
Figure 18-37. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
520
Figure 18-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
521
Figure 18-39. PCM Standard Short Frame Synchronization Mode Timing Diagram
522
Figure 18-40. PCM Standard Short Frame Synchronization Mode Timing Diagram
522
Figure 18-41. PCM Standard Short Frame Synchronization Mode Timing Diagram
522
Figure 18-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
522
Figure18-43. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
522
Figure 18-44. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
522
Figure 18-45. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
522
Figure 18-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
522
Figure18-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
523
Figure 18-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
523
Figure 18-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
523
Figure 18-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
523
Figure 18-51. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
523
Figure 18-52. PCM Standard Long Frame Synchronization Mode Timing Diagram
523
Figure 18-53. PCM Standard Long Frame Synchronization Mode Timing Diagram
523
Figure 18-54. Block Diagram of I2S Clock Generator
524
Table 18-7. I2S Bitrate Calculation Formulas
524
Figure 18-55. I2S Initialization Sequence
525
Table 18-8. Audio Sampling Frequency Calculation Formulas
525
Table 18-9. Direction of I2S Interface Signals for each Operation Mode
525
Figure 18-56. I2S Master Reception Disabling Sequence
528
Table 18-10. I2S Interrupt
530
Table 20-1. List of Abbreviations Used in Register
544
Table 20-2. List of Terms
544
Table 21-1. Revision History
546
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