Download Print this page

GigaDevice Semiconductor GD32E50 Series User Manual

GigaDevice Semiconductor GD32E50 Series User Manual

Arm cortex-m33 32-bit mcu

page of 1245

/ 1245
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

GigaDevice Semiconductor Inc.

GD32E50x

®

Arm

Cortex

-M33 32-bit MCU

®

For GD32E503xx, GD32E505xx, GD32E507xx, GD32E508xx,

GD32EPRTxx

User Manual

Revision 1.7

(Jun. 2022)

Table of Contents

Advertisement

Chapters

Table of Contents

Need help?

Need help?

Do you have a question about the GD32E50 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for GigaDevice Semiconductor GD32E50 Series

Page 1 GigaDevice Semiconductor Inc. GD32E50x ® Cortex -M33 32-bit MCU ® For GD32E503xx, GD32E505xx, GD32E507xx, GD32E508xx, GD32EPRTxx User Manual Revision 1.7 (Jun. 2022)
Page 2: Table Of Contents
GD32E50x User Manual Table of Contents Table of Contents......................... 2 List of Figures ........................21 List of Tables ........................31 1. System and me mory architecture ................36 1.1. ® Cortex ® -M33 processor.................. 36 1.2. System architecture ....................37 1.3.
Page 3 GD32E50x User Manual 2.4.5. Control register (FMC_CTL)..................61 2.4.6. Address register (FMC_ADDR) ................62 2.4.7. Option byte status register (FMC_OBSTAT) ...............62 2.4.8. Erase/Program protection register (FMC_WP) ............63 2.4.9. Product ID register (FMC_PID).................63 3. Backup registers (BKP)....................65 3.1. Overview........................65 3.2. Characteristics ......................65 3.3.
Page 4 GD32E50x User Manual 5.3. Register definition....................94 5.3.1. Control register (RCU_CTL)..................94 5.3.2. Clock configuration register 0 (RCU_CFG0) ...............95 5.3.3. Clock interrupt register (RCU_INT) ................99 5.3.4. APB2 reset register (RCU_APB2RST)..............101 5.3.5. APB1 reset register (RCU_APB1RST)..............104 5.3.6. AHB enable register (RCU_AHBEN) ............... 107 5.3.7.
Page 5 GD32E50x User Manual 5.6.14. Additional clock control register (RCU_ADDCTL) ............162 5.6.15. Additional Clock configuration register (RCU_ADDCFG) ..........164 5.6.16. Additional clock interrupt register (RCU_ADDINT) ............. 165 5.6.17. PLL clock spread spectrum control register (RCU_PLLSSCTL) ........166 5.6.18. Clock configuration register 2 (RCU_CFG2) ............. 167 5.6.19.
Page 6 GD32E50x User Manual 8.3.2. External interrupt/event lines .................. 194 8.3.3. Alternate functions (AF)..................194 8.3.4. Input configuration....................194 8.3.5. Output configuration ..................... 195 8.3.6. Analog configuration ..................... 195 8.3.7. Alternate function (AF) configuration ............... 196 8.3.8. IO pin function selection ..................196 8.3.9.
Page 7 GD32E50x User Manual 3.2.21. AFIO port configuration register E (AFIO_PCFE)............233 3.2.22. AFIO port configuration register G (AFIO_PCFG) ............234 9. Cyclic redundancy checks manage ment unit (CRC) ........... 237 3.3. Overview........................ 237 3.4. Characteristics ...................... 237 3.5. Function overview....................238 3.6.
Page 8 GD32E50x User Manual 11.3. Block diagram ....................255 11.4. Function overview ..................... 255 11.4.1. DMA operation..................... 255 11.4.2. Peripheral handshake ................... 257 11.4.3. Arbitration ......................257 11.4.4. Address generation ....................258 11.4.5. Circular mode ...................... 258 11.4.6. Memory to memory mode ..................258 11.4.7.
Page 9 GD32E50x User Manual 13.4.3. ADCON enable ....................280 13.4.4. Single-ended and differential input channels............. 280 13.4.5. Routine sequence ....................281 13.4.6. Operation modes ....................281 13.4.7. Conversion result threshold monitor ................ 284 13.4.8. Data storage mode ....................284 13.4.9. Sample time configuration ..................285 13.4.10.
Page 10 GD32E50x User Manual 14.3.2. DAC output buffer ....................309 14.3.3. DAC data configuration ..................310 14.3.4. DAC trigger ......................310 14.3.5. DAC workflow ...................... 310 14.3.6. DAC output FIFO ....................311 14.3.7. DAC noise wave ....................311 14.3.8. DAC output calculate .................... 312 14.3.9.
Page 11 GD32E50x User Manual 16.1.3. Function overview ....................336 16.1.4. Register definition ....................339 16.2. Window watchdog timer (WWDGT) ..............342 16.2.1. Overview ......................342 16.2.2. Characteristics..................... 342 16.2.3. Function overview ....................342 16.2.4. Register definition ....................345 Real-time clock (RTC).................... 347 3.7.
Page 12 GD32E50x User Manual 18.3.1. Overview ......................455 18.3.2. Characteristics..................... 455 18.3.3. Block diagram...................... 455 18.3.4. Function overview ....................456 18.3.5. TIMERx registers(x=8, 11) ..................467 18.4. General level2 timer (TIMERx, x=9, 10, 12, 13) ..........480 18.4.1. Overview ......................480 18.4.2.
Page 13 GD32E50x User Manual 20.1. Universal synchronous/asynchronous receiver /transmitter (USARTx, x=0..4) 20.1.1. Overview ......................683 20.1.2. Characteristics..................... 683 20.1.3. Function overview ....................684 20.1.4. Register definition ....................700 20.2. Universal synchronous/asynchronous receiver /transmitter (USARTx, x=5) .. 714 20.2.1. Overview ......................714 20.2.2.
Page 14 GD32E50x User Manual 22.4.4. I2S clock ......................844 22.4.5. Operation......................845 22.4.6. DMA function ..................... 849 22.4.7. I2S interrupts ..................... 849 Register definition ..................... 852 22.5. 22.5.1. Control register 0 (SPI_CTL0) ................852 22.5.2. Control register 1 (SPI_CTL1) ................854 22.5.3.
Page 15 GD32E50x User Manual 24.5. Card functional description ................882 24.5.1. Card registers ...................... 882 24.5.2. Commands ......................883 24.5.3. Responses......................894 24.5.4. Data packets format ..................... 898 24.5.5. Two status fields of the card................... 899 24.6. Programming sequence ..................906 24.6.1.
Page 16 GD32E50x User Manual 25.3.3. External device address mapping ................938 25.3.4. NOR/PSRAM controller..................941 25.3.5. NAND Flash or PC Card controller ................960 25.4. Registers definition.................... 966 25.4.1. NOR/PSRAM controller registers ................966 25.4.2. NAND Flash/PC Card controller registers..............970 Controller area network (CAN)................
Page 17 GD32E50x User Manual 26.4.20. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0,1)...... 1012 26.4.21. Filter control register (CAN_FCTL) ................ 1013 26.4.22. Filter mode configuration register (CAN_FMCFG) ........... 1013 26.4.23. Filter scale configuration register (CAN_FSCFG) ............ 1014 26.4.24. Filter associated FIFO register (CAN_FAFIFO) ............1015 26.4.25.
Page 18 GD32E50x User Manual 27.4.20. MAC address 3 high register (ENET_MAC_ADDR3H) ..........1091 27.4.21. MAC address 3 low register (ENET_MAC_ADDR3L) ..........1092 27.4.22. MAC flow control threshold register (ENET_MAC_FCTH)......... 1092 27.4.23. MSC control register (ENET_MSC_CTL) ............... 1093 27.4.24. MSC receive interrupt flag register (ENET_MSC_RINTF) ......... 1094 27.4.25.
Page 19 GD32E50x User Manual 28.2. Main features ....................1124 28.3. Block diagram ....................1125 28.4. Signal description .................... 1125 28.5. Clock configuration ..................1125 28.6. Function overview ................... 1126 28.6.1. USB endpoints....................1126 28.6.2. Operation procedure................... 1129 28.6.3. USB events and interrupts ................... 1131 28.6.4.
Page 20 GD32E50x User Manual 29.7. Register definition ................... 1167 29.7.1. USBHS global registers..................1167 29.7.2. Host control and status registers................1196 29.7.3. Device control and status registers ............... 1210 29.7.4. Power and clock control register (USBHS_PWRCLKCTL) ........1239 Appendix ....................... 1241 List of abbreviations used in register .............
Page 21: List Of Figures
GD32E50x User Manual List of Figures ® Figure 1-1. The structure of the Cortex -M33 processor ...........37 Figure 1-2. GD32E50x system architecture ...............39 Figure 2-1. Process of page erase operation ..............51 Figure 2-2. Process of mass erase operation..............52 Figure 2-3. Process of word program operation..............54 Figure 4-1.
Page 22 GD32E50x User Manual Figure 13-7. Discontinuous operation mode ..............283 Figure 13-8. 12-bit data storage mode ................284 Figure 13-9. 6-bit data storage mode ................285 Figure 13-10. 20-bit to 16-bit re sult truncation ..............288 Figure 13-11. Numerical example with 5-bits shift and rounding........288 Figure 13-12.
Page 23 GD32E50x User Manual Figure 18-23. Hall sensor timing between two timers............378 Figure 18-24. Restart mode..................... 379 Figure 18-25. Pause mode ....................380 Figure 18-26. Event mode ....................380 Figure 18-27. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 ......381 Figure 18-28.
Page 24 GD32E50x User Manual Figure 18-67. Basic timer block diagram................. 500 Figure 18-68. Timing chart of internal clock divided by 1 ..........501 Figure 18-69. Timing chart of PSC value change from 0 to 2........... 501 Figure 18-70. Timing chart of up counting mode, PSC=0/2 ..........502 Figure 18-71.
Page 25 GD32E50x User Manual Figure 19-40. Regular entry for bunch mode..............552 Figure 19-41. Delayed entry for bunch mode ..............553 Figure 19-42. Emulate bunch mode example ..............554 Figure 19-43. Extern event y(y=0..4) processed diagram..........556 Figure 19-44. Extern event y(y=5..9) processed diagram..........556 Figure 19-45.
Page 26 GD32E50x User Manual Figure 21-5. SDA line arbitration ..................752 Figure 21-6. I2C communication flow with 7-bit address ..........753 Figure 21-7. I2C communication flow with 10-bit address (Master Transmit)....753 Figure 21-8. I2C communication flow with 10-bit address (Master Receive) ....753 Figure 21-9.
Page 27 GD32E50x User Manual Figure 22-9. Timing diagram of TI master mode with continuous transfer....... 829 Figure 22-10. Timing diagram of TI slave mode .............. 829 Figure 22-11. Timing diagram of NSS pulse with continuous transmit ......830 Figure 22-12. Timing diagram of write operation in Quad-SPI mode ....... 831 Figure 22-13.
Page 28 GD32E50x User Manual Figure22-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....................842 Figure 22-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ....................843 Figure 22-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....................
Page 29 GD32E50x User Manual Figure 24-18. Multiple block 4-Bit write interrupt cycle timing......... 920 Figure 24-19. The operation for command completion disable signal ......921 Figure 25-1. The EXMC block diagram ................937 Figure 25-2. EXMC memory banks.................. 938 Figure 25-3. Four regions of bank0 address mapping ............. 939 Figure 25-4.
Page 30 GD32E50x User Manual Figure 27-7. Transmit descriptor in normal mode ............1044 Figure 27-8. Transmit descriptor in enhanced mode ............. 1050 Figure 27-9. Receive descriptor in normal mode............1054 Figure 27-10. Receive descriptor in enhanced mode ............ 1060 Figure 27-11. Wakeup frame filter register ..............1065 Figure 27-12.
Page 31: List Of Tables
GD32E50x User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ....37 Table 1-2. Memory map of GD32E50x devices ..............40 Table 1-3. Boot modes......................44 Table 2-1. GD32E50x_HD and GD32E50x_CL base address and size for flash memory ..47 Table 2-2.
Page 32 GD32E50x User Manual Table 13-1. ADC internal input signals................277 Table 13-2. ADC input pins definition ................277 Table 13-3. External trigger source for ADC0 and ADC1 ..........285 Table 13-4. External trigger source for ADC2 ..............285 timings depending on resolution............287 Table 13-5.
Page 33 GD32E50x User Manual semiconductors) ..................... 750 Table 21-2. Event status flags ..................764 Table 21-3. Error flags ....................765 Table 21-4. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) ..................... 781 Table 21-5. Data setup time and data hold time............... 786 Table 21-6.
Page 34 GD32E50x User Manual Table 24-25. Performance move field ................904 Table 24-26. AU_SIZE field ....................905 Table 24-27. Maximum AU size ..................905 Table 24-28. Erase size field ................... 905 Table 24-29. Erase timeout field ..................906 Table 24-30. Erase offset field..................906 Table 24-31.
Page 35 GD32E50x User Manual Table 28-6. Endpoint kind meaning ................1140 Table 28-7. Transmission status encoding ..............1141 Table 29-1. USBHS signal description ................1145 Table 29-2. USBHS supported speeds ................1146 Table 29-3. USBHS global interrupt ................1165 Table 30-1. List of abbreviations used in register ............1241 Table 30-2.
Page 36: System And Memory Architecture
GD32E50x User Manual System and memory architecture The devices of GD32E50x series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M33 processor. The Arm Cortex -M33 processor includes two AHB buses ® ® known as Code and System buses. All memory accesses of the Arm Cortex -M33 processor are executed on these two buses according to the different purposes and the target memory...
Page 37: System Architecture
GD32E50x User Manual ® Figure 1-1. The structure of the Cortex -M33 processor Cortex-M33 processor Cortex-M33 core Nested Interrupts Vectored Floating Point Interrupt Unit(FPU) Controller (NVIC) DSP Extension Data Breakpoint Memory Watchpoint Unit Protection And Trace (BPU) Unit(MPU) (DWT) Serial-Wire Or JTAG Instrumentation Trace Port...
Page 38 GD32E50x User Manual CBUS SBUS DMA0 DMA1 ENET OTGHS APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including CBUS, SBUS, DMA0, DMA1, ENET and OTGHS. CBUS is the code bus of the Cortex®-M33 core, which is used for any instruction fetch and data access to the Code region.
Page 39: Memory Map
GD32E50x User Manual Figure 1-2. GD32E50x system architecture SW/JTAG TPIU POR/ PDR Flash Flash ARM Cortex-M33 Memory Memory Cbus Processor Controller Fmax:180MHz : 180MHz NVIC Master FMC SQPI TMU CRC SDIO 1.1V GP DMA 12 chs Slave AHB Peripherals Master 8MHz ENET SRAM...
Page 40: Table 1-2. Memory Map Of Gd32E50X Devices
GD32E50x User Manual ® Additionally, a pre-defined memory map is provided by the Cortex -M33 processor to reduce the software complexity of repeated implementation of different device vendors. In the map, ® ® some regions are used by the Arm Cortex -M33 system peripherals which can not be modified.
Page 41 GD32E50x User Manual Pre-defined Address Peripherals Regions 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved...
Page 42 GD32E50x User Manual Pre-defined Address Peripherals Regions 0x4000 C800 - 0x4000 CBFF 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF I2C2 0x4000 8C00 - 0x4000 BFFF Reserved 0x4000 8800 - 0x4000 8BFF CAN2SRAM 0x4000 8400 - 0x4000 87FF USBSRAM_B 0x4000 8000 - 0x4000 BFFF Reserved...
Page 43: On-Chip Sram Memory
GD32E50x User Manual Pre-defined Address Peripherals Regions 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved SRAM 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2000 0000 - 0x2001FFFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes...
Page 44: Boot Configuration
GD32E50x User Manual Kbytes are called High-density devices (GD32E50x_HD). GD32E505xx and GD32E507xx microcontrollers are called connectivity line devices (GD32E50x_CL). Refer to Flash memory controller (FMC) Chapter for more details. Boot configuration 1.4. The GD32E50x devices provide three kinds of boot sources which can be selected by the BOOT0 and BOOT1 pins.
Page 45: Memory Density Information
GD32E50x User Manual Memory density information 1.5.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes. Example: 0x0080 indicates 128 Kbytes.
Page 46: System Configuration Registers
GD32E50x User Manual Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID System configuration registers 1.6.
Page 47: Flash Memory Controller (Fmc)
GD32E50x User Manual Flash memory controller (FMC) Overview 2.1. The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 512K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 48: Read Operations
GD32E50x User Manual Block Nam e Address range Size(bytes) Information GD32E50x_HD 0x1FFF E000- 0x1FFF F7FF Boot loader area block GD32E50x_CL 0x1FFF B000- 0x1FFF F7FF 18KB Option bytes block Option bytes 0x1FFF F800 - 0x1FFF F80F One-time program block OTP bytes 0x1FFF_7000~0x1FFF_77FF Note: The information block stores the boot loader.
Page 49: Unlock The Fmc_Ctl Register
GD32E50x User Manual Current buffer: The current buffer is always enabled. Each time read from flash memory, 128-bit data get and store in current buffer. The CPU only need 32-bit or 16-bit in each read operation. So in the case of sequential code, the next data can get from current buffer without repeat fetch from flash memory.
Page 50: Page Erase
GD32E50x User Manual operations to the FMC_KEY, will set the LK bit to 1, and lock the FMC_CTL register, and lead to a bus error. The OBPG bit and OBER bit in the FMC_CTL are still protected even the FMC_CTL is unlocked.
Page 51: Mass Erase
GD32E50x User Manual Figure 2-1. Process of page erase operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Mass erase...
Page 52: Main Flash Programming
GD32E50x User Manual and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Since all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or using the debugging tool that accesses the FMC registers directly.
Page 53 GD32E50x User Manual  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 54: Otp Programming
GD32E50x User Manual Figure 2-3. Process of word program operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish Note: Reading the flash should be avoided when a program/erase operation is ongoing in the same bank.
Page 55: Option Bytes Modify
GD32E50x User Manual  Unlock the option bytes operation bits in the FMC_CTL register if necessary.  Wait until the OBWEN bit is set in the FMC_CTL register.  Set the OBER bit in the FMC_CTL register.  Send the option bytes erase command to the FMC by setting the START bit in the FMC_CTL register.
Page 56: Table 2-3. Option Bytes
GD32E50x User Manual Table 2-3. Option bytes Address Nam e Description option bytes security protection value 0xA5 : no security protection 0x1fff f800 any value except 0xA5 or 0xCC : protection level low 0xCC : protection level high 0x1fff f801 SPC_N SPC complement value [7:6]: BOR_TH (Brow n out reset threshold)
Page 57: Page Erase / Program Protection
GD32E50x User Manual Page erase / program protection 2.3.11. The FMC provides page erase/program protection functions to prevent inadvertent operations on the flash memory. The page erase or program will not be accepted by the FMC on protected pages. If the page erase or program command is sent to the FMC on a protected page, the WPERR bit in the FMC_STAT register will be set by the FMC.
Page 58: Register Definition
GD32E50x User Manual Protection level high: when setting SPC byte to 0xCC, protection level high performed. When this level is programmed, debug mode, boot from SRAM or boot from boot loader mode are disabled. The main flash block is accessible by all operations from user code. The SPC byte cannot be reprogrammed.
Page 59: Unlock Key Register (Fmc_Key)
GD32E50x User Manual 1: Pre-fetch enable Reserved Must be kept at reset value. WSCNT[2:0] Wait state counter register These bits is set and reset by softw are. 000: 0 w ait state added 001: 1 w ait state added 010: 2 w ait state added 011: 3 w ait state added 100: 4 w ait state added 101 ~111: reserved...
Page 60: Status Register (Fmc_Stat)
GD32E50x User Manual Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_CTL option bytes operation unlock register These bits are only be w ritten by softw are. Write OBKEY[31:0] w ith keys to unlock option bytes command in the FMC_CTL register. Status register (FMC_STAT) 2.4.4.
Page 61: Control Register (Fmc_Ctl)
GD32E50x User Manual Control register (FMC_CTL) 2.4.5. Address offset: 0x10 Reset value: 0x0000 0080 This register has to be accessed by word (32-bit) Reserved Reserved ENDIE Reserved ERRIE OBWEN Reserved START OBER OBPG Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. ENDIE End of operation interrupt enable bit This bit is set or cleared by softw are...
Page 62: Address Register (Fmc_Addr)
GD32E50x User Manual This bit is set or clear by softw are 0: no effect 1: option bytes program command Reserved Must be kept at reset value. Main flash mass erase command bit This bit is set or cleared by softw are 0: no effect 1: main flash mass erase command Main flash page erase command bit...
Page 63: Erase/Program Protection Register (Fmc_Wp)
GD32E50x User Manual Reserved DATA[15:6] DATA[5:0] USER[7:0] OBERR Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:10 DATA[15:0] Store DATA[15:0] of option bytes block after system reset. USER[7:0] Store USER of option bytes block after system reset. Option bytes security protection code 0: no protection 1: protection...
Page 64 GD32E50x User Manual PID[31:16] PID[15:0] Bits Field Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by softw are. These bits are unchanged constant after pow er on. These bits are one time program w hen the chip produced.
Page 65: Backup Registers (Bkp)
GD32E50x User Manual Backup registers (BKP) Overview 3.1. The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from Standby mode or system reset do not affect these registers.
Page 66 GD32E50x User Manual and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection configuration should be set before enable TAMPER pin.
Page 67: Register Definition
GD32E50x User Manual Register definition 3.4. BKP base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..41) 3.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). DATA [15:0] Bits Fields...
Page 68: Tamper Pin Control Register (Bkp_Tpctl)
GD32E50x User Manual 0: RTC alarm pulse is selected as the RTC output 1: RTC second pulse is selected as the RTC output This bit is reset only by a Backup domain reset. ASOEN RTC alarm or second signal output enable 0: Disable RTC alarm or second output 1: Enable RTC alarm or second output When enable, the TAMPER pin w ill output the RTC output.
Page 69: Tamper Control And Status Register (Bkp_Tpcs)
GD32E50x User Manual Tamper control and status register (BKP_TPCS) 3.4.4. Address offset: 0x34 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved TPIE Bits Fields Descriptions 15:10 Reserved Must be kept at reset value. Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred...
Page 70: Power Management Unit (Pmu)
GD32E50x User Manual Power management unit (PMU) Overview 4.1. The power consumption is regarded as one of the most important issues for the devices of GD32E50x series. According to the Power management unit (PMU), provides five types of power saving modes, including Sleep, Deep-sleep, Deep-sleep 1, Deep-sleep 2 and Standby mode.
Page 71: Backup Domain
GD32E50x User Manual Figure 4-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD BREG PB15 WKUPN NRST WKUPF FWDGT SLEEPING Cortex-M33 SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.1V Domain 1.1V Domain Domain IRC8M IRC40K 3.3V...
Page 72: Vdd / V Dda
GD32E50x User Manual time, the RTC alarm will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the Real-time clock (RTC). When the Backup domain is supplied by V pin is connected to V ), the following functions are available:...
Page 73: Figure 4-3. Waveform Of The Bor
GD32E50x User Manual Figure 4-2. Waveform of the POR / PDR 40mV hyst RSTTEMPO Power Reset (Active Low) The BOR circuit is used to detect V and generate the power reset signal which resets the whole chip except the Backup domain when the BOR_TH bits in option bytes is not 0b11 and the supply voltage is lower than the specified threshold which defined in the BOR_TH bits in option bytes.
Page 74: Figure 4-4. Waveform Of The Lvd Threshold
GD32E50x User Manual domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register(PMU_CS0), indicates if V is higher or lower than the LVD threshold.
Page 75: 1.1V Power Domain
GD32E50x User Manual 1.1V power domain 4.3.3. ® The main functions that include Cortex -M33 logic, AHB/APB peripherals, the APB interfaces for the Backup domain and the V domain, etc, are located in this power domain. Once the 1.1V is powered up, the POR will generate a reset sequence on the 1.1V power domain. If need to enter the expected power saving mode, the associated control bits must be configured.
Page 76 GD32E50x User Manual ® According to the SLEEPONEXIT bit in the Cortex -M33 System Control Register, there are two options to select the Sleep mode entry mechanism.  Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.
Page 77 GD32E50x User Manual If not, the program will skip the entry process of Deep-sleep mode to continue to execute the following procedure. Deep-sleep 1 mode ® The Deep-sleep 1 mode is based on the SLEEPDEEP mode of the Cortex -M33. In Deep- sleep 1 mode, all clocks in the 1.1V domain are off, and all of IRC8M, IRC48M, HXTAL and PLLs are disabled.
Page 78: Table 4-1. Power Saving Mode Summary
GD32E50x User Manual system, refer to Cortex -M33 Technical Reference Manual). Waking up from Deep-sleep 2 ® mode needs an additional delay to power on COREOFF0/COREOFF1 domain. Notice that an additional wakeup delay will be incurred if the LDO operates in low power mode. The low-driver mode in Deep-sleep 2 mode can be entered by configuring the LDEN, LDNP , LDLP, LDOLP bits in the PMU_CTL0 register.
Page 79 GD32E50x User Manual Mode Sleep Deep-sleep Deep-sleep 1 Deep-sleep 2 Standby Entry WFI or WFE WFI or WFE WFI or WFE WFI or WFE WFI or WFE NRST Any interrupt for Any interrupt from EXTI Any interrupt from EXTI Any interrupt from lines for WFI lines for WFI EXTI lines for WFI...
Page 80: Register Definition
GD32E50x User Manual Register definition 4.4. PMU base address: 0x4000 7000 Control register 0 (PMU_CTL0) 4.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). LDEN[1:0] Reserved HDEN Reserved LDNP...
Page 81 GD32E50x User Manual 1: Low -driver mode enabled w hen LDEN is 11 and use normal pow er LDO LDLP Low -driver mode w hen use low pow er LDO. 0: normal driver w hen use low pow er LDO 1: Low -driver mode enabled w hen LDEN is 11 and use low pow er LDO Reserved Must be kept at reset value.
Page 82: Control And Status Register 0 (Pmu_Cs0)
GD32E50x User Manual Note: Some peripherals may w ork w ith the IRC8M clock in the Deep-sleep / Deep- sleep 1 / Deep-sleep 2 mode. In this case, the LDO automatically sw itches from the low pow er mode to the normal mode and remains in this mode until the peripheral stop w orking.
Page 83 GD32E50x User Manual Reserved Must be kept at reset value. WUPEN5 WKUP Pin5(PB5) Enable 0: Disable WKUP pin5 function 1: Enable WKUP pin5 function If WUPEN5 is set before entering the pow er saving mode, a rising edge on the WKUP pin5 w akes up the system from the pow er saving mode.
Page 84: Control Register 1 (Pmu_Ctl1)
GD32E50x User Manual And set this bit w ill trigger a w akup event w hen the input is aready high. WUPEN6 WKUP Pin6(PB15) Enable 0: Disable WKUP pin6 function 1: Enable WKUP pin6 function If WUPEN6 is set before entering the pow er saving mode, a rising edge on the WKUP pin6 w akes up the system from the pow er saving mode.
Page 85: Control And Status Register 1 (Pmu_Cs1)
GD32E50x User Manual DPMOD2 Deep-sleep 2 mode enable 0: Not care SLEEPDEEP bit is set and the STBMOD bit 1:Go to Deep-sleep 2 mode w hen is clear DPMOD1 Deep-sleep 1 mode enable 0: Not care the SLEEPDEEP bit is set and the STBMOD 1:Go to Deep-sleep 1 mode w hen bit is clear and the DPMOD2 bit is clear Control and status register 1 (PMU_CS1)
Page 86: Reset And Clock Unit (Rcu)
GD32E50x User Manual Reset and clock unit (RCU) High density reset and clock control unit (RCU) Reset control unit (RCTL) 5.1. Overview 5.1.1. GD32E50x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 87: Clock Control Unit (Cctl)
GD32E50x User Manual A system reset resets the processor core and peripheral IP components except for the SW- DP controller and the backup domain. A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset).
Page 88: Figure 5-2. Clock Tree
GD32E50x User Manual Figure 5-2. Clock tree CK48MSEL USBD Presacaler CK_USBD /1,1.5,2,2.5 3,3.5,4 (to USBD) (to FMC) CK_IRC48M CK_CTC CK_FMC CK_PLLSRC 48 MHz IRC48M SCS[1:0] CK_I2S (to I2S1,2) I2S enable CK_IRC8M CK_AHB 8 MHz ×2,3,4 CK_EXMC CK_SYS CK_PLL IRC8M Prescaler 180 MHz max EXMC enable (to EXMC)
Page 89: Characteristics
GD32E50x User Manual The SDIO, EXMC are clocked by the clock of CK_AHB. The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1).
Page 90: Figure 5-3. Hxtal Clock Source
GD32E50x User Manual Figure 5-3. HXTAL clock source The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL. The HXTALSTB flag in control register RCU_CTL indicates if the high- speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released for use until this HXTALSTB bit is set by the hardware.
Page 91 GD32E50x User Manual The frequency accuracy of the IRC8M can be calibrated by the manufacturer, but its operating frequency is still less accurate than HXTAL. The application requirements, environment and cost will determine which oscillator type is selected. If the HXTAL or PLL is the system clock source, to minimize the time required for the system to recover from the Deep-sleep Mode, the hardware forces the IRC8M clock to be the system clock when the system initially wakes-up.
Page 92 GD32E50x User Manual drives the OSC32IN pin. Internal 40K RC oscillator (IRC40K) The internal RC oscillator has a frequency of about 40 kHz and is a low power clock source for the real time clock circuit or the rree watchdog timer. The IRC40K offers a low cost clock source as no external components are required.
Page 93: Table 5-1. Clock Output 0 Source Select
GD32E50x User Manual Table 5-1. Clock output 0 source select Clock source 0 selection bits Clock source NO CLK CK_SYS CK_IRC8M CK_HXTAL CK_PLL/2 Voltage control The 1.1V domain voltage in Deep-sleep mode can be controlled by DSLPVS[2:0] bit in the Deep-sleep mode voltage register (RCU_DSV).
Page 94: Register Definition
GD32E50x User Manual Register definition 5.3. RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLLSTB Reserved CKMEN...
Page 95: Clock Configuration Register 0 (Rcu_Cfg0)
GD32E50x User Manual HXTALBPS High speed crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be w ritten only if the HXTALEN is 0. 0: Disable the HXTAL Bypass mode 1: Enable the HXTAL Bypass mode in w hich the HXTAL output clock is equal to the input clock.
Page 96 GD32E50x User Manual USBDPS ADCPSC[ PLLMF[5] Reserved PLLMF[4] CKOUT0SEL[2:0] USBDPSC[1:0] PLLMF[3:0] PREDV0 PLLSEL C[2] ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions USBDPSC[2] Bit 2 of USBDPSC see bits 23:22 of RCU_CFG0 PLLMF[5] Bit 5 of PLLMF see bits 21:18 of RCU_CFG0 Reserved Must be kept at reset value.
Page 97 GD32E50x User Manual 000010: CK_SYS = CK_PLL x 4 000011: CK_SYS = CK_PLL x 5 000100: CK_SYS = CK_PLL x 6 000101: CK_SYS = CK_PLL x 7 000110: CK_SYS = CK_PLL x 8 000111: CK_SYS = CK_PLL x 9 001000: CK_SYS = CK_PLL x 10 001001: CK_SYS = CK_PLL x 11 001010: CK_SYS = CK_PLL x 12 001011: CK_SYS = CK_PLL x 13...
Page 98 GD32E50x User Manual clock of PLL 15:14 ADCPSC[1:0] ADC clock prescaler selection These bits, bit 28 of RCU_CFG0 and bit 29 of RCU_CFG1 are w ritten by softw are to define the ADC prescaler factor.Set and cleared by softw are. 0000: (CK_APB2 / 2) selected 0001: (CK_APB2 / 4) selected 0010: (CK_APB2 / 6) selected...
Page 99: Clock Interrupt Register (Rcu_Int)
GD32E50x User Manual SCSS[1:0] System clock sw itch status Set and reset by hardw are to indicate the clock source of system clock. 00: Select CK_IRC8M as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_PLL as the CK_SYS source 11: Reserved SCS[1:0] System clock sw itch...
Page 100 GD32E50x User Manual 1: Reset PLLSTBIF flag HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by softw are to reset the HXTALSTBIF flag. 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC IRC8M stabilization interrupt clear Write 1 by softw are to reset the IRC8MSTBIF flag. 0: Not reset IRC8MSTBIF flag 1: Reset IRC8MSTBIF flag LXTALSTBIC...
Page 101: Apb2 Reset Register (Rcu_Apb2Rst)
GD32E50x User Manual CKMIF HXTAL clock stuck interrupt flag Set by hardw are w hen the HXTAL clock is stuck. Reset w hen setting the CKMIC bit by softw are. 0: Clock operating normally 1: HXTAL clock stuck Reserved Must be kept at reset value. PLLSTBIF PLL stabilization interrupt flag Set by hardw are w hen the PLL is stable and the PLLSTBIE bit is set.
Page 102 GD32E50x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SHRTIME USART5 TIMER10 TIMER9 TIMER8 Reserved Reserved Reserved ADC2RS USART0 TIMER7R TIMER0R ADC1RS ADC0RS SPI0RST PGRST PFRST PERST PDRST PCRST PBRST PARST Reserved AFRST Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 103 GD32E50x User Manual 0: No reset 1: Reset the USART0 TIMER7RST Timer 7 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER7 SPI0RST SPI0 reset This bit is set and reset by softw are. 0: No reset 1: Reset the SPI0 TIMER0RST...
Page 104: Apb1 Reset Register (Rcu_Apb1Rst)
GD32E50x User Manual This bit is set and reset by softw are. 0: No reset 1: Reset the GPIO port C PBRST GPIO port B reset This bit is set and reset by softw are. 0: No reset 1: Reset the GPIO port B PARST GPIO port A reset This bit is set and reset by softw are.
Page 105 GD32E50x User Manual 1: Reset pow er control unit BKPIRST Backup interface reset This bit is set and reset by softw are. 0: No reset 1: Reset backup interface CAN1RST CAN1 reset This bit is set and reset by softw are. 0: No reset 1: Reset the CAN1 CAN0RST...
Page 106 GD32E50x User Manual 0: No reset 1: Reset the USART2 USART1RST USART1 reset This bit is set and reset by softw are. 0: No reset 1: Reset the USART1 Reserved Must be kept at reset value. SPI2RST SPI2 reset This bit is set and reset by softw are. 0: No reset 1: Reset the SPI2 SPI1RST...
Page 107: Ahb Enable Register (Rcu_Ahben)
GD32E50x User Manual This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER5 TIMER4RST TIMER4 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER4 TIMER3RST TIMER3 reset This bit is set and reset by softw are.
Page 108: Apb2 Enable Register (Rcu_Apb2En)
GD32E50x User Manual This bit is set and reset by softw are. 0: Disabled SDIO clock 1: Enabled SDIO clock Reserved Must be kept at reset value. EXMCEN EXMC clock enable This bit is set and reset by softw are. 0: Disabled EXMC clock 1: Enabled EXMC clock Reserved...
Page 109 GD32E50x User Manual SHRTIME USART5 TIMER10 TIMER9E TIMER8E Reserved Reserved Reserved USART0 TIMER7E TIMER0E ADC2EN SPI0EN ADC1EN ADC0EN PGEN PFEN PEEN PDEN PCEN PBEN PAEN Reserved AFEN Bits Fields Descriptions 31:30 Reserved Must be kept at reset value SHRTIMEREN SHRTIMER clock enable This bit is set and reset by softw are.
Page 110 GD32E50x User Manual 0: Disabled USART0 clock 1: Enabled USART0 clock TIMER7EN TIMER7 clock enable This bit is set and reset by softw are. 0: Disabled TIMER7 clock 1: Enabled TIMER7 clock SPI0EN SPI0 clock enable This bit is set and reset by softw are. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER0EN...
Page 111: Apb1 Enable Register (Rcu_Apb1En)
GD32E50x User Manual This bit is set and reset by softw are. 0: Disabled GPIO port C clock 1: Enabled GPIO port C clock PBEN GPIO port B clock enable This bit is set and reset by softw are. 0: Disabled GPIO port B clock 1: Enabled GPIO port B clock PAEN GPIO port A clock enable...
Page 112 GD32E50x User Manual 1: Enabled PMU clock BKPIEN Backup interface clock enable This bit is set and reset by softw are. 0: Disabled backup interface clock 1: Enabled backup interface clock CAN1EN clock enable This bit is set and reset by softw are. 0: Disabled CAN clock 1: Enabled CAN1 clock...
Page 113 GD32E50x User Manual 0: Disabled USART2 clock 1: Enabled USART2 clock USART1EN USART1 clock enable This bit is set and reset by softw are. 0: Disabled USART1 clock 1: Enabled USART1 clock Reserved Must be kept at reset value. SPI2EN SPI2 clock enable This bit is set and reset by softw are.
Page 114: Backup Domain Control Register (Rcu_Bdctl)
GD32E50x User Manual This bit is set and reset by softw are. 0: Disabled TIMER5 clock 1: Enabled TIMER5 clock TIMER4EN TIMER4 clock enable This bit is set and reset by softw are. 0: Disabled TIMER4 clock 1: Enabled TIMER4 clock TIMER3EN TIMER3 clock enable This bit is set and reset by softw are.
Page 115: Reset Source/Clock Register (Rcu_Rstsck)
GD32E50x User Manual 0: No reset 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by softw are. 0: Disabled RTC clock 1: Enabled RTC clock 14:10 Reserved Must be kept at reset value. RTCSRC[1:0] RTC clock entry selection Set and reset by softw are to control the RTC clock source.
Page 116 GD32E50x User Manual reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). WWDGT FWDGT BORRSTF RSTFC Reserved RSTF RSTF RSTF RSTF RSTF RSTF IRC40K Reserved IRC40KEN Bits Fields Descriptions LPRSTF Low -pow er reset flag Set by hardw are w hen Deep-sleep /standby reset generated.
Page 117: Ahb Reset Register (Rcu_Ahbrst)
GD32E50x User Manual 0: No external pin reset generated 1: External pin reset generated BORRSTF BOR reset flag Set by hardw are w hen a BOR reset generated. Reset by w riting 1 to the RSTFC bit. 0: No BOR reset generated 1: BOR reset generated RSTFC Reset flag clear...
Page 118: Clock Configuration Register 1 (Rcu_Cfg1)
GD32E50x User Manual Clock configuration register 1 (RCU_CFG1) 5.3.12. Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLLPRES ADCPSC[ Reserved Reserved Reserved Bits Fields Descriptions Reserved Must be kept at reset value. PLLPRESEL PLL clock source preselection 0: HXTAL selected as PLL source clock...
Page 119: Additional Clock Control Register (Rcu_Addctl)
GD32E50x User Manual 010: The core voltage is 0.8V in Deep-sleep mode 011: The core voltage is 0.7V in Deep-sleep mode 1xx: Reserved Additional clock control register (RCU_ADDCTL) 5.3.14. Address offset: 0xC0 Reset value: 0x8000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC48MS IRC48ME IRC48MCALIB[7:0]...
Page 120: Additional Clock Interrupt Register (Rcu_Addint)
GD32E50x User Manual Additional clock interrupt register (RCU_ADDINT) 5.3.15. Address offset: 0xCC Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC48MS Reserved Reserved TBIC IRC48MS IRC48MS Reserved Reserved Reserved TBIE TBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value.
Page 121: Clock Configuration Register 2 (Rcu_Cfg2)
GD32E50x User Manual The spread spectrum modulation is available only for the main PLL clock The RCU_PLLSSCTL register must be written when the main PLL is disabled This register is used to configure the PLL spread spectrum clock generation according to the following formulas: MODCNT = round(f /4/f...
Page 122: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32E50x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. I2C2SEL[1:0] I2C2 Clock Source Selection Set and reset by softw are to control the I2C2 clock source. 00: APB1 clock selected as I2C2 source clock 01: System clock selected as I2C2 source clock 1x: CK_IRC8M clock selected as I2C2 source clock Reserved Must be kept at reset value.
Page 123 GD32E50x User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved Reserved Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. CTCEN CTC clock enable This bit is set and reset by softw are. 0: Disabled CTC clock 1: Enabled CTC clock 26:0...
Page 124: Connectivity Line Devices: Reset And Clock Control Unit (Rcu)
GD32E50x User Manual Connectivity line devices: reset and clock control unit (RCU) Reset control unit (RCTL) 5.4. Overview 5.4.1. GD32E50x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 125: Clock Control Unit (Cctl)
GD32E50x User Manual source (external or internal reset). Figure 5-5. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have previously been powered off).
Page 126: Figure 5-6. Clock Tree
GD32E50x User Manual Figure 5-6. Clock tree CK_PLLUSB USBHS PHY clock 24Mhz to 60Mhz (to USBHS in high-speed mode) CK48MSEL[1:0] PLLUSBPR ESEL PLLUSBMF USBHSDV PLLUSBPREDV 48 0M H z CK_PLL2 PHSEL CK_IRC48M × 16 , 17 m ax / 1, 2, 3 / 2, 4 48 MHz/ 12 7...
Page 127: Characteristics
GD32E50x User Manual The I2C2 is clocked by IRC8M clock or system clock or APB1 clock, which selected by I2C2SEL bits in configuration register 2 (RCU_CFG2). The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1).
Page 128: Function Overview
GD32E50x User Manual Function overview 5.5.3. High speed crystal oscillator (HXTAL) The high speed external crystal oscillator (HXTAL), which has a frequency from 4 to 32 MHz, produces a highly accurate clock source for use as the system clock. A crystal with a specific frequency must be connected and located close to the two HXTAL pins.
Page 129 GD32E50x User Manual Internal 8M RC oscillators (IRC8M) The internal 8M RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up. The IRC8M oscillator provides a lower cost type clock source as no external components are required.
Page 130 GD32E50x User Manual can be generated if the related interrupt enable bit, PLL1STBIE, in the RCU_INT Register, is set as the PLL1 becomes stable. The PLL2 can be switched on or off by using the PLL2EN bit in the RCU_CTL register. The PLL2STB flag in the RCU_CTL register will indicate if the PLL2 clock is stable.
Page 131: Table 5-3. Clock Output 0 Source Select
GD32E50x User Manual register 0, RCU_CFG0. When the SCS value is changed, the CK_SYS will continue to operate using the original clock source until the target clock source is stable. When a clock source is directly or indirectly (by PLL) used as the CK_SYS, it is not possible to stop it. HXTAL clock monitor (CKM) The HXTAL clock monitor function is enabled by the HXTAL clock monitor rnable bit, CKMEN, in the control register (RCU_CTL).
Page 132: Table 5-4. 1.1V Domain Voltage Selected In Deep-Sleep Mode
GD32E50x User Manual Table 5-4. 1.1V domain voltage selected in deep-sleep mode DSLPVS[2:0] Deep-sleep m ode voltage(V)
Page 133: Register Definition
GD32E50x User Manual Register definition 5.6. RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.6.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB Reserved...
Page 134 GD32E50x User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by softw are. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardw are w hen entering Deep-sleep or Standby mode. 0: PLL is sw itched off 1: PLL is sw itched on 23:20...
Page 135: Clock Configuration Register 0 (Rcu_Cfg0)
GD32E50x User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M internal 8MHz RC oscillator stabilization flag Set by hardw are to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable...
Page 136 GD32E50x User Manual 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 1100: CK_IRC48M clock selected 1101: (CK_IRC48M / 8) clock selected 1110: (CK_PLLUSB / 32) clock selected 23:22 USBHSPSC[1:0] USBHS clock prescaler selection...
Page 137 GD32E50x User Manual 010111: (PLL source clock x 24) 011000: (PLL source clock x 25) 011001: (PLL source clock x 26) 011010: (PLL source clock x 27) 011011: (PLL source clock x 28) 011100: (PLL source clock x 29) 011101: (PLL source clock x 30) 011110: (PLL source clock x 31) 011111: (PLL source clock x 32) 100000: (PLL source clock x 33)
Page 138: Clock Interrupt Register (Rcu_Int)
GD32E50x User Manual 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0] APB1 prescaler selection Set and reset by softw are to control the APB1 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected...
Page 139 GD32E50x User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIC STBIC STBIC STBIC STBIC STBIC STBIC STBIC PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K PLL2 PLL1 HXTAL IRC8M LXTAL...
Page 140 GD32E50x User Manual 0: Not reset LXTALSTBIF flag 1: Reset LXTALSTBIF flag IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by softw are to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag Reserved Must be kept at reset value. PLL2STBIE PLL2 stabilization interrupt enable Set and reset by softw are to enable/disable the PLL2 stabilization interrupt.
Page 141 GD32E50x User Manual 1: HXTAL clock stuck PLL2STBIF PLL2 stabilization interrupt flag Set by hardw are w hen the PLL2 is stable and the PLL2STBIE bit is set. Reset w hen setting the PLL2STBIC bit by softw are. 0: No PLL2 stabilization interrupt generated 1: PLL2 stabilization interrupt generated PLL1STBIF PLL1 stabilization interrupt flag...
Page 142: Apb2 Reset Register (Rcu_Apb2Rst)
GD32E50x User Manual APB2 reset register (RCU_APB2RST) 5.6.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SHRTIME USART5 TIMER10 TIMER9 TIMER8 CMPRST Reserved Reserved Reserved RRST ADC2RS USART0 TIMER7R TIMER0R ADC1RS ADC0RS SPI0RST PGRST...
Page 143 GD32E50x User Manual 0: No reset 1: Reset the TIMER8 18:16 Reserved Must be kept at reset value. ADC2RST ADC2 reset This bit is set and reset by softw are. 0: No reset 1: Reset the ADC2 USART0RST USART0 Reset This bit is set and reset by softw are.
Page 144: Apb1 Reset Register (Rcu_Apb1Rst)
GD32E50x User Manual 1: Reset the GPIO port F PERST GPIO port E reset This bit is set and reset by softw are. 0: No reset 1: Reset the GPIO port E PDRST GPIO port D reset This bit is set and reset by softw are. 0: No reset 1: Reset the GPIO port D PCRST...
Page 145 GD32E50x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DACRST DAC reset This bit is set and reset by softw are. 0: No reset 1: Reset DAC unit PMURST Pow er control reset This bit is set and reset by softw are. 0: No reset 1: Reset pow er control unit BKPIRST...
Page 146 GD32E50x User Manual 0: No reset 1: Reset the UART4 UART3RST UART3 reset This bit is set and reset by softw are. 0: No reset 1: Reset the UART3 USART2RST USART2 reset This bit is set and reset by softw are. 0: No reset 1: Reset the USART2 USART1RST...
Page 147: Ahb Enable Register (Rcu_Ahben)
GD32E50x User Manual This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER11 TIMER6RST TIMER6 reset This bit is set and reset by softw are. 0: No reset 1: Reset the TIMER6 TIMER5RST TIMER5 reset This bit is set and reset by softw are.
Page 148 GD32E50x User Manual Bits Fields Descriptions SQPIEN SQPI clock enable This bit is set and reset by softw are. 0: Disabled SQPI clock 1: Enabled SQPI clock TMUEN TMUEN clock enable This bit is set and reset by softw are. 0: Disabled TMUEN clock 1: Enabled TMUEN clock 29:17...
Page 149: Apb2 Enable Register (Rcu_Apb2En)
GD32E50x User Manual CRCEN CRC clock enable This bit is set and reset by softw are. 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value. FMCSPEN FMC clock enable w hen sleep mode This bit is set and reset by softw are to enable/disable FMC clock during Sleep mode. 0: Disabled FMC clock during Sleep mode 1: Enabled FMC clock during Sleep mode Reserved...
Page 150 GD32E50x User Manual This bit is set and reset by softw are. 0: Disabled CMP clock 1: Enabled CMP clock Reserved Must be kept at reset value SHRTIMEREN SHRTIMER clock enable This bit is set and reset by softw are. 0: Disabled SHRTIMER clock 1: Enabled SHRTIMER clock USART5EN...
Page 151 GD32E50x User Manual SPI0EN SPI0 clock enable This bit is set and reset by softw are. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER0EN TIMER0 clock enable This bit is set and reset by softw are. 0: Disabled TIMER0 clock 1: Enabled TIMER0 clock ADC1EN ADC1 clock enable...
Page 152: Apb1 Enable Register (Rcu_Apb1En)
GD32E50x User Manual 1: Enabled GPIO port B clock PAEN GPIO port A clock enable This bit is set and reset by softw are. 0: Disabled GPIO port A clock 1: Enabled GPIO port A clock Reserved Must be kept at reset value. AFEN Alternate function IO clock enable This bit is set and reset by softw are.
Page 153 GD32E50x User Manual CAN1EN CAN1 clock enable This bit is set and reset by softw are. 0: Disabled CAN1 clock 1: Enabled CAN1 clock CAN0EN CAN0 clock enable This bit is set and reset by softw are. 0: Disabled CAN0 clock 1: Enabled CAN0 clock I2C2EN I2C2 clock enable...
Page 154 GD32E50x User Manual SPI2EN SPI2 clock enable This bit is set and reset by softw are. 0: Disabled SPI2 clock 1: Enabled SPI2 clock SPI1EN SPI1 clock enable This bit is set and reset by softw are. 0: Disabled SPI1 clock 1: Enabled SPI1 clock 13:12 Reserved...
Page 155: Backup Domain Control Register (Rcu_Bdctl)
GD32E50x User Manual TIMER3EN TIMER3 clock enable This bit is set and reset by softw are. 0: Disabled TIMER3 clock 1: Enabled TIMER3 clock TIMER2EN TIMER2 clock enable This bit is set and reset by softw are. 0: Disabled TIMER2 clock 1: Enabled TIMER2 clock TIMER1EN TIMER1 clock enable...
Page 156: Reset Source/Clock Register (Rcu_Rstsck)
GD32E50x User Manual 14:10 Reserved Must be kept at reset value. RTCSRC[1:0] RTC clock entry selection Set and reset by softw are to control the RTC clock source. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset.
Page 157 GD32E50x User Manual IRC40K IRC40KE Reserved Bits Fields Descriptions LPRSTF Low -pow er reset flag Set by hardw are w hen Deep-sleep /standby reset generated. Reset by w riting 1 to the RSTFC bit. 0: No Low -pow er management reset generated 1: Low -pow er management reset generated WWDGTRSTF Window w atchdog timer reset flag...
Page 158: Ahb Reset Register (Rcu_Ahbrst)
GD32E50x User Manual 1: BOR reset generated RSTFC Reset flag clear This bit is set by softw are to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags 23:2 Reserved Must be kept at reset value. IRC40KSTB IRC40K stabilization flag Set by hardw are to indicate if the IRC40K output clock is stable and ready for use.
Page 159: Clock Configuration Register 1 (Rcu_Cfg1)
GD32E50x User Manual This bit is set and reset by softw are. 0: No reset 1: Reset the ENET Reserved Must be kept at reset value. USBHSRST USBHS reset This bit is set and reset by softw are. 0: No reset 1: Reset the USBHS 11:0 Reserved...
Page 160 GD32E50x User Manual I2S2SEL I2S2 clock source selection Set and reset by softw are to control the I2S2 clock source. 0: System clock selected as I2S2 source clock 1: (CK_PLL2 x 2) selected as I2S2 source clock I2S1SEL I2S1 clock source selection Set and reset by softw are to control the I2S1 clock source.
Page 161 GD32E50x User Manual 111111: (PLL2 source clock x 80) 11:8 PLL1MF[3:0] The PLL1 clock multiplication factor Set and reset by softw are. 00xx: Reserve 010x: Reserve 0110: (PLL1 source clock x 8) 0111: (PLL1 source clock x 9) 1000 :(PLL1 source clock x 10) 1001: (PLL1 source clock x 11) 1010: (PLL1 source clock x 12) 1011: (PLL1 source clock x 13)
Page 162: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32E50x User Manual 0100: PREDV0 input source clock divided by 5 0101: PREDV0 input source clock divided by 6 0110: PREDV0 input source clock divided by 7 0111: PREDV0 input source clock divided by 8 1000: PREDV0 input source clock divided by 9 1001: PREDV0 input source clock divided by 10 1010: PREDV0 input source clock divided by 11 1011: PREDV0 input source clock divided by 12...
Page 163 GD32E50x User Manual IRC48MS IRC48ME IRC48MCALIB[7:0] Reserved PLLUSBS PLLUSBE USBSWE USBHSS Reserved USBHSDV[2:0] CK48MSEL[1:0] Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register These bits are load automatically at pow er on. 23:18 Reserved Must be kept at reset value. IRC48MSTB Internal 48MHz RC oscillator clock stabilization flag Set by hardw are to indicate if the IRC48M oscillator is stable and ready for use.
Page 164: Additional Clock Configuration Register (Rcu_Addcfg)
GD32E50x User Manual USBHSSEL USBHS clock source selection Set and reset by softw are to control the USBHS clock source. 0: 48M clock selected as USBHS source clock 1: 60M clock selected as USBHS source clock CK48MSEL[1:0] USB 48M clock source selection 00: not effect (select PLL/USBPRE) 01: CK_IRC48M select as CK48M clock source 10: CK_PLLUSB/USBHSDV select as CK48M clock source...
Page 165: Additional Clock Interrupt Register (Rcu_Addint)
GD32E50x User Manual 0: CK_ HXTAL selected as PLLUSB source clock 1: CK_IRC48M output clock selected as PLLUSB source clock 15:4 Reserved Must be kept at reset value. PLLUSBPREDV[3:0] PLLUSBPREDV division factor This bit is set and reset by softw are. 0000: Reserved 0001: PLLUSBPREDV input source clock divided by 1 0010: PLLUSBPREDV input source clock divided by 2...
Page 166: Pll Clock Spread Spectrum Control Register (Rcu_Pllssctl)
GD32E50x User Manual 1: Reset PLLUSBSTBIF flag IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization interrupt clear Write 1 by softw are to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag 1: Reset IRC48MSTBIF flag 21:16 Reserved Must be kept at reset value. PLLUSBSTBIE PLLUSB stabilization interrupt enable Set and reset by softw are to enable/disable the PLLUSB stabilization interrupt...
Page 167: Clock Configuration Register 2 (Rcu_Cfg2)
GD32E50x User Manual Where f represents the PLL input clock frequency, f represents the spread spectrum PLLIN modulation frequency, mdamp represents the spread spectrum modulation amplitude expressed as a percentage, PLLN represents the PLL clock frequency multiplication factor. SSCGO SS_TYP MODSTEP[14:3] Reserved MODSTEP[2:0]...
Page 168: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32E50x User Manual 00: APB1 clock selected as I2C2 source clock 01: System clock selected as I2C2 source clock 1x: CK_IRC8M clock selected as I2C2 source clock Reserved Must be kept at reset value. USART5SEL[1:0] USART5 clock source selection Set and reset by softw are to control the USART5 clock source. 00: CK_APB2 selected as USART5 source clock 01: CK_SYS selected as USART5 source clock 10: CK_LXTAL selected as USART5 source clock...
Page 169 GD32E50x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). CAN2EN Reserved Reserved Reserved Bits Fields Descriptions CAN2EN CAN2 enable This bit is set and reset by softw are. 0: Disabled CAN clock 1: Enabled CAN clock 30:28 Reserved Must be kept at reset value.
Page 170: Clock Trim Controller (Ctc)
GD32E50x User Manual Clock trim controller (CTC) Overview 6.1. The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the frequency of the IRC48M based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 171: Ref Sync Pulse Generator
GD32E50x User Manual Figure 6-1. CTC overview PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 6.3.1.
Page 172: Frequency Evaluation And Automatically Trim Process
GD32E50x User Manual and then up- counting to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 173: Software Program Guide
GD32E50x User Manual If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 174 GD32E50x User Manual The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 175: Register Definition
GD32E50x User Manual Register definition 6.4. CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 176: Control Register 1 (Ctc_Ctl1)
GD32E50x User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim w arning (CKWARNIF) interrupt enable...
Page 177: Status Register (Ctc_Stat)
GD32E50x User Manual 01: LXTAL clock selected 10: Reserved. 11: Reserved Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by softw are 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8 100: Reference signal divided by 16...
Page 178 GD32E50x User Manual REFDIR CTC trim counter direction w hen reference sync pulse When a reference sync pulse occurred during the counter is w orking, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Dow n-counting 14:11 Reserved Must be kept at reset value.
Page 179: Interrupt Clear Register (Ctc_Intc)
GD32E50x User Manual 0 : No Error occur 1: An error occur CKWARNIF Clock trim w arning interrupt flag This bit is set by hardw are w hen a clock trim w arning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM w hen a reference sync pulse detected, this bit w ill be set.
Page 180 GD32E50x User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is w ritten by softw are and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect. CKOKIC CKOKIF interrupt clear bit This bit is w ritten by softw are and read as 0.
Page 181: Interrupt/Event Controller (Exti)
GD32E50x User Manual Interrupt/event controller (EXTI) Overview 7.1. ® Cortex -M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. You can read the -M33 for more details about NVIC.
Page 182: Table 7-1. Nvic Exception Types In Cortex ® -M33
GD32E50x User Manual ® Table 7-1. NVIC exception types in Cortex -M33 Vector Exception type priority (a) Vector address Description num ber 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault...
Page 183 GD32E50x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector address num ber num ber interrupt description interrupt description interrupt interrupt DMA0 channel4 global DMA0 channel4 global IRQ 15 0x0000_007C interrupt interrupt DMA0 channel5 global DMA0 channel5 global IRQ 16 0x0000_0080 interrupt interrupt...
Page 184 GD32E50x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector address num ber num ber interrupt description interrupt description USBD w akeup from EXTI USBHS w akeup from EXTI IRQ 42 0x0000_00E8 interrupt interrupt TIMER7 break interrupt and TIMER7 break interrupt and IRQ 43 0x0000_00EC TIMER11 global interrupt...
Page 185 GD32E50x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector address num ber num ber interrupt description interrupt description IRQ69 SHRTIMER_IRQ2 interrupt SHRTIMER_IRQ2 interrupt 0x0000_0154 IRQ70 SHRTIMER_IRQ3 interrupt SHRTIMER_IRQ3 interrupt 0x0000_0158 IRQ71 SHRTIMER_IRQ4 interrupt SHRTIMER_IRQ4 interrupt 0x0000_015C IRQ72 SHRTIMER_IRQ5 interrupt SHRTIMER_IRQ5 interrupt 0x0000_0160 IRQ73...
Page 186: External Interrupt And Event (Exti) Block Diagram
GD32E50x User Manual External interrupt and event (EXTI) block diagram 7.4. Figure 7-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~21 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External Interrupt and event function overview 7.5.
Page 187 GD32E50x User Manual Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in AFIO module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 188 GD32E50x User Manual EXTI Line Source Num ber RTC Alarm USB Wakeup Ethernet Wakeup I2C2 Wakeup USART5 Wakeup...
Page 189: Exti Register
GD32E50x User Manual EXTI Register 7.6. EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7 INTEN6...
Page 190: Rising Edge Trigger Enable Register (Exti_Rten)
GD32E50x User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5...
Page 191: Pending Register (Exti_Pd)
GD32E50x User Manual Reserved SWIEV21 SWIEV20 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21: 0 SWIEVx Interrupt / Event softw are trigger x (x = 0…21) 0: Deactivate the EXTIx softw are interrupt / event request 1: Activate the EXTIx softw are interrupt / event request...
Page 192: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32E50x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 8.1. There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions.
Page 193: Gpio Pin Configuration
GD32E50x User Manual Table 8-1. GPIO configuration table Configuration m ode CTL[1:0] SPDy: MD[1:0] OCTL don’t care Analog don’t care Input floating Input x 00 Input pull-dow n Input pull-up x 00: Reserved Push-pull 0 or 1 General purpose x 01: Speed up to 10MHz Output (GPIO) Open-drain 0 or 1...
Page 194: External Interrupt/Event Lines
GD32E50x User Manual Floating PB3: JTDO in mode. The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen.
Page 195: Output Configuration
GD32E50x User Manual Output configuration 8.3.5. When GPIO pin is configured as output:  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors are disabled.  The output buffer is enabled.  Open Drain Mode: The pad output low level when a “0” in the output control register; while the pad leaves Hi-Z when a “1”...
Page 196: Alternate Function (Af) Configuration
GD32E50x User Manual Alternate function (AF) configuration 8.3.7. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software. When be configured as alternate function:  The output buffer is enabled in Open-Drain or Push-Pull configuration. ...
Page 197: Gpio Locking Function
GD32E50x User Manual 0b10, or 0b11 and configuring CTLy bits of corresponding port in GPIOx_CTL0/GPIOx_CTL1 register to 0b10 (for AF push-pull output) or 0b11 (for AF open-drain output). Some alternate function need to configure, the configuration registers are AFIO_PCFA- AFIO_PCFE, and AFIO_PCFG. GPIO locking function 8.3.9.
Page 198: Jtag/Swd Alternate Function Remapping
GD32E50x User Manual JTAG/SWD alternate function remapping 8.4.3. The debug interface signals are mapped on the GPIO ports as shown in table below. Table 8-2. Debug interface signals Pin Nam e Function description PA13 JTMS / SWDIO PA14 JTCK / SWCLK PA15 JTDI JTDO / TRACESWO...
Page 199: Timer Af Remapping
GD32E50x User Manual Register ADC0 ADC1 routine conversion is connected to TIMER7_TRGO ADC1 external signal trigger ADC1_ETRGRT_REMA P routine conversion is connected to EXTI11 ADC1_ETRGRT_REMA P ADC1 external signal trigger routine conversion is connected to TIMER7_TRGO Remap available only for High-density devices TIMER AF remapping 1.1.1.
Page 200: Usart Af Remapping
GD32E50x User Manual TIMERx_REMAP [1:0](x = 0，1，2) TIMERx_REMAP(x = 8，9，10，12， Alternate function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full rem ap) rem ap) rem ap) rem ap) TIMER2_CH3 TIMER3_CH0 PD12 TIMER3_CH1 PD13 TIMER3_CH2 PD14 TIMER3_CH3 PD15 TIMER8_CH0 TIMER8_CH1 TIMER9_CH0 TIMER10_CH0 TIMER12_CH0 TIMER13_CH0...
Page 201: I2C0 Af Remapping
GD32E50x User Manual PB7(USART0_RX) PA0(USART1_CTS) PA1(USART1_RTS) USART1_REMA P = 0 PA2(USART1_TX) PA3(USART1_RX) PA4(USART1_CK) PD3(USART1_CTS) PD4(USART1_RTS) USART1_REMA P = 1 PD5(USART1_TX) PD6(USART1_RX) PD7(USART1_CK) PB10(USART2_TX) PB11(USART2_RX) USART2_REMA P[1:0] PB12(USART2_CK) = “00” (no remap) PB13(USART2_CTS) PB14(USART2_RTS) PC10(USART2_TX) USART2_REMA P PC11(USART2_RX) [1:0] =“01” (partial PC12(USART2_CK) remap) PB13(USART2_CTS)
Page 202: Can0/1 Af Remapping
GD32E50x User Manual Table 8-9. SPI0/SPI2/I2S alternate function remapping Register SPI0 SPI2/I2S PA4(SPI0_NSS) PA5(SPI0_SCK) SPI0_REMA P = 1 PA6(SPI0_MISO) PA7(SPI0_MOSI) PA15(SPI0_NSS) PB3(SPI0_SCK) SPI0_REMA P = 1 PB4(SPI0_MISO) PB5(SPI0_MOSI) PA15(SPI2_NSS/ I2S2_WS) PB3(SPI2_SCK/ I2S2_CK) SPI2_REMA P = 0 PB4(SPI2_MISO) PB5(SPI2_MOSI/I2S2_SD) PA4(SPI2_NSS/ I2S2_WS) PC10(SPI2_SCK/ I2S2_CK) SPI2_REMA P = 1 PC11(SPI2_MISO)
Page 203: Ethernet Af Remapping
GD32E50x User Manual Ethernet AF remapping 3.1.4. Table 8-11. ENET alternate function remapping Register ENET PA7(RX_DV-CRS_DV) PC4(RXD0) ENET_REMA P = “0” PC5(RXD1) PB0(RXD2) PB1(RXD3) PD8(RX_DV-CRS_DV) PD9(RXD0) ENET_REMA P = “1” PD10(RXD1) PD11(RXD2) PD12(RXD3) CTC AF remapping 3.1.5. Refer to AFIO port configuration register 1 (AFIO_ PCF1). Table 8-12.
Page 204 GD32E50x User Manual OSC_OUT...
Page 205: Register Definition
GD32E50x User Manual Register definition 3.2. GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..G) 3.2.1.
Page 206 GD32E50x User Manual 21:20 MD5[1:0] Port 5 mode bits These bits are set and cleared by softw are refer to MD0[1:0]description 19:18 CTL4[1:0] Port 4 configuration bits These bits are set and cleared by softw are refer to CTL0[1:0]description 17:16 MD4[1:0] Port 4 mode bits These bits are set and cleared by softw are...
Page 207: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32E50x User Manual 11: AFIO output w ith open-drain MD0[1:0] Port 0 mode bits These bits are set and cleared by softw are 00: Input mode (reset state) 01: Output mode(10MHz) 10: Output mode(2MHz) 11: Output mode(50MHz) Port control register 1 (GPIOx_CTL1, x=A..G) 3.2.2.
Page 208: Port Input Status Register (Gpiox_Istat, X=A
GD32E50x User Manual 19:18 CTL12[1:0] Port 12 configuration bits These bits are set and cleared by softw are refer to CTL0[1:0]description 17:16 MD12[1:0] Port 12 mode bits These bits are set and cleared by softw are refer to MD0[1:0]description 15:14 CTL11[1:0] Port 11 configuration bits These bits are set and cleared by softw are...
Page 209: Port Output Control Register (Gpiox_Octl, X=A
GD32E50x User Manual ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT 0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 ISTATy Port input status(y=0..15)
Page 210: Port Bit Clear Register (Gpiox_Bc, X=A
GD32E50x User Manual BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by softw are 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy...
Page 211: Port Bit Speed Register (Gpiox_ Spd, X=A
GD32E50x User Manual LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can alw ays be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked.
Page 212: Event Control Register (Afio_Ec)
GD32E50x User Manual Event control register (AFIO_EC) 3.2.9. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PORT[2:0] PIN[3:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Event output enable ®...
Page 213 GD32E50x User Manual Memory map and bit definitions for High-density devices: ADC1_ET ADC0_ET TIMER4C SPI2_RE CAN1_RE Reserved Reserved SWJ_CFG[2:0] Reserved Reserved RGRT_R Reserved RGRT_R Reserved H3_IREM EMAP EMAP PD01_RE TIMER3_ TIMER2_REMAP[1:0 TIMER1_REMAP[1:0 TIMER0_REMAP[1:0 USART2_REMAP[1: USART1_ USART0_ I2C0_RE SPI0_RE CAN0_REMAP[1:0] REMAP REMAP REMAP Bits...
Page 214 GD32E50x User Manual ADC0_ETRGRT_RE ADC 0 external trigger routine conversion remapping This bit is set and reset by softw are. 0: Connect the ADC0 external signal trigger routine conversion to EXTI11. 1: Connect the ADC0 external signal trigger routine conversion to TIM7_TRGO. Reserved Must be kept at reset value.
Page 215 GD32E50x User Manual 10: not used Enable remapping function fully(TIMER1_CH0- TIMER1_ETI/PA 15, TIMER1_CH1/PB3, TIMER1_CH2/PB10, TIMER1_CH3/PB11) TIMER0_REMA P TIMER0 remapping [1:0] These bits are set and reset by softw are 00: Disable the remapping function(TIMER0_ETI / PA12, TIMER0_CH0 / PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11, TIMER0_B K IN / PB12, TIMER0_CH0_ON / PB13, TIMER0_CH1_ON / PB14, TIMER0_CH2_ON / PB15) 01: Enable the remapping function partially(TIMER0_ETI / PA12, TIMER0_CH0 /...
Page 216 GD32E50x User Manual SPI0_REMA P SPI0 remapping This bit is set and cleared by softw are. 0: Disable the remapping function (SPI0_NSS/PA4, SPI0_SCK /PA5, SPI0_MISO /PA6,SPI0_MOSI /PA7) 1: Enable the remapping function (SPI0_NSS/PA15, SPI0_SCK /PB3, SPI0_MISO /PB4,SPI0_MOSI /PB5) Memory map and bit definitions for connectivity devices: TIMER1IT TIMER4C PTP_PPS...
Page 217 GD32E50x User Manual Other: Undefined ENET_PHY_SEL Ethernet MII or RMII PHY selection 0:Select an MII PHY 1: Select an RMII PHY CAN1_REMA P CAN1 I/O remapping 0: Disable the remapping function (CAN1_RX/PB12,CA N_TX/PB13) 1: Enable the remapping function (CAN1_RX/PB5,CAN_TX/PB6) ENET_REMA P Ethernet MAC I/O remapping 0: Disable the remapping function (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
Page 218 GD32E50x User Manual TIMER1_CH1/PA1, TIMER1_CH2/PA2, TIMER1_CH3/PA3) 01: Enable the remapping function partially 0 (TIMER1_CH0- TIMER1_ETI/PA 15, TIMER1_CH1/PB3, TIMER1_CH2/PA2, TIMER1_CH3/PA3) 10: Enable the remapping function partially 1 (TIMER1_CH0-TIMER1_ETI/ PA 0, TIMER1_CH1/PA1, TIMER1_CH2/PB10, TIMER1_CH3/PB11) 11: Enable the remapping function fully (TIMER1_CH0- TIMER1_ETI/PA 15, TIMER1_CH1/PB3, TIMER1_CH2/PB10, TIMER1_CH3/PB11) TIMER0_REMA P[1:0 TIMER0 remapping...
Page 219: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32E50x User Manual 0: Disable the remapping function (SPI0_NSS/PA4, SPI0_SCK /PA5, SPI0_MIS O /PA6, SPI0_MOSI /PA7) 1: Enable the remapping function (SPI0_NSS/PA15, SPI0_SCK /PB3, SPI0_MIS O /PB4, SPI0_MOSI /PB5) EXTI sources selection register 0 (AFIO_EXTISS0) 3.2.11. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 220: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32E50x User Manual 0011: PD1 pin 0100: PE1 pin 0101: PF1 pin 0110: PG1 pin Other configurations are reserved. EXTI0_SS [3:0] EXTI 0 sources selection 0000: PA0 pin 0001: PB0 pin 0010: PC0 pin 0011: PD0 pin 0100: PE0 pin 0101: PF0 pin 0110: PG0 pin Other configurations are reserved.
Page 221: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32E50x User Manual 0010: PC6 pin 0011: PD6 pin 0100: PE6 pin 0101: PF6 pin 0110: PG6 pin Other configurations are reserved. EXTI5_SS [3:0] EXTI 5 sources selection 0000: PA5 pin 0001: PB5 pin 0010: PC5 pin 0011: PD5 pin 0100: PE5 pin 0101: PF5 pin 0110: PG5 pin...
Page 222: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32E50x User Manual 0001: PB11 pin 0010: PC11 pin 0011: PD11 pin 0100: PE11 pin 0101: PF11 pin 0110: PG11 pin Other configurations are reserved. 11:8 EXTI10_SS [3:0] EXTI 10 sources selection 0000: PA10 pin 0001: PB10 pin 0010: PC10 pin 0011: PD10 pin 0100: PE10 pin 0101: PF10 pin...
Page 223 GD32E50x User Manual Reserved EXTI15_SS[3:0] EXTI14_SS[3:0] EXTI13_SS[3:0] EXTI12_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI15_SS [3:0] EXTI 15 sources selection 0000: PA15 pin 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin Other configurations are reserved.
Page 224: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32E50x User Manual 0100: PE12 pin 0101: PF12 pin 0110: PG12 pin Other configurations are reserved. AFIO port configuration register 1 (AFIO_PCF1) 3.2.15. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXMC_N TIMER13_ IMER12_...
Page 225: Io Compensation Control Register (Afio_Cpsctl)
GD32E50x User Manual alternate function onto the GPIO ports 0: Disable the remapping function (PA6) 1: Enable the remapping function (PF8) TIMER10_REMA P TIMER10 remapping This bit is set and cleared by softw are, it controls the mapping of the TIMER10_ C H0 alternate function onto the GPIO ports 0: Disable the remapping function (PB9) 1: Enable the remapping function (PF7)
Page 226: Afio Port Configuration Register A (Afio_Pcfa)
GD32E50x User Manual 1: I/O compensation cell is ready Reserved Must be kept at reset value. CPS_EN I/O compensation cell enable. When the port output speed is more than 50 MHz, the user should enable the compensation cell. 0: I/O compensation cell is pow er-dow n 1: I/O compensation cell is enable AFIO port configuration register A (AFIO_PCFA) 3.2.17.
Page 227 GD32E50x User Manual 10/11: Configure PA11 alternate function to SHRTIMER 21:20 PA10_AFCFG[1:0] PA10 AF function configuration bits These bits are set and cleared by softw are. 00: Do not configure PA10 alternate function to SHRTIMER/CA N2/CMP5 01: Configure PA10 alternate function to CAN2 10: Configure PA10 alternate function to CMP5 11: Configure PA10 alternate function to SHRTIMER Note: CAN2 is available only in connectivity line devices.
Page 228: Afio Port Configuration Register B (Afio_Pcfb)
GD32E50x User Manual AFIO port configuration register B (AFIO_PCFB) 3.2.18. Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). PB15_AF Reserved PB14_AFCFG[1:0] PB13_AFCFG[1:0] PB12_AFCFG[1:0] PB11_AFCFG[1:0] PB10_AFCFG[1:0] PB9_AFCFG[1:0] PB8_AFCFG[1:0] PB7_AFC PB6_AFC PB3_ PB0_ Reserved Reserved PB5_AFCFG[1:0] PB4_AFCFG[1:0]...
Page 229 GD32E50x User Manual 11: Configure PB11 alternate function to SHRTIMER Note: CAN2 is available only in connectivity line devices. 21:20 PB10_AFCFG[1:0] PB10 AF function configuration bits These bits are set and cleared by softw are. 00: Do not configure PB10 alternate function to SHRTIMER/USBHS/CA N2 01: Configure PB10 alternate function to CAN2 10: Configure PB10 alternate function to USBHS 11: Configure PB10 alternate function to SHRTIMER...
Page 230: Afio Port Configuration Register C (Afio_Pcfc)
GD32E50x User Manual 10: Configure PB4 alternate function to I2C2 11: Configure PB4 alternate function to SHRTIMER Reserved Must be kept at reset value PB3_AFCFG PB3 AF function configuration bit This bit is set and cleared by softw are. 0: Do not configure PB3 alternate function to SHRTIMER 1: Configure PB3 alternate function to SHRTIMER PB2_AFCFG[1:0] PB2 AF function configuration bits...
Page 231 GD32E50x User Manual 31:25 Reserved Must be kept at reset value PC12_AFCFG PC12 AF function configuration bit This bit is set and cleared by softw are. 0: Do not configure PC12 alternate function to SHRTIMER 1: Configure PC12 alternate function to SHRTIMER 23:22 PC11_AFCFG[1:0] PC11 AF function configuration bits...
Page 232: Afio Port Configuration Register D (Afio_Pcfd)
GD32E50x User Manual 0: Do not configure PC3 alternate function to USBHS 1: Configure PC3 alternate function to USBHS PC2_AFCFG[1:0] PC2 AF function configuration bits These bits are set and cleared by softw are. 00: Do not configure PC2 alternate function to USBHS/I2S1 01/11: Configure PC2 alternate function to I2S1 10: Configure PC2 alternate function to USBHS Reserved...
Page 233: Afio Port Configuration Register E (Afio_Pcfe)
GD32E50x User Manual AFIO port configuration register E (AFIO_PCFE) 3.2.21. Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). PE13_AF PE12_AF PE11_AF PE10_AF PE9_AFC PE8_AFC Reserved Reserved Reserved Reserved Reserved Reserved Reserved PE1_AFCFG[1:0] PE0_AFCFG[1:0] Bits Fields...
Page 234: Afio Port Configuration Register G (Afio_Pcfg)
GD32E50x User Manual 1: Configure PE9 alternate function to CMP3 Reserved Must be kept at reset value PE8_AFCFG PE8 AF function configuration bit This bit is set and cleared by softw are. 0: Do not configure PE8 alternate function to CMP1 1: Configure PE8 alternate function to CMP1 15:4 Reserved...
Page 235 GD32E50x User Manual 1: Configure PG14 alternate function to USART5 Reserved Must be kept at reset value. PG13_AFCFG PG13 AF function configuration bit This bit is set and cleared by softw are. 0: Do not configure PG13 alternate function to SHRTIMER 1: Configure PG13 alternate function to SHRTIMER Reserved Must be kept at reset value.
Page 236 GD32E50x User Manual 1: Configure PG10 alternate function to SHRTIMER 11:0 Reserved Must be kept at reset value.
Page 237: Cyclic Redundancy Checks Management Unit (Crc)
GD32E50x User Manual Cyclic redundancy checks management unit (CRC) Overview 3.3. A cyclic redundancy check management (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial.
Page 238: Function Overview
GD32E50x User Manual Function overview 3.5.  CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 239: Register Definition
GD32E50x User Manual Register definition 3.6. CRC base address: 0x4002 3000 Data register (CRC_DATA) 3.6.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Softw are w rites and reads.
Page 240: Control Register (Crc_Ctl)
GD32E50x User Manual by any other peripheral. The CRC_CTL register w ill generate no effect to the byte. Control register (CRC_CTL) 9.1.1. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O REV_I[1:0] PS[1:0]...
Page 241: Polynomial Register (Crc_Poly)
GD32E50x User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA w ill be programmed to this value. Polynomial register (CRC_POLY) 9.1.3.
Page 242: Trigonometric Math Unit (Tmu)
GD32E50x User Manual Trigonometric Math Unit (TMU) Overview 10.1. The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. The TMU calculation unit can be used to calculate total 9 kinds of operations. The operation data must meet IEEE 32-Bit Single Precision Floating-Point Format.
Page 243: Data Format
GD32E50x User Manual Figure 10-1. Block diagram of Trigonometric Math Unit Data format 10.3.2. The operation data and calculation result data format is given in Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format. They must meet IEEE 32 bit Single Precision Floating-Point.
Page 244: Mode 0 Description
GD32E50x User Manual in the given floating-point format. Under such cases, a positive or negtive Infinity value is returned. If a TMU operation generates an overflow condition, then the latched overflow flag (OVRF) is set to 1. The OVRF flag will remain latched until the next new operation is started. Rounding: There are various rounding formats supported by the IEEE standard.
Page 245: Mode 2 Description
GD32E50x User Manual If R0 result is too small for floating-point number (E < 0), R0 = 0.0, UDRF = 1. Mode 2 description 10.3.5. This operation is equivalent as R0 = √ x. x is the input operation data, R0 is the calculation result.
Page 246: Mode 5 Description
GD32E50x User Manual 2. R0 = cos(PerUnit * 2π). In control applications radians are usually normalized to the range of -1.0 to 1.0. It means that the range of PerUnit * 2π values is (-2π, 2π). So only the fraction part of operation data x is used in this mode. The x whole part has no effect on the result.
Page 247: Figure 10-2. Calculation Of R1 (Quadrant) And R0 (Ratio) Based On Y And X Values
GD32E50x User Manual if( X >= 0.0 ) R1( Quadrant ) = 0.0; else { if( Y >= 0.0 ) R1( Quadrant ) = 0.5; else R1( Quadrant ) = -0.5; }else { R0( Ratio ) = - X / Y; if( Y >= 0.0 ) R1( Quadrant ) = 0.25;...
Page 248: Mode 7 Description
GD32E50x User Manual Mode 7 description 10.3.10. This operation is equivalent as R0 = x/y. x and y is the input operation data, R0 is the calculation result. This mode has both UDRF and OVRF. The UDRF and OVRF condition is as below table: Table 10-7.
Page 249: Figure 10-3. Tmu Program Guidline
GD32E50x User Manual Figure 10-3. TMU program guidline Write TMU_IDATA0 Mode==6 or Mode == 7 or Mode ==8 Write TMU_IDATA1 Configure mode and interrupt enable Write 1 into TMUEN bit Interrupt enabled? Polling and Wait Step into interrupt TMUEN==0 routine Read TMU_DATA0 Mode == 6 Read TMU_DATA1...
Page 250: Tmu Register
GD32E50x User Manual TMU register 10.5. TMU base address: 0x4008 0000 Input data0 register (TMU_IDATA0) 10.5.1. Address offset: 0x00 Reset value: 0x3F80 0000 This register has to be accessed by word (32-bit). IDATA0[31:16] IDATA0[15:0] Bits Fields Descriptions 31:0 IDATA0[31:0] The value of input data Mode0~5: IDATA0 is the only operation data Mode6: IDATA0 is the X value Mode7: IDATA0 is the dividend...
Page 251: Control Register (Tmu_Ctl)
GD32E50x User Manual mode7: IDATA1 is the divisor mode8: IDATA1 is the X value or Y value IDATA1 must meet IEEE 32-Bit Single Precision Floating-Point Format. Control register (TMU_CTL) 10.5.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CFIF...
Page 252: Data0 Register (Tmu_Data0)
GD32E50x User Manual Data0 register (TMU_DATA0) 10.5.4. Address offset: 0x0C Reset value: 0x3400 0000 This register has to be accessed by word (32-bit). DATA0[31:16] DATA0[15:0] Bits Fields Descriptions 31:0 DATA0[31:0] The result of calculation Mode 0~5,7,8: TMU_DATA0 is the only result value Mode6: TMU_DATA0=Ratio of X and Y TMU_DATA0 must meet IEEE 32-Bit Single Precision Floating-Point Format.
Page 253 GD32E50x User Manual This register has to be accessed by word (32-bit). Reserved Reserve UDRF OVRF Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. UDRF The flag of underflow 0: No underflow 1: Underflow This bit is set and cleared by hardw are. w hen the next TMU calculation is started, this bit is cleared by hardw are.
Page 254: Direct Memory Access Controller (Dma)
GD32E50x User Manual Direct memory access controller (DMA) Overview 11.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 255: Block Diagram
GD32E50x User Manual Block diagram 11.3. Figure 11-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 256: Table 11-1. Dma Transfer Operation
GD32E50x User Manual Table 11-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 257: Peripheral Handshake
GD32E50x User Manual The DMA transmission is disabled by clearing the CHEvN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 258: Address Generation
GD32E50x User Manual channel number. Address generation 11.4.4. Two kinds of address generation algorithm are implemented independently for memory and peripheral, including the fixed mode and the increased mode. The PNAGA and MNAGA bit in the DMA_CHxCTL register are used to configure the next address generation algorithm of peripheral and memory.
Page 259: Interrupt
GD32E50x User Manual transfer error interrupt in the DMA_CHxCTL register. Configure the DMA_CHxPADDR register for setting the peripheral base address. Configure the DMA_CHxMADDR register for setting the memory base address. Configure the DMA_CHxCNT register to set the total transfer data number. 10.
Page 260: Figure 11-4. Dma0 Request Mapping
GD32E50x User Manual Table 11-3. DMA0 requests for each channel lists the support request from peripheral for each channel of DMA0, and Table 11-4. DMA1 requests for each channel lists the support request from peripheral for each channel of DMA1. Figure 11-4.
Page 261: Figure 11-5. Dma1 Request Mapping
GD32E50x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER2_CH3 TIMER2_CH0 ● ● ● ● TIMER2 TIMER2_CH2 TIMER2_UP TIMER2_TG ● ● ● TIMER3 TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_UP ● ● ● ● ●...
Page 262 GD32E50x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER7_UP TIMER7_TG TIMER7_CMT ● ● ● ● ADC2 ADC2 ● ● ● DAC_CH0 DAC_CH1 SPI2/I2S2_R ● SPI/I2S SPI2/I2S2_TX I2S2ADD_RX I2S2ADD_TX UART3_RX UART3_TX ● ● ● USART USART5_RX USART5_TX ●...
Page 263: Register Definition
GD32E50x User Manual Register definition 11.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 11.5.1.
Page 264: Interrupt Flag Clear Register (Dma_Intc)
GD32E50x User Manual Interrupt flag clear register (DMA_INTC) 11.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2...
Page 265 GD32E50x User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Softw are set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be w ritten w hen CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 266: Channel X Counter Register (Dma_Chxcnt)
GD32E50x User Manual CMEN Circular mode enable Softw are set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be w ritten w hen CHEN is ‘1’. Transfer direction Softw are set and cleared 0: Read from peripheral and w rite to memory 1: Read from memory and w rite to peripheral This bit can not be w ritten w hen CHEN is ‘1’.
Page 267: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be w ritten w hen CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer.
Page 268 GD32E50x User Manual MADDR[31:16] MADDR[15:0] Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be w ritten w hen CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 269: Debug (Dbg)
GD32E50x User Manual Debug (DBG) Introduction 12.1. The GD32E50x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSightTM module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm ®...
Page 270: Jtag Daisy Chained Structure
GD32E50x User Manual PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JT AG function without NJTRST pin, then the PB4 can be used to other GPIO functions (NJTRST tied to 1 by hardware).
Page 271: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32E50x User Manual When SLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN 12.3.2.
Page 272: Dbg Registers
GD32E50x User Manual DBG registers 12.4. DEBUG base address: 0xE0044000 ID code register (DBG_ID) 12.4.1. Address offset: 0x00 Read only This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by softw are.
Page 273 GD32E50x User Manual 1: Hold the TIMER10 counter for debug w hen core halted. TIMER9_HOLD TIMER9 hold bit This bit is set and reset by softw are. 0: no effect 1: Hold the TIMER9 counter for debug w hen core halted. TIMER8_HOLD TIMER8 hold bit This bit is set and reset by softw are.
Page 274 GD32E50x User Manual TIMER4_HOLD TIMER4 hold bit This bit is set and reset by softw are. 0: no effect 1: Hold the TIMER4 counter for debug w hen core halted. TIMER7_HOLD TIMER7 hold bit This bit is set and reset by softw are. 0: no effect 1: Hold the TIMER7 counter for debug w hen core halted.
Page 275 GD32E50x User Manual 1: Hold the WWDGT counter clock for debug w hen core halted. FWDGT_HOLD FWDGT hold bit This bit is set and reset by softw are. 0: no effect 1: Hold the FWDGT counter clock for debug w hen core halted. Reserved Must be kept at reset value.
Page 276: Analog-To-Digital Converter (Adc)
GD32E50x User Manual Analog-to-digital converter (ADC) Introduction 13.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment(LSB) or the most significant bit alignment(MSB).
Page 277: Pins And Internal Signals
GD32E50x User Manual  Module supply requirements: the typical power supply voltage is 3.3V: – 1.62V to 2.4V, with ADC maximum frequency is 14MHz. – 2.4V to 3.6V, with ADC maximum frequency is 35MHz.  ≤V ≤V Channel input range: V REF- REF+.
Page 278: Functional Overview
GD32E50x User Manual Functional overview 13.4. Figure 13-1. ADC module block diagram (for ADC0 and ADC1) watchdog event 0/1/2 SHRTIMER Analog watchdog watchdog 0/1/2 Trig select event 0/1/2 Interrupt Routine channels Channel Management ADC_IN0 ADC_IN1 GPIO Over ADC_IN15 Routine data registers SAR ADC （16 bits）...
Page 279: Foreground Calibration Function
GD32E50x User Manual Figure 13-2. ADC module block diagram (for ADC2) Trig select Routine channels Interrupt Interrupt Channel Management generator watchdog Analog event watchdog 0/1/2 0/1/2 ADC_IN0 ADC_IN8 GPIO ADC_IN10 Routine data registers Over SAR ADC ADC_IN13 （16 bits） sampler SENSE REFINT TOVS...
Page 280: Adc Clock
GD32E50x User Manual Set RSTCLB (optional). Set CLB=1. Wait until CLB=0. ADC clock 13.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller. ADC clock can be divided and configured by RCU controller. ADCON enable 13.4.3.
Page 281: Routine Sequence
GD32E50x User Manual Routine sequence 13.4.5. The channel management circuit can organize the sampling conversion channels into a sequence: routine sequence. The routine sequence supports up to 16 channels, and each channel is called routine channel. The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length. The ADC_RSQ0~ADC_RSQ2 registers specify the selected channels of the routine sequence.
Page 282: Figure 13-4. Continuous Operation Mode
GD32E50x User Manual stored in the ADC_RDATA register. Figure 13-4. Continuous operation mode Software procedure for continuous conversion on a routine channel: Set the CTN bit in the ADC_CTL1 register. Configure RSQ0 with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 283: Figure 13-5. Scan Operation Mode, Continuous Operation Mode Disable
GD32E50x User Manual Figure 13-5. Scan operation mode, continuous operation mode disable Software procedure for scan conversion on a routine sequence: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure ADC_RSQx and ADC_SAMPTx registers. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 284: Conversion Result Threshold Monitor
GD32E50x User Manual Configure ADC_RSQx and ADC_SAMPTx registers. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need. Prepare the DMA module to transfer data from the ADC_RDATA (refer to the spec of the DMA module). Set the SWRCST bit, or generate an external trigger for the routine sequence. Repeat step6 if in need.
Page 285: Sample Time Configuration
GD32E50x User Manual 6-bit resolution data alignment is different from 12-bit/10-bit/8-bit resolution data alignment, shown as Figure 13-9. 6-bit data storage mode Figure 13-9. 6-bit data storage mode Sample time configuration 13.4.9. The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers.
Page 286: Dma Request
GD32E50x User Manual ETSRC[3:0] Trigger Source Trigger Type 0011 TIMER7_CH0 0100 TIMER7_TRGO 0101 TIMER4_CH0 0110 TIMER4_CH2 0111 Softw are trigger SWRCST 1000~1111 reserved DMA request 13.4.11. The DMA request, which is enabled by the DMA bit of ADC_CTL1 register, is used to transfer data of routine sequence for conversion of more than one channel.
Page 287: Programmable Resolution (Dres)
GD32E50x User Manual the datasheet. Avg_Slope: average slope for curve between temperature vs. internal temperature sensor output voltage, the typical value please refer to the datasheet. Programmable resolution (DRES) 13.4.13. The resolution is configured by programming the DRES[1:0] bits in the ADC_OVSAMPCTL register.
Page 288: Figure 13-10. 20-Bit To 16-Bit Result Truncation
GD32E50x User Manual Figure 13-10. 20-bit to 16-bit result truncation Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. Figure 13-11. Numerical example with 5-bits shift and rounding shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.
Page 289: Adc Sync Mode
GD32E50x User Manual indicates truncation) 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Oversa shift shift shift shift shift shift shift shift shift m pling OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= ratio data 0000 0001 0010 0011 0100 0101 0110...
Page 290: Free Mode
GD32E50x User Manual Figure 13-12. ADC sync block diagram Routine Routine data registers （16 bits ） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO Routine Routine data registers ADC_IN15 （16 bits ） channels SENSE Syncl mode control EXTI_11 Routine trigger mux ADC0 (master) Free mode 13.5.1.
Page 291: Routine Follow-Up Fast Mode
GD32E50x User Manual Figure 13-13. Routine parallel mode on 10 channels Routine follow-up fast mode 13.5.3. The follow-up fast mode is applicable to sample the same channel of two ADCs. The source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register).
Page 292: Adc Interrupts
GD32E50x User Manual Continuous operation mode can’t be used in this mode, because it continuously converts the routine channel. The behavior of follow-up slow mode shows in the Figure 13-15. Routine follow-up slow mode on routine sequence channel. After an EOC interrupt is generated by ADC0 (if EOCIE bit is set), we can use a 32-bit DMA, which transfers to SRAM the ADC_RDATA register containing the ADC1 converted data in the [31: 16] bits field and the ADC0 converted data in the [15: 0] bits field.
Page 293: Adc Registers
GD32E50x User Manual ADC registers 13.7. ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 3C00 Status register (ADC_STAT) 13.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). WDE2 WDE1 Reserved...
Page 294: Control Register 0 (Adc_Ctl0)
GD32E50x User Manual Set by hardw are at the end of a routine sequence conversion. Cleared by softw are writing 0 to it or by reading the ADC_RDATA register. WDE0 Analog w atchdog 0 event flag 0: Analog w atchdog 0 event is not happened 1: Analog w atchdog 0 event is happening Set by hardw are w hen the converted voltage crosses the values programmed in the ADC_WDLT0 and ADC_WDHT0 registers.
Page 295 GD32E50x User Manual any configuration change. 15:13 DISNUM[2:0] Number of conversions in discontinuous mode The number of channels to be converted after a trigger w ill be DISNUM+1 in routine sequence. Reserved Must be kept at reset value. DISRC Discontinuous mode on routine channels 0: Discontinuous operation mode on routine channels disable 1: Discontinuous operation mode on routine channels enable Reserved...
Page 296: Control Register 1 (Adc_Ctl1)
GD32E50x User Manual 10000: ADC channel16 10001: ADC channel17 Other values are reserved. Note: ADC0 analog inputs Channel16 and Channel17 are internally connected to the temperature sensor, and to V inputs. ADC1 analog inputs Channel16, and REFINT Channel17 are internally connected to V .
Page 297 GD32E50x User Manual 0011: TIMER1_CH1 0100: TIMER2_TRGO 0101: TIMER3_CH3 0110: EXTI Line11/ TIMER7_TRGO 0111: SWRCST 1000: SHRTIMER_A DCTRG0 1001: SHRTIMER_A DCTRG2 Others: Reserved For ADC2: 0000: TIMER2_CH0 0001: TIMER1_CH2 0010: TIMER0_CH2 0011: TIMER7_CH0 0100: TIMER7_TRGO 0101: TIMER4_CH0 0110: TIMER4_CH2 0111: SWRCST 1xxx: Reserved 16:12 Reserved...
Page 298: Sample Time Register 0 (Adc_Sampt0)
GD32E50x User Manual 1: Initialize calibration register start ADC calibration 0: Calibration done 1: Calibration start Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC w ill be w ake up w hen this bit is changed from low to high and take a stabilization time.
Page 299: Sample Time Register 1 (Adc_Sampt1)
GD32E50x User Manual 010: Channel sampling time is 13.5 cycles 011: Channel sampling time is 28.5 cycles 100: Channel sampling time is 41.5 cycles 101: Channel sampling time is 55.5 cycles 110: Channel sampling time is 71.5 cycles 111: Channel sampling time is 239.5 cycles Sample time register 1 (ADC_SAMPT1) 13.7.5.
Page 300: Watchdog High Threshold Register 0 (Adc_Wdht0)
GD32E50x User Manual 110: Channel sampling time is 71.5 cycles 111: Channel sampling time is 239.5 cycles Watchdog high threshold register 0 (ADC_WDHT0) 13.7.6. Address offset: 0x24 Reset value: 0x0000 0FFF This register has to be accessed by word(32-bit). Reserved Reserved WDHT0[11:0] Bits...
Page 301: Routine Sequence Register 1 (Adc_Rsq1)
GD32E50x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RL[3:0] RSQ15[4:1] RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 RL[3:0] Routine sequence length. The total number of conversion in routine sequence equals to RL[3:0]+1. 19:15 RSQ15[4:0] refer to RSQ0[4:0] description...
Page 302: Routine Sequence Register 2 (Adc_Rsq2)
GD32E50x User Manual RSQ7[4:0] refer to RSQ0[4:0] description RSQ6[4:0] refer to RSQ0[4:0] description Routine sequence register 2 (ADC_RSQ2) 13.7.10. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RSQ5[4:0] RSQ4[4:0] RSQ3[4:1] RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits...
Page 303: Oversample Control Register (Adc_Ovsampctl)
GD32E50x User Manual 31:16 ADC1RDTR[15:0] ADC1 routine channel data In ADC0: In sync mode, these bits contain the routine data of ADC1. These bits are only used in ADC0. 15:0 RDATA[15:0] Routine channel data These bits contain the conversion result from routine channel, w hich is read only. Oversample control register (ADC_OVSAMPCTL) 13.7.12.
Page 304: Watchdog 1 Channel Selection Register (Adc_Wd1Sr)
GD32E50x User Manual 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Other values are reserved. Note: The softw are allow s this bit to be w ritten only w hen ADCON=0 (this ensures that no conversion is in progress). OVSR[2:0] Oversampling ratio This bit filed defines the number of oversampling ratio.
Page 305: Watchdog 2 Channel Selection Register (Adc_Wd2Sr)
GD32E50x User Manual 17:0 AWD1CS[17:0] Analog w atchdog 1 channel selection These bits are set and cleared by softw are. They enable and select the input channels to be guarded by the analog w atchdog 1. AWD1CS[n] = 0: ADC analog input channel n is not monitored by analog w atchdog AWD1CS[n] = 1: ADC analog input channel n is monitored by analog w atchdog 1 When AWD1CH[17:0] = 000..0, the analog w atchdog 1 is disabled Note:...
Page 306: Watchdog Threshold Register 2 (Adc_Wdt2)
GD32E50x User Manual Reset value: 0x00FF 0000 This register has to be accessed by word(32-bit). Reserved WDHT1[7:0] Reserved WDLT1[7:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:16 WDHT1[7:0] High threshold for analog w atchdog 1 These bits define the high threshold for the analog w atchdog 1. Note: Softw are is allow ed to w rite these bits only w hen the ADC is disabled (ADCON =0).
Page 307: Differential Mode Control Register (Adc_Difctl)
GD32E50x User Manual 15:8 Reserved Must be kept at reset value. WDLT2[7:0] Low threshold for analog w atchdog 2 These bits define the high threshold for the analog w atchdog 2. Note: Softw are is allow ed to w rite these bits only w hen the ADC is disabled (ADCON =0).
Page 308: Digital-To-Analog Converter (Dac)
GD32E50x User Manual Digital-to-analog converter (DAC) Introduction 14.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 309: Function Description
GD32E50x User Manual Figure 14-1. DAC block diagram DAC control register DTSELx[3:0] DBOFFx TIMER5_TRGO TIMER7_TRGO TIMER6_TRGO SHRTIMER_ DACTRIGs EXTI9 SWTRx Control logic Buff DAC_OUTx FIFO OUTx_DO OUTx_DH (4-bit) 12-bit 12-bit 12-bit Note: The TIMER7_TRGO trigger is replaced by TIMER2_TRGO, in connectivity line devices. Table 14-1.
Page 310: Dac Data Configuration
GD32E50x User Manual The output buffer, which is turned on by default, can be turned off by setting the DBOFFx bits in the DAC_CTL0 register. DAC data configuration 14.3.3. The 12-bit DAC holding data (OUTx_DH) can be configured by writing any one of the OUTx_R12DH, OUTx_L12DH and OUTx_R8DH registers.
Page 311: Dac Output Fifo
GD32E50x User Manual voltage and the analog output load. DAC output FIFO 14.3.6. There is a 4-depth data FIFO which is implemented between the data hold register and the output register. The FIFO can be enabled by setting the FIFOENx bit in the DAC_CTL1 register.
Page 312: Dac Output Calculate
GD32E50x User Manual Figure 14-2. DAC LFSR algorithm Triangle noise mode: in this mode, a triangle signal is added to the OUTx_DH value, and then the result is stored into the OUTx_DO register. The minimum value of the triangle signal is 0, while the maximum value of the triangle signal is (2 <<...
Page 313: Dac Concurrent Conversion
GD32E50x User Manual occurs, a DAC DMA request will be generated. If a second external trigger arrives before the acknowledgement of the previous request, the new request will not be serviced, and an underrun error event occurs. The DDUDRx bit in the DAC_STAT0 register is set, an interrupt will be generated if the DDUDRIEx bit in the DAC_CTL0 register is set.
Page 314: Dac Registers
GD32E50x User Manual DAC registers 14.4. DAC base address: 0x4000 7400 Control register 0 (DAC_CTL0) 14.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DDUDR DTSEL1 DDMA Reserved DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 DDUDR...
Page 315 GD32E50x User Manual 1001: The bit w idth of the w ave signal is 10 1010: The bit w idth of the w ave signal is 11 ≥1011: The bit w idth of the w ave signal is 12 23:22 DWM1[1:0] DAC_OUT1 noise w ave mode These bits specify the mode selection of the noise w ave signal of DAC_OUT1 w hen...
Page 316 GD32E50x User Manual 0: DAC_OUT0 DMA underrun interrupt enabled DDMAEN0 DAC_OUT0 DMA enable 0: DAC_OUT0 DMA mode disabled 1: DAC_OUT0 DMA mode enabled 11:8 DWBW0[3:0] DAC_OUT0 noise w ave bit w idth These bits specify bit w idth of the noise w ave signal of DAC_OUT0. These bits indicate that unmask LFSR bit [n-1, 0] in LFSR noise mode or the amplitude of the triangle is ((2<<(n-1))-1) in triangle noise mode, w here n is the bit w idth of w ave.
Page 317: Software Trigger Register (Dac_Swt)
GD32E50x User Manual 1011~1111: Reserved. DTEN0 DAC_OUT0 trigger enable 0: DAC_OUT0 trigger disabled 1: DAC_OUT0 trigger enabled DBOFF0 DAC_OUT0 output buffer turn off 0: DAC_OUT0 output buffer turns on to reduce the output impedance and improv e the driving capability 1: DAC_OUT0 output buffer turns off DEN0 DAC_OUT0 enable...
Page 318: Dac_Out0 12-Bit Left-Aligned Data Holding Register (Out0_L12Dh)
GD32E50x User Manual Reserved Reserved OUT0_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT0_DH[11:0] DAC_OUT0 12-bit right-aligned data. These bits specify the data that is to be converted by DAC_OUT0. DAC_OUT0 12-bit left-aligned data holding register (OUT0_L12DH) 14.4.4.
Page 319: Dac_Out1 12-Bit Right-Aligned Data Holding Register (Out1_R12Dh)
GD32E50x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. OUT0_DH[7:0] DAC_OUT0 8-bit right-aligned data. These bits specify the MSB 8 bits of the data that is to be converted by DAC_OUT0. DAC_OUT1 12-bit right-aligned data holding register (OUT1_R12DH) 14.4.6.
Page 320: Dac_Out1 8-Bit Right-Aligned Data Holding Register (Out1_R8Dh)
GD32E50x User Manual Reserved Must be kept at reset value. DAC_OUT1 8-bit right-aligned data holding register (OUT1_R8DH) 14.4.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT1_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 321: Dac Concurrent Mode 12-Bit Left-Aligned Data Holding Register (Dacc_L12Dh)
GD32E50x User Manual concurrent mode 12-bit left-aligned data holding register 14.4.10. (DACC_L12DH) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). OUT1_DH[11:0] Reserved OUT0_DH[11:0] Reserved Bits Fields Descriptions 31:20 OUT1_DH[11:0] DAC_OUT1 12-bit left-aligned data These bits specify the data that is to be converted by DAC_OUT1.
Page 322: Dac_Out0 Data Output Register (Out0_Do)
GD32E50x User Manual OUT0_DH[7:0] DAC_OUT0 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DAC_OUT0. DAC_OUT0 data output register (OUT0_DO) 14.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DO [11:0]...
Page 323: Dac Status Register 0 (Dac_Stat0)
GD32E50x User Manual DAC Status register 0 (DAC_STAT0) 14.4.14. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). DDUDR1 Reserved Reserved rc_w1 DDUDR0 Reserved Reserved rc_w1 Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DDUDR1 DAC_OUT1 DMA underrun flag, set by hardw are, cleared by softw are write 1.
Page 324: Dac Status Register 1 (Dac_Stat1)
GD32E50x User Manual 0: DAC_OUT1 FIFO underflow interrupt disabled. 1: DAC_OUT1 FIFO underflow interrupt enabled. FIFOOVRIE1 DAC_OUT1 FIFO overflow interrupt enable. 0: DAC_OUT1 FIFO overflow interrupt disabled. 1: DAC_OUT1 FIFO overflow interrupt enabled. FIFOEN1 DAC_OUT1 data FIFO enable. The DTEN1 bit should be set and DDMAEN1 should be reset, w hen FIFOEN1 is set.
Page 325 GD32E50x User Manual 001: the number of data is 1 010: the number of data is 2 011: the number of data is 3 100: the number of data is 4 101~111: reserved FIFOUDR1 DAC_OUT1 FIFO underflow flag 0: DAC_OUT1 FIFO is not underflow. 1: DAC_OUT1 FIFO is underflow.
Page 326: Comparator (Cmp)
GD32E50x User Manual Comparator (CMP) The CMP is only available on CL series. Overview 15.1. The general purpose comparators, CMP1, CMP3 and CMP5, can work either standalone (all terminal are available on I/Os) or together with the timers. It blanking function can be used for false overcurrent detection in motor control applications. 15.2.
Page 327: Cmp I/O Configuration
GD32E50x User Manual Figure 15-1. CMP block diagram of GD32E50x series CMP1MSEL[3:0] CMP1PL CMP1OSEL[3:0] CMP3MSEL[3:0] CMP3PL CMP3OSEL[3:0] CMP5MSEL[3:0] CMP5PL CMP5OSEL[3:0] Note: V is 1.2V. REFINT CMP I/O configuration 15.3.1. These I/Os must be configured in analog mode in the GPIOs registers before they are selected as CMPs inputs.
Page 328: Cmp Output Blanking
GD32E50x User Manual The CMP output can be redirected internally and externally simultaneously. . Table 15-1. CMP inputs and outputs summary CMP1 CMP3 CMP5 CMP non inverting inputs connected PB11 to I/Os CMP inverting inputs connected PA2/PA4/PA5 PB2/PA4/PA5 PB15/PA4/PA5 to I/Os REFINT REFINT REFINT...
Page 329: Cmp Register Write Protection
GD32E50x User Manual Figure 15-2. The CMP outputs signal blanking Current threshold Current signal PWM signal Blanking window signal CMP outputs raw singal CMP outputs final singal CMP register write protection 15.3.3. The CMP control and status register (CMP_CS) can be protected from writing by setting CMPxLK bit to 1.
Page 330: Cmp Registers
GD32E50x User Manual 15.4. CMP registers CMP base address：0x4001 7C00 CMP1 Control/status register (CMP1_CS) 15.4.1. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1MS CMP1LK CMP1O Reserved Reserved CMP1BLK[2:0] Reserved EL[3] CMP1PL Reserved CMP1OSEL[3:0] Reserved CMP1MSEL[2:0]...
Page 331: Cmp3 Control/Status Register (Cmp3_Cs)
GD32E50x User Manual 17:16 Reserved Must be kept at reset value. CMP1PL Polarity of CMP1 output This bit is used to select the polarity of CMP1 output. 0 : Output is not inverted 1 : Output is inverted Reserved Must be kept at reset value 13:10 CMP1OSEL[3:0] Comparator 1 output selection...
Page 332 GD32E50x User Manual CMP3MS CMP3LK CMP3O Reserved Reserved CMP3BLK[2:0] Reserved EL[3] CMP3PL Reserved CMP3OSEL[3:0] Reserved CMP3MSEL[2:0] Reserved CMP3EN Bits Fields Descriptions CMP3LK CMP3 lock This bit allow s to have all control bits of CMP3 as read-only. It can only be set once by softw are and cleared by a system reset.
Page 333: Cmp5 Control/Status Register (Cmp5_Cs)
GD32E50x User Manual 0110: TIMER2 channel2 input capture 0111~1111: Reserved Reserved Must be kept at reset value CMP3MSEL[2:0] CMP3_IM input selection These bits, together w ith bit 22, are used to select the source connected to the CMP3_IM input of the CMP3. 0000: V REFINT 0001: V...
Page 334 GD32E50x User Manual This bit is a copy of CMP5 output state, w hich is read only. 0: Non-inverting input below inverting input and the output is low 1: Non-inverting input above inverting input and the output is high 29:23 Reserved Must be kept at reset value.
Page 335 GD32E50x User Manual 0111: PB15 1000~1111: Reserved Reserved Must be kept at reset value CMP5EN CMP5 enable 0: CMP5 disabled 1: CMP5 enabled...
Page 336: Watchdog Timer (Wdgt)
GD32E50x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 337: Figure 16-1. Free Watchdog Block Diagram
GD32E50x User Manual Figure 16-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at anytime.
Page 338 GD32E50x User Manual Min tim eout (m s) Max tim eout (m s) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 128 0.025 13104.025 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: When after the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 339: Register Definition
GD32E50x User Manual Register definition 16.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 340 GD32E50x User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to w ait until...
Page 341 GD32E50x User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free w atchdog timer counter reload value update During a w rite operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
Page 342: Window Watchdog Timer (Wwdgt)
GD32E50x User Manual Window watchdog timer (WWDGT) 16.2. Overview 16.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 343: Figure 16-3. Window Watchdog Timing Diagram
GD32E50x User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set).
Page 344: Table 16-2. Min/Max Timeout Value At 100 Mhz (F Pclk1 )
GD32E50x User Manual Table 16-2. Min/max timeout value at 100 MHz (f PCLK1 Min tim eout value Max tim eout value Prescaler divider PSC[1:0] CNT[6:0]=0x40 CNT[6:0]=0x7F 40.96 μs 1 / 1 2.62 ms 81.92 μs 1 / 2 5.24 ms 163.84 μs 1 / 4 10.49 ms...
Page 345: Register Definition
GD32E50x User Manual Register definition 16.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 346 GD32E50x User Manual reaches 0x40. It can be cleared by a hardw are reset or softw are reset by setting the WWDGTRST bit of the RCU module. A w rite operation of ‘0’ has no effect. PSC[1:0] Prescaler. The time base of the w atchdog timer counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4...
Page 347: Real-Time Clock (Rtc)
GD32E50x User Manual Real-time clock (RTC) Overview 3.7. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register.
Page 348: Rtc Reset
GD32E50x User Manual (stored in the RTC_ALRMH/L register). Figure 17-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK LXTAL RTC_DIV RTC_CNT OVIF NVIC OVIE interrupt IRC40K RTC_Alarm Reload controler COMPARE ALRMIF RTC_PSC ALRMIE...
Page 349: Rtc Flag Assertion
GD32E50x User Manual bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete. The value of the LWOFF bit in the RTC_CTL register set s to ‘1’, if the write operation finished.
Page 350: Figure 17-3. Rtc Second And Overflow Waveform Example (Rtc_Psc= 3)
GD32E50x User Manual Figure 17-3. RTC second and overflow waveform example (RTC_PSC= 3) RTCCLK RTC_ PSC RTC_Second FFFFFFFD FFFFFFFE FFFFFFFF RTC_ CNT RTC_ Overflow OVIF OVIF flag can be cleared by software...
Page 351: Rtc Register
GD32E50x User Manual RTC Register 3.10. RTC base address: 0x4000 2800 RTC interrupt enable register (RTC_INTEN) 17.1.5. Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions 31:3...
Page 352: Rtc Prescaler High Register (Rtc_Psch)
GD32E50x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. LWOFF Last w rite operation finished flag 0: Last w rite operation on RTC registers did not finished. 1: Last w rite operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode.
Page 353: Rtc Prescaler Low Register (Rtc_Pscl)
GD32E50x User Manual 31:4 Reserved Must be kept at reset value. PSC[19:16] RTC prescaler value high RTC prescaler low register (RTC_PSCL) 17.1.8. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits Fields...
Page 354: Rtc Counter High Register (Rtc_Cnth)
GD32E50x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved DIV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardw are w hen the RTC prescaler or RTC counter register updated.
Page 355: Rtc Alarm High Register (Rtc_Alrmh)
GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] RTC counter value low RTC alarm high register (RTC_ALRMH) 17.1.13. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits...
Page 356: Timer (Timerx)
GD32E50x User Manual Timer (TIMERx) Table 18-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1~4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit(TIMER1) Counter 16-bit 16-bit 16-bit 16-bit 16-bit(TIMER2~4) UP,DOWN, UP,DOWN, Count m ode UP ONLY...
Page 357: Advanced Timer (Timerx, X=0, 7)
GD32E50x User Manual Advanced timer (TIMERx, x=0, 7) 18.1. Overview 18.1.1. The advanced timer module (Timer0&Timer7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 358: Block Diagram
GD32E50x User Manual Block diagram 18.1.3. Figure 18-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 18-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2...
Page 359: Figure 18-2. Timing Chart Of Internal Clock Divided By 1
GD32E50x User Manual Figure 18-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock ...
Page 360: Figure 18-3. Timing Chart Of Psc Value Change From 0 To 2
GD32E50x User Manual Figure 18-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 361: Figure 18-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E50x User Manual Figure 18-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-5.
Page 362: Figure 18-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32E50x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated.
Page 363: Figure 18-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32E50x User Manual Figure 18-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 364: Figure 18-8. Timing Chart Of Center-Aligned Counting Mode
GD32E50x User Manual Figure 18-8. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 365: Figure 18-9. Repetition Timechart For Center-Aligned Counter
GD32E50x User Manual of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow.
Page 366: Figure 18-11. Repetition Timechart For Down-Counter
GD32E50x User Manual Figure 18-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 367: Figure 18-12. Channel Input Capture Principle
GD32E50x User Manual Figure 18-12. Channel Input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 368: Figure 18-13. Channel Output Compare Principle (With Complementary Output, X=0,1,2)
GD32E50x User Manual and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 369: Figure 18-15. Output-Compare In Three Modes
GD32E50x User Manual (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNEN=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;...
Page 370 GD32E50x User Manual Figure 18-15. Output-compare in three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 371: Figure 18-16. Timing Chart Of Eapwm
GD32E50x User Manual Figure 18-16. Timing chart of EAPWM Figure 18-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal Figure 18-13.
Page 372 GD32E50x User Manual set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 373: Table 18-2. Complementary Outputs Controlled By Parameters
GD32E50x User Manual Table 18-2. Complementary outputs controlled by parameters Com plem entary Param eters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off -state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 374: Figure 18-18. Complementary Output With Dead-Time Insertion
GD32E50x User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 375: Figure 18-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32E50x User Manual bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0. If IOS is 0 then the timer releases the enable output else the enable output remains high.
Page 376: Figure 18-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32E50x User Manual Table 18-3. Counting direction in different quadrature decoder mode CI0FE0 CI1FE1 Counting mode Level Fallin Rising Rising Falling CI1FE1=1 Down Quadrature decoder mode 0 SMC[2:0]=3’b000 CI1FE1=0 Down Quadrature decoder mode 1 CI0FE0=1 Down SMC [2:0]=3’b010 CI0FE0=0 Down CI1FE1=1 Down Quadrature decoder mode 2 CI1FE1=0...
Page 377: Figure 18-22. Hall Sensor I S Used To Bldc Motor
GD32E50x User Manual Figure 18-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in (Advanced/GeneralL0 TIMER) should accept three HALL sensor signals. Each of the three input of HALL sensors provides a pulse that applied to an input capture pin, can then be analyzed and both speed and position can be deduced.
Page 378: Figure 18-23. Hall Sensor Timing Between Two Timers
GD32E50x User Manual Figure 18-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 379: Figure 18-24. Restart Mode
GD32E50x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 101: CI0FE0 If ETIFP is selected as prescaler can be 110: CI1FE1 the trigger source, used. 111: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by inversion.
Page 380: Figure 18-25. Pause Mode
GD32E50x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-25. Pause m ode TIMER_CK CNT_REG CI0FE0 TRGIF Event m ode ETPSC = 1, ETI is The counter w ill start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2.
Page 381: Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
GD32E50x User Manual counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register. After a trigger rising occurs in the single pulse mode, the OxCPRE signal will immediately be forced to the state which the OxCPRE signal will change to, as the compare match event occurs without taking the comparison result into account.
Page 382 GD32E50x User Manual Figure 18-28. Timer0 master/slave mode example TIMER 14 TIMER0 TRGS Master ITI0 TRGO mode Prescaler Counter control TIMER 1 Master ITI1 TRGO mode Prescaler Counter control TIMER 2 Trigger Master ITI2 selection TRGO mode Prescaler Counter control CI0F_ED CI0FE0 CI1FE1...
Page 383: Figure 18-29. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32E50x User Manual Select TIMER2 as TIMER0 input trigger source (TRGS=3’b010 in the TIMERx_SMCFG register). Configure TIMER0 in event mode (SMC=3’b110 in the TIMER0_SMCFG register). When the CI0 signal of TIMER2 generates a rising edge, two timer counters start counting synchronously with the internal clock and both TRGIF flags are set.
Page 384 GD32E50x User Manual Timer debug mode When the Cortex®-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register is set to 1, the TIMERx counter stops.
Page 385: Timerx Registers(X=0, 7)
GD32E50x User Manual TIMERx registers(x=0, 7) 18.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS...
Page 386 GD32E50x User Manual can be set. After the counter is enabled, cannot be sw itched from 0x00 to non 0x00. Direction 0: Count up 1: Count dow n If the timer w ork in center-aligned mode or quadrature decode mode, this bit is read only.
Page 387 GD32E50x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 388 GD32E50x User Manual 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit.
Page 389 GD32E50x User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 390 GD32E50x User Manual EXTFC[3:0] Tim es SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 TIMER_CK 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 391 GD32E50x User Manual 010: Quadrature decoder mode 1.The counter counts on CI1FE1 edge, w hile the direction depends on CI0FE0 level. 011: Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1 edge, w hile the direction depends on each other. 100: Restart mode.
Page 392 GD32E50x User Manual 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled...
Page 393 GD32E50x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description...
Page 394 GD32E50x User Manual Refer to CH0IF description Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardw are and cleared by softw are. When channel 0 is in input mode, this flag is set w hen a capture event occurs.
Page 395 GD32E50x User Manual set, the TRGIF flag in TIMERx_INTF register is set, related interrupt or DMA transfer can occur if enabled. 0: No generate a trigger event 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by softw are and cleared by hardw are automatically. When this bit is set, channel’s capture/compare control...
Page 396 GD32E50x User Manual Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output com pare m ode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0]...
Page 397 GD32E50x User Manual equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low w hen the counter is equals to the output compare register TIMERx_CH0CV. 011: Toggle on match. O0CPRE toggles w hen the counter is equals to the output compare register TIMERx_CH0CV.
Page 398 GD32E50x User Manual 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. Input capture m ode: Bits Fields Descriptions 31:16 Reserved...
Page 399 GD32E50x User Manual 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection Same as Output compare mode...
Page 400 GD32E50x User Manual Note: When CH3MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. CH2COMCEN Channel 2 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal w ill be cleared.
Page 401 GD32E50x User Manual CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output w ill be accelerated if the channel is configured in PWM1 or PWM2 mode.
Page 402 GD32E50x User Manual 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset w hen CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 403 GD32E50x User Manual CH2NP Channel 2 complementary output polarity Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description...
Page 404 GD32E50x User Manual trigger operation in slave mode. And CIxFE0 w ill not be inverted. [CH0NP==0, CH0P==1]: CIxFE0’s falling edge is the active signal for capture or trigger operation in slave mode. And CIxFE0 w ill be inverted. [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: Reserved.
Page 405 GD32E50x User Manual PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed w ill be loaded to the corresponding shadow register at every update event.
Page 406 GD32E50x User Manual 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting dow n to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed w hen these shadow registers are enabled.
Page 407 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 408 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 409 GD32E50x User Manual This bit can be modified only w hen PROT [1:0] bit-filed in TIMERx_CCHP register is 00. BRKP Break input polarity This bit specifies the polarity of the BRKIN input signal. 0: BRKIN input active low 1; BRKIN input active high BRKEN Break input enable This bit can be set to enable the BRKIN and CKM clock failure event inputs.
Page 410 GD32E50x User Manual This bit-field can be w ritten only once after the reset. Once the TIMERx_ CCHP register has been w ritten, this bit-field w ill be w riting protected. DTCFG[7:0] Dead time configure The relationship betw een DTVAL value and the duration of dead-time is as follow : DTCFG[7:5] The duration of dead-time 3’b0xx...
Page 411 GD32E50x User Manual DMA transfer buffer register (TIMERx_DMATB) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) w ill be accessed.
Page 412 GD32E50x User Manual 1: If POEN and IOS is 0, the output disabled 0: No effect...
Page 413: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32E50x User Manual General level0 timer (TIMERx, x=1, 2, 3, 4) 18.2. Overview 18.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 414: Function Overview
GD32E50x User Manual Figure 18-30. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection TIMER_CK DMA REQ/ACK Trigger Selector&Counter ETIFP...
Page 415: Figure 18-31. Timing Chart Of Internal Clock Divided By 1
GD32E50x User Manual Figure 18-31. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111(  external clock mode 0 ). External input pin source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 416: Figure 18-32. Timing Chart Of Psc Value Change From 0 To 2
GD32E50x User Manual Figure 18-32. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 417: Figure 18-33. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E50x User Manual Figure 18-33. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 18-34.
Page 418: Figure 18-35. Timing Chart Of Down Counting Mode,Psc=0/2
GD32E50x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow.
Page 419: Figure 18-36. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32E50x User Manual Figure 18-36. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 420: Figure 18-37. Timing Chart Of Center-Aligned Counting Mode
GD32E50x User Manual Figure 18-37. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-37. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 421: Figure 18-38. Channel Input Capture Principle
GD32E50x User Manual generated if enabled by CHxIE = 1. Figure 18-38. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock CI1FE0 Counter presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT...
Page 422: Figure 18-39. Channel Output Compare Principle (X=0,1,2,3)
GD32E50x User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be ass erted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 423: Figure 18-40. Output-Compare In Three Modes
GD32E50x User Manual So the process can be divided to several steps as below: Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE...
Page 424: Figure 18-41. Timing Chart Of Eapwm
GD32E50x User Manual The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 18-41. Timing chart of EAPWM shows the EAPWM output and interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV.
Page 425: Figure 18-42. Timing Chart Of Capwm
GD32E50x User Manual Figure 18-42. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal (x=0,1,2,3), when the As is shown in Figure 18-39.
Page 426: Table 18-5. Examples Of Slave Mode
GD32E50x User Manual The OxCPRE signal can be forced to 0 when the ETIFE signal is derived from the external ETI pin and when it is set to a high level by setting the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register.
Page 427: Figure 18-43. Restart Mode
GD32E50x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-43. Restart m ode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Pause m ode TI0S=0 (Non-xor) The counter w ill be [CH0NP=0, CH0P=0] paused w hen the TRGS[2:0]=3’b101 CI0FE0 does not Filter is bypassed in...
Page 428: Figure 18-45. Event Mode
GD32E50x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-45. Event m ode Single pulse mode Single pulse mode Refer to Timers interconnection Advanced timer (TIMERx, x=0, 7). Refer to Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB;...
Page 429: Timerx Registers(X=1, 2, 3, 4)
GD32E50x User Manual TIMERx registers(x=1, 2, 3, 4) 18.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 430 GD32E50x User Manual center-aligned and channel is configured in output mode (CHxMS=00 TIMERx_CHCTL0 register). Both w hen counting up and counting dow n, CHxF bit can be set. After the counter is enabled, cannot be sw itched from 0x00 to non 0x00. Direction 0: Count up 1: Count dow n...
Page 431 GD32E50x User Manual This register has to be accessed by word (32-bit). Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 432 GD32E50x User Manual Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved...
Page 433 GD32E50x User Manual The external trigger can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 434 GD32E50x User Manual Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) w hen CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, w hile the direction depends on CI1FE1 level.
Page 435 GD32E50x User Manual 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled...
Page 436 GD32E50x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 437 GD32E50x User Manual mode, this flag is set w hen a compare event occurs. If Channel0 is set to input mode, this bit w ill be reset by reading TIMERx_CH0CV. 0: No Channel 0 interrupt occurred 1: Channel 0 interrupt occurred UPIF Update interrupt flag This bit is set by hardw are on an update event and cleared by softw are.
Page 438 GD32E50x User Manual 0, it is automatically cleared by hardw are. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag w as already high.
Page 439 GD32E50x User Manual This bit-field specifies the direction of the channel and the input signal selection. This bit-field is w ritable only w hen the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 440 GD32E50x User Manual The PWM mode can be used w ithout verifying the shadow register only in single pulse mode (w hen SPM=1) CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output w ill be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 441 GD32E50x User Manual 4’b0010 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset w hen CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 442 GD32E50x User Manual Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection.
Page 443 GD32E50x User Manual than TIMERx_CH2CV, and high otherw ise. When counting dow n, O2CPRE is high w hen the counter is larger than TIMERx_CH2CV , and low otherw ise. If configured in PWM mode, the O2CPRE level changes only w hen the output compare mode is adjusted from “Timing”...
Page 444 GD32E50x User Manual CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the signal.
Page 445 GD32E50x User Manual CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3NP Channel 3 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value.
Page 446 GD32E50x User Manual 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] w ill select the active trigger or capture polarity for CI0FE0 or CI1FE0.
Page 447 GD32E50x User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 448 GD32E50x User Manual Bits Fields Descriptions 31:0 CARL[31:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter auto reload register (TIMERx_CAR) (x=2,3,4) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits...
Page 449 GD32E50x User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Channel 0 capture/compare value register (TIMERx_CH0CV) (x=2,3,4) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits...
Page 450 GD32E50x User Manual When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) (x=2,3,4) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 451 GD32E50x User Manual corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event.
Page 452 GD32E50x User Manual When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 453 GD32E50x User Manual 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA w ill access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value.
Page 454 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or w rite operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) w ill be accessed. The transfer Timer is calculated by hardw are, and ranges from 0 to DMATC.
Page 455: General Level1 Timer (Timerx, X=8, 11)
GD32E50x User Manual General level1 timer (TIMERx, x=8, 11) 18.3. Overview 18.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 456: Function Overview
GD32E50x User Manual Figure 18-46. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter Trigger processor TIMERx_TRGO PSC_CLK TIMER_CK Trigger Selector&Counter Quadrate Decoder Output Logic CH0_O generation of outputs signals in compare, PWM,and mixed modes according to initialization, software CH1_O...
Page 457: Figure 18-47. Timing Chart Of Internal Clock Divided By 1
GD32E50x User Manual Figure 18-47. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111 (  external clock mode 0 ). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 458: Figure 18-48. Timing Chart Of Psc Value Change From 0 To 2
GD32E50x User Manual Figure 18-48. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 459: Figure 18-50. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E50x User Manual Figure 18-49. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-50.
Page 460: Figure 18-51. Channel Input Capture Principle
GD32E50x User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 461: Figure 18-52. Channel Output Compare Principle (X=0,1)
GD32E50x User Manual Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more. Step4: Interrupt enable.
Page 462: Figure 18-53. Output-Compare Under Three Modes
GD32E50x User Manual If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. In Output Compare mode, the TIMERx can generate timed pulses with programmable position, polarity, duration, and frequency.
Page 463: Figure 18-54. Pwm Mode Timechart
GD32E50x User Manual Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers. The period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV. Figure 18-54.
Page 464: Figure 18-55. Restart Mode
GD32E50x User Manual Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values.
Page 465: Figure 18-56. Pause Mode
GD32E50x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler and it w ill start w hen rising edge only. the trigger input is high. Figure 18-56. Pause m ode TIMER_CK CNT_REG CI0FE0 TRGIF Event m ode CH0P=0, The counter w ill start CI0FE0 does not TRGS[2:0]=3’b101...
Page 466: Figure 18-58. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32E50x User Manual a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software. If the CEN bit is cleared to 0 using software, the counter will be stopped and its value held.
Page 467: Timerx Registers(X=8, 11)
GD32E50x User Manual TIMERx registers(x=8, 11) 18.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS...
Page 468 GD32E50x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded w ith their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 469 GD32E50x User Manual synchronize the counter. 000: ITI0 001: ITI1 010: ITI2 011: ITI3 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed w hen slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode.
Page 470 GD32E50x User Manual 1: enabled Reserved Must be kept at reset value. CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000...
Page 471 GD32E50x User Manual trigger input can generates a trigger event. 0: No trigger event occurred. 1: Trigger interrupt occurred. Reserved Must be kept at reset value. Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardw are and cleared by softw are.
Page 472 GD32E50x User Manual Channel 1’s capture or compare event generation CH1G Refer to CH0G description Channel 0’s capture or compare event generation CH0G This bit is set by softw are in order to generate a capture or compare event in channel 0, it is automatically cleared by hardw are.
Page 473 GD32E50x User Manual This bit-field specifies the direction of the channel and the input signal selection. This bit-field is w ritable only w hen the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 474 GD32E50x User Manual capture/compare output w ill be accelerated if the channel is configured in PWM0 or PWM1 mode. The output channel w ill treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison.
Page 475 GD32E50x User Manual 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset w hen CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 476 GD32E50x User Manual CH1EN Channel 1 capture/compare function enable Refer to CH1EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, together w ith CH0P, this bit is used to define the polarity of CI0.
Page 477 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 478 GD32E50x User Manual This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 479 GD32E50x User Manual When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Configuration register (TIMERx_CFG ) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 480: General Level2 Timer (Timerx, X=9, 10, 12, 13)
GD32E50x User Manual General level2 timer (TIMERx, x=9, 10, 12, 13) 18.4. Overview 18.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 481: Function Overview
GD32E50x User Manual Figure 18-59. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector...
Page 482: Figure 18-60. Timing Chart Of Internal Clock Divided By 1
GD32E50x User Manual Figure 18-60. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 483: Figure 18-62. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E50x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 484: Figure 18-63. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E50x User Manual Figure 18-63. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 485: Figure 18-64. Channel Input Capture Principle
GD32E50x User Manual Figure 18-64. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling Capture Clock presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal First, the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 486: Figure 18-65. Channel Output Compare Principle
GD32E50x User Manual software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 487: Figure 18-66. Output-Compare Under Three Modes
GD32E50x User Manual * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN.
Page 488 GD32E50x User Manual relative bit definition. Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values.
Page 489: Timerx Registers(X=9, 10, 12, 13)
GD32E50x User Manual TIMERx registers(x=9, 10, 12, 13) 18.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 490 GD32E50x User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded w ith their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 491 GD32E50x User Manual The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 492 GD32E50x User Manual Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardw are w hen a capture event occurs w hile CH0IF flag has already been set.
Page 493 GD32E50x User Manual Channel 0’s capture or compare event generation CH0G This bit is set by softw are in order to generate a capture or compare event in channel 0, it is automatically cleared by hardw are. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 494 GD32E50x User Manual compare register TIMERx_CH0CV. 100: Force low . O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high w hen the counter is smaller than TIMERx_CH0CV, and low otherw ise.
Page 495 GD32E50x User Manual filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follow s: CH0CAPFLT [3:0] Tim es...
Page 496 GD32E50x User Manual Reserved.. CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementar y output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together w ith CH0P, this bit is used to...
Page 497 GD32E50x User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 498 GD32E50x User Manual CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 499 GD32E50x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by softw are. 1: If w rite the CHxVAL register, the w rite value is same as the CHxVAL value, the w rite access ignored 0: No effect Reserved...
Page 500: Basic Timer (Timerx, X=5, 6)
GD32E50x User Manual Basic timer (TIMERx, x=5, 6) 18.5. Overview 18.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 501: Figure 18-68. Timing Chart Of Internal Clock Divided By 1
GD32E50x User Manual Figure 18-68. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 502: Figure 18-70. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E50x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 503: Figure 18-71. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32E50x User Manual Figure 18-71. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 504: Timerx Registers(X=5, 6)
GD32E50x User Manual TIMERx registers(x=5, 6) 18.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS Bits...
Page 505 GD32E50x User Manual The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 506 GD32E50x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled...
Page 507 GD32E50x User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by softw are, and cleared by hardw are automatically.
Page 508 GD32E50x User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 509: Super High-Resolution Timer (Shrtimer)
GD32E50x User Manual Super High-Resolution Timer (SHRTIMER) 19.1. Overview SHRTIMER has a super high-resolution counting clock and can be used for high-precision timing. It can generate 10 super high resolution and flexible digital signals to control motor or be used for power management applications. The 10 digital signals can be output independently or coupled into 5 pairs of complementary signals.
Page 510: Function Overview
GD32E50x User Manual Figure 19-1. SHRTIMER block diagram Master_TIMER Master_TIMER Interrupt request repetition counter auto repetition Synchronization counter auto DMA mode DMA mode register DMA request DMA request reload register register reload register control control output/input ADC trigger Counter Compare Counter Compare DAC trigger...
Page 511: Table 19-1. The Limitations Of Auto-Reload And Compare Y (Y=0..3) Register
GD32E50x User Manual Figure 19-2. Master_TIMER diagram Slave_TIMERx(x=0..4) CREP Counter Synchronization repetition Start counter input Reset Counter SHRTIMER_PSCCK Half SHRTIMER_HPCK CMP0 mode 64 * f SHRTIMER_CK SHRTIMER_CK CMP1 (from RCU) SHRTIMER_CK CMP2 CMP3 The auto-reload register compare y (y=0..3) register have the following limitations: ...
Page 512: Figure 19-3. Counter Clock When Divided By 32
GD32E50x User Manual below: CNTCKDIV[2:0]+1 SHRTIMER_PSCCK SHRTIMER_HPCK When the CNTCKDIV[3] bit in SHRTIMER_MTACTL register is ‘1’, the CNTCKDIV[2:0] bit- filed can only be configured with ‘3’b000’ and the frequency relationship between SHRTIMER_PSCCK and SHRTIMER_HPCK can be expressed below: SHRTIMER_PSCCK SHRTIMER_HPCK Note: The clock division CNTCKDIV[3:0] cannot be modified once the Master_TIMER is enabled.
Page 513: Figure 19-4. Counter Behavior In Single Pulse Mode
GD32E50x User Manual In single pulse mode, after setting the bit MTCEN in SHRTIMER_MTCTL0 register, the first reset event will start the counter. When counting up to the counter-reload value, the counter stops and generates a period event. Then the other reset event will reset and restart the counter.
Page 514: Figure 19-6. Repetition Counter Behavior In Continuous Mode
GD32E50x User Manual Repetition counter When MTCEN bit in SHRTIMER_MTCTL0 register is set to 1, the repetition counter load the value of SHRTIMER_MTCREP register. The repetition counter is decremented when the counter is cleared due to either a roll-over event in continuous mode or a reset event. When the repetition counter has reached zero, the coming roll-over event in continuous mode or reset event will generate a repetition event and reload the value of SHRTIMER_MTCREP register.
Page 515: Figure 19-8. Repetition Counter Behavior In Single Pulse Mode With Cntrstm = 1
GD32E50x User Manual shows repetition counter operation diagram in single pulse mode with CNTRSTM = 1. Figure 19-8. Repetition counter behavior in single pulse mode with CNTRSTM = 1 MTCEN or STxCEN(x=0..4) Reset event CARL CARL Counter when CTNM = 0 CNTRSTM = 1 CREP[7:0] 0x03...
Page 516: Table 19-3. Master_Timer Shadow Registers And Update Event
GD32E50x User Manual the counter value matches the compare registers value, a coincident compare event is generated. The compare event will set the corresponding compare interrupt flag to 1 (CMPxIF bit in SHRTIMER_MTINTF where x=0..3), and a compare interrupt or DMA request is issued if enabled (CMPxIE = 1 or CMPxDEN = 1 bits in SHRTIMER_MTDMAINTEN register where x=0..3).
Page 517 GD32E50x User Manual Table 19-3. Master_TIMER shadow registers and update event Registers Shadow registers Update event. that contain shadow registers enable bit SHRTIMER_MTDMAINTEN Software(MTSUP bit) SHRTIMER_MTCAR Repetition event(UPREP = 1) DMA mode end SHRTIMER_MTCREP SHWEN bit in event(UPSEL[1:0] = 2’b01) SHRTIMER_MT SHRTIMER_MTCMP0V CTL0 register...
Page 518: Slave_Timerx(X=0
GD32E50x User Manual Slave_TIMERx(x=0..4) unit 19.4.2. The SHRTIMER has 5 slave timers with similar structure: Slave_TIMERx(x=0..4). Each unit is built around the following components:  16-bit counter.  Auto reload register: counting period.  Repetition counter. Compare y (y=0..3) register. ...
Page 519: Table 19-4. The Limitations Of Counter And Capture Y(Y=0,1) Value Registers
GD32E50x User Manual counter clock division below 64 (CNTCKDIV[3:0] < 4’b0101 or CNTCKDIV[3:0] =4’b1000), Table the least significant bits are not significant. They cannot be written and read 0. Refer to 19-4. The limitations of counter and capture y(y=0,1) value registers. Table 19-4.
Page 520 GD32E50x User Manual the SHRTIMER_STxCAR register. There are two counter operating modes: single pulse mode (CTNM = 0 in SHRTIMER_STxCTL0 register) and continuous mode (CTNM = 1 in SHRTIMER_STxCTL0 register). In single pulse mode, after setting the bit STxCEN in SHRTIMER_MTCTL0 register, the first reset event will start the counter.
Page 521 GD32E50x User Manual All these sources are logical ORed, they can be valid simultaneously. If multiple reset events occur in the same t cycle, only the last one is valid. The counter reset requests are SHRTIMER_CK taken into account only once the related Slave_TIMERx are enabled Note: If the external events is configured with level sensitivity, only one external events can be enabled in the SHRTIMER_STxCNTRST register.
Page 522: Figure 19-11. Capture 0 Triggered By Exev0 And Exev1
GD32E50x User Manual The capture 0 trigger events are defined in SHRTIMER_STxCAP0TRG register and the capture 1 trigger events are defined in SHRTIMER_STxCAP1TRG register. All the trigger events are logical ORed and they are all valid when multiple trigger events are selected. Note: If the external events is configured with level sensitivity, only one external events can be enabled in the SHRTIMER_STxCAPyTRG(y=0,1) register.
Page 523: Figure 19-12．Compare 1 Behavior With Stxcar=0X8, Stxcmp1V=0X02
GD32E50x User Manual Figure 19-12．Compare 1 behavior with STxCAR=0x8, STxCMP1V=0x02 Cleared by CMP1IFC Cleared by CMP1IFC Half mode When HALFM bit in SHRTIMER_STxCTL0 is set to 1, the half mode is enabled. This mode forces the value of compare 0 active register to be half of the counter-reload value, but the value of SHRTIMER_STxCMP0V register is not updated with the SHRTIMER_MTCAR/2 value.
Page 524: Figure 19-14. Compare 1 Delayed Mode 0
GD32E50x User Manual generated. Once the relative capture is triggered, the value in compare y active register is summed with the relative SHRTIMER_STxCAP0V/ SHRTIMER_STxCAP1V, and it is compared to the counter. Compare 1 is associated with capture 0 and compare 0/2, while compare 3 is associated with capture 1 and compare 0/2.
Page 525: Figure 19-15. Compare 1 Delayed Mode 1
GD32E50x User Manual Compare 1 event occurs as soon as the counter value is equal to the recomputed compare 1 value. If capture 0 trigger occurs first, the later compare 0 event is ignored. If compare 0 event occurs first, the capture 0 trigger after the compare 1 event is ignored. Refer to Figure 19-15.
Page 526: Figure 19-16. Compare Delayed Mode With Shwen = 0
GD32E50x User Manual Figure 19-16. Compare delayed mode with SHWEN = 0 MTCEN or STxCEN(x=0..4) previous+ C1 C2+ C1 update event Counter when CTNM = 1 Preload=previous Active=previous + C1 Capture event C a p t u r e C a p t u r e previous register register...
Page 527: Figure 19-18. O0Pre Wave: Set On Cmp0, Reset On Cmp1
GD32E50x User Manual Output prepare signal Slave_TIMERx has a set/reset output module. The module can generate two output prepare signals: O0PRE and O1PRE. O0PRE is controlled by SHRTIMER_STxCH0SET and SHRTIMER_STxCH0RST registers. O1PRE is controlled by SHRTIMER_STxCH1SET and SHRTIMER_STxCH1RST registers. The high level of OyPRE(y=0,1) is active level, while the low level is inactive level.
Page 528: Table 19-5. Slave_Timer Interconnection Event
GD32E50x User Manual Slave_TIMERx interconnection event: there are 9 interconnect events from other  Slave_TIMERy (for instance x=1, then y=0, 2..4). Refer to Table 19-5. Slave_TIMER interconnection event External event y(y=0..9): EXEVy conditioned by external event filter in Slave_TIMERx  ...
Page 529: Figure 19-19. Arbitration Mechanism During Each T
GD32E50x User Manual Figure 19-19. Arbitration The arbitration process for each type of event is shown in mechanism during each tSHRTMER_CK period Figure 19-19. Arbitration mechanism during each t period SHRTMER_CK Arbiter0: Arbiter0: STx interconnection Arbiter1: only one event Arbiter1: Arbiter2: CMP3>...
Page 530: Figure 19-20． Arbitration Mechanism Example
GD32E50x User Manual are: From Master_TIMER: compare 0 event, compare 1 event. From Slave_TIMER0 itself: compare 3 event, period event. Interconnection event to Slave_TIMER0: interconnection event 7 (Slave_TIMER4 compare 2 event), interconnection event 8 (Slave_TIMER4 compare 3 event). Low-precision events: external event 2(EXEV2), external event 3(EXEV3) ...
Page 531: Figure 19-23. Super High-Resolution Oxpre Wave
GD32E50x User Manual Figure 19-21. A pulse of 1 t period SHRTMER_CK SHRTIMER_CK SHRTIMER_CK OxPRE postponed super high- resolution SHRTIMER_CK OxPRE super high- anticipated resolution super high- OxPRE postponed resolution SHRTIMER_CK super high- OxPRE SHRTIMER_CK resolution anticipated Legend: set request reset request If the “set and reset requests”...
Page 532: Figure 19-24. Oxpre Wave With Cntckdiv[3:0] = 4'B0110
GD32E50x User Manual active edge of the SHRTIMER_PSCCK, even if the arbitration is still performed every cycle. SHRTIMER_CK When “set and reset requests” from different event sources simultaneously occur in a tSHRTIMER_CK cycle, the “reset request” has the highest priority. In SHRTIMER_PSCCK cycle, subsequent requests override previous requests, and only the last request of that cycle Figure 19-24.
Page 533 GD32E50x User Manual O0PRE will be set to high level. SHRTIMER_STxCH0RST = 0x0000 0010: compare 1 event produces “reset request”  and O0PRE will be set to low level.  SHRTIMER_STxCMP0V = 0x0060  SHRTIMER_STxCMP1V = 0x00E0 Figure 19-25. C0OPRE wave in regular mode SHRTIMER_CK 0x00 0x20...
Page 534: Figure 19-26. C0Opre And C1Opre Complementary Wave With De Ad-Time
GD32E50x User Manual When the Slave_TIMERx(x=0..4) runs in the RUN or IDEL state and the C0OPRE goes from active to inactive level, CH0ONAIF bit in SHRTIMER_STxINTF register will be set to 1, and a output inactive interrupt or a DMA request is issued if enabled (CH0ONAIE = 1 or CH0ONADEN = 1 bit in SHRTIMER_STxDMAINTEN register).
Page 535: Figure 19-28. Structure Chart In Balanced Mode
GD32E50x User Manual Figure 19-27. Complementary wave with pulse width less than dead-time O0PRE O0PRE DTRCFG[15:0] DTRCFG[15:0] DTRCFG[15:0] Skip dead-time C0OPRE C0OPRE following rising DTRS = 0 DTRS = 0 DTFS = 0 DTFCFG[15:0] DTFCFG[15:0] DTFS = 0 DTFCFG[15:0] Skip dead-time C1OPRE following falling C1OPRE...
Page 536: Figure 19-29. C0Opre And C1Opre Wave In Balanced Mode
GD32E50x User Manual inactive level (low level). When the output of toggle logic module is 0(low level), C1OPRE is connected to O1PRE and C0OPRE is set to inactive level (low level). It is advised to make SHRTIMER_STxCH0SET = SHRTIMER_STxCH1SET and SHRTIMER_STxCH0RST = SHRTIMER_STxCH1RST, in order to achieve a balanced operation with identical waveforms.
Page 537: Table 19-6. Crossbar And Idle Control Stage Work Together
GD32E50x User Manual Figure 19-29. C0OPRE and C1OPRE wave in balanced mode SHRTIMER_CK 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 Counter Compare 0 previous Preload=0x0080/Active=0x0080 register...
Page 538: Table 19-7. Request To Enter In Idle And Exit Idle State
GD32E50x User Manual Table 19-7. Request to enter in IDLE and SHRTIMER_STxCHOCTL register. Refer to exit IDLE state. ISOy define the CHyOPRE level in IDLE state. The IDLE mode is permanently maintained but the counter continues to run, until the output is re-enabled to exit delayed IDLE.
Page 539: Figure 19-30. Iso0 = 0 And Chop = 0 In Delayed Idle
GD32E50x User Manual Figure 19-30. ISO0 = 0 and CHOP = 0 in delayed IDLE SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 0 CH0P = 0 CH0OPRE RUN State RUN State IDLE State re-enable EXEV6 ISO0 = 0 CH0P = 0 CH0OPRE...
Page 540: Figure 19-32. Iso0 = 0 And Chop = 1 In Delayed Idle
GD32E50x User Manual Figure 19-32. ISO0 = 0 and CHOP = 1 in delayed IDLE SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 0 CH0P = 1 CH0OPRE RUN State RUN State IDLE State re-enable EXEV6 ISO0 = 0 CH0P = 1 CH0OPRE...
Page 541: Figure 19-34. Balanced Idel With Iso0 = 0 And Iso1 = 0
GD32E50x User Manual When the selected event arrives, the CHyOPRE (y=0,1) enters IDLE state and takes the level defined by ISOy bits in the SHRTIMER_STxCHOCTL register. Meanwhile the DLYIIF in SHRTIMER_STxINTF register is set to 1.The selected external event triggers a capture of the counter value into the compare 3 active register (this value is not user-accessible).
Page 542: Table 19-8. Output During Idel State Controlled By Bunch Mode
GD32E50x User Manual Balanced IDLE can be used together with the bunch mode under the following conditions:  BMSTx bit must be reset (counter clock(SHRTIMER_PSCCK) is maintained and the counter operates normally)  No balanced IDLE are triggered while the outputs are in IDLE state controlled by bunch mode.
Page 543: Figure 19-35. Stxchy_O Wave With Chyp=0 Or Chyp=1
GD32E50x User Manual Table 19-9. Output stage status programming (x=0..4, y=0,1) STxCHyEN STxCHyDISF output stage status Run state Idle state Fault state Note: “×” means “0/1”. Writing 1 to STxCHyDIS in SHRTIMER_CHOUTDIS register will disable output and make output stage enters the Idle state. The priority order of the three states is: Idle state > Fault state >...
Page 544: Figure 19-36. Carrier-Signal Structure Diagram
GD32E50x User Manual 19-36. Carrier-signal structure diagram. Figure 19-36. Carrier-signal structure diagram Carrier-signal generator 0 CH0CSEN Carrier-signal generator 1 O0PRE CH1CSEN SHRTIMER_CSGCK O1PRE prescaler: CH1CSEN/ CH0CSEN SHRTIMER_CK IDLE CH0OPRE CH1OPRE In carrier-signal mode, it is possible to define a specific pulse width before the beginning of the carrier-signal.
Page 545: Figure 19-37. Shrtimer Output With Carrier-Signal Mode Enabled
GD32E50x User Manual (logic ANDed). The carrier-signal signal is stopped as soon as the OyPRE(y=0,1) is inactive, Figure 19-37. SHRTIMER even if the current carrier period is not completed. Refer to output with carrier-signal mode enabled. Figure 19-37. SHRTIMER output with carrier-signal mode enabled Compare 1 active value Slave_TIMER0...
Page 546: Table 19-10. Slave_Timerx Shadow Registers And Update Event
GD32E50x User Manual active register and take effect immediately on update event. Table 19-10. Slave_TIMERx shadow registers and update event lists the registers that contain shadow registers and corresponding update events. Table 19-10. Slave_TIMERx shadow registers and update event Registers Shadow registers Update event.
Page 547: Figure 19-38. Blanking Mode And Windowing Mode
GD32E50x User Manual  Windowing mode: external events that occur within a specified time are taken into account. Figure 19-38. Blanking mode and windowing mode Refer to Figure 19-38. Blanking mode and windowing mode EXEVyC EXEVyC EXEVy EXEVy Blanking mode Windowing mode Windowing signal Blanking signal...
Page 548: Table 19-13. Filtering Signals Mapping In Windowing Mode
GD32E50x User Manual Slave_TIMER Slave_TIMER Slave_TIMER Slave_TIMER Slave_TIMER From compare 0 compare 0 CH1OPRE compare 1 compare 3 STBLKSRC4 Slave_TIMER2 Slave_TIMER2 Slave_TIMER3 Slave_TIMER2 Slave_TIMER2 compare 3 compare 1 compare 0 CH1OPRE CH1OPRE STBLKSRC5 Slave_TIMER2 Slave_TIMER2 Slave_TIMER3 Slave_TIMER4 Slave_TIMER3 CH1OPRE CH1OPRE compare 3 compare 0 compare 0...
Page 549: Dll Calibrate
GD32E50x User Manual DAC trigger When the Slave_TIMERx update event occurs with DACTRGS[1:0] != 2’b00 in SHRTIMER_STxCTL0 register, a DAC trigger request can be generated SHRTIMER_DACTRIGOy(y=0..3). If DACTRGS[1:0] = 2’b00 in SHRTIMER_STxCTL0 register, Slave_TIMERx won’t generate trigger request. SHRTIMER_DACTRIGOy(y=0..3) is the internal signal connected from Slave_TIMERx to the DAC module.
Page 550: Figure 19-39. Bunch Mode Timing Chart
GD32E50x User Manual the counter-reload value (SHRTIMER_BMCAR), the BM-counter is stopped. When counts up to the counter-reload value (SHRTIMER_BMCAR), BMPERIF in SHRTIMER_INTF register is set to 1 and bunch mode controller generates a bunch mode period interrupt request if BMPERIE=1 in SHRTIMER_INTEN register. The BMPERIF bit can be cleared by writing 1 to BMPERIFC bit in SHRTIMER_INTC register.
Page 551: Figure 19-40. Regular Entry For Bunch Mode
GD32E50x User Manual the SHRTIMER_BMCMPV compare register is written. Bunch mode entry There are 32 events defined in SHRTIMER_BMSTRG register can be used to trigger the bunch mode operation. These trigger events can be selected simultaneously and are logic ORed. During BM-counter counting process, these trigger events are ignored. These trigger events are divided into seven categories: 1.
Page 552 GD32E50x User Manual Figure 19-40. Regular entry for bunch mode Compare 1 active value Slave_TIMER0 OyPRE(y=0,1) EXEV Bunch mode termination. CHyOPRE(y=0,1) IDLE in bunch mode RUN in bunch mode ISOy=0 RUN state Bunch mode operation RUN state EXEV Bunch mode termination.
Page 553: Figure 19-41. Delayed Entry For Bunch Mode
GD32E50x User Manual Figure 19-41. Delayed entry for bunch mode Compare 1 active value Slave_TIMER0 Slave_TIMER0 O0PRE O0PRE Bunch mode EXEV termination. RUN in bunch mode Rrising Rrising Rrising dead-time dead-time IDLE in bunch mode Rrising dead-time dead-time CH0OPRE CH0OPRE ISO0 = 0 Entry arrives not during ISO0 = 0...
Page 554: Synchronization Input/Output
GD32E50x User Manual Period event is used to produce “set request”.  Write two 32-bit data to the SHRTIMER_STxCMP0CP register consecutively using DMA  (upon repetition event), as below: SHRTIMER_STxCMP0CP = {CREP[7:0] = (RUN number of periods - 1); CMP0VAL[15:0] = duty cycle} SHRTIMER_STxCMP0CP = {CREP[7:0] = (IDLE number of periods - 1);...
Page 555: External Event
GD32E50x User Manual is re-started after having reached the period value in single pulse mode, a reset which occurs during the counting with CTNM or CNTRSTM bits set to 1.  2’b01: Master_TIMER compare 0 event  2’b10: Slave_TIMER0 reset and start event. It is similar to Master_TIMER start event, except for the following: counter roll-over in continuous mode, discarded reset request in single pulse mode with CNTRSTM=0.
Page 556: Figure 19-43. Extern Event Y(Y=0..4) Processed Diagram
GD32E50x User Manual external event y(y=5..9) are configured using the SHRTIMER_EXEVCFG0 and SHRTIMER_EXEVDFCTL registers. The process by which external event y(y=0..4) are processed is shown in Figure 19-43. Extern event y(y=0..4) processed diagram. Figure 19-43. Extern event y(y=0..4) processed diagram configuration of external event y(y=0..4) is as follows:...
Page 557: Fault Input
GD32E50x User Manual The digital filters sampling clock f is defined with EXEVFDIV[2:0] bit-field in SHRTIMER_EXEVFCK SHRTIMER_EXEVDFCTL register. These external events sources EXEVySRCz(y=0..9,z=0..4) can come from comparators, digital input pins, ADC’s analog watchdogs and TIMER_TRGO. Refer to Table 19-15. External events mapping. Table 19-15.
Page 558: Table 19-16. Fault Channel Mapping
GD32E50x User Manual Figure 19-45. Fault input diagram Fault channel Fault channel FLTyINEN Digital Digital chip external pin Filter Filter comparator FLTyINP FLTyINP FLTyINSRC FLTyINSRC FLTyINFC[3:0] FLTyINFC[3:0] FLTyEN SystemFault Channel output stage Channel output stage STxCH0_O Idle STxCH1_O CH0P/ CH0P/ CH1P Fault output state CH1P...
Page 559: Trigger To Adc
GD32E50x User Manual Fault channel FLTyINSRC = 0 (input pin) FLTyINSRC = 1(com parator) Fault channel 4 PC7/PG10 Note: “×” means not available. The polarity of the signal can be configured by the FLTyINP polarity bit in SHRTIMER_FLTINCFG0 and SHRTIMER_FLTINCFG1 registers. If FLTyINP = 0, the signal is active at low level;...
Page 560: Trigger To Dac
GD32E50x User Manual Figure 19-46. Trigger to ADC selection overview SHRTIMER SHRTIMER_ADCTRIG0 SHRTIMER_ADCTRIGS0 SHRTIMER_ADCTRIGS1 SHRTIMER_ADCTRIG1 SHRTIMER_ADCTRIG2 SHRTIMER_ADCTRIGS2 SHRTIMER_ADCTRIGS3 SHRTIMER_ADCTRIG3 There are up to 32 events which can be combined (ORed) for each trigger output. They are defined in SHRTIMER_ADCTRIGSy(y=0..3) registers. SHRTIMER_ADCTRIGSy(y=0..3) registers are preloaded and can be updated synchronously with the timer they are related to.
Page 561: Interrupt
GD32E50x User Manual Figure 19-47. Trigger to DAC selection overview Master_TIMER No trigger Update event SHRTIMER_DACTRIG0 DACTRGS[1:0] in SHRTIMER_MTCTL0 SHRTIMER_DACTRIG1 Slave_TIMERx No trigger SHRTIMER_DACTRIG2 Update event DACTRGS[1:0] in SHRTIMER_STxCTL0 Interrupt 19.4.10. Most events can generate interrupt requests. All interrupt requests are grouped in 7 vectors (SHRTIMER_IRQy,y=0..6).Refer to Table 19-17.
Page 562: Dma Request
GD32E50x User Manual Interrupt Num ber Event Control bit Repetition event REPIE in SHRTIMER_STx DMA INTEN Slave_TIMER4: Compare 3 event CMP3IE in SHRTIMER_STx DMA INTEN SHRTIMER_IRQ5 Compare 2 event CMP2IE in SHRTIMER_STx DMA INTEN Compare 1 event CMP1IE in SHRTIMER_STx DMA INTEN Compare 0 event CMP0IE in SHRTIMER_STx DMA INTEN Bunch mode period event...
Page 563: Dma Mode
GD32E50x User Manual DMA mode 19.4.12. Timer’s DMA mode is the function that configures SHRTIMER’s multiple registers by DMA module with a single DMA request. The relative registers (7 registers in total) are as follows:  SHRTIMER_DMAUPMTR: Defines which registers in the Master_TIMER are updated. Most of Master_TIMER control and data registers are associated with a selection bit.
Page 564: Debug Mode
GD32E50x User Manual Figure 19-48. DMA mode operation flowchart The DMA request to write SHRTIMER_DMATB Parse SHRTIMER_DMAUPSTyR(Y=1..3) register and The process is similar to Parse SHRTIMER_DMAUPST0R register Data is transferred to Data is transferred to MTCTL0 bit SHRTIMER_MTCTL0 ST0CTL0bit SHRTIMER_ST0CTL0 and trigger a new DMA is 1? is 1?
Page 565: Master_Timer Registers
GD32E50x User Manual The registers can be segmented for ease of addressing： SHRTIMER Master_TIMER registers base address: 0x4001 7400 SHRTIMER Slave_TIMER0 registers base address: 0x4001 7480 SHRTIMER Slave_TIMER1 registers base address: 0x4001 7500 SHRTIMER Slave_TIMER2 registers base address: 0x4001 7580 SHRTIMER Slave_TIMER3 registers base address: 0x4001 7600 SHRTIMER Slave_TIMER4 registers base address: 0x4001 7680 SHRTIMER Common registers base address: 0x4001 7780...
Page 566 GD32E50x User Manual Note: UPREP can be set only if UPSEL[1:0] = 2’b00 or 2’b01. Reserved Must be kept at reset value SHWEN Shadow registers enable 0: The shadow registers are disabled 1: The shadow registers are enabled 26:25 DACTRGS[1:0] Trigger source to DAC The timer can also generate a DAC trigger event w hen an update event occurs.
Page 567 GD32E50x User Manual This bit-field specifies the event to be sent to the synchronization output pad SHRTIMER_SCOUT. 00: Master_TIMER start event. 01: Master_TIMER compare 0 event 10: Slave_TIMER0 reset and start event 11: Slave_TIMER0 compare 0 event 13:12 SYNOPLS[1:0] Synchronization output pulse This bit-field specifies...
Page 568 GD32E50x User Manual 1: The counter can be reset at any time (running or stopped). CTNM Continuous mode 0: Single pulse mode. The counter stops by hardw are w hen it reaches the SHRTIMER_MTCA R value. 1: Continuous mode. The counter rolls over to zero and count continuously w hen it reaches the SHRTIMER_MTCA R value CNTCKDIV[2:0] Counter clock division...
Page 569 GD32E50x User Manual This flag is set by hardw are w hen an update event occurs. 0: No update interrupt occurred 1: Update interrupt occurred SYNIIF Synchronization input interrupt flag This flag is set by hardw are w hen synchronization input occurs. 0: No synchronization input interrupt occurred 1: Synchronization input interrupt occurred REPIF...
Page 570 GD32E50x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value UPIFC Clear update interrupt flag 0: No effect 1: Clear update interrupt flag SYNIIFC Clear synchronization input interrupt flag 0: No effect 1: Clear synchronization input interrupt flag REPIFC Clear repetition interrupt flag 0: No effect...
Page 571 GD32E50x User Manual Bits Fields Descriptions 31:23 Reserved Must be kept at reset value UPDEN Update DMA request enable 0: disabled 1: enabled SYNIDEN Synchronization input DMA request enable 0: disabled 1: enabled REPDEN Repetition DMA request enable 0: disabled 1: enabled CMP3DEN Compare 3 DMA request enable...
Page 572 GD32E50x User Manual 1: enabled CMP2IE Compare 2 interrupt enable 0: disabled 1: enabled CMP1IE Compare 1 interrupt enable 0: disabled 1: enabled CMP0IE Compare 0 interrupt enable 0: disabled 1: enabled SHRTIMER Master_TIMER counter register (SHRTIMER_MTCNT) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved...
Page 573 GD32E50x User Manual This register has to be accessed by word (32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter. This register has a shadow register.
Page 574 GD32E50x User Manual shadow register. SHRTIMER Master_TIMER compare 0 value register (SHRTIMER_MTCMP0V) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CMP0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP0VAL[15:0] Compare 0 value...
Page 575 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP1VAL[15:0] Compare 1 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 576 GD32E50x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CMP3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP3VAL[15:0] Compare 3 value This bit-field contains value to be compared to the counter. This register has a shadow register.
Page 577: Slave_Timerx Registers(X=0
GD32E50x User Manual super high resolution clock (SHRTIMER_HPCK) the counter clock (SHRTIMER_PSCCK). When the CNTCKDIV[3] is ‘0’, f CNTCKDIV[2:0]+1 SHRTIMER_PSCCK SHRTIMER_HPCK When the CNTCKDIV[3] bit in the SHRTIMER_MTACTL is ‘1’ and CNTCKDIV[2:0] can only be configured w ith ‘3’b000’: f SHRTIMER_PSSCK SHRTIMER_HPCK Note: The CNTCKDIV[3:0] bit-field cannot be modified once the timer is enabled...
Page 578 GD32E50x User Manual 0110: Update event generated on the update event follow ing the rising edge of STxUPIN0. 0111: Update event generated on the update event follow ing the rising edge of STxUPIN1. 1000: Update event generated on the update event follow ing the rising edge of STxUPIN2.
Page 579 GD32E50x User Manual Note: This bit does not exist in Slave_TIMER3. UPBST2 Update by Slave_TIMER2 update event When the bit is set, the Slave_TIMERx(x=0,1,3,4) update event are synchronized w ith Slave_TIMER2 update event and the active registers of them are updated by the Slave_TIMER2 update event 0: The active registers is not update by Slave_TIMER2.
Page 580 GD32E50x User Manual value for capture 1 event, or compare 3 active register value + compare 0 value for compare 0 event). Compare match occurs as soon as the counter equals the recalculated value. 11: Compare 3 delayed mode 2. After a capture 1 event or compare 2 event, the recalculated value of compare 3 is: (compare 3 active register value + capture 1 value for capture 1 event, or compare 3 active register value + compare 2 value for compare 2 event).
Page 581 GD32E50x User Manual in SHRTIMER_MTCTL0 register). HALFM Half mode When the bit is set, SHRTIMER_STx CMP0V active register is alw ays the half of counter auto-reload value (SHRTIMER_STx CAR). 0: Half mode disable. 1: Half mode enable. CNTRSTM Counter reset mode This bit defines the behavior of the timer counter in single pulse mode.
Page 582 GD32E50x User Manual Reserved CH1F CH0F Reserved BLNIF CBLNF CH1ONAI CH0ONAI Reserved DLYIIF RSTIF CH1OAIF CH0OAIF CAP1IF CAP0IF UPIF Reserved REPIF CMP3IF CMP2IF CMP1IF CMP0IF Bits Fields Descriptions 31:22 Reserved Must be kept at reset value CH1F Channel 1 output flag This bit indicates the output level state of channel 1.
Page 583 GD32E50x User Manual 0: No counter reset or roll-over interrupt occurred 1: Counter reset or roll-over interrupt occurred CH1ONAIF Channel 1 output inactive interrupt flag Refer to CH0ONAIF description. CH1OAIF Channel 1 output active interrupt flag Refer to CH0OAIF description. CH0ONAIF Channel 0 output inactive interrupt flag This flag is set by hardw are w hen channel 0 output inactive (C0OPRE from active...
Page 584 GD32E50x User Manual This flag is set by hardw are w hen a compare 2 event occurs. 0: No compare 2 interrupt occurred 1: Compare 2 interrupt occurred CMP1IF Compare 1 interrupt flag This flag is set by hardw are w hen a compare 1 event occurs. 0: No compare 1 interrupt occurred 1: Compare 1 interrupt occurred CMP0IF...
Page 585 GD32E50x User Manual Clear CH1OAIF in SHRTIMER_STx INTF register. Refer to CH0OAIFC description. CH0ONAIFC Clear channel 0 output inactive interrupt flag 0: No effect Clear channel output inactive interrupt flag (CH0ONAIF SHRTIMER_STx INTF register) CH0OAIFC Clear channel 0 output active interrupt flag 0: No effect 1: Clear channel 0 output inactive interrupt flag (CH0OAIF in SHRTIMER_STx INT F register)
Page 586 GD32E50x User Manual SHRTIMER Slave_TIMERx interrupt enable register (SHRTIMER_STxDMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) CH1ONAD CH1OADE CH0ONAD CH0OADE Reserved DLYIDEN RSTDEN CAP1DEN CAP0DEN UPDEN Reserved REPDEN CMP3DEN CMP2DEN CMP1DEN CMP0DEN CH1ONAI CH0ONAI Reserved...
Page 587 GD32E50x User Manual 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value REPDEN Repetition DMA request enable 0: disabled 1: enabled CMP3DEN Compare 3 DMA request enable 0: disabled 1: enabled CMP2DEN Compare 2 DMA request enable 0: disabled...
Page 588 GD32E50x User Manual 1: enabled CAP1IE Capture 1 interrupt enable 0: disabled 1: enabled CAP0IE Capture 0 interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value REPIE Repetition interrupt enable 0: disabled 1: enabled CMP3IE...
Page 589 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] The current counter value. Writing to it can change the value of the counter only w hen the Slave_TIMERx is stopped (STxCEN = 0 in SHRTIMER_STx CTL0 register). Note: (1) For counter clock division below 64 (CNTCKDIV[3:0] <...
Page 590 GD32E50x User Manual SHRTIMER Slave_TIMERx counter repetition register (SHRTIMER_STxCREP) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-field specifies the repetition event generation rate.
Page 591 GD32E50x User Manual 0), it holds the content of the active register; otherw ise, it holds the content of the shadow register. Note: (1) The minimum value must be greater than or equal to 3 t . For example: SHRTIMER_CK CARL[15:0] >= 0x60 w hen CNTCKDIV[3:0] = 4’b0000.
Page 592 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP1VAL[15:0] Compare 1 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 593 GD32E50x User Manual SHRTIMER Slave_TIMERx compare 3 value register (SHRTIMER_STxCMP3V) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CMP3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP3VAL[15:0] Compare 3 value This bit-field contains value to be compared to the counter.
Page 594 GD32E50x User Manual 31:16 Reserved Must be kept at reset value 15:0 CAP0VAL[15:0] Capture 0 value This bit-field indicates the counter value corresponding to the last capture event. And this bit-field is read-only. Note: For counter clock division below 64 (CNTCKDIV[3:0] < 5), the least significant bits of the counter are not significant.
Page 595 GD32E50x User Manual DTRSVP DTRSPR DTGCKDIV[3:0] DTRS DTRCFG[8:0] Bits Fields Descriptions DTFSVPROT Dead-time falling edge protection for value and sign This bit-field specifies the w rite protection for dead-time falling edge (value and sign). 0: Protect disable. DTFS and DTFCFG[15:0] are w ritable. 1: Protect enable.
Page 596 GD32E50x User Manual DTRSPROT Dead-time rising edge protection for sign This bit-field specifies the w rite protection for dead-time rising edge (only sign). 0: protect disable. DTRS in SHRTIMER_STx DTCTL register is w ritable. 1: protect enable. DTRS in SHRTIMER_STx DTCTL register is read-only. Note: This bit is not preloaded 13:10 DTGCKDIV[3:0]...
Page 597 GD32E50x User Manual SHRTIMER Slave_TIMERx channel request register (SHRTIMER_STxCH0SET) Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SEXE CH0SSTE CH0SSTE CH0SSTE CH0SSTE CH0SSTE CH0SUP CH0SST CH0SSTE CH0SSTE...
Page 598 GD32E50x User Manual Refer to CH0SEXEV0 description. External event 0 generates channel 0 “set request” CH0SEXEV0 When this bit is set, external event 0 can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”. Slave_TIMERx interconnection event 8 generates channel 0 “set request”...
Page 599 GD32E50x User Manual 1: The event can generate “set request”. Master_TIMER compare 0 event generates channel 0 “set request” CH0SMTCMP0 When this bit is set, Master_TIMER compare 0 event can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”.
Page 600 GD32E50x User Manual set, it can generate channel 0 “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”. Note: This bit is not preloaded SHRTIMER Slave_TIMERx channel reset request register (SHRTIMER_STxCH0RST) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) CH0RSU...
Page 601 GD32E50x User Manual External event 3 generates channel 0 “reset request” CH0RSEXEV3 Refer to CH0RSEXEV0 description. External event 2 generates channel 0 “reset request” CH0RSEXEV2 Refer to CH0RSEXEV0 description. External event 1 generates channel 0 “reset request” CH0RSEXEV1 Refer to CH0RSEXEV0 description. External event 0 generates channel 0 “reset request”...
Page 602 GD32E50x User Manual When this bit is set, Master_TIMER compare 2 event can generate channel “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Master_TIMER compare 1 event generates channel 0 “reset request” CH0RSMTCMP1 When this bit is set, Master_TIMER compare 1 event can generate channel “reset request”.
Page 603 GD32E50x User Manual Slave_TIMERx period event generates channel 0 “reset request” CH0RSPER When this bit is set, Slave_TIMERx period event can generate channel “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Slave_TIMERx reset event generates channel 0 “reset request” CH0RSRST When this bit is set, Slave_TIMERx reset event from synchronous input and softw are can generate channel “reset request”.
Page 604 GD32E50x User Manual Refer to CH1SEXEV0 description. External event 8 generates channel 1 “set request” CH1SEXEV8 Refer to CH1SEXEV0 description. External event 7 generates channel 1 “set request” CH1SEXEV7 Refer to CH1SEXEV0 description. External event 6 generates channel 1 “set request” CH1SEXEV6 Refer to CH1SEXEV0 description.
Page 605 GD32E50x User Manual Slave_TIMERx interconnection event 1 generates channel 1 “set request” CH1SSTEV1 Refer to CH1SSTEV0 description. Slave_TIMERx interconnection event 0 generates channel 1 “set request” CH1SSTEV0 When this bit is set, Slave_TIMERx interconnection event 0 can generate “set request”. Refer to Table 19-5.
Page 606 GD32E50x User Manual 0: The event cannot generate “set request”. 1: The event can generate “set request”. Slave_TIMERx compare 0 event generates channel 1 “set request” CH1SCMP0 When this bit is set, Slave_TIMERx compare 0 event can generate “set request”. 0: The event cannot generate “set request”.
Page 607 GD32E50x User Manual Update event generates channel 1 “reset request” CH1RSUP When this bit is set, update event can generate “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. External event 9 generates channel 1 “reset request” CH1RSEXEV9 Refer to CH1RSEXEV0 description.
Page 608 GD32E50x User Manual Slave_TIMERx interconnection event 3 generates channel 1 “reset request” CH1RSSTEV3 Refer to CH1RSSTEV0 description. Slave_TIMERx interconnection event 2 generates channel 1 “reset request” CH1RSSTEV2 Refer to CH1RSSTEV0 description. Slave_TIMERx interconnection event 1 generates channel 1 “reset request” CH1RSSTEV1 Refer to CH1RSSTEV0 description.
Page 609 GD32E50x User Manual request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Slave_TIMERx compare 2 event generates channel 1 “reset request” CH1RSCMP2 When this bit is set, Slave_TIMERx compare 2 event can generate channel “reset request”.
Page 610 GD32E50x User Manual SHRTIMER Slave_TIMERx external event filter configuration register 0 (SHRTIMER_STxEXEVFCFG0) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEV4FM[3:0] EXEV4ME EXEV3FM[3:0] EXEV3ME EXEV2FM Reserved Reserved Reserved EXEV0ME EXEV1FM[3:0] EXEV1ME EXEV0FM[3:0] EXEV0M EXEV2FM[2:0] Reserved Reserved...
Page 611 GD32E50x User Manual Reserved Must be kept at reset value EXEV0FM[3:0] External event 0 filter mode In blanking mode, the external event is ignored if it occurs during a blank. In w indow ing mode, the external event is taken into account only if it occurs w ithin a given time w indow .
Page 612 GD32E50x User Manual SHRTIMER Slave_TIMERx external event filter configuration register 1 (SHRTIMER_STxEXEVFCFG1) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEV9FM[3:0] EXEV9ME EXEV8FM[3:0] EXEV8ME EXEV7FM Reserved Reserved Reserved EXEV7ME EXEV6FM[3:0] EXEV6ME EXEV5FM[3:0] EXEV5M EXEV7FM[2:0] Reserved Reserved...
Page 613 GD32E50x User Manual Reserved Must be kept at reset value EXEV5FM[3:0] External event 5 filter mode Refer to EXEV0FM[3:0] in SHRTIMER_STx EXEVFCFG0 description. EXEV5MEEN External event 0 memorized enable Refer to EXEV0MEEN in SHRTIMER_STx EXEV FCFG0 description. SHRTIMER Slave_TIMERx counter reset register (SHRTIMER_STxCNTRST) Address offset: 0x54 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 614 GD32E50x User Manual counter. 0: Slave_TIMER3 compare 0 event do not reset counter 1: Slave_TIMER3 compare 0 event resets counter ST2CMP3RST Slave_TIMER2 compare 3 event resets counter Refer to ST2CMP0RST description. ST2CMP1RST Slave_TIMER2 compare 1 event resets counter Refer to ST2CMP0RST description. ST2CMP0RST Slave_TIMER2 compare 0 event resets counter This bit specifies w hether the Slave_TIMER2 compare 0 event can reset the...
Page 615 GD32E50x User Manual Refer to EXEV0RST description. EXEV1RST External event 1 resets counter Refer to EXEV0RST description. EXEV0RST External event 0 resets counter This bit specifies w hether the External event 0 can reset the counter. 0: External event 0 do not reset counter. 1: External event 0 resets counter.
Page 616 GD32E50x User Manual ST4CMP3 ST4CMP1 ST4CMP0 ST3CMP3 ST3CMP1 ST3CMP0 ST2CMP3 ST2CMP1 ST2CMP0 ST0CMP3 ST0CMP1 ST0CMP0 EXEV9RS EXEV8RS EXEV7RS Reserved EXEV6R EXEV5RS EXEV4RS EXEV3RS EXEV2RS EXEV1RS EXEV0RS MTCMP3 MTCMP2 MTCMP1 MTCMP0 MTPERRS CMP3RST CMP1RST UPRST Reserved Bits Fields Descriptions Reserved Must be kept at reset value ST4CMP3RST Slave_TIMER4 compare 3 event resets counter Refer to ST4CMP0RST description.
Page 617 GD32E50x User Manual Refer to ST0CMP0RST description. ST0CMP1RST Slave_TIMER0 compare 1 event resets counter Refer to ST0CMP0RST description. ST0CMP0RST Slave_TIMER0 compare 0 event resets counter This bit specifies w hether the Slave_TIMER0 compare 0 event can reset the counter. 0: Slave_TIMER0 compare 0 event do not reset counter 1: Slave_TIMER0 compare 0 event resets counter EXEV9RST External event 9 resets counter...
Page 618 GD32E50x User Manual MTCMP0RST Master_TIMER compare 0 event resets counter This bit specifies w hether the Master_TIMER compare 0 event can reset the counter. 0: Master_TIMER compare 0 event do not reset counter 1: Master_TIMER compare 0 event resets counter MTPERRST Master_TIMER period event resets counter This bit specifies w hether the Master_TIMER period event can reset the counter.
Page 619 GD32E50x User Manual This bit specifies w hether the Slave_TIMER4 compare 0 event can reset the counter. 0: Slave_TIMER4 compare 0 event do not reset counter 1: Slave_TIMER4 compare 0 event resets counter ST3CMP3RST Slave_TIMER3 compare 3 event resets counter Refer to ST3CMP0RST description.
Page 620 GD32E50x User Manual EXEV6RST External event 6 resets counter Refer to EXEV0RST description. EXEV5RST External event 5 resets counter Refer to EXEV0RST description. EXEV4RST External event 4 resets counter Refer to EXEV0RST description. EXEV3RST External event 3 resets counter Refer to EXEV0RST description. EXEV2RST External event 2 resets counter Refer to EXEV0RST description.
Page 621 GD32E50x User Manual UPRST Slave_TIMER2 update event resets counter This bit specifies w hether the update event can reset the counter. 0: Update event do not reset counter 1: Update event resets counter Reserved Must be kept at reset value For Slave_TIMER3 ST4CMP3 ST4CMP1...
Page 622 GD32E50x User Manual Refer to ST1CMP0RST description. ST1CMP1RST Slave_TIMER1 compare 1 event resets counter Refer to ST1CMP0RST description. ST1CMP0RST Slave_TIMER1 compare 0 event resets counter This bit specifies w hether the Slave_TIMER1 compare 0 event can reset the counter. 0: Slave_TIMER1 compare 0 event do not reset counter 1: Slave_TIMER1 compare 0 event resets counter ST0CMP3RST Slave_TIMER0 compare 3 event resets counter...
Page 623 GD32E50x User Manual This bit specifies w hether the External event 0 can reset the counter. 0: External event 0 do not reset counter. 1: External event 0 resets counter. MTCMP3RST Master_TIMER compare 3 event resets counter Refer to MTCMP0RST description MTCMP2RST Master_TIMER compare 2 event resets counter Refer to MTCMP0RST description...
Page 624 GD32E50x User Manual EXEV6R EXEV5RS EXEV4RS EXEV3RS EXEV2RS EXEV1RS EXEV0RS MTCMP3 MTCMP2 MTCMP1 MTCMP0 MTPERRS CMP3RST CMP1RST UPRST Reserved Bits Fields Descriptions Reserved Must be kept at reset value ST3CMP3RST Slave_TIMER3 compare 3 event resets counter Refer to ST3CMP0RST description. ST3CMP1RST Slave_TIMER3 compare 1 event resets counter Refer to ST3CMP0RST description.
Page 625 GD32E50x User Manual ST0CMP0RST Slave_TIMER0 compare 0 event resets counter This bit specifies w hether the Slave_TIMER0 compare 0 event can reset the counter. 0: Slave_TIMER0 compare 0 event do not reset counter 1: Slave_TIMER0 compare 0 event resets counter EXEV9RST External event 9 resets counter Refer to EXEV0RST description.
Page 626 GD32E50x User Manual 1: Master_TIMER compare 0 event resets counter MTPERRST Master_TIMER period event resets counter This bit specifies w hether the Master_TIMER period event can reset the counter. 0: Master_TIMER period event do not reset counter 1: Master_TIMER period event resets counter CMP3RST Slave_TIMER4 compare 3 event resets counter Refer to CMP1RST description...
Page 627 GD32E50x User Manual … 1110: t = 15*t CSFSTPW SHRTIMER_CSGCK 1111: t = 16*t CSFSTPW SHRTIMER_CSGCK CSDTY[2:0] Carrier signal duty cycle This bit-field defines the duty cycle of carrier signal (except the first pulse) w hich is equal to CSDTY[2:0]/8. 000: 0%(only the first pulse is present).
Page 628 GD32E50x User Manual This bit reserved only in Slave_TIMER4. Refer to CP0BST0CMP0 description. CP0BST4NA Capture 0 triggered by ST4CH0_O output active to inactive transition This bit reserved only in Slave_TIMER4. Refer to CP0BST0NA description. CP0BST4A Capture 0 triggered by ST4CH0_O output inactive to active transition This bit reserved only in Slave_TIMER4.
Page 629 GD32E50x User Manual Refer to CP0BST0CMP0 description. CP0BST1NA Capture 0 triggered by ST1CH0_O output active to inactive transition This bit reserved only in Slave_TIMER1. Refer to CP0BST0NA description. CP0BST1A Capture 0 triggered by ST1CH0_O output inactive to active transition This bit reserved only in Slave_TIMER1. Refer to CP0BST0A description.
Page 630 GD32E50x User Manual Refer to CP0BEXEV0 description. CP0BEXEV3 Capture 0 triggered by external event 3 Refer to CP0BEXEV0 description. CP0BEXEV2 Capture 0 triggered by external event 2 Refer to CP0BEXEV0 description. CP0BEXEV1 Capture 0 triggered by external event 1 Refer to CP0BEXEV0 description. CP0BEXEV0 Capture 0 triggered by external event 0 When the bit is set, capture 0 is triggered by external event 0...
Page 631 GD32E50x User Manual Refer to CP1BST0CMP1 description. CP1BST4CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER4 This bit reserved only in Slave_TIMER4. Refer to CP1BST0CMP0 description. CP1BST4NA Capture 1 triggered by ST4CH0_O output active to inactive transition. This bit reserved only in Slave_TIMER4. Refer to CP1BST0NA description.
Page 632 GD32E50x User Manual CP1BST1CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER1 This bit reserved only in Slave_TIMER1. Refer to CP1BST0CMP0 description. CP1BST1NA Capture 1 triggered by ST1CH0_O output active to inactive transition This bit reserved only in Slave_TIMER1. Refer to CP1BST0NA description.
Page 633 GD32E50x User Manual Refer to CP1BEXEV0 description. CP1BEXEV4 Capture 1 triggered by external event 4 Refer to CP1BEXEV0 description. CP1BEXEV3 Capture 1 triggered by external event 3 Refer to CP1BEXEV0 description. CP1BEXEV2 Capture 1 triggered by external event 2 Refer to CP1BEXEV0 description. CP1BEXEV1 Capture 1 triggered by external event 1 Refer to CP1BEXEV0 description.
Page 634 GD32E50x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value BMCH1DTI Channel 1 dead-time insert in bunch mode In bunch mode, a dead-time can be inserted before output entering the IDLE state. 0: The output enter IDLE immediately. 1: Dead-time is inserted before entering the IDLE state.
Page 635 GD32E50x User Manual 16:13 Reserved Must be kept at reset value 12:10 DLYISCH[2:0] Delayed IDLE source and channel This bit-field specifies the source and channel on w hich the delayed IDLE state mode are enabled (DLYISMEN = 1). In SHRTIMER_STy CHOCTL(y=0,1,2) register: 000: channel 0 output delayed IDLE on external event 5 001: channel 1 output delayed IDLE on external event 5 010: channel 0 and channel 1 output delayed IDLE on external event 5...
Page 636 GD32E50x User Manual by DTRCFG[15:0] Note: (1) This bit must not be modified once the counter is enabled (STxCEN bit set). (2) This bit can be set only if one of the output idle state is active (ISO0 = 1, y=0,1) during IDLE in bunch mode, and the dead-time value is positive (DTFSPROT / DTRSPROT set to 0).
Page 637 GD32E50x User Manual This register has to be accessed by word(32-bit) FLTENP Reserved Reserved FLT4EN FLT3EN FLT2EN FLT1EN FLT0EN Bits Fields Descriptions FLTENPROT Protect fault enable This bit-field specifies w hether the w rite protection function is enable or not. This bit is w rite-once.
Page 638 GD32E50x User Manual DTFCFG[15:9] Reserved CNTCKDI DTRCFG[15:9] Reserved Reserved V[3] Bits Fields Descriptions 31:25 DTFCFG[15:9] Falling edge dead-time value configure This bit-field controls the value of the dead-time follow ing a falling edge of output prepare signal (OyPRE,y=0,1): DTFvalue = DTFCFG[15:0]x SHRTIMER_DTGCK = 1/ f SHRTIMER_DTGCK...
Page 639: Common Registers
GD32E50x User Manual Common registers 19.5.3. SHRTIMER Master_TIMER registers base address: 0x4001 7780 SHRTIMER control register 0 (SHRTIMER_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved ADTG3USRC[2:0] ADTG2USRC [2:0] ADTG1USRC [2:0] ADTG0USRC [2:0] Reserved ST4UPDIS ST3UPDIS ST2UPDIS ST1UPDIS ST0UPDIS MTUPDIS Bits...
Page 640 GD32E50x User Manual 000: Master_TIMER update event 001: Slaver_TIMER0 update event 010: Slaver_TIMER1 update event 011: Slaver_TIMER2 update event 100: Slaver_TIMER3 update event 101: Slaver_TIMER4 update event Other values are reserved 18:16 ADTG0USRC[2:0] SHRTIMER_A DCTRIG0 update source This bit-field can be configured by softw are to specify the the source to update the SHRTIMER_A DCTRIGS0 register.
Page 641 GD32E50x User Manual 0: Update event enable. 1: Update event disable. SHRTIMER control register 1 (SHRTIMER_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved ST4SRST ST3SRST ST2SRST ST1SRST ST0SRST MTSRST Reserved ST4SUP ST3SUP ST2SUP ST1SUP ST0SUP MTSUP Bits...
Page 642 GD32E50x User Manual bit is set, the counter is reset. 0: No effect. 1: The counter is reset. MTSRST Master_TIMER softw are reset This bit can be set by softw are, and cleared by hardw are automatically. When this bit is set, the counter is reset. 0: No effect.
Page 643 GD32E50x User Manual This bit can be set by softw are, and cleared by hardw are automatically. When this bit is set, the content of shadow register is transferred to the active register and any pending update request is cancelled. 0: No effect.
Page 644 GD32E50x User Manual FLT3IF Fault 3 interrupt flag Refer to FLT0IF description. FLT2IF Fault 2 interrupt flag Refer to FLT0IF description. FLT1IF Fault 1 interrupt flag Refer to FLT0IF description. FLT0IF Fault 0 interrupt flag This flag is set by hardw are w hen the fault 0 occurred. It is cleared by softw are w riting it at 1.
Page 645 GD32E50x User Manual Writing 1 to this bit clears the SYSFLTIF in SHRTIMER_INTF register. 0: No effect 1: Clear system fault completed interrupt flag FLT4IFC Clear fault 4 interrupt flag Writing 1 to this bit clears the FLT4IF in SHRTIMER_INTF register. Refer to FLT0IF description.
Page 646 GD32E50x User Manual 0: disabled 1: enabled 15:6 Reserved Must be kept at reset value SYSFLTIE System fault interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value SHRTIMER channel output enable register (SHRTIMER_CHOUTEN) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved...
Page 647 GD32E50x User Manual by ST3CH0DISF bit in the SHRTIMER_CHOUTDISF register. ST2CH1EN Slave_TIMER2 channel 1 output (ST2CH1_O) enable Refer to ST0CH0EN description. Note: The disable status corresponds to both Idle and Fault states w hich is given by ST2CH1DISF bit in the SHRTIMER_CHOUTDISF register. ST2CH0EN Slave_TIMER2 channel 0 output (ST2CH0_O) enable Refer to ST0CH0EN description.
Page 648 GD32E50x User Manual ST4CH1DI ST4CH0DI ST3CH1DI ST3CH0DI ST2CH1DI ST2CH0DI ST1CH1DI ST1CH0DI ST0CH1DI ST0CH0DI Reserved Bits Fields Descriptions 31:10 Reserved Must be kept at reset value ST4CH1DIS Slave_TIMER4 channel 1 output (ST4CH1_O) disable. Refer to ST0CH0DIS description. ST4CH0DIS Slave_TIMER4 channel 0 output (ST4CH0_O) disable. Refer to ST0CH0DIS description.
Page 649 GD32E50x User Manual This register has to be accessed by word(32-bit) Reserved ST4CH1DI ST4CH0DI ST3CH1DI ST3CH0DI ST2CH1DI ST2CH0DI ST1CH1DI ST1CH0DI ST0CH1DI ST0CH0DI Reserved Bits Fields Descriptions 31:10 Reserved Must be kept at reset value ST4CH1DISF Slave_TIMER4 channel 1 output (ST4CH1_O) disable flag. Refer to ST0CH0DISF description.
Page 650 GD32E50x User Manual SHRTIMER bunch mode control register (SHRTIMER_BMCTL) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) BMOPTF Reserved BMST4 BMST3 BMST2 BMST1 BMST0 BMMT rc_w0 Reserved BMSE BMPSC[3:0] BMCLKS[3:0] BMCTN BMEN Bits Fields Descriptions BMOPTF...
Page 651 GD32E50x User Manual is reset Note: (1) This bit cannot be changed w hile the bunch mode is enabled. (2) This bit must not be set w hen the balanced IDLE mode is active (DLYISCH[2:0] = 3’bx11 in SHRTIMER_STx CHOCTL register). BMST1 Slave_TIMER1 bunch mode 0: Slave_TIMER1 counter clock(SHRTIMER_PSCCK) is maintained and the...
Page 652 GD32E50x User Manual 0000: f SHRTIMER_BMCNTCK SHRTIMER_CK 0001: f SHRTIMER_BMCNTCK SHRTIMER_CK 0010: f SHRTIMER_BMCNTCK SHRTIMER_CK 0011: f SHRTIMER_BMCNTCK SHRTIMER_CK 0100: f SHRTIMER_BMCNTCK SHRTIMER_CK 0101: f SHRTIMER_BMCNTCK SHRTIMER_CK 0110: f SHRTIMER_BMCNTCK SHRTIMER_CK 0111: f /128 SHRTIMER_BMCNTCK SHRTIMER_CK 1000: f /256 SHRTIMER_BMCNTCK SHRTIMER_CK 1001: f /512...
Page 653 GD32E50x User Manual the bit is set. Writing this bit to 0 w ill terminate bunch mode. 0: Bunch mode disable. 1: Bunch mode enable. SHRTIMER bunch mode start trigger register (SHRTIMER_BMSTRG) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) ST3EXEV ST0EXEV CISGN...
Page 654 GD32E50x User Manual operation. 0：No effect on bunch mode operation. 1：Slave_TIMER0 period event follow ing external event 6 is starting bunch mode operation. ST4CMP1 Slave_TIMER4 compare 1 event triggers bunch mode operation Refer to MTCMP1 description. ST4CMP0 Slave_TIMER4 compare 0 event triggers bunch mode operation Refer to MTCMP0 description.
Page 655 GD32E50x User Manual Refer to MTRST description. ST0CMP1 Slave_TIMER0 compare 1 event triggers bunch mode operation Refer to MTCMP1 description. ST0CMP0 Slave_TIMER0 compare 0 event triggers bunch mode operation Refer to MTCMP0 description. ST0REP Slave_TIMER0 repetition event triggers bunch mode operation Refer to MTREP description.
Page 656 GD32E50x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved BMCMPVAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 BMCMPVAL[15:0] Bunch mode compare value This bit-field contains value to be compared to the BM-counter and defines the duration of the IDLE.
Page 657 GD32E50x User Manual SHRTIMER external event configuration register 0 (SHRTIMER_EXEVCFG0) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEV2EG Reserved EXEV4EG[1:0] EXEV4P EXEV4SRC[1:0] Reserved EXEV3EG[1:0] EXEV3P EXEV3SRC[1:0] Reserved EXEV2E EXEV2P EXEV2SRC[1:0] Reserved EXEV1EG[1:0] EXEV1P EXEV1SRC[1:0] Reserved...
Page 658 GD32E50x User Manual Reserved Must be kept at reset value 10:9 EXEV1EG[1:0] External event 1 edge sensitivity Refer to EXEV0EG[1:0] description. EXEV1P External event 1 polarity Refer to EXEV0P description. EXEV1SRC[1:0] External event 1 source Refer to EXEV0SRC[1:0] description. Reserved Must be kept at reset value EXEV0EG[1:0] External event 0 edge sensitivity...
Page 659 GD32E50x User Manual Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:27 EXEV9EG[1:0] External event 9 edge sensitivity Refer to EXEV0EG[1:0] in SHRTIMER_EXEV CFG0 register description. EXEV9P External event 9 polarity Refer to EXEV0P in SHRTIMER_EXEV CFG0 register description. 25:24 EXEV9SRC[1:0] External event 9 source...
Page 660 GD32E50x User Manual Refer to EXEV0P in SHRTIMER_EXEV CFG0 register description. EXEV5SRC[1:0] External event 5 source Refer to EXEV0SRC[1:0] in SHRTIMER_EXEVCFG0 register description. SHRTIMER external event digital filter control register (SHRTIMER_EXEVDFCTL) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEVFDIV[2:0] Reserved EXEV9FC[3:0]...
Page 661 GD32E50x User Manual 11:10 Reserved Must be kept at reset value EXEV6FC[3:0] External event 6 filter control Refer to EXEV5FC[3:0] description. Reserved Must be kept at reset value EXEV5FC[3:0] External event 5 filter control An event counter is used in the digital filter, in w hich a transition on the output occurs after N input events.
Page 662 GD32E50x User Manual TRG0ST4PER SHRTIMER_A DCTRIG0 on Slave_TIMER4 period event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG0. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 period event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER4 period event.
Page 663 GD32E50x User Manual Refer to TRG0ST2C1 description. TRG0ST2C1 SHRTIMER_A DCTRIG0 on Slave_TIMER2 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG0. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER2 compare 1 event.
Page 664 GD32E50x User Manual TRG0ST0C2 SHRTIMER_A DCTRIG0 on Slave_TIMER0 compare 2 event Refer to TRG0ST0C1 description. TRG0ST0C1 SHRTIMER_A DCTRIG0 on Slave_TIMER0 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG0. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER0 compare 1 event.
Page 665 GD32E50x User Manual SHRTIMER trigger source 1 to ADC register (SHRTIMER_ADCTRIGS1) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) TRG1ST4 TRG1ST4 TRG1ST4 TRG1ST4 TRG1ST3 TRG1ST3 TRG1ST3 TRG1ST3 TRG1ST3 TRG1ST2 TRG1ST2 TRG1ST2 TRG1ST2 TRG1ST2 TRG1ST1 TRG1ST1...
Page 666 GD32E50x User Manual 0: No ADC trigger event generated on SHRTIMER Slave_TIMER3 period event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER3 period event. TRG1ST3C3 SHRTIMER_A DCTRIG1 on Slave_TIMER3 compare 3 event Refer to TRG1ST3C1 description. TRG1ST3C2 SHRTIMER_A DCTRIG1 on Slave_TIMER3 compare 2 event Refer to TRG1ST3C1 description.
Page 667 GD32E50x User Manual Refer to TRG1ST1C1 description. TRG1ST1C2 SHRTIMER_A DCTRIG1 on Slave_TIMER1 compare 2 event Refer to TRG1ST1C1 description. TRG1ST1C1 SHRTIMER_A DCTRIG1 on Slave_TIMER1 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG1. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event.
Page 668 GD32E50x User Manual The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG1. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Master_TIMER period event. 1: ADC trigger event generated on SHRTIMER Master_TIMER period event. TRG1MTC3 SHRTIMER_A DCTRIG1 on Master_TIMER compare 3 event Refer to TRG1MTC0 description.
Page 669 GD32E50x User Manual Refer to TRG2ST4C1 description. TRG2ST4C2 SHRTIMER_A DCTRIG2 on Slave_TIMER4 compare 2 event Refer to TRG2ST4C1 description. TRG2ST4C1 SHRTIMER_A DCTRIG2 on Slave_TIMER4 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG2. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 compare 1 event.
Page 670 GD32E50x User Manual 1: ADC trigger event generated on SHRTIMER Slave_TIMER2 compare 1 event. TRG2ST1RST SHRTIMER_A DCTRIG2 on Slave_TIMER1 reset The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG2. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 reset .
Page 671 GD32E50x User Manual event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER0 compare 1 event. TRG2EXEV4 SHRTIMER_A DCTRIG2 on external event 4 Refer to TRG2EXEV0 description. TRG2EXEV3 SHRTIMER_A DCTRIG2 on external event 3 Refer to TRG2EXEV0 description. TRG2EXEV2 SHRTIMER_A DCTRIG2 on external event 2 Refer to TRG2EXEV0 description.
Page 672 GD32E50x User Manual This register has to be accessed by word (32-bit) TRG3ST4 TRG3ST4 TRG3ST4 TRG3ST4 TRG3ST3 TRG3ST3 TRG3ST3 TRG3ST3 TRG3ST3 TRG3ST2 TRG3ST2 TRG3ST2 TRG3ST2 TRG3ST2 TRG3ST1 TRG3ST1 TRG3ST1 TRG3ST1 TRG3ST0 TRG3ST0 TRG3ST0 TRG3ST0 TRG3EXE TRG3EXE TRG3EXE TRG3EXE TRG3EXE TRG3MTP TRG3MTC TRG3MTC TRG3MTC...
Page 673 GD32E50x User Manual Refer to TRG3ST3C1 description. TRG3ST3C1 SHRTIMER_A DCTRG3 on Slave_TIMER3 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRG3. This bit specifies w hether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER3 compare 1 event.
Page 674 GD32E50x User Manual 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event. TRG3ST0PER SHRTIMER_A DCTRG3 on Slave_TIMER0 period event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRG3. This bit specifies w hether the event can generate the ADC trigger event.
Page 675 GD32E50x User Manual TRG3MTC2 SHRTIMER_A DCTRG3 on Master_TIMER compare 2 event Refer to TRG3MTC0 description. TRG3MTC1 SHRTIMER_A DCTRG3 on Master_TIMER compare 1 event Refer to TRG3MTC0 description. TRG3MTC0 SHRTIMER_A DCTRG3 on Master_TIMER compare 0 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_A DCTRIG3. This bit specifies w hether the event can generate the ADC trigger event.
Page 676 GD32E50x User Manual Writing 1 to the bit starts the DLL calibration w hen CLBPEREN = 0. This bit is w rite- only. 0: No effect. 1: DLL calibration start once. Note: CLBPEREN bit and CLBSTRT bit must not be set simultaneously. SHRTIMER fault input configuration register 0 (SHRTIMER_FLTINCFG0) Address offset: 0x50 Reset value: 0x0000 0000...
Page 677 GD32E50x User Manual FLT2INP Fault 2 input polarity Refer to FLT0INP description. FLT2INEN Fault 2 input enable Refer to FLT0INEN description. FLT1INPROT Protect fault 1 input configuration Refer to FLT0INPROT description. 14:11 FLT1INFC[3:0] Fault 1 input filter control Refer to FLT0INFC[3:0] description. FLT1INSRC Fault 1 input source Refer to FLT0INSRC description.
Page 678 GD32E50x User Manual 1110: f /32, N=6. SAMP SHRTIMER_FLTFCK 1111: f /32, N=8. SAMP SHRTIMER_FLTFCK Note: (1) This bit-field can be w ritten only w hen FLT0INEN bit is reset. (2) This bit-field cannot be modified w hen FLT0INPROT has been programmed. FLT0INSRC Fault 0 input source 0: The source of fault 0 input is chip external pin.
Page 679 GD32E50x User Manual 00: f SHRTIMER_FLTFCK SHRTIMER_CK 01: f SHRTIMER_FLTFCK SHRTIMER_CK 10: f SHRTIMER_FLTFCK SHRTIMER_CK 11: f SHRTIMER_FLTFCK SHRTIMER_CK Note: This bit must be configured before setting any FLTyINEN(y=0..4). 23:8 Reserved Must be kept at reset value FLT4INPROT Protect fault 4 input configuration Refer to FLT0INPROT in SHRTIMER_FLTINCFG0 register description.
Page 680 GD32E50x User Manual Refer to MTCTL0 description. MTCMP1V SHRTIMER_MTCMP1V update by DMA mode Refer to MTCTL0 description. MTCMP0V SHRTIMER_MTCMP0V update by DMA mode Refer to MTCTL0 description. MTCREP SHRTIMER_MTCREP update by DMA mode Refer to MTCTL0 description. MTCAR SHRTIMER_MTCA R update by DMA mode Refer to MTCTL0 description.
Page 681 GD32E50x User Manual Refer to STxCTL0 bit description. 30:21 Reserved Must be kept at reset value STxFLTCTL SHRTIMER_STx FLTCTL update by DMA mode Refer to STxCTL0 bit description. STxCHOCTL SHRTIMER_STx CHOCTL update by DMA mode Refer to STxCTL0 bit description. STxCSCTL SHRTIMER_STx CSCTL update by DMA mode Refer to STxCTL0 bit description.
Page 682 GD32E50x User Manual Refer to STxCTL0 bit description. STxCNT SHRTIMER_STx CNT update by DMA mode Refer to STxCTL0 bit description. STxDMAINTEN SHRTIMER_STx DMAINTEN update by DMA mode Refer to STxCTL0 bit description. STxINTC SHRTIMER_STx INTC update by DMA mode Refer to STxCTL0 bit description. STxCTL0 SHRTIMER_STx CTL0 update by DMA mode This bit defines if the SHRTIMER_STxCTL0 register is updated by the DMA mode.
Page 683: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32E50x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) Universal synchronous/asynchronous receiver /transmitter 20.1. (USARTx, x=0..4) Overview 20.1.1. The USART provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK(PCLK1 or PCLK2) to produce a dedicated baud rate clock for the USART transmitter and receiver.
Page 684: Table 20-1. Description Of Usart Important Pins
GD32E50x User Manual  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface. – Character mode (T=0). – Block mode (T=1). – Direct and inverse convention.  Multiprocessor communication. – Enter into mute mode if address match does not occur. –...
Page 685: Figure 20-1. Usart Module Block Diagram
GD32E50x User Manual Figure 20-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controler Flow nCTS Controler USART Control Registers USART Address Transmitter Transimit clock...
Page 686 GD32E50x User Manual STB[1:0] stop bit length (bit) usage description Smartcard mode for receiving Normal USART and single-w ire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 687: Figure 20-3. Usart Transmit Procedure
GD32E50x User Manual can be output through the CK pin. After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_DATA when the TBE bit in the USART_STAT0 register is asserted.
Page 688: Figure 20-4. Receiving A Frame Bit By Oversampling Method
GD32E50x User Manual USART receiver After power on, the USART receiver can be enabled by the following procedure: Set the UEN bit in USART_CTL0 to enable the USART. Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1 to configure the number of stop bits.
Page 689 GD32E50x User Manual the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value. If they are not the same, the parity error (PERR) bit in USART_STAT0 register will be set.
Page 690: Figure 20-5. Configuration Step When Using Dma For Usart Transmission
GD32E50x User Manual Figure 20-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_DATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 691: Figure 20-6. Configuration Steps When Using Dma For Usart Reception
GD32E50x User Manual Figure 20-6. Configuration steps when using DMA for USART reception Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 692: Figure 20-8. Hardware Flow Control
GD32E50x User Manual data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared by reading the USART_DATA register. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 693: Figure 20-9. Break Frame Occurs During Idle State
GD32E50x User Manual an address frame differ from the ADDR[3:0] bits in the USART_CTL1 register, the hardware sets the RWU bit and enters mute mode automatically. In this situation, the RBNE bit is not set. If the address match method is selected, the receiver does not check the parity value of an address frame by default.
Page 694: Figure 20-11. Example Of Usart In Synchronous Mode
GD32E50x User Manual Synchronous mode The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1. The LMEN bit in USART_CTL1 and SCEN, HDEN, IREN bits in USART_CTL2 should be cleared in synchronous mode. The CK pin is the clock output of the synchronous USART transmitter, and can be only activated when the TEN bit is enabled.
Page 695: Figure 20-13. Irda Sir Endec Module
GD32E50x User Manual In IrDA mode, the USART transmission data frame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin. The SIR receive decoder receives the modulated signal from the infrared LED through the RX pin, and puts the demodulated data frame to the USART receiver.
Page 696: Figure 20-15. Iso7816-3 Frame Format
GD32E50x User Manual division ratio is configured by the PSC[7:0] bits in USART_GP register. The pulse width on the TX pin is 3 cycles of this low speed period. The receiver decoder works in the same manner as the normal IrDA mode. Half-duplex communication mode The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2.
Page 697 GD32E50x User Manual Character (T=0) mode Comparing to the timing in normal operation, the transmission time from transmit shift register to the TX pin is delayed by half baud clock, and the TC flag assertion time is delayed by a guard time that is configured by the GUAT[7:0] bits in USART_GP.
Page 698: Table 20-3. Usart Interrupt Requests
GD32E50x User Manual The USART uses a block length counter, which is reset when the USART is transmitting (TBE=0), to count the number of received characters. The length of the block, which must be programmed to the BL[7:0] bits in the USART_RT register, is received from the smartcard in the third byte of the block (prologue field).
Page 699: Figure 20-16. Usart Interrupt Mapping Diagram
GD32E50x User Manual Enable Interrupt event Event flag Control register Control bit Reception errors (noise flag, NERR or ORERR or overrun error, framing error) in USART_CTL2 ERRIE FERR DMA reception Collision detected USART_GDCTL CDIE All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time.
Page 700 GD32E50x User Manual Register definition 20.1.4. USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register 0 (USART_STAT0) Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 701 GD32E50x User Manual 1: Transmit data buffer is empty. Transmission complete This bit is set after pow er on. If the TBE bit has been set, this bit is set w hen the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
Page 702 GD32E50x User Manual registers one by one. 0: The USART does not detect a framing error. 1: The USART has detected a framing error. PERR Parity error flag This bit is set w hen the parity bit of a receive frame does not match the expected parity value.
Page 703 GD32E50x User Manual INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value. 15:4 INTDIV[11:0] Integer part of baud-rate divider. FRADIV[3:0] Fraction part of baud-rate divider. Control register 0 (USART_CTL0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 704 GD32E50x User Manual 1: Parity check function enabled. Parity mode 0: Even parity. 1: Odd parity. PERRIE Parity error interrupt enable. If this bit is set, an interrupt occurs w hen the PERR bit in USART_STAT0 is set. 0: Parity error interrupt is disabled. 1: Parity error interrupt is enabled.
Page 705 GD32E50x User Manual 1: Receiver in mute mode. SBKCMD Send break command Softw are can set this to send a break frame. Hardw are resets this bit automatically w hen the break frame has been transmitted. 0: Do not transmit a break frame. 1: Transmit a break frame.
Page 706 GD32E50x User Manual This bit specifies the phase of the CK pin in synchronous mode. 0: The capture edge of the LSB bit is the first edge of CK pin. 1: The capture edge of the LSB bit is the second edge of CK pin. This bit is reserved for UART3/4.
Page 707 GD32E50x User Manual This bit selects the sample method. The noise detection flag (NF) is disabled w hen the one sample bit method is selected. 0: Three sample bit method. 1: One sample bit method. CTSIE CTS interrupt enable If this bit is set, an interrupt occurs w hen the CTSF bit in USART_STAT0 is set. 0: CTS interrupt is disabled.
Page 708 GD32E50x User Manual 1: Half duplex mode is enabled. IRLP IrDA low -pow er This bit selects low -pow er mode of IrDA mode. 0: Normal mode. 1: Low -pow er mode. IREN IrDA mode enable This bit enables the IrDA mode of USART. 0: IrDA disabled.
Page 709 GD32E50x User Manual 11111111: divides by 255 When the USART w orks in IrDA normal mode, these bits must be set to 00000001. When the USART smartcard mode is enabled, the PSC [4:0] bits specify the division factor that is used to divide the peripheral clock (APB1/APB2) to generate the smartcard clock (CK).
Page 710 GD32E50x User Manual This bit field cannot be w ritten w hen the USART is enabled (UEN=1). RINV RX pin level inversion This bit specifies the polarity of the RX pin. 0: RX pin signal values are not inverted. 1: RX pin signal values are inverted. This bit field cannot be w ritten w hen the USART is enabled (UEN=1).
Page 711 GD32E50x User Manual RT[15:0] Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in Smartcard T=1 Reception. Its value equals to the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1. This value, w hich must be programmed only once per received block, can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field).
Page 712 GD32E50x User Manual Busy flag This bit is set w hen the USART is receiving a data frame. 0: USART reception path is idle. 1: USART reception path is w orking. 15:13 Reserved Must be kept the reset value. End of block flag This bit is set w hen the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4.
Page 713 GD32E50x User Manual 0: no collision detected. 1: collision detected in halfduplex mode. Reserved Forced by hardw are to 0. CDEN Collision detection enable 0: disable 1: enable Reserved Forced by hardw are to 0.
Page 714 GD32E50x User Manual Universal synchronous/asynchronous receiver /transmitter 20.2. (USARTx, x=5) Overview 20.2.1. The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK(PCLK2, CK_USART5) to produce a dedicated wide range baud rate clock for the USART transmitter and receiver.
Page 715: Table 20-4. Description Of Usart Important Pins
GD32E50x User Manual  IrDA support  Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface – Character mode (T=0) – Block mode (T=1) – Direct and inverse convention  Multiprocessor communication – Enter into mute mode if address match does not occur –...
Page 716: Figure 20-17. Usart Module Block Diagram
GD32E50x User Manual Figure 20-17. USART module block diagram CPU/DMA Transmit Read Write Shift Buffer Buffer Register SW_RX IrDA Block Receive Shift Read FiFO Register USART Guard Time and Prescaler Register nRTS Hardware CK Controler Flow nCTS Controler USART Control Registers USART Address...
Page 717 GD32E50x User Manual STB[1:0] stop bit length (bit) usage description Normal USART and single-w ire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 718: Figure 20-19. Usart Transmit Procedure
GD32E50x User Manual After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_TDATA when the TBE bit in the USART_STAT register is asserted.
Page 719: Figure 20-20. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32E50x User Manual USART receiver After power on, the USART receiver can be enabled by the following procedure: Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1. Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. Set the baud rate in USART_BAUD.
Page 720 GD32E50x User Manual the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value. If they are not the same, the parity error (PERR) bit in USART_STAT register will be set. An interrupt is generated, if the PERRIE bit in USART_CTL0 register is set.
Page 721: Figure 20-21. Configuration Step When Using Dma For Usart Transmission
GD32E50x User Manual Figure 20-21. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 722: Figure 20-22. Configuration Step When Using Dma For Usart Reception
GD32E50x User Manual Figure 20-22. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 723: Figure 20-23. Break Frame Occurs During Idle State
GD32E50x User Manual If the PCEN bit in USART_CTL0 is set, the MSB bit will be checked as the parity bit, and the bit preceding the MSB bit is detected as the address bit. If the ADDM bit is set and the receive frame is a 7bit data, the LSB 6 bits will be compared with ADDR[5:0].
Page 724: Figure 20-25. Example Of Usart In Synchronous Mode
GD32E50x User Manual the clock output of the synchronous USART transmitter, and can be only activated when the TEN bit is enabled. No clock pulse will be sent through the CK pin during the transmission of the start bit and stop bit. The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last (address flag) bit transmission.
Page 725: Figure 20-27. Irda Sir Endec Module
GD32E50x User Manual Figure 20-27. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 726: Figure 20-29. Iso7816-3 Frame Format
GD32E50x User Manual Half-duplex communication mode The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 727 GD32E50x User Manual gap of 2.5 bits time will be inserted before the start of a resented frame. At the end of the last repeated character the TC bit is set immediately without guard time. The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed number of retries.
Page 728 GD32E50x User Manual The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set). The RT interrupt may occur in case of an error in the block length. Direct and inverse convention The smartcard protocol defines two conventions: direct and inverse.
Page 729: Figure 20-30. Usart Receive Fifo Structure
GD32E50x User Manual Figure 20-30. USART receive FIFO structure If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out. The PERR/NERR/FERR/EBF flags should be cleared before reading a receive data out.
Page 730 GD32E50x User Manual Interrupt event Event flag Enable Control bit read Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE Parity error flag PERR PERRIE Break detected flag in LIN LBDF LBDIE mode Reception errors (noise flag, overrun error, framing error) in NERR or ORERR or FERR ERRIE...
Page 731: Figure 20-31. Usart Interrupt Mapping Diagram
GD32E50x User Manual Figure 20-31. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 732 GD32E50x User Manual Register defintion 20.2.4. USART5 base address: 0x4001 7000 Control register 0 (USART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE Reserved OVSMOD AMIE PCEN PERRIE TBEIE TCIE RBNEIE IDLEIE...
Page 733 GD32E50x User Manual This bit field cannot be w ritten w hen the USART is enabled (UEN=1). Wakeup method in mute mode 0: Idle Line 1: Address Mark This bit field cannot be w ritten w hen the USART is enabled (UEN=1). PCEN Parity control enable.
Page 734 GD32E50x User Manual 1: USART able to w ake up the MCU from Deep-sleep mode. Providing that the clock source for the USART must be IRC8M or LXTAL. USART enable 0: USART prescaler and outputs disabled. 1: USART prescaler and outputs enabled. Control register 1 (USART_CTL1) Address offset: 0x04 Reset value: 0x0000 0000...
Page 735 GD32E50x User Manual 1: Data bit signal values are inverted. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). TINV TX pin level inversion. 0: TX pin signal values are not inverted. 1: TX pin signal values are inverted. This bit field cannot be w ritten w hen the USART is enabled (UEN=1).
Page 736 GD32E50x User Manual 1: The clock pulse of the last data bit (MSB) is output to the CK pin in synchronous mode. This bit field cannot be w ritten w hen the USART is enabled (UEN=1). Reserved Must be kept at reset value. LBDIE LIN break detection interrupt enable.
Page 737 GD32E50x User Manual These bits are used to specify the event w hich activates the WUF (Wakeup from Deep-sleep mode flag) in the USART_STAT register. 00: WUF active on address match, w hich is defined by ADDR and ADDM. 01: Reserved. 10: WUF active on Start bit.
Page 738 GD32E50x User Manual 10:8 Reserved Must be kept at reset value. DENT DMA enable for transmission. 0: DMA mode is disabled for transmission. 1: DMA mode is enabled for transmission. DENR DMA enable for reception. 0: DMA mode is disabled for reception. 1: DMA mode is enabled for reception.
Page 739 GD32E50x User Manual Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 BRR[15:4] Integer of baud-rate divider INTDIV = BRR[15:4] BRR [3:0] Fraction of baud-rate divider If OVSMOD = 0, FRADIV = BRR [3:0]; If OVSMOD = 1, FRADIV = BRR [2:0], BRR [3] must be reset.
Page 740 GD32E50x User Manual factor is tw ice as the prescaler value. 00000: Reserved - do not program this value. 00001: divides the source clock by 2. 00010: divides the source clock by 4. 00011: divides the source clock by 6. This bit field cannot be w ritten w hen the USART is enabled (UEN=1).
Page 741 GD32E50x User Manual Command register (USART_CMD) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TXFCMD RXFCMD MMCMD SBKCMD Reserved Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. TXFCMD Transmit data flush request.
Page 742 GD32E50x User Manual Receive enable acknow ledge flag. This bit, w hich is set/reset by hardw are, reflects the receive enable state of the USART core logic. 0: The USART core receiving logic has not been enabled. 1: The USART core receiving logic has been enabled. Transmit enable acknow ledge flag.
Page 743 GD32E50x User Manual 1: USART reception path is w orking. 15:13 Reserved Must be kept at reset value. End of block flag. 0: End of Block not reached. 1: End of Block (number of characters) reached. An interrupt is generated if the EBIE=1 in the USART_CTL1 register.
Page 744 GD32E50x User Manual 0: Data is not received. 1: Data is received and ready to be read. An interrupt w ill occur if the RBNEIE bit is set in USART_CTL0. Set by hardw are w hen the content of the receive shift register has been transferred to the USART_RDATA.
Page 745 GD32E50x User Manual Set by hardw are w hen a parity error occurs in receiver mode. Cleared by w riting 1 to PEC bit in USART_INTC register. Interrupt status clear register (USART_INTC) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Reserved...
Page 746 GD32E50x User Manual OREC Overrun error clear. Writing 1 to this bit clears the ORERR bit in the USART_STAT register. Noise detected clear. Writing 1 to this bit clears the NERR bit in the USART_STAT register. Frame error flag clear. Writing 1 to this bit clears the FERR bit in the USART_STAT register.
Page 747 GD32E50x User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. TDATA[8:0] Transmit Data value. The transmit data character is contained in these bits. The value w ritten in the MSB (bit 7 or bit 8 depending on the data length) w ill be replaced by the parity, w hen transmitting w ith the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
Page 748 GD32E50x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. RFFINT Receive FIFO full interrupt flag. 14:12 RFCNT[2:0] Receive FIFO counter number. Receive FIFO full flag. 0: Receive FIFO not full. 1: Receive FIFO full. Receive FIFO empty flag 0: Receive FIFO not empty.
Page 749: Figure 21-1. I2C Module Block Diagram
GD32E50x User Manual Inter-integrated circuit interface (I2C) Inter-integrated circuit interface (I2Cx, x=0, 1) 21.1. Overview 21.1.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL.
Page 750: Table 21-1. Definition Of I2C-Bus Terminology
GD32E50x User Manual Figure 21-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 21-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 751: Figure 21-2. Data Validation
GD32E50x User Manual connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V Data validation The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW (see Figure 21-2.
Page 752: Figure 21-4. Clock Synchronization
GD32E50x User Manual a HIGH wait-state during this time. Figure 21-4. Clock synchronization Arbitration Arbitration, like synchronization, is part of the protocol where more than one master is used in the system. Slaves are not involved in the arbitration procedure. A master may start a transfer only if the bus is free.
Page 753: Figure 21-6. I2C Communication Flow With 7-Bit Address
GD32E50x User Manual An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation. Figure 21-6. I2C communication flow with 7-bit address Figure 21-7. I2C communication flow with 10-bit address (Master Transmit) Figure 21-8.
Page 754 GD32E50x User Manual I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus. After receiving a START signal followed by a matched address, either in 7-bit format or in 10-bit format, the I2C hardware sets the ADDSEND bit in I2C_STAT0 register, which should be monitored by software either by polling or interrupt.
Page 755: Figure 21-9. Programming Model For Slave Transmitting (10-Bit Address Mode)
GD32E50x User Manual Figure 21-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 756 GD32E50x User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 21-10.
Page 757: Figure 21-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32E50x User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 758 GD32E50x User Manual reception and then sending a STOP signal on I2C bus. So, special attention should be paid to ensure the correct ending of data reception. Two solutions for master receiving are provided here for applications: Solution A and B. Solution A requires the software’s quick response to I2C events, while Solution B doesn’t.
Page 759: Figure 21-12. Programming Model For Master Receiving Using Solution A
GD32E50x User Manual Figure 21-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 760: Figure 21-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32E50x User Manual If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 761 GD32E50x User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 762 GD32E50x User Manual SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur. Use DMA for data transfer As is shown in Programming Model, each time TBE or RBNE is asserted, software should write or read a byte, this may cause CPU to be high overloaded.
Page 763 GD32E50x User Manual  SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications.
Page 764: Table 21-2. Event Status Flags
GD32E50x User Manual The programming flow for SMBus is similar to normal I2C. In order to use SMBus mode, the application should configure several SMBus specific registers, respond to some SMBus specific flags and implement the upper protocols described in SMBus specification. Before communication, SMBEN bit in I2C_CTL0 should be set and SMBSEL and ARPEN bits should be configured to desired values.
Page 765: Table 21-3. Error Flags
GD32E50x User Manual Table 21-3. Error flags Error Nam e Description BERR Bus error LOSTARB Arbitration lost OUERR Over-run or under-run w hen SCL stretch is disabled. AERR No acknow ledge received CRC value doesn’t match PECERR SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert...
Page 766 GD32E50x User Manual Register definition 21.1.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved SALT POAP...
Page 767 GD32E50x User Manual 1: ACKEN bit specifies w hether to send ACK or NACK for the next byte that is to be received, PECTRA NS bit indicates the next byte that is to be received is a PEC byte ACKEN Whether or not to send an ACK This bit is set and cleared by softw are and cleared by hardw are w hen I2CEN=0 0: ACK w ill not be sent...
Page 768 GD32E50x User Manual 1: I2C is enabled Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[6:0] Bits Fields Descriptions 31:13 Reserved...
Page 769 GD32E50x User Manual 0000000 - 0000001: Not allow ed 0000010 - 1011010: 2MHz~90MHz 1011011 - 1111111: Not allow ed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 770 GD32E50x User Manual Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) Address offset: 0x10 Reset value: 0x0000 0000...
Page 771 GD32E50x User Manual 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardw are and cleared by w riting 0. 0: SMBA pin not pulled dow n (device mode) or no Alert detected (host mode) 1: SMBA pin pulled dow n and Alert address received (device mode) or Alert detected (host mode) SMBTO...
Page 772 GD32E50x User Manual cleared by w riting a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, w riting I2C_DATA w on’t clear TBE (refer to Programming Model for detail). 0: I2C_DATA is not empty 1: I2C_DATA is empty, softw are can w rite RBNE I2C_DATA is not empty during receiving This bit is set by hardw are after it moves a byte from shift register to I2C_DATA and...
Page 773 GD32E50x User Manual mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardw are and cleared by reading I2C_STAT0 and w riting I2C_DATA. 0: No START signal sent 1: START signal sent Transfer status register 1 (I2C_STAT1) Address offset: 0x18...
Page 774 GD32E50x User Manual Reserved Must be kept at reset value. Transmitter or receiver This bit indicates w hether the I2C is a transmitter or a receiver. It is cleared by hardw are after a STOP or a START signal or I2CEN=0 or LOSTARB=1. 0: Receiver 1: Transmitter I2CBSY...
Page 775 GD32E50x User Manual =CLKC* T =2*CLKC* T high PCLK1 PCLK1 In fast speed mode or fast mode plus, if DTCY=1: =9*CLKC*T =16*CLKC* T high PCLK1 PCLK1 Note: If DTCY is 0, w hen PCLK1 is an integral multiple of 3, the baud rate w ill be more accurate.
Page 776 GD32E50x User Manual Txframe rise flag, cleared by softw are by w riting 0 Txframe fall flag, cleared by softw are by w riting 0 11:10 Reserved Must be kept at reset value. Level of rxframe signal Level of txframe signal RFRIE Rxframe rise interrupt enable 0: Rxframe rise interrupt disabled...
Page 777 GD32E50x User Manual 31:16 Reserved Must be kept at reset value. 15:9 ADDM[6:0] Defines w hich bits of register ADDRESS[7:1] are compared w ith an incoming address byte, and w hich bits are ignored. Any bit set to 1 in ADDM[6:0] enables comparisons w ith the corresponding bit in ADDRESS[7:1].
Page 778 GD32E50x User Manual STLOIE Interrupt enable for start lost 0: interrupt disable 1: interrupt enable Reserved Must be kept at reset value. STPSEND Stop condition sent out in master mode This bit is set by hardw are and cleared by softw are write 0 0: No STOP condition sent 1: STOP condition sent STLO...
Page 779 GD32E50x User Manual ADD10SEND C ADD10SEND status clear When SRCEN bit is set to 1, softw are can clear the ADD10SEND bit of I2C_STAT0 by w riting 1 to this bit BTCC BTC status clear When SRCEN bit is set to 1, softw are can clear the BTC bit of I2C_STAT0 by w riting 1 to this bit ADDSENDC ADDSEND status clear...
Page 780: Figure 21-14. I2C Module Block Diagram
GD32E50x User Manual Inter-integrated circuit interface (I2Cx, x=2) 21.2. Overview 21.2.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 781: Table 21-4. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32E50x User Manual Figure 21-14. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter...
Page 782: Figure 21-15. Data Validation
GD32E50x User Manual with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 260ns. Digital filter delay is DNF[3:0]×t I2CCLK The period of PCLK clock t match the conditions as follows:...
Page 783: Figure 21-16. Start And Stop Signal
GD32E50x User Manual Figure 21-16. START and STOP signal Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. It operates in slave mode by default. When it generates a START signal, the interface automatically switches from slave to master.
Page 784: Figure 21-18. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32E50x User Manual Figure 21-18. I2C communication flow with 7-bit address (Master Transmit) Figure 21-19. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent. When HEAD10R=0, the complete 10 bit address read sequence must be excuted with START + header of 10-bit address in write direction + slave address byte 2 + RESTART + header of 10-bit address in read direction, as is shown in...
Page 785: Figure 21-22. Data Hold Time
GD32E50x User Manual be configured before the I2C peripheral is enabled according to the actual requirements. The analog noise filter is disabled by setting the ANOFF bit in I2C_CTL0 register and enabled when ANOFF is 0. It can suppress spikes with a pulse width up to 50ns in fast mode and fast mode plus.
Page 786: Table 21-5. Data Setup Time And Data Hold Time
GD32E50x User Manual When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t =SDADELY*t where t = ( PSC+1 ) *t SDADELY I2CCLK I2CCLK effects t . The total delay of SDA output is t +{ [ SDADELY* ( PSC+1 ) SDADELY HD;DAT...
Page 787: Figure 21-24. Data Transmission
GD32E50x User Manual I2C reset A software reset can be performed by clearing the I2CEN bit in the I2C_CTL0 register. When a software reset is generated, the SCL and SDA are released. The communication control bits and status bits come back to the reset value. Software reset have no effect on configuration registers.
Page 788: Figure 21-25. Data Reception
GD32E50x User Manual Figure 21-25. Data reception SCL Stretch data1 data2 Shift register RBNE read data0 read data1 data0 data1 data2 I2C_RDATA  Reload and automatic end mode In order to manage byte transfer and to shut down the communication in modes as is shown Table 21-6.
Page 789 GD32E50x User Manual When works in slave mode, at least one slave address should be enabled. Slave address 1 can be programmed in I2C_SADDR0 register and slave address 2 can be programmed in I2C_SADDR1 register. ADDRESSEN in I2C_SADDR0 register and ADDRESS2EN in I2C_SADDR1 register should be set when the corresponding address is used.
Page 790 GD32E50x User Manual  Slave byte control mode In slave receiving mode, the slave byte control mode can be enabled by setting the SBCTL bit in the I2C_CTL0 register to allow byte ACK control. When SS=1, the slave byte control mode is not allowed.
Page 791: Figure 21-26. I2C Initialization In Slave Mode
GD32E50x User Manual Figure 21-26. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1 Configure ADDRESS[9:0], ADDFORMAT and ADDRESSEN in I2C_SADDR0, ADDRESS2[7:1], ADDMSK2[2:0] and ADDRESS2EN in I2C_SADDR1, ADDM[6:0] in I2C_CTL2...
Page 792: Figure 21-27. Programming Model For Slave Transmitting When Ss=0
GD32E50x User Manual When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine. So the first byte to be sent must be programmed in the I2C_TDATA register previously. This data can be the one which is written in the last TI event of the last transfer.
Page 793: Figure 21-28. Programming Model For Slave Transmitting When Ss=1
GD32E50x User Manual Figure 21-28. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 794: Figure 21-29. Programming Model For Slave Receiving
GD32E50x User Manual Figure 21-29. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 795: Figure 21-30. I2C Initialization In Master Mode
GD32E50x User Manual mode, the HEAD10R bit must be configured to decide whether the complete address sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register. If the number of bytes to be transferred is equal to or greater than 255, BYTENUM[7:0] should be configured as 0xFF.
Page 796: Figure 21-31. Programming Model For Master Transmitting (N<=255)
GD32E50x User Manual bit in I2C_CTL1 can be set to generate a STOP signal automatically. When AUTOEND is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signal by setting the STOP bit in the I2C_CTL1 register. Or generate a RESTART signal to start a new transfer.
Page 797: Figure 21-32. Programming Model For Master Transmitting (N>255)
GD32E50x User Manual Figure 21-32. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 798: Figure 21-33. Programming Model For Master Receiving (N<=255)
GD32E50x User Manual Figure 21-33. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 799: Figure 21-34. Programming Model For Master Receiving (N>255)
GD32E50x User Manual Figure 21-34. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 800 GD32E50x User Manual  Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 801 GD32E50x User Manual of the SMBus peripheral is greater than (BUSTOB+1)*2048*t and within the timeout I2CCLK interval described in the bus idle detection section, the TIMEOUT bit in the I2C_STAT register will be set.  Packet error checking There is a CRC-8 calculator in I2C block to perform Packet Error Checking for I2C data. A PEC (packet error code) byte is appended at the end of each transfer.
Page 802: Figure 21-35. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32E50x User Manual  SMBus slave mode The SMBus receiver must be able to NACK each command or data it receives. For ACK control in slave mode, slave byte control mode can be enabled by setting SBCTL bit in I2C_CTL0 register. SMBus-specific addresses should be enabled when needed.
Page 803: Figure 21-36. Smbus Master Receiver And Slave Transmitter Communication Flow
GD32E50x User Manual  If the SMBus master is required to receive PEC at the end of bytes transfer, automatic end mode can be enabled. Before sending a START signal on the bus, PECTRANS bit must be set and slave addresses must be programmed. After receiving BYTENUM-1 data, the next received byte will be compared with the data in the I2C_PEC register automatically.
Page 804: Table 21-7. I2C Error Flags
GD32E50x User Manual Use DMA for data transfer As is shown in I2C slave mode and I2C master mode, each time TI or RBNE is asserted, software should write or read a byte, this may cause CPU’s high overload. The DMA controller can be used to process TI and RBNE flag: each time TI or RBNE is asserted, DMA controller does a read or write operation automatically.
Page 805 GD32E50x User Manual I2C debug mode When the microcontroller enters the debug mode (Cortex®-M33 core halted), the SMBus timeout either continues to work normally or stops, depending on the I2Cx_HOLD configuration bits in the DBG module.
Page 806 GD32E50x User Manual Register definition 21.2.4. I2C2 base address: 0x4000 C000 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SMBALT SMBDAE SMBHAE Reserved PECEN GCEN WUEN SBCTL STPDETI DENR DENT Reserved ANOFF...
Page 807 GD32E50x User Manual 1 mode and Deep-sleep 2 mode. 0: Wakeup from pow er saving mode disable. 1: Wakeup from pow er saving mode enable. Note: WUEN can be set only w hen DNF[3:0] = 0000 Whether to stretch SCL low w hen data is not ready in slave mode. This bit is set and cleared by softw are.
Page 808 GD32E50x User Manual 0: Stop detection (STPDET) interrupt is disabled 1: Stop detection (STPDET) interrupt is enabled NACKIE NACK received interrupt enable 0: NACK received interrupt is disabled 1: NACK received interrupt is enabled ADDMIE Address match interrupt enable in slave mode 0: Address matchinterrupt is disabled 1: Address matchnterrupt is enabled RBNEIE...
Page 809 GD32E50x User Manual 1: Transfer PEC Note: This bit has no effect w hen RELOAD=1, or SBCTL=0 in slave mode. AUTOEND Automatic end mode in master mode 0: TC bit is set w hen the transfer of BYTENUM[7:0] bytes is completed. 1: a STOP signal is sent automatically w hen the transfer of BYTENUM[7:0] bytes is completed.
Page 810 GD32E50x User Manual 1: The 10 bit master receive address sequence is RESTART + header of 10-bit address (read). Note: When the START bit is set, this bit can not be changed. ADD10EN 10-bit addressing mode enable in master mode 0: 7-bit addressing in master mode 1: 10-bit addressing in master mode Note: When the START bit is set, this bit can not be modified.
Page 811 GD32E50x User Manual 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address 1: 10-bit address Note: When ADDRESSEN is set, this bit should not be w ritten. ADDRESS[9:8] Highest tw o bits of a 10-bit address Note: When ADDRESSEN is set, this bit should not be w ritten.
Page 812 GD32E50x User Manual 111: ADDRESS2[7:1] are masked. All 7-bit received addresses are acknow ledged except the reserved address (0b0000xxx and 0b1111xxx). Note: When ADDRESS2EN is set, these bits should not be w ritten. If ADDMSK2 is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknow ledged even if all the bits are matched.
Page 813 GD32E50x User Manual =(SCLH+1)* t SCLH Note: These bits can only be used in master mode. SCLL[7:0] SCL low period SCL low period can be generated by configuring these bits. =(SCLL+1)*t SCLL Note: These bits can only be used in master mode. Timeout register (I2C_TIMEOUT) Address offset: 0x14 Reset value: 0x0000 0000...
Page 814 GD32E50x User Manual 0: BUSTOA is used to detect SCL low timeout 1: BUSTOA is used to detect both SCL and SDA high timeout w hen the bus is idle Note: This bit can be w ritten only w hen TOEN =0. 11:0 BUSTOA[11:0] Bus timeout A...
Page 815 GD32E50x User Manual setting the SMBALTC bit. This bit is cleared by hardw are w hen I2CEN=0. 0: SMBALERT event is not detected on SMBA pin 1: SMBALERT event is detected on SMBA pin TIMEOUT TIMEOUT flag. When a timeout or extended clock timeout occurred, this bit w ill be set. It is cleared by softw are by setting the TIMEOUTC bit and cleared by hardw are w hen I2CEN=0.
Page 816 GD32E50x User Manual BYTENUM[7:0] bytes have been transferred. It is cleared by softw are w hen START bit or STOP bit is set. 0: Transfer of BYTENUM[7:0] bytes is not completed 1: Transfer of BYTENUM[7:0] bytes is completed STPDET STOP signal detected in slave mode This flag is set by hardw are w hen a STOP signal is detected on the bus.
Page 817 GD32E50x User Manual Status clear register (I2C_STATC) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMBALT TIMEOUT PECERR LOSTAR STPDET ADDSEN Reserved OUERRC BERRC Reserved NACKC Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value.
Page 818 GD32E50x User Manual PEC register (I2C_PEC) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PECV[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PECV[7:0] Packet Error Checking Value that calculated by hardw are w hen PEC is enabled. PECV is cleared by hardw are w hen I2CEN = 0.
Page 819 GD32E50x User Manual Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value...
Page 820 GD32E50x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 22.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 821: Figure 22-1. Block Diagram Of Spi
GD32E50x User Manual  Master clock (MCK) can be output.  Transmission and reception using DMA. 22.3. SPI function overview SPI block diagram 22.3.1. Figure 22-1. Block diagram of SPI SYSCLK MOSI TX Buffer MISO RX Buffer SPI signal description 22.3.2.
Page 822: Table 22-2. Quad-Spi Signal Description
GD32E50x User Manual Pin nam e Direction Description Master in hardw are NSS mode: w hen NSSDRV=1, it is NSS output, suitable for single master application; w hen NSSDRV=0, it is NSS input, suitable for multi-master application. Slave in hardw are NSS mode: NSS input, as a chip select signal for slave.
Page 823: Figure 22-2. Spi Timing Diagram In Normal Mode
GD32E50x User Manual Figure 22-2. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[0] D[2] D[4] D[5] D[1] D[6] D[7] LF=1 FF16=0 MISO D[2] D[1] D[5] D[6] D[7] D[0] D[3]...
Page 824: Table 22-3. Nss Function In Slave Mode
GD32E50x User Manual NSS function 22.3.4. Slave mode When slave mode is configured (MSTMOD=0), SPI gets NSS level from NSS pin in hardware NSS mode (SWNSSEN = 0) or from SWNSS bit in software NSS mode (SWNSSEN = 1) and transmits/receives data only when NSS level is low.
Page 825: Table 22-5. Spi Operation Modes
GD32E50x User Manual Mode Register configuration Description configuration error w ill occur and the CONFERR bit w ill be set to 1. Applicable to multi-master mode. Once MSTMOD = 1 SWNSS = 0, SPI w ill automatically SWNSSEN = 1 enter slave mode, and a master SWNSS = 0 configuration error w ill occur and the...
Page 826: Figure 22-4. A Typical Full-Duplex Connection
GD32E50x User Manual Mode Description Register configuration Data pin usage BDEN = 0 BDOEN: Don’t care MSTMOD = 0 Slave reception w ith RO = 1 MOSI: reception unidirectional connection BDEN = 0 MISO: not used BDOEN: Don’t care MSTMOD = 0 Slave transmission w ith RO = 0 MOSI: not used...
Page 827: Figure 22-6. A Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
GD32E50x User Manual Figure 22-6. A typical simplex connection (Master: transmit only, Slave: receive) Figure 22-7. A typical bidirectional connection Initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 828 GD32E50x User Manual Basic transmission and reception sequence Transmission sequence After the initialization sequence, the SPI is enabled and stays at idle state. In master mode, the transmission starts when the application writes a data into the transmission buffer. In slave mode the transmission starts when SCK clock signal begins to toggle at SCK pin and NSS level is low, so application should ensure that data is already written into transmission buffer before the transmission starts in slave mode.
Page 829: Figure 22-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32E50x User Manual similar to normal mode described above. The modes described above (MFD, MTU, MRU, MTB, MRB, SFD, STU, SRU, STB and SRB) are still supported in TI mode. While, in TI mode the CKPL and CKPH bits in SPI_CTL0 registers take no effect and the SCK sample edge is falling edge.
Page 830: Figure 22-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32E50x User Manual LSB bit of the last data byte, and after a half-bit time, the master begins to sample the line. To make sure that the master samples the right value, the slave should continue to drive this bit after the falling sample edge of SCK for a period of time before releasing the pin. This time is calledT is decided by PSC [2:0] bits in SPI_CTL0 register.
Page 831: Figure 22-12. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32E50x User Manual QRD bit in SPI_QCTL register. Quad write operation SPI works in quad write mode when QMOD is set and QRD is cleared in SPI_QCTL register. In this mode, MOSI, MISO, IO2 and IO3 are all used as output pins. SPI begins to generate clock on SCK line and transmit data on MOSI, MISO, IO2 and IO3 as soon as data is written into SPI_DATA (TBE is cleared) and SPIEN is set.
Page 832: Figure 22-13. Timing Diagram Of Read Operation In Quad-Spi Mode
GD32E50x User Manual Write an arbitrary byte (for example, 0xFF) to SPI_DATA register. Wait until the RBNE flag is set and read SPI_DATA to get the received byte. Write an arbitrary byte (for example, 0xFF) to SPI_DATA to receive the next byte. Figure 22-13.
Page 833 GD32E50x User Manual NSS pulse mode The disabling sequence of NSSP mode is the same as the sequences described above. Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared.
Page 834 GD32E50x User Manual SPI interrupts 22.3.8. Status flags  Transmission buffer empty flag (TBE) This bit is set when the transmission buffer is empty, the software can write the next data to the transmission buffer by writing the SPI_DATA register. ...
Page 835: Figure 22-14. Block Diagram Of I2S
GD32E50x User Manual when they are different. Table 22-6. SPI interrupt requests Interrupt Flag Description Clear m ethod enable bit Transmission buffer empty Write SPI_DATA register. TBEIE RBNE Reception buffer not empty Read SPI_DATA register. RBNEIE Read or w rite SPI_STAT register, CONFERR Configuration fault error then w rite SPI_CTL0 register.
Page 836: Figure 22-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E50x User Manual I2S signal description 22.4.2. There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 837: Figure 22-16. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32E50x User Manual Figure 22-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame. Figure 22-17.
Page 838: Figure 22-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32E50x User Manual bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits: D[23:8], and the second one should be a 16-bit data. The higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value.
Page 839: Figure 22-25. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32E50x User Manual Figure 22-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 22-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 22-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 22-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) 24-bit data...
Page 840: Figure 22-31. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32E50x User Manual than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below. Figure 22-31.
Page 841: Figure 22-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E50x User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 842: Figure22-40. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32E50x User Manual (DTLEN=01, CHLEN=1, CKPL=0) Figure22-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 22-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK...
Page 843: Figure 22-45. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32E50x User Manual (DTLEN=00, CHLEN=0, CKPL=1) Figure 22-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK 13 bits I2S_WS 32 bits I2S_SD Figure 22-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2...
Page 844: Figure 22-50. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32E50x User Manual Figure 22-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) I2S clock 22.4.4. Figure 22-51. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 22-51. Block diagram of I2S clock generator.The I2S interface clocks are configured by the DIV bits, the OF bit, the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register.
Page 845: Table 22-8. Audio Sampling Frequency Calculation Formulas
GD32E50x User Manual Table 22-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Form ula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) Operation 22.4.5.
Page 846: Figure 22-52. I2S Initialization Sequence
GD32E50x User Manual Figure 22-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 847 GD32E50x User Manual (TBE is high) and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmission buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 848: Figure 22-53. I2S Master Reception Disabling Sequence
GD32E50x User Manual Figure 22-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTD ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 849 GD32E50x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 850: Table 22-10. I2S Interrupt
GD32E50x User Manual  Transmission buffer empty flag (TBE) This bit is set when the transmission buffer is empty, the software can write the next data to the transmission buffer by writing the SPI_DATA register.  Reception buffer not empty flag (RBNE) This bit is set when reception buffer is not empty, which means that one data is received and stored in the reception buffer, and software can read the data by reading the SPI_DATA register.
Page 851 GD32E50x User Manual Interrupt Interrupt flag Description Clear m ethod enable bit TXURERR Transmission underrun error Read SPI_STAT register Read SPI_DATA register and then RXORERR Reception overrun error ERRIE read SPI_STAT register. FERR I2S format error Read SPI_STAT register...
Page 852 GD32E50x User Manual 22.5. Register definition SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 I2S1_ADD base address: 0x4000 3400 I2S2_ADD base address: 0x4000 4000 Control register 0 (SPI_CTL0) 22.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 853 GD32E50x User Manual When the transfer is managed by DMA, CRC value is transferred by hardw are. This bit should be cleared. In full-duplex or transmit-only mode, set this bit after the last data is w ritten to SPI_DATA register. In receive only mode, set this bit after the second last data is received.
Page 854 GD32E50x User Manual MSTMOD Master mode enable 0: Slave mode 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low w hen SPI is idle. 1: CLK pin is pulled high w hen SPI is idle. CKPH Clock phase selection 0: Capture the first data at the first clock transition.
Page 855 GD32E50x User Manual 1: Enable SPI NSS pulse mode NSSDRV Drive NSS output 0: Disable master NSS output 1: Enable master NSS output DMATEN Transmit buffer DMA enable 0: Disable transmit buffer DMA 1: Enable transmit buffer DMA, w hen the TBE bit in SPI_STAT is set, it w ill be a DMA request on corresponding DMA channel.
Page 856 GD32E50x User Manual RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardw are and cleared by a read operation on the SPI_DATA register follow ed by a read access to the SPI_STA T register. CONFERR SPI configuration error 0: No configuration fault occurs.
Page 857 GD32E50x User Manual Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register. the hardw are has tw o buffers, including transmission buffer and reception buffer. Write data to SPI_DATA w ill save the data to transmission buffer and read data from SPI_DATA w ill get the data from reception buffer.
Page 858 GD32E50x User Manual This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardw are computes the CRC value of the received bytes and saves them in RCRC register.
Page 859 GD32E50x User Manual is set, a read to this register could return an intermediate value. The different frame formats (LF bit of the SPI_CTL0) w ill get different CRC values. This register is reset w hen the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is set.
Page 860 GD32E50x User Manual This bit is not used in SPI mode. Reserved Must be kept at reset value. I2SSTD[1:0] I2S standard selection 00: I2S Phillips standard 01: MSB justified standard 10: LSB justified standard 11: PCM standard These bits should be configured w hen I2S mode is disabled. These bits are not used in SPI mode.
Page 861 GD32E50x User Manual Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: Disable I2S_MCK output 1: Enable I2S_MCK output This bit should be configured w hen I2S mode is disabled. This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1...
Page 862 GD32E50x User Manual This bit is only available in SPI0. Quad-SPI mode enable. QMOD 0: SPI is in single w ire mode. 1: SPI is in Quad-SPI mode. This bit can only be configured w hen the SPI is not busy (the TRANS bit is cleared). This bit is only available in SPI0.
Page 863: Table 23-1. Sqpi Controller Mode Definition
GD32E50x User Manual Serial/Quad Parallel Interface (SQPI) 23.1. Overview Serial/Quad Parallel Interface (SQPI) is a controller for external serial/dual/quad parallel interface memory peripheral. For example: SQPI-PSRAM and SQPI-FLASH. With this controller, users can use external SQPI interface memory as SRAM simply. 23.2.
Page 864: Figure 23-1. Sqpi_Pl Example
GD32E50x User Manual SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Address Phase SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Waitcycle Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout Data Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout Note: O – Output, I – Input, IO – Inout, 0 – Output 0, 1 – Output 1, X - Hiz 23.3.
Page 865: Figure 23-2. Sqpi_Sc Example
GD32E50x User Manual SQPI controller special command 23.3.2. SQPI controller special command (SQPI_SC) function can send only command phase with no address, waitcycle, and data phase. Special command function will be mandatory to SSS mode by hardware. If you set SQPI_SC bit to 1, you must read this bit and wait it cleared before doing other memory access because this can ensure the operation has performed in the interface.
Page 866: Figure 23-4. Sqpi_Clk Example
GD32E50x User Manual SQPI controller output clock configuration 23.3.4. SQPI clock period is configured by SQPI_CLKDIV bits. The frequency formula of SQPI_CLK �� ℎ�� _�� _�� + 1 Note: SQPI_CLKDIV cannot be 0. When SPI_CLKDIV field is even number, the output clock high level time has 1 HCLK period more than low level time.
Page 867: Figure 23-5. Sqpi Sss Mode Timing (Spi)
GD32E50x User Manual memory logic address will transfer to one of below timing: Figure 23-5. SQPI SSS Mode Timing (SPI) SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase Figure 23-6. SQPI SSQ Mode Timing SQPI_CLK SQPI_CSN SQPI_D0...
Page 868: Figure 23-8. Sqpi Qqq Mode Timing (Qpi)
GD32E50x User Manual Figure 23-8. SQPI QQQ Mode Timing (QPI) SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase Data Phase Figure 23-9. SQPI SSD Mode Timing SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase...
Page 869 GD32E50x User Manual SQPI Initial Register (SQPI_INIT) 23.4.1. Address offset: 0x00 Reset Value: 0x1805 0000 This register has to be accessed by word (32-bit). SQPI_PL SQPI_IDLEN[1:0] SQPI_ADDRBIT[4:0] SQPI_CLKDIV[5:0] SQPI_CMDBIT[1:0] Reserved Bits Fields Descriptions SQPI_PL Read data sample polarity. 0: Sample data at rising edge(default) 1: Sample data at falling edge.
Page 870 GD32E50x User Manual This register has to be accessed by word (32-bit). SQPI_RI SQPI_RMODE[2:0] SQPI_RWAITCYCLE[3:0] Reserved SQPI_RCMD[15:0] Bits Fields Descriptions SQPI_RID Send read ID command, command code comes from SQPI_RCMD. 30:23 Reserved Must be kept at reset value. 22:20 SQPI_RMODE[2:0] SQPI controller read command mode: 000: SSQ mode 001: SSS mode...
Page 871 GD32E50x User Manual Bits Fields Descriptions SQPI_SC Send special command w hich does not have address and data phase, command code comes from SQPI_WCMD. 30:23 Reserved Must be kept at reset value. 22:20 SQPI_WMODE[2:0] SQPI controller w rite command mode: 000: SSQ mode 001: SSS mode 010: SQQ mode...
Page 872 GD32E50x User Manual This register has to be accessed by word (32-bit). SQPI_IDH[31:16] SQPI_IDH[15:0] Bits Fields Descriptions 31:0 SQPI_IDH[31:0] ID High Data saved for SQPI read ID command This register only valid w hen SQPI_IDL EN = 00.
Page 873 GD32E50x User Manual Secure digital input/output interface (SDIO) Introduction 24.1. The secure digital input/output interface (SDIO) defines the SD, SD I/O, MMC and CE -ATA card host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC) and CE-ATA devices. The supported SD memory card and SD I/O card system specifications are defined in the SD card Association website at www.sdcard.org.
Page 874: Figure 24-1. Sdio "No Response" And "No Data" Operations
GD32E50x User Manual Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
Page 875: Figure 24-2. Sdio Multiple Blocks Read Operation
GD32E50x User Manual has an optional busy before it is ready to receive the data. Figure 24-2. SDIO multiple blocks read operation Figure 24-3. SDIO multiple blocks write operation Command Response Command Response Host to Device Device to Host Host to Device Device to Host DATA BLOCK CRC DATA BLOCK CRC...
Page 876: Figure 24-5. Sdio Sequential Write Operation
GD32E50x User Manual Figure 24-5. SDIO sequential write operation SDIO functional description 24.4. The following figure shows the SDIO structure. There have two main parts: The SDIO adapter block consists of control unit which manage clock, command unit  which manage command transfer, data unit which manage data transfer. ...
Page 877: Table 24-1. Sdio I/O Definitions
GD32E50x User Manual a one bit transfer on the command line (SDIO_CMD) and on all the data lines (SDIO_DAT). The SDIO_CLK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3.31, between 0 and 48 MHz for a Multimedia Card V4.2, or between 0 and 25 MHz for an SD/SD I/O card.
Page 878 GD32E50x User Manual avoid the corresponded error. Only state machines are frozen, the AHB interface is still alive. So, the FIFO can access by AHB bus. Command unit The command unit implements command transfer to the card. The data transfer flow is controlled by Command State Machine (CSM).
Page 879 GD32E50x User Manual CS_Receive Receive the response and check the CRC. → 1.Response Received in CE-ATA mode CS_Waitcompl interrupt disabled and w ait for CE-ATA Command Completion signal enabled → 2.Response Received in CE-ATA mode CS_Pend interrupt disabled and w ait for CE-ATA Command Completion signal disabled →...
Page 880 GD32E50x User Manual DS_Send Transmit data to the card. → 1.Data block transmitted DS_Busy → 2.DSM disabled DS_Idle → 3.Data FIFO underrun error occurs DS_Idle → 4. Internal CRC error DS_Idle DS_Busy Waits for the CRC status flag. → 1.Receive a positive CRC status DS_WaitS →...
Page 881 GD32E50x User Manual and memory. The following example describes how to implement this method: 1. Complete the card identification process 2. Increase the SDIO_CLK frequency 3. Send CMD7 to select the card and configure the bus width 4. Configure the DMA1 as follows: Enable DMA1 controller and clear any pending interrupts.
Page 882 GD32E50x User Manual Card functional description 24.5. Card registers 24.5.1. Within the card interface registers are defined: OCR, CID, CSD, EXT_CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
Page 883: Figure 24-7. Command Token Format
GD32E50x User Manual length, transfer rate or number of cards). The CSD register carries the information about the DSR register usage. The default value of the DSR register is 0x404. The host can use CMD4 to get the content of this register. SCR register: Just SD/SD I/O (if has memory port) have this register.
Page 884: Table 24-3. Card Command Classes (Cccs)
GD32E50x User Manual Command classes The command set of the Card system is divided into several classes (See Table 24-3. Card command classes (CCCs)). Each class supports a set of card functionalities. Table 24-3. Card command classes (CCCs) determines the setting of CCC from the card supported commands.
Page 885 GD32E50x User Manual CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61...
Page 886: Table 24-4. Basic Commands (Class 0)
GD32E50x User Manual ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC.CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card. CMD60, CMD61 are only available for CE-ATA device. 2.
Page 887 GD32E50x User Manual [31:26] Set to 0 [25:24] Access Only for MMC. Sw itches the [23:16] Index mode of operation of the selected CMD6 SWITCH [15:8] Value card or modifies the EXT_CS D [7:3] Set to 0 registers. [2:0] Cmd Set Command toggles card...
Page 888: Table 24-5. Block-Oriented Read Commands (Class 2)
GD32E50x User Manual Table 24-5. Block-Oriented read commands (class 2) Cm d Response type argum ent Abbreviation Description index form at the case of a Standar d Capacity SD and MMC, this command sets the block length (in bytes) for all follow ing bloc k commands (read, w rite, lock).
Page 889: Table 24-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32E50x User Manual Table 24-6. Stream read commands (class 1) and stream write commands (class 3) Cm d Response type argum ent Abbreviation Description index form at Reads data stream from the card, [31:0] data READ_DAT_UNTI starting at the given address, CMD11 adtc address...
Page 890: Table 24-8. Erase Commands (Class 5)
GD32E50x User Manual Cm d Response type argum ent Abbreviation Description index form at Programming card identification register. This command shall be issued only once. card contains CMD26 adtc [31:0] stuff bits PROGRA M_CID hardw are prevent this operation after first programming.
Page 891: Table 24-9. Block Oriented Write Protection Commands (Class 6)
GD32E50x User Manual Table 24-9. Block oriented write protection commands (class 6) Cm d Response type argum ent Abbreviation Description index form at If the card has w rite protection features, this command sets the w rite protection addressed group. The properties [31:0] data SET_WRITE_PRO of w rite protection are coded in...
Page 892: Table 24-11. Application-Specific Commands (Class 8)
GD32E50x User Manual Table 24-11. Application-specific commands (class 8) Cm d Response type argum ent Abbreviation Description index form at Sends host capacity support information (HCS) and asks [31]reserved bit the accessed card to send its [30]HCS operating condition [29:24]reserved SD_SEND_OP_ register(OCR) content in the ACMD41...
Page 893: Table 24-12. I/O Mode Commands (Class 9)
GD32E50x User Manual Table 24-12. I/O mode commands (class 9) Cm d Response type argum ent Abbreviation Description index form at Used to w rite and read 8 bit (register) data fields. command addresses a card and a register and provides the [31:16] RCA data for w riting if the w rite flag [15] register w rite...
Page 894: Table 24-13. Switch Function Commands (Class 10)
GD32E50x User Manual Cm d Response type argum ent Abbreviation Description index form at Count Note: 1.CMD39, CMD40 are only for MMC. 2. CMD52, CMD53 are only for SD I/O card. Table 24-13. Switch function commands (class 10) Cm d Response type argum ent...
Page 895: Figure 24-8. Response Token Format
GD32E50x User Manual  R7 : Card interface condition. The SD Memory Card support five types of them, R1 / R1b, R2, R3, R6, R7. And the SD I/O Card and MMC supports additional response types named R4 and R5, but they are not exactly the same for SD I/O Card and MMC.
Page 896: Table 24-15. Response R2
GD32E50x User Manual R2 (CID, CSD register) Code length is 136 bits. The contents of the CID register are sent as a response to the commands CMD2 and CMD10. The contents of the CSD register are sent as a response to CMD9.
Page 897: Table 24-18. Response R4 For Sd I/O
GD32E50x User Manual unique SD I/O response R4. Table 24-18. Response R4 for SD I/O [45:40] 39 [38:36] [34:32] 31 [30:8] [7:1] position Width ‘1111 ‘1111 ‘0’ ‘0’ ‘000’ Value 11’ 111’ Number descripti start transmiss Reser Memory Stuff Reser ion bit Present Bits...
Page 898: Figure 24-9. 1-Bit Data Bus Width
GD32E50x User Manual ‘0’ ‘0’ ‘000011’ ‘1’ Value start transmission New published RCA card status description CMD3 CRC7 of the card bits:23,22,19,12:0 R7 (Card interface condition) For SD memory only. Code length is 48 bits. The card support voltage information is sent by the response of CMD8.
Page 899: Figure 24-10. 4-Bit Data Bus Width
GD32E50x User Manual 4-bit data packet format Figure 24-10. 4-bit data bus width Start Byte Byte Byte Byte … … DAT3 … … DAT2 … … DAT1 … … DAT0 8-bit data packet format Figure 24-11. 8-bit data bus width Start Byte Byte...
Page 900: Table 24-23. Card Status
GD32E50x User Manual Type •E: Error bit. Send an error condition to the host. These bits are cleared as soon as the response (reporting the error) is sent out. •S: Status bit. These bits serve as information fields only, and do not alter the execution of the command being responded to.
Page 901 GD32E50x User Manual ’1’= error passw ord error been detected in lock/unlock card command. ’0’= no error COM_CRC_ERROR The CRC check of the previous ’1’= error command failed. ’0’= no error ILLEGAL_COMMAND Command not legal for the card ’1’= error state.
Page 902 GD32E50x User Manual 1 = ready receiving the command. If the 2 = identification command execution causes a 3 = stand by state change, it w ill be visible to 4 = transfer the host in the response to the 5 = send data next command.
Page 903: Table 24-24. Sd Status
GD32E50x User Manual Table 24-24. SD status Bits Identifier Type Value Description Clear Condition ’00’= 1 (default) [511: DAT_BUS_WIDTH Show s the currently defined ‘01’= reserved 510] data bus w idth that w as defined ‘10’= 4 bit w idth SET_BUS_W IDT H ‘11’= reserved command...
Page 904: Table 24-25. Performance Move Field
GD32E50x User Manual Bits Identifier Type Value Description Clear Condition time. [399: reserved 312] [311: reserved for manufacturer SIZE_OF_PROTECTED_AREA Setting this field differs between SDSC and SDHC/SDXC. In case of SDSC Card, the capacity of protected area is calculated as follows: Protected Area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.
Page 905: Table 24-26. Au_Size Field
GD32E50x User Manual PERFORMANCE_M OV E Value Definition Infinity AU_SIZE This 4-bit field indicates AU Size and the value can be selected from 16 KB. Table 24-26. AU_SIZE field AU_SIZE Value Definition Not Defined 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB...
Page 906: Table 24-29. Erase Timeout Field
GD32E50x User Manual ERASE_SIZ E Value Definition 0003h 3 AU ....FFFFh 65535 AU ERASE_TIMEOUT This 6-bit field indicates the T and the value indicates erase timeout from offset when ERASE multiple AUs are erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending...
Page 907 GD32E50x User Manual voltage range, identifies cards and asks them to publish Relative Card Address (RCA). This operation is done to each card separately on its own CMD line. All data communication in the Card Identification Mode uses the command line (CMD) only. During the card identification process, the card shall operate in the clock frequency of the identification clock rate F (400 kHz).
Page 908 GD32E50x User Manual the following steps: 1. Check if the card is connected. 2. Identify the card type; SD, MMC(CE-ATA), or SD I/O. – Send CMD5 first. If a response is received, then the card is SD I/O – If not, send ACMD41; if a response is received, then the card is SD. –...
Page 909 GD32E50x User Manual Single block or multiple block write 24.6.3. During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card. The block consists of start bits (1 or 4 bits LOW), data block, CRC and end bits(1 or 4 bits HIGH).
Page 910 GD32E50x User Manual task file, then use CMD61 to write the data. After writing to the CMD register, host starts executing a command, when the command is sent to the bus, the CMDRECV flag is set. 5. Write data to SDIO_FIFO. 6.
Page 911 GD32E50x User Manual read and CMD18 for a multiple-block read. For SD I/O cards, using CMD53 for both single- block and multiple-block transfers. For CE-ATA, first using CMD60 to write the ATA task file, then using CMD 61 to read the data. After writing to the CMD register, the host starts executing the command, when the command is sent to the bus, the CMDRECV flag is set.
Page 912 GD32E50x User Manual the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command. As the host sends CMD12, the card will respond with the TXURE bit set and return to Transfer state Stream read There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11).
Page 913 GD32E50x User Manual write blocks which are the basic writable units of the card. The size of the Erase Group is a card specific parameter and defined in the CSD. The host can erase a contiguous range of Erase Groups. Starting the erase process is a three steps sequence.
Page 914 GD32E50x User Manual Protection management 24.6.8. In order to allow the host to protect data against erase or write, three methods for the cards are supported in the card: CSD register for card protection (optional) The entire card may be write protected by setting the permanent or temporary write protect bits in the CSD.
Page 915: Table 24-31. Lock Card Data Structure
GD32E50x User Manual card data structure describes the structure of the command data block. Table 24-31. Lock card data structure Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved(all set to 0) ERASE LOCK_UNLOCK CLR_PWD...
Page 916 GD32E50x User Manual Reset the password Select a card (CMD7), if not previously selected.   Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the currently used password. Send the card lock/unlock command with the appropriate data block size on the data line ...
Page 917: Figure 24-12. Read Wait Control By Stopping Sdio_Clk
GD32E50x User Manual Read Wait operation Suspend/resume operation Interrupts The SD I/O supports these operations only if the SDIO_DATACTL[11] bit is set, except for read suspend that does not need specific hardware implementation. SD I/O read wait operation The optional Read Wait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The Read Wait operation allows a host to signal a card that is executing a read multiple (CMD53) operation to temporarily stall the data transfer while allowing the host to send commands to any function within the SD I/O card.
Page 918: Figure 24-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
GD32E50x User Manual SDIO_DATACTL[8] = 1) and data direction is from card to SD I/O (SDIO_DATACTL[1] = 1), the DSM directly moves from Idle to Read Wait. In Read Wait the DSM drives SDIO_DAT[2] to 0 after 2 SDIO_CLK clock cycles. In this state, when you set the RWSTOP bit (SDIO_DATACTL[9]), the DSM remains in Wait for two more SDIO_CLK clock cycles to drive SDIO_DAT[2] to 1 for one clock cycle.
Page 919: Figure 24-15. Read Interrupt Cycle Timing
GD32E50x User Manual on the SD interface. Pin number 8, which is used as SDIO_DAT[1] when operating in the 4- bit SD mode, is used to signal the card’s interrupt to the host. The us e of interrupt is optional for each card or function within a card.
Page 920: Figure 24-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
GD32E50x User Manual during a 4-bit multi-block write. Figure 24-17. Multiple block 4-Bit read interrupt cycle timing Figure 24-18. Multiple block 4-Bit write interrupt cycle timing CE-ATA specific operations 24.7.2. The CE-ATA device supports these specific operations: Receive command completion signal Send command completion disable signal The SDIO supports these operations only when SDIO_CMDCTL[14] is set.
Page 921: Figure 24-19. The Operation For Command Completion Disable Signal
GD32E50x User Manual Command completion disable signal The host may cancel the ability for the device to return a command completion signal by issuing the command completion signal disable. The host shall only issue the command completion signal disable when it has received an R1b response for an outstanding RW_MULTIPLE_BLOCK (CMD61) command.
Page 922 GD32E50x User Manual SDIO registers 24.8. SDIO base address: 0x4001 8000 Power control register (SDIO_PWRCTL) 24.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value PWRCTL[1:0] SDIO pow er control bits.
Page 923 GD32E50x User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division betw een the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL. 30:15 Reserved Must be kept at reset value. HWCLKEN Hardw are Clock Control enable bit If this bit is set, hardw are controls the SDIO_CLK on/off depending on the system...
Page 924 GD32E50x User Manual Command argument register (SDIO_CMDAGMT) 24.8.3. Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits...
Page 925 GD32E50x User Manual 1: CE-ATA enable NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used w hen CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
Page 926: Table 24-32. Sdio_Respx Register At Different Response Type
GD32E50x User Manual Command index response register (SDIO_RSPCMDIDX) 24.8.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RSPCMDIDX[5:0] Last response command index Read-only bits field.
Page 927 GD32E50x User Manual Register Short response Long response SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 Data timeout register (SDIO_DATATO) 24.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits...
Page 928 GD32E50x User Manual starts, the data counter loads this register and starts decrement. Note: If block data transfer selected, the content of this register must be a multiple of the block size (refer to SDIO_DATACTL). The data timer register and the data length register must be updated before being written to the data control register when need a data transfer.
Page 929 GD32E50x User Manual 0101: block size = 2 = 32 bytes 0110: block size = 2 = 64 bytes 0111: block size = 2 = 128 bytes 1000: block size = 2 = 256 bytes 1001: block size = 2 = 512 bytes 1010: block size = 2 = 1024 bytes...
Page 930 GD32E50x User Manual Bits Fields Descriptions 31:25 Reserved Must be kept at reset value 24:0 DATACNT[24:0] Data count value Read-only bits field. When these bits are read, the number of remaining data bytes to be transferred is returned. Status register (SDIO_STAT) 24.8.11.
Page 931 GD32E50x User Manual Transmit FIFO is full Receive FIFO is half full: at least 8 w ords can be read in the FIFO Transmit FIFO is half empty: at least 8 w ords can be w ritten into the FIFO RXRUN Data reception in progress TXRUN...
Page 932 GD32E50x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag. 21:11 Reserved Must be kept at reset value...
Page 933 GD32E50x User Manual ATAENDI SDIOINTI RXDTVA TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE CMDRUN DTBLKE CMDSEN CMDREC DTTMOU CMDTMO DTCRCE CCRCER RFHIE TFHIE RXRUNIE TXRUNIE STBITEIE DTENDIE RXOREIE TXUREIE NDIE UTIE RRIE Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDIE CE-ATA command completion signal received interrupt enable Write 1 to this bit to enable the interrupt.
Page 934 GD32E50x User Manual Write 1 to this bit to enable the interrupt. STBITEIE Start bit error interrupt enable Write 1 to this bit to enable the interrupt. DTENDIE Data end interrupt enable Write 1 to this bit to enable the interrupt. CMDSENDIE Command sent interrupt enable Write 1 to this bit to enable the interrupt.
Page 935 GD32E50x User Manual These bits define the remaining number w ords to be w ritten or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is w ord- aligned or SDIO_DA TALEN[24:2]+1 if SDIO_DATALEN is not w ord-aligned) w hen DATAEN is set, and start count decrement w hen a w ord w rite to or read from the FIFO.
Page 936 GD32E50x User Manual External memory controller (EXMC) Overview 25.1. The external memory controller EXMC, is used as a translator for MCU to access a variety of external memory. By configuring the related registers, it can automatically convert AMBA memory access protocol into a specific memory access protocol, such as SRAM, ROM, NOR Flash, NAND Flash and PC Card.
Page 937: Figure 25-1. The Exmc Block Diagram
GD32E50x User Manual Figure 25-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NAND-Flash/PC Card NOR-Flash/PSRAM Controller Controller NOR/PSRAM Shared PSRAM NOR/PSRAM NAND PC Card /NAND Pins Pins Pins Pins Pins Shared Pins Basic regulation of EXMC access...
Page 938: Figure 25-2. Exmc Memory Banks
GD32E50x User Manual External device address mapping 25.3.3. Figure 25-2. EXMC memory banks EXMC access space is divided into multiple banks. Each bank is 256 Mbytes. The first bank (Bank0) is further divided into four regions, and each region is 64 Mbytes. Bankx(x=1, 2) is divided into two spaces, the attribute memory space and the common memory space.
Page 939 GD32E50x User Manual Figure 25-3. Four regions of bank0 address mapping HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency. EXMC can adjust HADDR to accommodate the data width of the external memory according to the following rules. –...
Page 940: Figure 25-4. Nand/Pc Card Address Mapping
GD32E50x User Manual Figure 25-4. NAND/PC Card address mapping EXMC Memory Address Memory Space Bank 0x7000 0000 Common Memory Space 0x73FF FFFF Bank1 0x7800 0000 Attribute Memory Space 0x7BFF FFFF 0x8000 0000 Common Memory Space 0x83FF FFFF Bank2 0x8800 0000 Attribute Memory Space 0x8BFF FFFF...
Page 941: Table 25-1. Nor Flash Interface Signals Description
GD32E50x User Manual – When HADDR [17:16] = 00, the data area is selected. – When HADDR [17:16] = 01, the command area is selected. – When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as follows.
Page 942: Table 25-2. Psram Non-Muxed Signal Description
GD32E50x User Manual EXMC Pin Direction Mode Functional description Async/Sync Input/output Data bus (non-muxed) Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal EXMC_NL( NA DV) Output Async/Sync Address valid Table 25-2.
Page 943: Table 25-4. Nor / Psram Controller Timing Parameters
GD32E50x User Manual Mem ory Mem ory Access Mode Transaction Transaction Com m ents Size Size EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync Split into 2 EXMC Sync accesses...
Page 944: Table 25-5. Exmc_Timing Models
GD32E50x User Manual Param eter Function Access m ode Unit DSET Data setup time Async HCLK AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 25-5. EXMC_timing models Tim ing Extend Write tim ing Read tim ing Mode description m odel m ode...
Page 945: Figure 25-6. Mode 1 Read Access
GD32E50x User Manual Figure 25-6. Mode 1 read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK) Figure 25-7.
Page 946: Figure 25-8. Mode A Read Access
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value NREN No effect Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 0x0000 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect Time betw een EXMC_NE[x] rising edge to 19-16...
Page 947: Figure 25-9. Mode A Write Access
GD32E50x User Manual Figure 25-9. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The difference between mode A and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode A write timing configuration is independent of its read configuration.
Page 948: Figure 25-10. Mode 2/B Read Access
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value Time betw een EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30 Reserved...
Page 949: Figure 25-11. Mode 2 Write Access
GD32E50x User Manual Figure 25-11. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET+1 HCLK) (DSET HCLK) Figure 25-12. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 950: Figure 25-13. Mode C Read Access
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value NREN Depends on memory NRTP 0x2, NOR Flash NRMUX NRBKEN EXMC_SNTCFGx( Read and w rite in m ode 2,read in m ode B) 31-30 Reserved 0x0000 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect...
Page 951: Figure 25-14. Mode C Write Access
GD32E50x User Manual Figure 25-14. Mode C write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The differences between mode C and mode 1 write timing are that read/write timing is specified by the same set of timing configuration, while mode C write timing configuration is independent of its read configuration, and the toggle of NOE and NADV are different.
Page 952: Figure 25-15. Mode D Read Access
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value Time betw een EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved...
Page 953: Figure 25-16. Mode D Write Access
GD32E50x User Manual Figure 25-16. Mode D write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WAHLD+1 HCLK) (WDSET HCLK) Table 25-10.
Page 954: Figure 25-17. Multiplex Mode Read Access
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value AHLD Depends on memory and user ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode D:0x3 27-20 Reserved 0x00 Time betw een EXMC_NE[x] rising edge to 19-16 WBUSLAT EXMC_NE[x] falling edge...
Page 955: Table 25-11. Multiplex Mode Related Registers Configuration
GD32E50x User Manual Table 25-11. Multiplex mode related registers configuration Bit Position Bit Nam e Reference Setting Value EXMC_SNCTLx 31-20 Reserved 0x000 SYNCWR 18-16 ASYNCWAIT Depends on memory EXMODEN NRWTEN WREN Depends on memory NRWTCFG No effect WRAPEN NRWTPOL Meaningful only w hen the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 956: Figure 25-19. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32E50x User Manual maxT ≥ T (25-2) WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE ≥(maxT )+4HCLK (25-3) DATA_SETUP WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE Otherwise ≥ 4HCLK (25-4) DATA_SETUP Figure 25-19. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1...
Page 957 GD32E50x User Manual CKDIV is the synchronous clock divider ratio, it is configured through the CKDIV control field in the EXMC_SNTCFGx register. 1. Data latency and NOR Flash latency Data latency is the number of EXMC_CLK cycles to wait before sampling the data. The relationship between data latency and NOR Flash specification’s latency parameter is as follows: For NOR Flash’s specification excluding the EXMC_NADV cycle, their relationship should be:...
Page 958: Figure 25-21. Read Timing Of Synchronous Multiplexed Burst Mode
GD32E50x User Manual For synchronous burst transmission, if the needed data of AHB is 16-bit, EXMC will perform a burst transmission whose length is 1. If the needed data of AHB is 32-bit, EXMC will make the transmission divided into two 16-bit transmissions, that is, EXMC performs a burst transmission whose length is 2.
Page 959: Figure 25-22. Write Timing Of Synchronous Multiplexed Burst Mode
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value EXMC_SNCTLx Depends on memory，0x1/0x2 NRTP NRMUX 0x1, Depends on memory and users NRBKEN EXMC_SNTCFGx( Read) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1, EXMC_CLK=2HCLK Time betw een EXMC_NE[x] rising edge to 19-16 BUSLAT...
Page 960: Table 25-14. 8-Bit Or 16-Bit Nand Interface Signal
GD32E50x User Manual Bit Position Bit Nam e Reference Setting Value EXMC_SNCTLx AYSNCWAIT EXMODEN NRWTEN Depends on memory WREN NRWTCFG 0x0(Here must be zero) WRAPEN NTWTPOL Depends on memory SBRSTEN No effect Reserved NREN Depends on memory NRTP NRMUX 0x1, Depends on users NRBKEN EXMC_SNTCFGx( Write) 31-30...
Page 961: Table 25-15. 16-Bit Pc Card Interface Signal
GD32E50x User Manual EXMC Pin Direction Functional description EXMC_NOE( NRE) Output Output enable EXMC_NWE Output Write enable EXMC_NWAIT/ Input NAND Flash ready/busy input signal to the EXMC, x=1, 2 EXMC_INT[x] Table 25-15. 16-bit PC Card interface signal EXMC Pin Direction Functional description EXMC_A[10:0] Output...
Page 962: Figure 25-23. Access Timing Of Common Memory Space Of Pc Card Controller
GD32E50x User Manual such as EXMC_NPCTLx, EXMC_NPINTENx, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 and EXMC_NECCx. Among these registers, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 registers contain four timing parameters individually which are configured according to user specification and features of the external memory. Table 25-17. NAND Flash or PC Card programmable parameters NAND Flash/ Program m able param eter Unit...
Page 963: Figure 25-24. Access To None "Nce Don't Care" Nand Flash
GD32E50x User Manual signal (EXMC_A[16]) or address latch signal (EXMC_A[17]), namely, the CPU needs to perform write operation in particular address. Example: NAND Flash read operation steps: Configure EXMC_NPCTLx and EXMC_NPCTCFGx register. When pre-waiting is needed, EXMC_NPATCFGx has to be configured. Send the command of NAND Flash read operation to the common space.
Page 964 GD32E50x User Manual Write ADD1 into NAND Flash bank common space address area. Write ADD2 into NAND Flash bank common space address area. Write ADD3 into NAND Flash bank common space address area. Write CMD1 into NAND Flash bank attribute space command area. In step 6, EXMC uses the operation timing defined in EXMC_NPATCFGx register.
Page 965 GD32E50x User Manual 8- or 16-bit access operation is being performed. EXMC_NWE and EXMC_NOE dictates whether the on-going operation is a write or read operation, and EXMC_NREG is low during attribute space access. IO space: EXMC_NCE3_x (x = 0, 1) is the chip enable signal, it indicates whether 8- or 16-bit access operation is being performed.
Page 966 GD32E50x User Manual Registers definition 25.4. EXMC base address: 0xA000 0000 NOR/PSRAM controller registers 25.4.1. SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DX This register has to be accessed by word (32-bit) SYNCWR CPS[2:0]...
Page 967 GD32E50x User Manual insertion via the NWAIT signal: 0: Disable NWAIT signal 1: Enable NWAIT signal WREN Write enable 0: Disabled w rite in the bank by the EXMC, otherw ise an AHB error is reported 1: Enabled w rite in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only w ork in synchronous mode 0: NWAIT signal is active one data cycle before w ait state...
Page 968 GD32E50x User Manual SRAM/NOR Flash timing configuration registers (EXMC_SNTCFGx) (x=0, 1, 2, Address offset: 0x04 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0FFF FFFF This register has to be accessed by word(32-bit) Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0]...
Page 969 GD32E50x User Manual This field is meaningful only in asynchronous access. 0x00: Reserved 0x01: Data setup time = 2 * HCLK period …… 0xFF: Data setup time = 256 * HCLK period AHLD[3:0] Address hold time This field is used to set the time of address hold phase, w hich only used in mode D and multiplexed mode.
Page 970 GD32E50x User Manual 11: Mode D access 27:20 Reserved Must be kept at reset value. 19:16 WBUSLAT[3:0] Bus latency Bus latency added at the end of each w rite transaction to match w ith the minimu m time betw een consecutive transactions. 0x0: Bus latency = 1 * HCLK period 0x1: Bus latency = 2 * HCLK period ……...
Page 971 GD32E50x User Manual ATR[2:0] CTR[3:0] Reserved ECCEN NDW[1:0] NDTP NDBKEN NDWTEN Reserved Bits Fields Description 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0]...
Page 972 GD32E50x User Manual 0: Disable w ait function 1: Enable w ait function Reserved Must be kept at reset value. NAND Flash/PC Card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0046 (for bank1 and bank2), 0x0000 0040 (for bank3) This register has to be accessed by word (32-bit) In addition to interrupt controlling bits, this register also contains a FIFO empty status bit,...
Page 973 GD32E50x User Manual INTHS Interrupt high-level status 0: Not detect interrupt high-level 1: Detect interrupt high-level INTRS Interrupt rising edge status 0: Not detect interrupt rising edge 1: Detect interrupt rising edge NAND Flash/PC Card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFCFC FCFC...
Page 974 GD32E50x User Manual 0x01: COMWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: COMWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: Reserved COMSET[7:0] Common memory setup time Define the time to build address before sending command 0x00: COMSET = 1 * HCLK ……...
Page 975 GD32E50x User Manual 0xFF: Reserved 15:8 ATTWAIT[7:0] Attribute memory w ait time Define the minimum time to maintain command 0x00: Reserved 0x01: ATTWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: ATTWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: Reserved ATTSET[7:0] Attribute memory setup time...
Page 976 GD32E50x User Manual 15:8 IOWAIT[7:0] IO space w ait time Define the minimum time to maintain command 0x00: Reserved 0x01: IOWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFF: IOWAIT = 256 * HCLK (+NWAIT active cycles) IOSET[7:0] IO space setup time Define the time to build address before sending command 0x00: IOSET = 1 * HCLK ……...
Page 977 GD32E50x User Manual Controller area network (CAN) Overview 26.1. CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The CAN network interfaces of the GD32E503xx, GD32E505xx and GD32E507xx series supports the CAN protocol 2.0A and B, and the GD32E508xx series also supports the ISO11898-1:2015 and BOSCH CAN-FD specifications.The CAN interface automatically handles the transmission and the reception of CAN frames.
Page 978: Figure 26-1. Can Module Block Diagram
GD32E50x User Manual  Disable retransmission automatically in time-triggered communication mode.  16-bit free timer  Time stamp on SOF reception  Time stamp sent in last two data bytes Function overview 26.3. Figure 26-1. CAN module block diagram shows the CAN block diagram. Figure 26-1.
Page 979 GD32E50x User Manual register. Initial working mode When the configuration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set.
Page 980: Figure 26-2. Transmission Register
GD32E50x User Manual Loopback communication mode Loopback communication mode means the transmitted messages are transferred into the Rx FIFOs, the RX pin is disconnected from the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave.
Page 981: Figure 26-3. State Of Transmit Mailbox
GD32E50x User Manual If FD frame would be transmitted, always write TMDATA00 registers when mailbox 0 is used, TMDATA01 register when mailbox 1 is used and TMDATA02 register when mailbox 2 is used until the end. For example, if application wants to transmit 64 bytes data using mailbox0, it needs to write the 64 bytes data through TMDATA00 register for 16 times.
Page 982 GD32E50x User Manual successful. Transmission options Abort MST bit in CAN_TSTAT register can abort the transmission. If the transmit mailbox’s status is pending or scheduled, the abort of transmission can be done immediately. In the transmit state, the abort of transmission does not take effect immediately until the transmission is finished.
Page 983: Figure 26-4. Reception Register
GD32E50x User Manual Figure 26-4. Reception register RFIFO0 RFIFOMI0 RFIFOMP0 Receive FIFO0 RFIFOMDATA00 RFIFOMDATA10 Application RFIFOMI1 RFIFOMP1 Receive FIFO1 RFIFOMDATA01 RFIFOMDATA11 RFIFO1 Rx FIFO Rx FIFO has three mailboxes. The reception frames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of frames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
Page 984: Figure 26-5. 32-Bit Filter
GD32E50x User Manual Steps of receiving a message Step 1: Check the number of frames in the Rx FIFO. Step Read CAN_RFIFOMIx, CAN_RFIFOMPx, CAN_RFIFOMDATA0x CAN_RFIFOMDATA1x. Step 3: Set the RFD bit in CAN_RFIFOx register. Filtering function 26.3.5. The CAN receives frames from the CAN bus. If the frame passes the filter, it is stored in the Rx FIFOs.
Page 985: Figure 26-8. 16-Bit Mask Mode Filter
GD32E50x User Manual Figure 26-8. 16-bit mask mode filter List mode The filter consists of frame identifiers. The filter can determine whether a frame will be discarded or not. When one frame arrived, the filter will check which member can match the identifier of the frame.
Page 986: Table 26-2. Filtering Index
GD32E50x User Manual Filtering index Each filter number corresponds to a filtering rule. When the frame which is associated with a filter number N passes the filters, the filter index is N. It stores in the FI bits in CAN_RFIFOMPx. Filter bank has filter index once it is associated with the FIFO no matter whether the bank is active or not.
Page 987 GD32E50x User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank nunber bank nunber F9DATA0[31:16]-16bits- F11DATA0[31:16]-16bits- Mask F9DATA1[15:0]-16bits- F11DATA1[15:0]-16bits- ID F9DATA1[31:16]-16bits- F11DATA1[31:16]-16bits- Mask F12DATA0-32bits-ID F13DATA0-32bits-ID F12DATA1-32bits-Mask F13DATA1-32bits- ID Priority The filters have the priority rules: 32-bits mode is higher than 16-bits mode. List mode is higher than mask mode.
Page 988: Figure 26-11. The Bit Time
GD32E50x User Manual Bit time On the bit-level, the CAN protocol uses synchronous bit transmission. This not only enhances the transmitting capacity but also requires a sophisticated method of bit synchronization. While bit synchronization in a character-oriented transmission (asynchronous) is performed upon the reception which the start bit is available with each character, the synchronous transmission protocol just need one start bit available at the beginning of a frame.
Page 989 GD32E50x User Manual If a valid edge is detected in BS1, not in SYNC_SEG, BS1 is added up to SJW maximumly, so that the sample point is delayed. Conversely, if a valid edge is detected in BS2, not in SYNC_SEG, BS2 is cut down to SJW at most, so that the transmit point is moved earlier.
Page 990 GD32E50x User Manual CAN_FDSTAT register to 1. The transmission of ESI bit (the bit before DLC bits, refer to ISO11898-1 or Bosch CAN FD Specification V1.0) is defined by ESIMOD bit in CAN_FDCTL register and ESI bit in CAN_TMPx register. If ESIMOD bit is 0, it will transmit the dominant bit by error active nodes and transmit the recessive bit by error passive nodes.
Page 991: Figure 26-12. Transmitter Delay Measurement
GD32E50x User Manual Figure 26-12. Transmitter Delay Measurement CANTX CANRX TDCV TDCO TDCMOD=0,TDCV>=TD TDCO TDCMOD=1 SSP position TDCF TDCO TDCMOD=0,TDCV<TDCF SSP position Error flags 26.3.10. The state of CAN bus can be reflected by Transmit Error Counter (TECNT) and Receive Error Counter (RECNT) of CAN_ERR register.
Page 992 GD32E50x User Manual The interrupt sources can be classified as:  Transmit interrupt  FIFO0 interrupt  FIFO1 interrupt  Error and status change interrupt Transmit interrupt The transmit interrupt can be generated by any of the following conditions and TMEIE bit in CAN_INTEN register will be set: ...
Page 993: Table 26-3. Can Event / Interrupt Flags
GD32E50x User Manual Table 26-3. CAN Event / Interrupt The CAN bus controller interrupt conditions can refer to flags. Table 26-3. CAN Event / Interrupt flags nterrupt event nterrupt / Event flag Enable control bit Mailbox 0 transmit finished flag (MTF0) Transmit interrupt Mailbox 1 transmit finished flag (MTF1) TMEIE...
Page 994 GD32E50x User Manual CAN registers 26.4. CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 CAN2 base address: 0x4000 CC00 Control register (CAN_CTL) 26.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit). Reserved SLPWMO SWRST...
Page 995 GD32E50x User Manual If this bit is set, the CAN leaves sleep w orking mode w hen CAN bus activity is detected, and SLPWMOD bit in CAN_CTL register w ill be cleared automatically. 0: The sleeping w orking mode is left manually by softw are 1: The sleeping w orking mode is left automatically by hardw are Automatic retransmission disable 0: Enable automatic retransmission...
Page 996 GD32E50x User Manual RX level LASTRX Last sample value of RX pin Receiving state 0: CAN is not w orking in the receiving state 1: CAN is w orking in the receiving state Transmitting state 0: CAN is not w orking in the transmitting state 1: CAN is w orking in the transmitting state Reserved Must be kept at reset value.
Page 997 GD32E50x User Manual 1: CAN is in the state of sleep w orking mode Initial w orking state This bit is set by hardw are w hen the CAN enters initial w orking mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal w orking mode to initial w orking mode, it must w ait the current frame transmission or reception to be completed.
Page 998 GD32E50x User Manual 0: Transmit mailbox 1 not empty 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in w hich the frame w ill be transmitted if at least one mailbox is empty.
Page 999 GD32E50x User Manual 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardw are w hen next transmit starts. MAL1 Mailbox 1 arbitration lost This bit is set w hen the arbitration lost occurs. This bit is reset by w ritting 1 to this bit or MTF1 bit in CAN_TSTAT register.
Page 1000 GD32E50x User Manual 1: Mailbox 0 transmit finished Receive message FIFO0 register (CAN_RFIFO0) 26.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved...

This manual is also suitable for:

Gd32e503 Gd32e505 Gd32e507 Gd32e508 Gd32eprt