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GigaDevice Semiconductor GD32F20x Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32F20x. We have
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GigaDevice Semiconductor GD32F20x manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32F20x User Manual (939 pages)
Arm Cortex-M3 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 8 MB
Table of Contents
Table of Contents
2
List of Figures
20
List of Tables
28
1 System and Memory Architecture
32
Arm Cortex-M3 Processor
32
Figure 1-1. Cortex ® -M3 Block Diagram
32
System Architecture
33
Figure 1-2. Gd32F20X Connectivity Line Series System Architecture
33
Memory Map
34
Table 1-1 Memory Map of Gd32F20X Devices
35
Bit-Banding
38
On-Chip SRAM Memory
39
On-Chip Flash Memory
39
Boot Configuration
39
Table 1-2. each Block of SRAM
39
Device Electronic Signature
40
Table 1-3. Boot Modes
40
Table 1-4. Bootloader Supported Peripherals
40
Memory Size Information
41
Unique Device ID (96 Bits)
41
System Configuration Registers
42
2 Flash Memory Controller (FMC)
44
Overview
44
Characteristics
44
Function Overview
44
Flash Memory Architecture
44
Table 2-1. Gd32F20X_Cl
44
Read Operations
45
Unlock the Fmc_Ctlx Registers
45
Page Erase
46
Mass Erase
47
Figure 2-1. Process of Page Erase Operation
47
Main Flash Programming
48
Figure 2-2. Process of Mass Erase Operation
48
Figure 2-3. Process of Word Program Operation
49
Option Bytes Erase
50
Option Bytes Modify
50
Option Bytes Description
51
Table 2-2. Option Byte
51
Page Erase/Program Protection
52
Security Protection
52
Register Definition
54
Wait State Register (FMC_WS)
54
Unlock Key Register 0 (FMC_KEY0)
54
Option Byte Unlock Key Register (FMC_OBKEY)
55
Status Register 0 (FMC_STAT0)
55
Control Register 0 (FMC_CTL0)
56
Address Register 0 (FMC_ADDR0)
57
Option Byte Status Register (FMC_OBSTAT)
58
Erase/Program Protection Register (FMC_WP)
58
Unlock Key Register 1 (FMC_KEY1)
59
Status Register 1 (FMC_STAT1)
59
Control Register 1 (FMC_CTL1)
60
Address Register 1 (FMC_ADDR1)
61
Wait State Enable Register (FMC_WSEN)
61
Product ID Register (FMC_PID)
62
3 Power Management Unit (PMU)
63
Overview
63
Characteristics
63
Function Overview
63
Figure 3-1. Power Supply Overview
63
Backup Domain
64
VDD / V Dda
65
Figure 3-2. Waveform of the por / PDR
65
Figure 3-3. Waveform of the LVD Threshold
66
Power Domain
67
Power Saving Modes
67
Table 3-1. Power Saving Mode Summary
69
Register Definition
70
Control Register (PMU_CTL)
70
Control and Status Register (PMU_CS)
71
4 Backup Registers (BKP)
73
Overview
73
Characteristics
73
Function Overview
73
RTC Clock Calibration
73
Tamper0 Detection
74
Tamper1 Detection
74
Waveform Detection
74
Register Definition
75
Backup Data Register X (Bkp_Datax) (X= 0
75
RTC Signal Output Control Register (BKP_OCTL)
75
Tamper Pin Control Register0 (BKP_TPCTL0)
76
Tamper Control and Status Register (BKP_TPCS)
77
Tamper Pin Control Register1 (BKP_TPCTL1)
78
5 Reset and Clock Unit (RCU)
80
Reset Control Unit (RCTL)
80
Overview
80
Function Overview
80
Clock Control Unit (CCTL)
81
Overview
81
Figure 5-1. the System Reset Circuit
81
Figure 5-2. Clock Tree
82
Characteristics
83
Function Overview
83
Figure 5-3. HXTAL Clock Source
84
Figure 5-4. HXTAL Clock Source in Bypass Mode
84
Table 5-1. Clock Output 0 Source Select
87
Table 5-2. Clock Output 1 Source Select
87
Table 5-3. 1.2V Domain Voltage Selected in Deep-Sleep Mode
87
Register Definition
89
Control Register (RCU_CTL)
89
Configuration Register 0 (RCU_CFG0)
91
Interrupt Register (RCU_INT)
94
APB2 Reset Register (RCU_APB2RST)
97
APB1 Reset Register (RCU_APB1RST)
100
AHB1 Enable Register (RCU_AHB1EN)
102
APB2 Enable Register (RCU_APB2EN)
104
APB1 Enable Register (RCU_APB1EN)
107
Backup Domain Control Register (RCU_BDCTL)
110
Reset Source/Clock Register (RCU_RSTSCK)
111
AHB1 Reset Register (RCU_AHB1RST)
113
Configuration Register 1 (RCU_CFG1)
113
Deep-Sleep Mode Voltage Register (RCU_DSV)
116
AHB2 Enable Register (RCU_AHB2EN)
116
APB2 Additional Enable Register (RCU_ADDAPB2EN)
117
APB1 Additional Enable Register (RCU_ADDAPB1EN)
118
AHB2 Reset Register (RCU_AHB2RST)
119
APB2 Additional Reset Register (RCU_ADDAPB2RST)
119
APB1 Additional Reset Register (RCU_ADDAPB1RST)
120
Configuration Register 2 (RCU_ CFG2)
121
PLLT Control Register (RCU_PLLTCTL)
122
PLLT Interrupt Register (RCU_PLLTINT)
123
PLLT Configuration Register (RCU_PLLTCFG)
124
6 Interrupt/Event Controller(EXTI)
126
Overview
126
Characteristics
126
Interrupts Function Overview
126
Table 6-1. NVIC Exception Types in Cortex ® -M3
127
Table 6-2. Interrupt Vector Table
127
External Interrupt and Event (EXTI) Block Diagram
130
External Interrupt and Event Function Overview
130
Figure 6-1. Block Diagram of EXTI
130
Table 6-3. EXTI Source
131
Register Definition
132
Interrupt Enable Register (EXTI_INTEN)
132
Event Enable Register (EXTI_EVEN)
132
Rising Edge Trigger Enable Register (EXTI_RTEN)
133
Falling Edge Trigger Enable Register (EXTI_FTEN)
133
Software Interrupt Event Register (EXTI_SWIEV)
133
Pending Register (EXTI_PD)
134
7 General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
135
Overview
135
Characteristics
135
Function Overview
135
GPIO Pin Configuration
136
Figure 7-1. the Basic Structure of a General-Pupose I/O
136
Table 7-1. GPIO Configuration Table
136
External Interrupt/Event Lines
137
Alternate Functions (AF)
137
Input Configuration
137
Figure 7-2. Basic Structure of Input Configuration
137
Output Configuration
138
Analog Configuration
138
Figure 7-3. Basic Structure of Output Configuration
138
Figure 7-4. Basic Structure of Analog Configuration
138
Alternate Function (AF) Configuration
139
IO Pin Function Selection
139
Figure 7-5. Basic Structure of Alternate Function Configuration
139
GPIO Locking Function
140
Remapping Function I/O and Debug Configuration
140
Introduction
140
Main Features
140
JTAG/SWD Alternate Function Remapping
140
Table 7-2. Debug Interface Signals
140
ADC AF Remapping
141
Table 7-3. Debug Port Mapping
141
Table 7-4. ADC0/1 External Trigger Routine Conversion AF Remapping Function
141
TIMER AF Remapping
142
Table 7-5. Timerx Alternate Function Remapping
142
USART AF Remapping
143
Table 7-6. TIMER4 Alternate Function Remapping
143
I2C AF Remapping
144
Table 7-7. USART0/1/2 Alternate Function Remapping
144
SPI AF Remapping
145
Table 7-8. SPI0/SPI1/I2S1/SP2/I2S2 Alternate Function Remapping
145
CAN0/1 AF Remapping
146
Table 7-9. CAN0/1 Alternate Function Remapping
146
Ethernet AF Remapping
147
Table 7-10. ENET Alternate Function Remapping
147
DCI AF Remapping
148
TLI AF Remapping
148
Table 7-11. DCI Alternate Function Remapping
148
Table 7-12. TLI Alternate Function Remapping
148
CLK Pins AF Remapping
149
Table 7-13. OSC32 Pins Configuration
149
Table 7-14. OSC Pins Configuration 1
149
Table 7-15. OSC Pins Configuration 2
150
Register Definition
151
Port Control Register 0 (Gpiox_Ctl0, X=A
151
Port Control Register 1 (Gpiox_Ctl1, X=A
153
Port Input Status Register (Gpiox_Istat, X=A
155
Port Output Control Register (Gpiox_Octl, X=A
155
Port Bit Operate Register (Gpiox_Bop, X=A
156
Port Bit Clear Register (Gpiox_Bc, X=A
156
Port Configuration Lock Register (Gpiox_Lock, X=A
157
Event Control Register (AFIO_EC)
157
AFIO Port Configuration Register 0 (AFIO_PCF0)
158
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
162
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
164
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
165
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
167
AFIO Port Configuration Register 1 (AFIO_PCF1)
168
AFIO Port Configuration Register 2 (AFIO_PCF2)
169
AFIO Port Configuration Register 3 (AFIO_PCF3)
172
AFIO Port Configuration Register 4 (AFIO_PCF4)
176
AFIO Port Configuration Register 5 (AFIO_PCF5)
179
8 Cyclic Redundancy Checks Management Unit (CRC)
183
Overview
183
Characteristics
183
Figure 8-1. Block Diagram of CRC Management Unit
183
Function Overview
184
Register Definition
185
Data Register (CRC_DATA)
185
Free Data Register (CRC_FDATA)
185
Control Register (CRC_CTL)
186
9 True Random Number Generator (TRNG)
187
Overview
187
Characteristics
187
Function Overview
187
Figure 8-2. TRNG Block Diagram
187
Operation Flow
188
Error Flags
188
Register Definition
189
Control Register (TRNG_CTL)
189
Status Register (TRNG_STAT)
189
Data Register (TRNG_DATA)
190
10 Cryptographic Acceleration Unit (CAU)
192
Overview
192
Characteristics
192
CAU Data Type and Initialization Vectors
193
Data Type
193
Figure 10-1. DATAM no Swapping and Half-Word Swapping
193
Initialization Vectors
194
Cryptographic Acceleration Processor
194
Figure 10-2. DATAM Byte Swapping and Bit Swapping
194
Figure 10-3. CAU Diagram
194
DES/TDES Cryptographic Acceleration Processor
195
Figure 10-4. DES/TDES ECB Encryption
196
Figure 10-5. DES/TDES ECB Decryption
197
Figure 10-6. DES/TDES CBC Encryption
198
AES Cryptographic Acceleration Processor
199
Figure 10-7. DES/TDES CBC Decryption
199
Figure 10-8. AES ECB Encryption
200
Figure 10-9. AES ECB Decryption
200
Figure 10-10. AES CBC Encryption
201
Figure 10-11. AES CBC Decryption
202
Figure 10-12. Counter Block Structure
202
Figure 10-13. AES CTR Encryption/Decryption
202
Operating Modes
203
CAU DMA Interface
204
CAU Interrupts
204
CAU Suspended Mode
205
Register Definition
207
CAU Control Register (CAU_CTL)
207
CAU Status Register 0 (CAU_STAT0)
208
CAU Data Input Register (CAU_DI)
209
CAU Data Output Register (CAU_DO)
210
CAU DMA Enable Register (CAU_DMAEN)
210
CAU Interrupt Enable Register (CAU_INTEN)
211
CAU Status Register 1 (CAU_STAT1)
211
CAU Interrupt Flag Register (CAU_INTF)
212
CAU Key Registers (CAU_KEY0
212
CAU Initial Vector Registers (CAU_IV0
215
11 Hash Acceleration Unit (HAU)
217
Overview
217
Characteristics
217
HAU Data Type
217
Figure 11-1. DATAM no Swapping and Half-Word Swapping
218
Figure 11-2. DATAM Byte Swapping and Bit Swapping
218
HAU Core
219
Automatic Data Padding
219
Figure 11-3. HAU Block Diagram
219
Digest Computing
220
Hash Mode
221
HMAC Mode
221
HAU Interrupt
221
Register Definition
223
HAU Control Register (HAU_CTL)
223
HAU Data Input Register (HAU_DI)
224
HAU Configuration Register (HAU_CFG)
225
HAU Data Output Register (HAU_DO0
226
HAU Interrupt Enable Register (HAU_INTEN)
228
HAU Status and Interrupt Flag Register (HAU_STAT)
228
12 Direct Memory Access Controller (DMA)
230
Overview
230
Characteristics
230
Block Diagram
231
Function Overview
231
DMA Operation
231
Figure 12-1. Block Diagram of DMA
231
Table 12-1. DMA Transfer Operations (Normal Mode)
232
Peripheral Handshake
233
Table 12-2. DMA Transfer Operations (Full_Data Mode)
233
Arbitration
234
Address Generation
234
Figure 12-2. Handshake Mechanism
234
Circular Mode
235
Memory to Memory Mode
235
Channel Configuration
235
Interrupt
235
DMA Request Mapping
236
Figure 12-3. DMA Interrupt Logic
236
Table 12-3. Interrupt Events
236
Table 12-4. DMA0 Requests for each Channel
236
Table 12-5. DMA1 Requests for each Channel
236
Figure 12-4. DMA0 Request Mapping
237
Figure 12-5. DMA1 Request Mapping
238
Register Definition
240
Interrupt Flag Register (DMA_INTF)
240
Interrupt Flag Clear Register (DMA_INTC)
240
Channel X Control Register (Dma_Chxctl)
241
Channel X Counter Register (Dma_Chxcnt)
243
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
244
Channel X Memory Base Address Register (Dma_Chxmaddr)
244
DMA Additional Configuration Register (DMA_ACFG)
245
13 Debug (DBG)
246
Overview
246
JTAG/SW Function Overview
246
Switch JTAG or SW Interface
246
Pin Assignment
246
JTAG Daisy Chained Structure
247
Debug Reset
247
JEDEC-106 ID Code
247
Table 13-1. Pin Assignment
247
Debug Hold Function Overview
248
Debug Support for Power Saving Mode
248
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
248
Register Definition
249
ID Code Register (DBG_ID)
249
Control Register (DBG_CTL)
249
14 Analog-To-Digital Converter (ADC)
253
Overview
253
Characteristics
253
Pins and Internal Signals
254
Figure 14-1. ADC Module Block Diagram
254
Table 14-1. ADC Internal Input Signals
254
Table 14-2. ADC Input Pins Definition
254
Function Overview
255
Foreground Calibration Function
255
ADC Clock
256
ADCON Enable
256
Routine Sequence
256
Operation Modes
256
Figure 14-2. Single Operation Mode
256
Figure 14-3. Continuous Operation Mode
257
Figure 14-4. Scan Operation Mode, Continuous Disable
258
Figure 14-5. Scan Operation Mode, Continuous Enable
258
Conversion Result Threshold Monitor Function
259
Data Storage Mode
259
Figure 14-6. Discontinuous Operation Mode
259
Figure 14-7. Data Storage Mode of 12-Bit Resolution
259
Figure 14-9. Data Storage Mode of 8-Bit Resolution
259
Figure 14-10. Data Storage Mode of 6-Bit Resolution
259
Sample Time Configuration
260
Figure 14-8. Data Storage Mode of 10-Bit Resolution
260
External Trigger Configuration
261
DMA Request
261
ADC Internal Channels
261
Table 14-3. External Trigger Source for ADC0 and ADC1
261
Table 14-4. External Trigger Source for ADC2
261
Programmable Resolution (DRES)
262
Table 14-5. Tconv Timings Depending on Resolution
262
On-Chip Hardware Oversampling
263
Figure 14-11. 20-Bit to 16-Bit Result Truncation
263
Figure 14-12. Numerical Example with 5-Bits Shift and Rounding
263
ADC Sync Mode
264
Table 14-6. Maximum Output Results Vs N and M Grayed Values Indicates Truncation
264
Free Mode
265
Routine Parallel Mode
265
Figure 14-13. ADC Sync Block Diagram
265
Table 14-7. ADC Sync Mode Table
265
Routine Follow-Up Fast Mode
266
Figure 14-14. Routine Parallel Mode on 10 Channels
266
Figure 14-15. Routine Follow-Up Fast Mode on Routine Sequence (the CTN Bit of Adcs Are Set)
266
Routine Follow-Up Slow Mode
267
Figure 14-16. Routine Follow-Up Slow Mode on Routine Sequence Channel
267
ADC Interrupts
268
Register Definition
269
Status Register (ADC_STAT)
269
Control Register 0 (ADC_CTL0)
269
Control Register 1 (ADC_CTL1)
271
Sample Time Register 0 (ADC_SAMPT0)
273
Sample Time Register 1 (ADC_SAMPT1)
274
Watchdog High Threshold Register (ADC_WDHT)
275
Watchdog Low Threshold Register (ADC_WDLT)
276
Routine Sequence Register 0 (ADC_RSQ0)
276
Routine Sequence Register 1 (ADC_RSQ1)
277
Routine Sequence Register 2 (ADC_RSQ2)
277
Routine Data Register (ADC_RDATA)
278
Oversample Control Register (ADC_OVSAMPCTL)
278
15 Digital-To-Analog Converter (DAC)
281
Overview
281
Characteristics
281
Function Overview
282
DAC Enable
282
DAC Output Buffer
282
Figure 15-1. DAC Block Diagram
282
Table 15-1. DAC I/O Description
282
DAC Data Configuration
283
DAC Trigger
283
DAC Workflow
283
DAC Noise Wave
283
Table 15-2. External Triggers of DAC
283
DAC Output Calculate
284
Figure 15-2. DAC LFSR Algorithm
284
Figure 15-3. DAC Triangle Noise Wave
284
DMA Function
285
DAC Concurrent Conversion
285
Register Definition
286
Control Register (DAC_CTL)
286
Software Trigger Register (DAC_SWT)
288
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)
289
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)
289
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)
290
DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12DH)
290
DAC1 12-Bit Left-Aligned Data Holding Register (DAC1_L12DH)
291
DAC1 8-Bit Right-Aligned Data Holding Register (DAC1_R8DH)
291
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
291
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
292
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
293
DAC0 Data Output Register (DAC0_DO)
293
DAC1 Data Output Register (DAC1_DO)
294
16 Watchdog Timer (WDGT)
295
Free Watchdog Timer (FWDGT)
295
Overview
295
Charateristics
295
Function Overview
295
Figure 16-1. Free Watchdog Block Diagram
295
Table 16-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
296
Register Definition
298
Window Watchdog Timer (WWDGT)
301
Overview
301
Charateristics
301
Function Overview
301
Figure 16-2. Window Watchdog Timer Block Diagram
301
Figure 16-3. Window Watchdog Timing Diagram
302
Table 16-2. Min/Max Timeout Value at 60 Mhz
303
Register Definition
304
17 Real-Time Clock(RTC)
306
Overview
306
Characteristics
306
Function Overview
306
RTC Reset
307
RTC Reading
307
RTC Configuration
307
Figure 17-1. Block Diagram of RTC
307
RTC Flag Assertion
308
Register Definition
310
RTC Interrupt Enable Register(RTC_INTEN)
310
RTC Control Register(RTC_CTL)
310
RTC Prescaler High Register (RTC_PSCH)
311
RTC Prescaler Low Register (RTC_PSCL)
312
RTC Divider High Register (RTC_DIVH)
312
RTC Divider Low Register (RTC_DIVL)
312
RTC Counter High Register(RTC_CNTH)
313
RTC Counter Low Register (RTC_CNTL)
313
RTC Alarm High Register(RTC_ALRMH)
314
RTC Alarm Low Register (RTC_ALRML)
314
18 Timer
315
Table 18-1. Timers (Timerx) Are Divided into Five Sorts
315
Advanced Timer (Timerx, X=0, 7)
316
Figure 18-1. Advanced Timer Block Diagram
316
Figure 18-2. Timing Chart of Internal Clock Divided by 1
318
Figure 18-3. Timing Chart of PSC Value Change from 0 to 2
319
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/2
319
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
320
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/2
321
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
322
Figure 18-8. Timing Chart of Center-Aligned Counting Mode
323
Figure 18-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
324
Figure 18-10. Repetition Counter Timing Chart of up Counting Mode
324
Figure 18-11. Repetition Counter Timing Chart of down Counting Mode
325
Figure 18-12. Channel Input Capture Principle
326
Figure 18-13. Channel Output Compare Principle (with Complementary Output, X=0,1,2)
327
Figure 18-14. Channel Output Compare Principle (CH3_O)
327
Figure 18-15. Output-Compare in Three Modes
328
Figure 18-16. Timing Chart of EAPWM
330
Figure 18-17. Timing Chart of CAPWM
330
Table 18-2. Complementary Outputs Controlled by Parameters
332
Figure 18-18. Channel Output Complementary PWM with Dead-Time Insertion
333
Figure 18-19. Output Behavior in Response to a Break (the Break High Active)
334
Figure 18-20. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
335
Figure 18-21. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
335
Table 18-3. Counting Direction in Different Quadrature Decoder Mode
335
Figure 18-22. Hall Sensor Is Used to BLDC Motor
336
Figure 18-23. Hall Sensor Timing between Two Timers
337
Table 18-4. Examples of Slave Mode
337
Figure 18-24. Restart Mode
338
Figure 18-25. Pause Mode
338
Figure 18-26. Event Mode
339
Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
339
Figure 18-28. Timer0 Master/Slave Mode Timer Example
340
Table 18-5. Input Trigger of Timer0 and Timer7
341
Table 18-6. Ouput Trigger of Timer0 and Timer7
341
Figure 18-29. Triggering TIMER0 with Enable Signal of TIMER2
342
Figure 18-30. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
343
Figure 18-31. General Level 0 Timer Block Diagram
372
Figure 18-32. Timing Chart of Internal Clock Divided by 1
374
Figure 18-33. Timing Chart of PSC Value Change from 0 to 2
375
Figure 18-34. Timing Chart of up Counting Mode, PSC=0/2
376
Figure 18-35. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
376
Figure 18-36. Timing Chart of down Counting Mode, PSC=0/2
377
Figure 18-37. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
378
Figure 18-38. Timing Chart of Center-Aligned Counting Mode
379
Figure 18-39. Channel Input Capture Principle
380
Figure 18-40. Channel Output Compare Principle (X=0,1,2,3)
381
Figure 18-41. Output-Compare in Three Modes
382
Figure 18-42. EAPWM Timechart
383
Figure 18-43. CAPWM Timechart
383
Table 18-7. Examples of Slave Mode
384
Figure 18-44. Restart Mode
385
Figure 18-45. Pause Mode
386
Figure 18-46. Event Mode
386
Table 18-8. Input Trigger of Timerx(X=1,2,3,4)
386
Table 18-9. Ouput Trigger of Timerx(X=1,2,3,4)
387
Figure 18-47. General Level1 Timer Block Diagram
411
Figure 18-48. Timing Chart of Internal Clock Divided by 1
412
Figure 18-49. Timing Chart of PSC Value Change from 0 to 2
413
Figure 18-50. Timing Chart of up Counting Mode, PSC=0/2
414
Figure 18-51. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
414
Figure 18-52. Timing Chart of down Counting Mode, PSC=0/2
415
Figure 18-53. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
416
Figure 18-54. Timing Chart of Center-Aligned Counting Mode
417
Figure 18-55. Channel Input Capture Principle
418
Figure 18-56. Channel Output Compare Principle (X=0,1)
419
Figure 18-57. Output-Compare under Three Modes
420
Figure 18-58. EAPWM Timechart
421
Figure 18-59. CAPWM Timechart
421
Table 18-10. Slave Mode Examples
422
Figure 18-60. Restart Mode
423
Figure 18-61. Pause Mode
423
Figure 18-62. Event Mode
424
Figure 18-63. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
424
Table 18-11. Input Trigger of Timerx(X=8,11)
425
Figure 18-64. General Level2 Timer Block Diagram
439
Figure 18-65. Timing Chart of Internal Clock Divided by 1
441
Figure 18-66. Timing Chart of PSC Value Change from 0 to 2
441
Figure 18-67. Up-Counter Timechart, PSC=0/2
442
Figure 18-68. Up-Counter Timechart, Change Timerx_Car on the Go
443
Figure 18-69. Down-Counter Timechart, PSC=0/2
443
Figure 18-70. Down-Counter Timechart, Change Timerx_Car on the Go
445
Figure 18-71. Center-Aligned Counter Timechart
445
Figure 18-72. Channels Input Capture Principle
447
Figure 18-73. Channel Output Compare Principle (X=0)
448
Figure 18-74. Output-Compare under Three Modes
449
Figure 18-75. Basic Timer Block Diagram
461
Figure 18-76. Timing Chart of Internal Clock Divided by 1
462
Figure 18-77. Timing Chart of PSC Value Change from 0 to 2
463
Figure 18-78. Timing Chart of up Counting Mode, PSC=0/2
463
Figure 18-79. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
464
Table 19-1. USART Important Pins Description
472
Figure 19-1. USART Module Block Diagram
473
Figure 19-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
473
Table 19-2. Stop Bits Configuration
473
Figure 19-3. USART Transmit Procedure
475
Figure 19-4. Oversampling Method of a Receive Frame Bit
476
Figure 19-5. Configuration Step When Using DMA for USART Transmission
477
Figure 19-6. Configuration Step When Using DMA for USART Reception
478
Figure 19-7. Hardware Flow Control between Two Usarts
479
Figure 19-8. Hardware Flow Control
479
Figure 19-9. Break Frame Occurs During Idle State
481
Figure 19-10. Break Frame Occurs During a Frame
481
Figure 19-11. Example of USART in Synchronous Mode
482
Figure 19-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
482
Figure 19-13. Irda SIR ENDEC Module
483
Figure 19-14. Irda Data Modulation
483
Figure 19-15. ISO7816-3 Frame Format
484
Table 19-3. USART Interrupt Requests
486
Figure 19-16. USART Interrupt Mapping Diagram
487
Figure 20-1. I2C Module Block Diagram
502
Table 20-1. Definition of I2C-Bus Terminology (Refre to the I2C Specification of Philips Semiconductors)
503
Figure 20-2. Data Validation
504
Figure 20-3. START and STOP Signal
504
Figure 20-4. Clock Synchronization
505
Figure 20-5. SDA Line Arbitration
505
Figure 20-6. I2C Communication Flow with 7-Bit Address
506
Figure 20-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
506
Figure 20-8. I2C Communication Flow with 10-Bit Address (Master Receive)
506
Figure 20-9. Programming Model for Slave Transmitting (10-Bit Address Mode)
508
Figure 20-10. Programming Model for Slave Receiving (10-Bit Address Mode)
508
Figure 20-11. Programming Model for Master Transmitting (10-Bit Address Mode)
509
Figure 20-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)
513
Figure 20-13. Programming Model for Master Receiving Mode Using Solution B
515
Table 20-2. Event Status Flags
518
Table 20-3. I2C Error Flags
518
Figure 21-1. Block Diagram of SPI
530
Table 21-1. SPI Signal Description
530
Figure 21-2. SPI Timing Diagram in Normal Mode
531
Table 21-2. Quad-SPI Signal Description
531
Figure 21-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
532
Table 21-3. NSS Function in Slave Mode
532
Table 21-4. NSS Function in Master Mode
533
Table 21-5. SPI Operation Modes
533
Figure 21-4. a Typical Full-Duplex Connection
535
Figure 21-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
535
Figure 21-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
535
Figure 21-7. a Typical Bidirectional Connection
535
Figure 21-8. Timing Diagram of Write Operation in Quad-SPI Mode
538
Figure 21-9. Timing Diagram of Read Operation in Quad-SPI Mode
539
Table 21-6. SPI Interrupt Requests
541
Figure 21-10. Block Diagram of I2S
542
Figure 21-11. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
543
Figure 21-12. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
543
Figure 21-13. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
544
Figure 21-14. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
544
Figure 21-15. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
544
Figure 21-16. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
544
Figure 21-17. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
545
Figure 21-18. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
545
Figure 21-19. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
545
Figure 21-20. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
545
Figure 21-21. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
545
Figure 21-22. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
546
Figure 21-23. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
546
Figure 21-24. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
546
Figure 21-25. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
546
Figure 21-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
546
Figure 21-27. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
547
Figure 21-28. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
547
Figure 21-29. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
547
Figure 21-30. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
547
Figure 21-31. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
548
Figure 21-32. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
548
Figure 21-33. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
548
Figure 21-34. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
548
Figure 21-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
548
Figure21-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
548
Figure 21-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
549
Figure 21-39. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
549
Figure21-40. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
549
Figure 21-41. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
549
Figure 21-42. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
550
Figure 21-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
550
Figure 21-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
550
Figure 21-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
550
Figure 21-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
550
Figure 21-47. Block Diagram of I2S Clock Generator
551
Table 21-7. I2S Bitrate Calculation Formulas
551
Table 21-8. Audio Sampling Frequency Calculation Formulas
551
Table 21-9. Direction of I2S Interface Signals for each Operation Mode
552
Figure 21-48. I2S Initialization Sequence
553
Figure 21-49. I2S Master Reception Disabling Sequence
555
Table 21-10. I2S Interrupt
557
Figure 22-1. DCI Module Block Diagram
568
Figure 22-2. Hardware Synchronization Mode
569
Table 22-1. Pins Used by DCI
569
Figure 22-3. Hardware Synchronization Mode: JPEG Format Supporting
570
Table 22-2. Memory View in Byte Padding Mode
571
Table 22-3. Memory View in Half-Word Padding Mode
572
Table 22-4. Status/Error Flags
572
Figure 23-1. TLI Module Block Diagram
582
Figure 23-2. Display Timing Diagram
582
Table 23-1. Pins of Display Interface Provided by TLI
582
Table 23-2. Supported Pixel Formats
584
Figure 23-3. Block Diagram of Blending
585
Table 23-3. Status Flags
586
Table 23-4. Error Flags
586
Figure 24-1 SDIO "No Response" and "No Data" Operations
604
Figure 24-2. SDIO Multiple Blocks Read Operation
605
Figure 24-3. SDIO Multiple Blocks Write Operation
605
Figure 24-4. SDIO Sequential Read Operation
605
Figure 24-5. SDIO Sequential Write Operation
606
Figure 24-6. SDIO Block Diagram
606
Table 24-1. SDIO I/O Definitions
607
Figure 24-7. Command Token Format
613
Table 24-2. Command Format
613
Table 24-3. Card Command Classes (Cccs)
614
Table 24-4. Basic Commands (Class 0)
616
Table 24-5. Block-Oriented Read Commands (Class 2)
618
Table 24-6. Stream Read Commands (Class 1) and Stream Write Commands (Class 3)
619
Table 24-7. Block-Oriented Write Commands (Class 4)
620
Table 24-8. Erase Commands (Class 5)
621
Table 24-9. Block Oriented Write Protection Commands (Class 6)
621
Table 24-10. Lock Card (Class 7)
622
Table 24-11. Application-Specific Commands (Class 8)
622
Table 24-12. I/O Mode Commands (Class 9)
623
Table 24-13. Switch Function Commands (Class 10)
625
Figure 24-8. Response Token Format
626
Table 24-14. Response R1
626
Table 24-15. Response R2
627
Table 24-16. Response R3
627
Table 24-17. Response R4 for MMC
627
Table 24-18. Response R4 for SD I/O
627
Table 24-19. Response R5 for MMC
628
Table 24-20. Response R5 for SD I/O
628
Table 24-21. Response R6
628
Figure 24-9. 1-Bit Data Bus Width
629
Figure 24-10. 4-Bit Data Bus Width
629
Figure 24-11. 8-Bit Data Bus Width
629
Table 24-22. Response R7
629
Table 24-23. Card Status
631
Table 24-24. SD Status
633
Table 24-25. Performance Move Field
635
Table 24-26. AU_SIZE Field
636
Table 24-27. Maximum au Size
636
Table 24-28. Erase Size Field
636
Table 24-29. Erase Timeout Field
637
Table 24-30. Erase Offset Field
637
Table 24-31. Lock Card Data Structure
646
Figure 24-12. Read Wait Control by Stopping SDIO_CLK
648
Figure 24-13. Read Wait Operation Using SDIO_DAT[2]
648
Figure 24-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
649
Figure 24-15. Read Interrupt Cycle Timing
650
Figure 24-16. Write Interrupt Cycle Timing
650
Figure 24-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
651
Figure 24-18. Multiple Block 4-Bit Write Interrupt Cycle Timing
651
Figure 24-19. the Operation for Command Completion Disable Signal
652
Table 24-32. Sdio_Respx Register at Different Response Type
657
Figure 25-1. the EXMC Block Diagram
669
Figure 25-2. EXMC Memory Banks
670
Figure 25-3. Four Regions of Bank0 Address Mapping
671
Figure 25-4. NAND/PC Card Address Mapping
672
Figure 25-5. Diagram of Bank1 Common Space
672
Figure 25-6. SDRAM Address Mapping
673
Table 25-1. SDRAM Mapping
673
Table 25-2. nor Flash Interface Signals Description
674
Table 25-3. PSRAM Non-Muxed Signal Description
674
Table 25-4. SQPI-PSRAM Signal Description
675
Table 25-5. EXMC Bank 0 Supports All Transactions
675
Table 25-6. nor / PSRAM Controller Timing Parameters
676
Table 25-7. Exmc_Timing Models
677
Figure 25-7. Mode 1 Read Access
678
Figure 25-8. Mode 1 Write Access
678
Table 25-8. Mode 1 Related Registers Configuration
678
Figure 25-9. Mode a Read Access
679
Figure 25-10. Mode a Write Access
680
Table 25-9. Mode a Related Registers Configuration
680
Figure 25-11. Mode 2/B Read Access
681
Figure 25-12. Mode 2 Write Access
681
Figure 25-13. Mode B Write Access
682
Table 25-10. Mode 2/B Related Registers Configuration
682
Figure 25-14. Mode C Read Access
683
Figure 25-15. Mode C Write Access
683
Table 25-11. Mode C Related Registers Configuration
684
Figure 25-16. Mode D Read Access
685
Figure 25-17. Mode D Write Access
685
Table 25-12. Mode D Related Registers Configuration
685
Figure 25-18. Multiplex Mode Read Access
686
Figure 25-19. Multiplex Mode Write Access
687
Table 25-13. Multiplex Mode Related Registers Configuration
687
Figure 25-20. Read Access Timing Diagram under Async-Wait Signal Assertion
688
Figure 25-21. Write Access Timing Diagram under Async-Wait Signal Assertion
689
Figure 25-22. Read Timing of Synchronous Multiplexed Burst Mode
690
Table 25-14. Timing Configurations of Synchronous Multiplexed Read Mode
690
Figure 25-23. Write Timing of Synchronous Multiplexed Burst Mode
692
Table 25-15. Timing Configurations of Synchronous Multiplexed Write Mode
692
Table 25-16. SPI/QPI Interface
693
Figure 25-24. SPI-PSRAM Access
694
Figure 25-25. SQPI-PSRAM Access
695
Figure 25-26. QPI-PSRAM Access
695
Table 25-17. 8-Bit or 16-Bit NAND Interface Signal
696
Table 25-18. 16-Bit PC Card Interface Signal
696
Table 25-19. Bank1/2/3 of EXMC Support the Memory and Access Mode
696
Figure 25-27. Access Timing of Common Memory Space of NAND Flash or PC Card Controller
697
Table 25-20. NAND Flash or PC Card Programmable Parameters
697
Figure 25-28. Access to None "NCE Don't Care" NAND Flash
699
Figure 25-29. SDRAM Controller Block Diagram
703
Table 25-21. SDRAM Command Truth Table
703
Table 25-22. IO Definition of SDRAM Controller
704
Figure 25-30. Burst Read Operation
706
Figure 25-31. Data Sampling Clock Delay Chain
707
Figure 25-32. Burst Write Operation
707
Figure 25-33. Read Access When FIFO Not Hit (BRSTRD=1, CL=2, SDCLK=2, PIPED=2)
708
Figure 25-34. Read Access When FIFO Hit (BRSTRD=1)
709
Figure 25-35. Cross Boundary Read Operation
710
Figure 25-36. Cross Boundary Write Operation
710
Figure 25-37. Process for Self-Refresh Entry and Exit
711
Figure 25-38. Process for Power-Down Entry and Exit
712
Figure 26-1. CAN Module Block Diagram
735
Figure 26-2. Transmission Register
737
Figure 26-3. State of Transmission Mailbox
738
Figure 26-4. Reception Register
739
Figure 26-5. 32-Bit Filter
741
Figure 26-6. 16-Bit Filter
741
Figure 26-7. 32-Bit Mask Mode Filter
741
Figure 26-8. 16-Bit Mask Mode Filter
741
Figure 26-9. 32-Bit List Mode Filter
741
Figure 26-10. 16-Bit List Mode Filter
741
Table 26-1. 32-Bit Filter Number
742
Table 26-2. Filtering Index
742
Figure 26-11. the Bit Time
745
Figure 27-1. ENET Module Block Diagram
768
Figure 27-2. Mac/Tagged MAC Frame Format
769
Table 27-1. Ethernet Pin Configuration
770
Figure 27-3. Station Management Interface Signals
772
Figure 27-4. Media Independent Interface Signals
773
Table 27-2. Clock Range
773
Table 27-3. Rx Interface Signal Encoding
774
Figure 27-5. Reduced Media-Independent Interface Signals
775
Table 27-4. Destination Address Filtering Table
783
Table 27-5. Source Address Filtering Table
784
Figure 27-6. Wakeup Frame Filter Register
789
Figure 27-7. System Time Update Using the Fine Correction Method
792
Figure 27-8. Descriptor Ring and Chain Structure
796
Figure 27-9. Transmit Descriptor
801
Figure 27-10. Receive Descriptor
809
Table 27-6. Error Status Decoding in RDES0, Only Used for Normal Descriptor
812
Figure 27-11. MAC Interrupt Scheme
816
Figure 27-12. Ethernet Interrupt Scheme
817
Figure 27-13. Wakeup Frame Filter Register
828
Figure 28-1. USBFS Block Diagram
864
Table 28-1. USBFS Signal Description
864
Figure 28-2. Connection with Host or Device Mode
865
Figure 28-3. Connection with OTG Mode
866
Figure 28-4. State Transition Diagram of Host Port
866
Figure 28-5. HOST Mode FIFO Space in SRAM
871
Figure 28-6. Host Mode FIFO Access Register Mapping
871
Figure 28-7. Device Mode FIFO Space in SRAM
872
Figure 28-8. Device Mode FIFO Access Register Mappimg
873
Table 28-2. USBFS Global Interrupt
877
Table 29-1. Revision History
938
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