Figure 17-11. Programming Model For Master Transmitting(10-Bit Address Mode) - GigaDevice Semiconductor GD32VF103 User Manual

Figure 17-11. Programming model for master transmitting(10-bit address mode)

I2C Line State
IDLE
Master generates START
condition
SCL stretched by master
Master sends Header
Slave sends Acknowledge
SCL stretched by master
Master sends Address
Slave sends Acknowledge
SCL stretched by master
Master sends DATA(1)
Slave sends Acknowledge
......（Data transmission）
Master sends DATA(N-2)
Slave sends Acknowledge
Master sends DATA(N-1)
Slave sends Acknowledge
Master sends DATA(N)
Slave sends Acknowledge
SCL stretched by master
Master generates STOP
condition
Programming model in master receiving mode
In master receiving mode, a master is responsible for generating NACK for the last byte
reception and then sending STOP condition on I2C bus. So, special attention should be paid
to ensure the correct ending of data reception. Two solutions for master receiving are provided
here for your application: Solution A and B. Solution A requires the software's quick response
to I2C events, while Solution B doesn't.
Solution A
1. First of all, software should enable I2C peripheral clock as well as configure clock related
registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured,
I2C operates in its default slave state and waits for START condition followed by address
on I2C bus.
GD32VF103 User Manual
Hardware Action
Set SBSEND
Set ADD10SEND
Set ADDSEND
Set TBE
Set TBE
Set TBE
Set TBE
Set TBE
Set BTC
Software Flow
1) Software initialization
2) Set START
3) Clear SBSEND
4) Clear ADD10SEND
4) Clear ADDSEND
5) Write DATA(1) to I2C_DATA
6) Write DATA(2) to I2C_DATA
7) Write DATA(3) to I2C_DATA
Write DATA(x) to I2C_DATA
8)Write DATA(N) to I2C_DATA
9) Set STOP
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