GigaDevice Semiconductor GD32VF103 User Manual page 527

15 EPACT
14:11 Reserved
10:0 MPL[10:0]
Device IN endpoint-x interrupt flag register (USBFS_DIEPxINTF) (x = 0..3, where
x = endpoint_number)
Address offset: 0x0908 + (endpoint_number × 0x20)
Reset value: 0x0000 0080
This register contains the status and events of an IN endpoint, when an IN endpoint interrupt
occurs, read this register for the respective endpoint to know the source of the interrupt. The
flag bits in this register are all set by hardware and cleared by writing 1 except the read-only
TXFE bit.
This register has to be accessed by word (32-bit)
31 30 29
15 14 13
Bits Fields
31:8 Reserved
7 TXFE
6 IEPNE
These is a data PID toggle scheme in interrupt or bulk transfer. Software should set
SD0PID to set this bit before a transfer starts and USBFS maintains this bit during
transfers following the data toggle scheme described in USB protocol.
0: Data packet's PID is DATA0
1: Data packet's PID is DATA1
Endpoint active
This bit controls whether this endpoint is active. If an endpoint is not active, it ignores
all tokens and doesn't make any response.
Must be kept at reset value
This field defines the maximum packet length in bytes.
28 27 26 25
12 11 10 9
Descriptions
Must be kept at reset value
Transmit FIFO empty
The Tx FIFO of this IN endpoint has reached the empty threshold value defined by
TXFTH field in USBFS_GAHBCS register.
IN endpoint NAK effective
GD32VF103 User Manual
24 23 22 21
8 7 6 5
r rc_w1
20 19 18 17
4 3 2
rc_w1 rc_w1 rc_w1
16
1 0
rc_w1
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