GigaDevice Semiconductor GD32F5 Series User Manual

Arm cortex-m33 32-bit mcu for gd32f527xx

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GigaDevice Semiconductor Inc.

GD32F5xx

Arm

Cortex

-M33 32-bit MCU

For GD32F527xx

User Manual

Revision 1.1

( Aug. 2024 )

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Summary of Contents for GigaDevice Semiconductor GD32F5 Series

Page 1 GigaDevice Semiconductor Inc. GD32F5xx Cortex -M33 32-bit MCU ® ® For GD32F527xx User Manual Revision 1.1 ( Aug. 2024 )
Page 2 GD32F5xx User Manual Table of Contents Table of Contents ......................2 List of Figures ......................26 List of Tables ........................ 36 1. System and memory architecture ................ 41 ® ® -M33 processor ................... 41 1.1. Cortex System architecture ....................42 1.2.
Page 3 GD32F5xx User Manual Memory security ......................73 2.3. 2.3.1. System Flash protection ....................... 73 2.3.2. User Flash protection ......................73 2.3.3. SRAM protection ........................75 2.3.4. Trusted code protection ......................75 2.3.5. Password protection ......................76 2.3.6. External memory protection ....................77 Boot protection ......................
Page 4 GD32F5xx User Manual 3.3.16. EFUSE read operation ......................100 3.3.17. EFUSE program operation ....................100 3.4. Register definition ....................102 3.4.1. Unlock key register (FMC_KEY) ..................102 3.4.2. Option byte unlock key register (FMC_OBKEY) ..............102 3.4.3. Status register (FMC_STAT) ....................103 3.4.4.
Page 5 GD32F5xx User Manual 5.2.3. Function overview ....................... 133 5.3. Register definition ....................138 5.3.1. Control register (RCU_CTL) ....................138 5.3.2. PLL register (RCU_PLL) ..................... 140 5.3.3. Clock configuration register 0 (RCU_CFG0) ..............142 5.3.4. Clock interrupt register (RCU_INT) ..................144 5.3.5.
Page 6 GD32F5xx User Manual 6.3.3. Frequency evaluation and automatic trim process ............. 195 6.3.4. Software program guide ..................... 196 Register definition ....................197 6.4. 6.4.1. Control register 0 (CTC_CTL0) ................... 197 6.4.2. Control register 1 (CTC_CTL1) ................... 198 6.4.3. Status register (CTC_STAT) ....................199 6.4.4.
Page 7 GD32F5xx User Manual 8.4.4. Port pull-up / pull-down register (GPIOx_PUD, x = A…I) ........... 225 8.4.5. Port input status register (GPIOx_ISTAT, x = A…I) ............227 8.4.6. Port output control register (GPIOx_OCTL, x = A…I) ............227 8.4.7. Port bit operate register (GPIOx_BOP, x = A…I) ..............228 8.4.8.
Page 8 GD32F5xx User Manual 11.3.8. Status, errors and interrupts ....................264 Register definition ....................266 11.4. 11.4.1. Control register (PKCAU_CTL) ................... 266 11.4.2. Status register (PKCAU_STAT) ..................267 11.4.3. Status clear register (PKCAU_STATC) ................268 Hash Acceleration Unit (HAU) ................. 270 Overview .......................
Page 9 GD32F5xx User Manual Operating modes ....................301 13.5. CAU DMA interface ....................302 13.6. CAU interrupts ...................... 303 13.7. CAU suspended mode ..................303 13.8. Register definition ....................305 13.9. 13.9.1. Control register (CAU_CTL) ....................305 13.9.2. Status register 0 (CAU_STAT0) ..................307 13.9.3.
Page 10 GD32F5xx User Manual 14.6.4. Interrupt flag clear register 1 (DMA_INTC1) ............... 339 14.6.5. Channel x control register (DMA_CHxCTL) ............... 340 14.6.6. Channel x counter register (DMA_CHxCNT) ..............344 14.6.7. Channel x peripheral base address register (DMA_CHxPADDR) ........345 14.6.8. Channel x memory 0 base address register (DMA_CHxM0ADDR) ........345 14.6.9.
Page 11 GD32F5xx User Manual 15.6.18. Image size register (IPA_IMS) ..................382 15.6.19. Line mark register (IPA_LM) ................... 383 15.6.20. Inter-timer control register (IPA_ITCTL) ................384 Debug (DBG) ..................... 385 Overview ....................... 385 16.1. JTAG/SW function overview ................385 16.2. 16.3. Switch JTAG or SW interface ................385 16.3.1.
Page 12 GD32F5xx User Manual 18.4.5. Operation modes ........................ 399 Conversion result threshold monitor function ..............402 18.4.6. 18.4.7. Data storage mode ......................403 Sample time configuration ....................403 18.4.8. External trigger configuration ....................404 18.4.9. 18.4.10. DMA request ........................404 18.4.11. Overflow detection ......................
Page 13 GD32F5xx User Manual 19.3.4. DAC trigger ......................... 431 19.3.5. DAC conversion ........................432 19.3.6. DAC noise wave ......................... 432 19.3.7. DAC output voltage ......................433 19.3.8. DMA request ........................433 19.3.9. DAC concurrent conversion ....................433 19.4. Register definition ....................435 19.4.1.
Page 14 GD32F5xx User Manual 21.3.5. Configurable periodic auto-wakeup counter ............... 459 21.3.6. RTC initialization and configuration ..................459 21.3.7. Calendar reading ........................ 460 21.3.8. Resetting the RTC ......................462 21.3.9. RTC shift function ....................... 462 21.3.10. RTC reference clock detection ..................463 21.3.11.
Page 15 GD32F5xx User Manual 22.2.1. Overview ..........................556 22.2.2. Characteristics ........................556 22.2.3. Function overview ....................... 556 22.2.4. Register definition ....................... 572 General level1 timer (TIMERx, x=8, 11) ............... 599 22.3. 22.3.1. Overview ..........................599 22.3.2. Characteristics ........................599 22.3.3. Function overview ....................... 600 22.3.4.
Page 16 GD32F5xx User Manual 23.4.4. Control register 0 (USART_CTL0) ..................676 23.4.5. Control register 1 (USART_CTL1) ..................678 23.4.6. Control register 2 (USART_CTL2) ..................679 23.4.7. Guard time and prescaler register (USART_GP) ............... 681 23.4.8. Control register 3 (USART_CTL3) ..................682 23.4.9.
Page 17 GD32F5xx User Manual I2S signal description ..................771 25.8. I2S function overview ..................772 25.9. 25.9.1. I2S audio standards ......................772 25.9.2. I2S clock ..........................780 25.9.3. Operation ..........................781 25.9.4. DMA function........................784 25.10. I2S interrupts ......................785 25.10.1. Status flags ........................
Page 18 GD32F5xx User Manual 26.3.17. Enable/Disable ........................ 816 26.3.18. Error flags ........................817 26.3.19. Interrupts ......................... 819 26.4. Register definition ....................821 26.4.1. Synchronize configuration register (SAI_SYNCFG) ............821 26.4.2. Block x configuration register0 (SAI_BxCFG0) (x = 0,1) ............ 821 26.4.3. Block x configuration register1 (SAI_BxCFG1) (x = 0,1) ............
Page 19 GD32F5xx User Manual Characteristics ..................... 848 28.2. Block diagram ...................... 848 28.3. Signal description ....................849 28.4. Function overview ....................849 28.5. 28.5.1. LCD display timing ......................849 28.5.2. Pixel DMA function ......................850 28.5.3. Pixel formats ........................851 28.5.4. Layer window and blending function ..................
Page 20 GD32F5xx User Manual SDIO bus topology ....................869 29.3. SDIO functional description ................872 29.4. 29.4.1. SDIO adapter ........................872 29.4.2. APB2 interface ........................876 Card functional description ................. 878 29.5. 29.5.1. Card registers ........................878 29.5.2. Commands .......................... 879 29.5.3.
Page 21 GD32F5xx User Manual Overview ....................... 933 30.1. Characteristics ..................... 933 30.2. Function overview ....................933 30.3. 30.3.1. Block diagram ........................933 30.3.2. Basic regulation of EXMC access..................934 30.3.3. External device address mapping..................935 30.3.4. NOR/PSRAM controller ...................... 939 30.3.5. NAND flash or PC card controller ..................
Page 22 GD32F5xx User Manual 31.4.11. FD transmitter delay compensation register (CAN_FDTDC) ........1031 31.4.12. Date Bit timing register (CAN_DBT) ................1032 31.4.13. Transmit mailbox identifier register (CAN_TMIx) (x = 0...2).......... 1032 31.4.14. Transmit mailbox property register (CAN_TMPx) (x = 0…2) ........1033 31.4.15.
Page 23 GD32F5xx User Manual 32.4.10. MAC wakeup management register (ENET_MAC_WUM) ..........1108 32.4.11. MAC debug register (ENET_MAC_DBG) ..............1110 32.4.12. MAC interrupt flag register (ENET_MAC_INTF) ............1111 32.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) ........... 1112 32.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) ..........1113 32.4.15.
Page 24 GD32F5xx User Manual 32.4.51. DMA control register (ENET_DMA_CTL) ..............1141 32.4.52. DMA interrupt enable register (ENET_DMA_INTEN) ............ 1144 32.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT) ..1146 32.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC) ......1147 32.4.55.
Page 25 GD32F5xx User Manual 34.5.7. Operation guide ........................ 1240 Interrupts ......................1247 34.6. Register definition ....................1249 34.7. 34.7.1. USBHS global registers ....................1249 34.7.2. Host control and status registers ..................1273 34.7.3. Device control and status registers .................. 1288 34.7.4. Power and clock control register (USBHS_PWRCLKCTL) ..........
Page 26 GD32F5xx User Manual List of Figures -M33 processor ............... 42 ® Figure 1-1. The structure of the Cortex Figure 1-2. The system architecture of GD32F5xx devices ..............44 Figure 1-3. ECC decoder ........................... 49 Figure 2-1. GD32F5xx memory access architecture ................73 Figure 2-2.
Page 27 GD32F5xx User Manual Figure 11-12. Montgomery parameter calculation ................251 Figure 11-13. Mutual mapping between Montgomery domain and natural domain ......252 Figure 11-14. Montgomery multiplication ..................... 253 Figure 11-15. Modular exponentiation of normal mode ............... 253 Figure 11-16. Modular exponentiation of fast mode ................254 Figure 11-17.
Page 28 GD32F5xx User Manual Figure 18-1. ADC module block diagram ....................398 Figure 18-2. Single operation mode....................... 399 Figure 18-3. Continuous operation mode ..................... 400 Figure 18-4. Scan operation mode, continuous disable ..............401 Figure 18-5. Scan operation mode, continuous enable ............... 401 Figure 18-6.
Page 29 GD32F5xx User Manual Figure 22-22. Complementary output with dead-time insertion............512 Figure 22-23. Output behavior in response to a break(The break high active) ......... 513 Figure 22-24. Counter behavior with CI0FE0 polarity non-inverted in mode 2 ......... 514 Figure 22-25. Counter behavior with CI0FE0 polarity inverted in mode 2 ......... 514 Figure 22-26.
Page 30 GD32F5xx User Manual Figure 22-65. Timing chart of up counting mode, PSC=0/2 ..............628 Figure 22-66. Timing chart of up counting mode, change TIMERx_CAR ongoing ......629 Figure 22-67. Channel input capture principle ..................630 Figure 22-68. Output-compare under three modes ................632 Figure 22-69.
Page 31 GD32F5xx User Manual Figure 24-18. I2C communication flow with 7-bit address (Master Transmit) ........720 Figure 24-19. I2C communication flow with 7-bit address (Master Receive) ........720 Figure 24-20. I2C communication flow with 10-bit address (Master Receive when HEAD10R=0) .. 720 Figure 24-21.
Page 32 GD32F5xx User Manual Figure 25-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....775 Figure 25-26. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ....775 Figure 25-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ....775 Figure 25-28. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ....775 Figure 25-29.
Page 33 GD32F5xx User Manual Figure 26-2. Clock divider logic ......................800 Figure 26-3 FS active width ........................803 Figure 26-4 FS polarity ..........................803 Figure 26-5 FS function ........................... 804 Figure 26-6 Slot activation ........................805 Figure 26-7 Slot distribution when FUNC = 0 ..................805 Figure 26-8 Slot distribution when FUNC = 1 ..................
Page 34 GD32F5xx User Manual Figure 30-1. The EXMC block diagram ....................934 Figure 30-2. EXMC memory banks......................935 Figure 30-3. Four regions of bank0 address mapping................. 936 Figure 30-4. NAND/PC card address mapping ..................936 Figure 30-5. Diagram of bank1 common space ..................937 Figure 30-6.
Page 35 GD32F5xx User Manual Figure 31-6. 16-bit filter ......................... 1009 Figure 31-7. 32-bit mask mode filter ....................1010 Figure 31-8. 16-bit mask mode filter ....................1010 Figure 31-9. 32-bit list mode filter ......................1010 Figure 31-10. 16-bit list mode filter ...................... 1010 Figure 31-11.
Page 36 GD32F5xx User Manual List of Tables Table 1-1. Bus Interconnection Matrix ..................... 42 Table 1-2. Memory map of GD32F5xx devices ..................45 Table 1-3. Boot modes ..........................51 Table 3-1. GD32F5xx base address and size for 4MB dual bank flash memory ......... 84 Table 3-2.
Page 37 GD32F5xx User Manual Table 14-5. FIFO counter critical value configuration rules ..............324 Table 14-6. DMA interrupt events ......................333 Table 15-1. IPA conversion mode ......................351 Table 15-2. Foreground and background CLUT pixel format ............. 353 Table 15-3. Foreground and background pixel format ................ 353 Table 15-4.
Page 38 GD32F5xx User Manual Table 25-1. SPI signal description ......................757 Table 25-2. Quad-SPI signal description ....................758 Table 25-3. NSS function in slave mod ....................760 Table 25-4. NSS function in master mod ....................760 Table 25-5. SPI operation modes ......................761 Table 25-6.
Page 39 GD32F5xx User Manual Table 29-14. Response R1 ........................892 Table 29-15. Response R2 ........................892 Table 29-16. Response R3 ........................892 Table 29-17. Response R4 for MMC ....................... 893 Table 29-18. Response R4 for SD I/O ..................... 893 Table 29-19. Response R5 for MMC ....................... 893 Table 29-20.
Page 40 GD32F5xx User Manual Table 31-3. CAN Event / Interrupt flags ....................1018 Table 32-1. Ethernet pin configuration ....................1045 Table 32-2. Clock range ......................... 1047 Table 32-3. Rx interface signal encoding .................... 1049 Table 32-4. Destination address filtering table ................... 1058 Table 32-5.
Page 41 GD32F5xx User Manual System and memory architecture The GD32F5xx series are 32-bit general-purpose microcontrollers based on the Arm ® Cortex -M33 processor. The Arm Cortex -M33 processor includes two AHB buses known as ® ® ® Code and System buses. All memory accesses of the Arm Cortex -M33 processor are ®...
Page 42 GD32F5xx User Manual ® Figure 1-1. The structure of the Cortex -M33 processor Cortex-M33 processor Cortex-M33 core Nested Interrupts Vectored Floating Point Interrupt Unit(FPU) Controller (NVIC) DSP Extension Data Breakpoint Memory Watchpoint Unit Protection And Trace (BPU) Unit(MPU) (DWT) Serial-Wire Or JTAG Instrumentation Trace Port...
Page 43 GD32F5xx User Manual CBUS SBUS DMA0M DMA0P DMA1M DMA1P ENET USBHS SRAM0 SRAM1 SRAM2 ADDSRAM EXMC AHB1 AHB2 APB1 APB2 As is shown above, there are ten masters connected with the AHB interconnect matrix, including CBUS, SBUS, DMA0M, DMA0P, DMA1M, DMA1P, ENET, TLI, USBHS and IPA. CBUS is the code bus of the Cortex -M33 core, which is used for any instruction fetch and ®...
Page 44 GD32F5xx User Manual Figure 1-2. The system architecture of GD32F5xx devices Powered By LDO (1.2V) Flash Memory TPIU SW/JTA G master slave Powered By V ARM Cortex-M33 Processor slave TCMSRAM Fmax: 200MHz master SRAM0 slave PLLs SRAM1 master slave DMA0 master slave SRAM2...
Page 45 GD32F5xx User Manual 1.3. Memory map The Arm Cortex -M33 processor is structured in Harvard architecture which can use ® ® separate buses to fetch instructions and load/store data. Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space which is the maximum address range of the Cortex -M33 since the bus address width is 32-bit.
Page 46 GD32F5xx User Manual Pre-defined Address Peripherals Regions 0x4002 6400 - 0x4002 67FF DMA1 0x4002 6000 - 0x4002 63FF DMA0 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF 0x4002 3800 - 0x4002 3BFF 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF...
Page 47 GD32F5xx User Manual Pre-defined Address Peripherals Regions 0x4001 3400 - 0x4001 37FF SPI3 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF Reserved 0x4001 2000 - 0x4001 23FF 0x4001 1C00 - 0x4001 1FFF Reserved 0x4001 1800 - 0x4001 1BFF...
Page 48 GD32F5xx User Manual Pre-defined Address Peripherals Regions 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF I2S1_add 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF...
Page 49 GD32F5xx User Manual Pre-defined Address Peripherals Regions 0x0880 0000 - 0x0FFF FFFF Reserved 0x0840 0000 - 0x0877 FFFF Main Flash(Bank1_Ex 3584kB) 0x0820 0000 - 0x083F FFFF Main Flash(Bank1 2MB) 0x0800 0000 - 0x081F FFFF Main Flash(Bank0 2MB) 0x0030 0000 - 0x07FF FFFF 0x0010 0000 - 0x002F FFFF Aliased to the boot device 0x0002 0000 - 0x000F FFFF...
Page 50 GD32F5xx User Manual EEIC The EEIC (ECC Error Interrupt Control) module provides the function of ECC error status management and ECC interrupt configuration. Enable ECCEN in Option byte and then By setting the SYSCFG_STAT register and SYSCFG_SRAM0ECC,SYSCFG_SRAM1ECC,SYSCFG_SRAM2ECC,SYSCFG_ADDSRA MECC, SYSCFG_TCMSRAMECC, SYSCFG_BKPSRAMECC register can realize the ECC error detection of SRAM0, SRAM1, SRAM2, ADDSRAM and TCMSRAM respectively.
Page 51 GD32F5xx User Manual Set the ECCSEIE0 bit in SYSCFG_SRAM0ECC register. When a two bits error non-correction event is detected, a NMI interrupt will be generated. On-chip Flash memory 1.3.2. The devices provide high-density on-chip flash memory, which is structured as follows: ...
Page 52 GD32F5xx User Manual Protection level OTP1 high ® ® After power-on sequence or a system reset, the Arm Cortex -M33 processor fetches the top-of-stack value from address 0x0000 0000 and the base address of boot code from 0x0000 0004 in sequence. Then, it starts executing code from the base address of boot code. The corresponding memory space of the selected boot source is aliased in the boot memory space which begins at the address 0x0000 0000.
Page 53 GD32F5xx User Manual 1.6. System configuration registers SYSCFG base address: 0x4001 3800 Configuration register 0 (SYSCFG_CFG0) 1.6.1. Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[2:0] may be any value according to the BOOT0 and BOOT1 pins) This register has to be accessed by word (32-bit). Reserved FMC_SW Reserved...
Page 54 GD32F5xx User Manual series without BANK1, no swapping. Reserved Must be kept at reset value BOOT_MODE[2:0] These bits select the device accessible at address 0x0000 0000. After reset, they take the initial value from the BOOT0 and BOOT1 pins according to the table. Table 1-3.
Page 55 GD32F5xx User Manual Fast mode+ I2C5FMP Enable on I2C5 Fast mode+ I2C4FMP Enable on I2C4 Fast mode+ I2C3FMP Enable on I2C3 EXTI sources selection register 0 (SYSCFG_EXTISS0) 1.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI3_SS[3:0] EXTI2_SS[3:0]...
Page 56 GD32F5xx User Manual EXTI1_SS[3:0] EXTI 1 sources selection 0000: PA1 pin 0001: PB1 pin 0010: PC1 pin 0011: PD1 pin 0100: PE1 pin 0101: PF1 pin 0110: PG1 pin 0111: PH1 pin 1000: PI1 pin Other configurations are reserved. EXTI0_SS[3:0] EXTI 0 sources selection 0000: PA0 pin 0001: PB0 pin...
Page 57 GD32F5xx User Manual 0011: PD7 pin 0100: PE7 pin 0101: PF7 pin 0110: PG7 pin 0111: PH7 pin 1000: PI7 pin Other configurations are reserved. 11:8 EXTI6_SS[3:0] EXTI 6 sources selection 0000: PA6 pin 0001: PB6 pin 0010: PC6 pin 0011: PD6 pin 0100: PE6 pin 0101: PF6 pin...
Page 58 GD32F5xx User Manual EXTI sources selection register 2 (SYSCFG_EXTISS2) 1.6.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI11_SS[3:0] EXTI10_SS[3:0] EXTI9_SS[3:0] EXTI8_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI11_SS[3:0] EXTI 11 sources selection...
Page 59 GD32F5xx User Manual 0100: PE9 pin 0101: PF9 pin 0110: PG9 pin 0111: PH9 pin 1000: PI9 pin Other configurations are reserved. EXTI8_SS[3:0] EXTI 8 sources selection 0000: PA8 pin 0001: PB8 pin 0010: PC8 pin 0011: PD8 pin 0100: PE8 pin 0101: PF8 pin 0110: PG8 pin 0111: PH8 pin...
Page 60 GD32F5xx User Manual Other configurations are reserved. 11:8 EXTI14_SS[3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin 0010: PC14 pin 0011: PD14 pin 0100: PE14 pin 0101: PF14 pin 0110: PG14 pin 0111: PH14 pin Other configurations are reserved. EXTI13_SS[3:0] EXTI 13 sources selection 0000: PA13 pin...
Page 61 GD32F5xx User Manual CPS_RD Reserved Reserved CPS_EN Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. CPS_RDY Compensation cell ready flag This bit is read-only. 0: Compensation cell is not ready 1: Compensation cell is ready Reserved Must be kept at reset value. CPS_EN Compensation cell power-down 0: I / O compensation cell is power-down...
Page 62 GD32F5xx User Manual ECCMEIF6 Flash two bits non-correction event flag The software can clear it by writing 1. 0: no flash non-correction event is detected. 1:flash non-correction event is detected. ECCSEIF5 BKPSRAM single bit correction event flag The software can clear it by writing 1. 0: no BKPSRAM single bit correction event is detected.
Page 63 GD32F5xx User Manual The software can clear it by writing 1. 0: no SRAM1 single bit correction event is detected. 1: SRAM1 single bit correction event is detected. ECCMEIF1 SRAM1 two bits non-correction event flag The software can clear it by writing 1. 0: no SRAM1 non-correction event is detected.
Page 64 GD32F5xx User Manual CKMNMIIE HXTAL clock moniotor NMI interrupt enable 0: disable 1: enable ECCSEIE0 SRAM0 single bit correction interrupt enable 0: SRAM0 single bit correction interrupt is disabled. 1: SRAM0 single bit correction interrupt is enabled. ECCMEIE0 SRAM0 two bits non-correction interrupt enable 0: SRAM0 non-correction interrupt is disabled.
Page 65 GD32F5xx User Manual SRAM2 ECC status register (SYSCFG_SRAM2ECC) 1.6.11. Address offset: 0x30 Reset value: 0x0000 0003 This register has to be accessed by word (32-bit). ECCEADDR2[15:0] ECCSEIE ECCMEIE ECCSERRBITS2[5:0] Reserved Bits Fields Descriptions 31:16 ECCEADDR2[15:0] Indicates the address of ECC event on SRAM2 occurred. NOTE: Physical SRAM2 word address = SRAM2 base address/4 + ECCEADDR2 15:10 ECCSERRBITS2[5:0] Indicates the error bit...
Page 66 GD32F5xx User Manual ECCSEIE ECCMEIE ECCEADDR3[17:0] ECCSERRBITS3[5:0] Reserved Bits Fields Descriptions 31:14 ECCEADDR3[17:0] Indicates the last address of ECC event on ADDSRAM occurred. NOTE: Physical ADDSRAM word address = ADDSRAM base address/4 + ECCEADDR3 13:8 ECCSERRBITS3[5:0] Indicates the error bit Which one bit has an ECC single-bit correctable error 0: no error 1: bit 0...
Page 67 GD32F5xx User Manual ECCEADDR4 17:12 ECCSERRBITS4[5:0] Indicates the error bit Which one bit has an ECC single-bit correctable error 0: no error 1: bit 0 … 32: bit 31 11:2 Reserved Must be kept at reset value ECCSEIE4 TCMSRAM single bit correction interrupt enable 0: TCMSRAM single bit correction interrupt is disabled.
Page 68 GD32F5xx User Manual ECCSEIE5 BKPSRAM single bit correction interrupt enable 0: BKPSRAM single bit correction interrupt is disabled. 1: BKPSRAM single bit correction interrupt is enabled. ECCMEIE5 BKPSRAM two bits non-correction interrupt enable 0: BKPSRAM non-correction interrupt is disabled. 1: BKPSRAM non-correction interrupt is enabled. FLASH ECC address register SYSCFG_FLASHECC_ADDR 1.6.15.
Page 69 GD32F5xx User Manual Which one bit has an ECC single-bit correctable error 0: no error 1: bit 0 … 32: bit 31 ECCSEIE6 FLASH single bit correction interrupt enable 0: FLASH single bit correction interrupt is disabled. 1: FLASH single bit correction interrupt is enabled. ECCMEIE6 FLASH two bits non-correction interrupt enable 0: FLASH non-correction interrupt is disabled.
Page 70 GD32F5xx User Manual FLASH _DENSITY[15:0] SRAM_DENSITY[15:0] Bits Fields Descriptions 31:16 FLASH_DENSITY Flash density [15:0] The value indicates the Flash density of the device in Kbytes. Example: 0x0020 indicates 32 Kbytes. 15:0 SRAM_DENSITY SRAM memory density [15:0] The value indicates the on-chip SRAM memory density of the device in Kbytes. Example: 0x0008 indicates 8 Kbytes.
Page 71 GD32F5xx User Manual Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF 7A18 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID...
Page 72 GD32F5xx User Manual System Security 2.1. Overview The GD32F5xx is designed with a comprehensive set of system security features. System security features cover several aspects, including firmware intellectual property protection, device private data protection, and service execution assurance. This chapter systematically introduces the key security features of GD32F5xx and lists the security features available to guide users in building security systems based on GD32F5xx microcontrollers.
Page 73 GD32F5xx User Manual 2.3. Memory security When building system security, memory protection is the most important factor. The memory holds sensitive code and data and should be inaccessible to any unintended interface (debug port) or unauthorized process (insider threat). Depending on the asset (code or data) to be protected, users can set up corresponding protection mechanisms for different storage types (Flash, SRAM, or external memory).
Page 74 GD32F5xx User Manual External read access protection Flash memory controller (FMC) provides a security protection feature to prevent illegal reading of flash memory, which can protect software and firmware from illegal user operations. FMC offer three levels of safety: No protection: When setting EFSPC = 0 in EFUSE control and SPC byte to 0xAA, no protection performed.
Page 75 GD32F5xx User Manual Note: Write protection should also be set for unused flash areas to prevent code modification or injection. Error Checking and Correction (ECC) GD32F5xx series support hardware ECC function for flash, user flash can use ECC to achieve error detection and correction (two-bit error detection, one error correction).
Page 76 GD32F5xx User Manual be flexibly configured based on user application scenarios. The data can be locked after the execution of the trusted code, and the data read and write properties can be set by region. For example, some data can be read by the APP, but some data cannot be read by the APP. The schematic diagram of the protection of the trusted code area is shown in Figure 2-2.
Page 77 GD32F5xx User Manual firmware. The trusted code can configure RLBE bit to lock read of OTP2 area, and then jump to the APP firmware. Data blocks corresponding to the OTP2 read lock block cannot be read by the APP code. It cannot be read by trusted code until the next time the MCU resets. For details on OTP2 refer to OTP block programming.
Page 78 GD32F5xx User Manual 2.4. Boot protection Boot protection protects the first software instruction in the system. If an attacker successfully tampers with the MCU boot address, they can execute their own code to bypass the MCU initial protection configuration, or execute insecure programs to access the MCU memory. The GD32F5xx series can be configured for boot, with the option to perform boot in the firmware in the user flash, system bootloader, or SRAM.
Page 79 GD32F5xx User Manual The signature obtained by encrypting the APP firmware through the shared key between the user and the MCU (PKCAU supports RSA and ECDSA algorithms), and is compared with the expected signature to realize authenticity check. HASH message-digest, shared keys, and APP firmware signatures should be stored in protected area.
Page 80 GD32F5xx User Manual When EFSPC in the EFUSE control segment is set to 1 or the SPC byte is set to any value other than 0xAA or 0xCC, the low protection level is activated. If the SPC byte is set to 0xCC, the high protection level is activated. When the MCU is in the above two security levels, the main flash block can only be accessed by user code, and cannot be accessed by user code through debug mode.
Page 81 GD32F5xx User Manual  Supports the ECB, CBC, CTR, GCM, GMAC, CCM, CFB and OFB chaining algorithms.  Supports 128-bit, 192-bit and 256-bit keys.  four 32-bit initialization vectors (IV) are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes. ...
Page 82 GD32F5xx User Manual security countermeasures ineffective. GD32F5xx supports low voltage detection (LVD), triggering low voltage interruption, and users can make corresponding countermeasures in the low voltage interruption. Clock security system 2.7.3. Clock safety systems are used to prevent the failure of external oscillators. If a fault is detected on the external clock, the microcontroller switches to use the internal clock to safely perform the operation.
Page 83 GD32F5xx User Manual Flash memory controller (FMC) Overview 3.1. The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the first 2048K bytes of the flash. It provides page (4KB) erase, sector erase, mass erase, and double word/word/half-word/byte program operations for flash memory.
Page 84 GD32F5xx User Manual sectors, 128K bytes of 30 sectors, 256K bytes of 14 sectors. Each sector can be erased individually. The flash memory structure is divided into 4MB dual bank, 2MB dual bank, 1MB single bank, and 512KB single bank. Each type of structure can have an extended Bank1 flash memory (Bank1_Ex), with the address of the Bank1_Ex fixed to start at 0x0840 0000 and the operation mode being the same as Bank1.
Page 85 GD32F5xx User Manual Block Name Address size(bytes) Sector53 0x0874 0000 - 0x0877 FFFF 256KB Information Block Bootloader 0x1FFF 0000- 0x1FFF 77FF 30KB data area 0x1FFF 7800 - 0x1FFF 783F OTP0 Block lock area 0x1FFF 7840 - 0x1FFF 787F data area 0x1FF0 0000 - 0x1FF1 FFFF 128KB OTP1 Block...
Page 86 GD32F5xx User Manual Block Name Address size(bytes) Sector 25 0x0812 0000 - 0x0813 FFFF 128KB Sector 26 0x0814 0000 - 0x0815 FFFF 128KB Sector 31 0x081E 0000 - 0x081F FFFF 128KB Sector40 0x0840 0000 - 0x0843 FFFF 256KB Sector41 0x0844 0000 - 0x0847 FFFF 256KB Bank1_ 3584KB...
Page 87 GD32F5xx User Manual Block Name Address size(bytes) Sector 7 0x0806 0000 - 0x0807 FFFF 128KB Sector40 0x0840 0000 - 0x0843 FFFF 256KB Sector41 0x0844 0000 - 0x0847 FFFF 256KB Bank1_ 3584KB Sector53 0x0874 0000 - 0x0877 FFFF 256KB Error Checking and Correcting (ECC) 3.3.2.
Page 88 GD32F5xx User Manual the data access from the flash are through the CBUS from the CPU. Unlock the FMC_CTL/FMC_OBCTLx register 3.3.4. After reset, the FMC_CTL register is not accessible in write mode, and the LK bit in FMC_CTL register is 1. An unlocking sequence consists of two write operations to the FMC_KEY register to open the access to the FMC_CTL register.
Page 89 GD32F5xx User Manual that a correct target page address (4KB alignment) must be confirmed. Or the software may run out of control if the target erase page is being used to fetch codes or to access data. The FMC will not provide any notification when this occurs. Additionally, the page erase operation will be ignored on erase / program protected sectors.
Page 90 GD32F5xx User Manual Unlock the FMC_CTL register if necessary. Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. Set the SER bit in FMC_CTL register. Write the sector number SN bits in the FMC_CTL register.
Page 91 GD32F5xx User Manual Mass erase 3.3.7. The FMC provides a complete erase function which is used to initialize the main flash block contents. This erase can affect only on Bank0 by setting MER0 bit to 1, or only on Bank1(include Bnak1_Ex) by setting MER1 bit to 1, or on entire flash by setting MER0 and MER1 bits to 1.
Page 92 GD32F5xx User Manual Figure 3-3. Process of mass erase operation Start Unlock FMC_CTL register Is LK bit 0？ Is BUSY bit 0？ Set the MER0/MER1 bit Send the command to FMC by setting START bit Is BUSY bit 0？ Finish Main flash programming 3.3.8.
Page 93 GD32F5xx User Manual Note: Multiple writes will reduce ECC security. Therefore, it is recommennded to write only one time. Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT register. Read and verify the Flash memory if required using a CBUS access. When the operation is executed successfully, the END in FMC_STAT register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set.
Page 94 GD32F5xx User Manual OTP block programming 3.3.9. The FMC provides a 64bit double word / 8-bit byte programming function which is used to modify OTP0 / OTP1 / OTP2 contents. Additionally, 32-bit word / 16-bit half word programming can be used to modify OTP1 data blocks / OTP2 data blocks. The programming sequence is same as main flash programming.
Page 95 GD32F5xx User Manual The OTP2 block can be divided to 16 data blocks which has 32 bytes each and 1 lock block which has 32 bytes. The lock block address is from 0x1FF2 0210 to 0x1FF2 022F. The data block address is from 0x1FF2 0000 to 0x1FF2 01FF. The OTP2 write lock block address is from 0x1FF2 0210 to 0x1FF2 021F.
Page 96 GD32F5xx User Manual Option bytes description 3.3.11. The option bytes block is reloaded to FMC_OBCTL0 and FMC_OBCTL1 registers after each Table 3-8. Option byte system reset, and the option bytes take effect. is the detail of option bytes. Table 3-8. Option byte Address Name Description...
Page 97 GD32F5xx User Manual Address Name Description 1: No effect when DRP is 0. Erase/program protection and CBUS read protection when DRP is 1 (Factory value). [7]: DRP CBUS data read protection bit. 0: The WP0 bits used as erase/program protection of each sector (Factory value).
Page 98 GD32F5xx User Manual Address Name Description DRP is 1. 1: No effect when DRP is 0. Erase/program protection and CBUS read protection when DRP is 1 Sector erase/program protection 3.3.12. The FMC provides sector erase/program protection functions to prevent inadvertent operations on the Flash memory.
Page 99 GD32F5xx User Manual If the DRP is 1, modify DRP to 0 or change WP0 [19:0]/WP1 [19:0] bit field from 1 to 0 must performed during changing the security protection level low to no security protection. Otherwise, the option byte modification ignored and WPERR bit in the FMC_STAT register will then be set by the FMC.
Page 100 GD32F5xx User Manual Table 3-11. system parameters shows the details of each efuse byte. Table 3-11. system parameters Width Start Program- Parameter Read-protected Description Note address protected Read out and Control bytes of relevant Can write take effect after parameters required for MCU multiple EFUSE system reset...
Page 101 GD32F5xx User Manual Clear the PGIF bit if it is SET, and make sure there are no overstep boundary errors. SET the EFRW bit in EFUSE_CS. Write the desired efuse address and size to EFUSE_ADDR register. Write the data to the corresponding register. Set the EFSTR bit EFUSE_CS register.
Page 102 GD32F5xx User Manual Register definition 3.4. FMC base address: 0x4002 3C00 Unlock key register (FMC_KEY) 3.4.1. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock register These bits can only be written by software.
Page 103 GD32F5xx User Manual Status register (FMC_STAT) 3.4.3. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved BUSY LDECCD Reserved RDCERR PGSERR PGMERR PGAERR WPERR Reserved OPERR rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields...
Page 104 GD32F5xx User Manual LDECCDET Two bits ECC error flag bit when load code. When detected ECC two bits error, this bit is set by hardware. The software can clear it by writing 1. OPERR Flash operation error flag bit. This bit is set by hardware when an error (an error while sets RDCERR/PGSERR/PGMERR/WPERR bit) occurs on a flash operation and ERRIE bit in FMC_CTL register is set.
Page 105 GD32F5xx User Manual LDECCIE Load code ECC error interrupt enable bit. This bit is set or cleared by software. 0: no interrupt generated by hardware 1: error interrupt enable ERRIE Error interrupt enable bit. This bit is set or cleared by software. 0: no interrupt generated by hardware 1: error interrupt enable ENDIE...
Page 106 GD32F5xx User Manual MER0 main flash mass erase for bank0 command bit. This bit is set or cleared by software. 0: no effect 1: main flash mass erase command for bank0 main flash sector erase command bit. This bit is set or cleared by software. 0: no effect 1: main flash sector erase command main flash program command bit.
Page 107 GD32F5xx User Manual 27:16 WP0[11:0] Erase/program protection of each sector when DRP is 0. Erase/program protection and CBUS read protection of each sector when DRP is 1. WP0[0] affect sector 0, WP0[1] affect sector 1, etc. 0: Erase/program protection when DRP is 0. No effect when DRP is 1. 1: No effect when DRP is 0.
Page 108 GD32F5xx User Manual Option byte control register 1 (FMC_OBCTL1) 3.4.6. Address offset: 0x18 Reset value: 0xXXXX XXXX. the initial value is 0x0FFF FFFF. Load Flash values after reset. This register has to be accessed by word(32-bit). Reserved WP1[11:0] WP1[19:12] WP0[19:12] Bits Fields Descriptions...
Page 109 GD32F5xx User Manual PE_EN Reserved PE_ADDR[28:16] PE_ADDR[15:0] Bits Fields Descriptions PE_EN The enable bit of page erase function 0: Disable page erase. 1: Enable page erase. 30:29 Reserved Must be kept at reset value. 28:0 PE_ADDR[28:0] Page address (4KB alignment). Unlock page erase key register (FMC_PEKEY) 3.4.8.
Page 110 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 OTP1REN[15:0] OTP1 read enable. OTP1REN[x] decides OTP1 data block x read or not, x=0..15. 0: data block can not be read 1: data block can be read Software can write 0, but only reset can set to 1.
Page 111 GD32F5xx User Manual 31:0 LDECCADDR1[31:0] ECC two bits error base address (aligned to 64bit) when load code from main flash / bootloader OTP1. Any bits in 64bit may be wrong. Load code ECC error address2 (FMC_LDECCADDR2) 3.4.12. Address offset: 0x34 Reset value: 0xFFFF FFFF.
Page 112 GD32F5xx User Manual Product ID register (FMC_PID) 3.4.14. Address offset: 0x100 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). PID[31:16] PID[15:0] Bits Fields Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by software. These bits are unchanged constant after power on.
Page 113 GD32F5xx User Manual 1: Clear program operation completed interrupt flag Reserved Must be kept at reset value. OVBERIE Enable bit for overstep boundary error interrupt. 0: Disable the overstep boundary error interrupt 1: Enable the overstep boundary error interrupt RDIE Enable bit for read operation completed interrupt.
Page 114 GD32F5xx User Manual EFUSE address register (EFUSE_ADDR) 3.4.16. Address offset: 0x204 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved EFSIZE[4:0] Reserved EFADDR[4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 EFSIZE[4:0] Read or write efuse data size.
Page 115 GD32F5xx User Manual 0: unlock EFUSE_USER_DATA register 1: lock EFUSE_USER_DATA register Reserved Must be kept at reset value. BTFOSEL Select Boot from flash or OTP1. This bit actives when NBTSB is 1 or BOOT0 is 0. 0: boot from main flash block 1: boot from flash OTP1 block NBTSB Not boot from SRAM or bootloader.
Page 116 GD32F5xx User Manual Power management unit (PMU) Overview 4.1. The power consumption is regarded as one of the most important issues for the devices of GD32F5xx series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 117 GD32F5xx User Manual Figure 4-1. Power supply overview VBAT Backup Domain Power Switch 3.3V LXTAL BPOR WKUPR WKUP BLDO BKP PAD 1.2V WKUPN NRST BKPSRAM WKUPF SLEEPING Cortex-M33 FWDGT SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC48M IRC16M...
Page 118 GD32F5xx User Manual by 2 to 31. When V is shut down, only LXTAL is valid for RTC. Before entering the power ® saving mode by executing the WFI / WFE instruction, the Cortex -M33 can setup the RTC register with an expected wakeup time and enable the wakeup function to achieve the RTC wakeup event.
Page 119 GD32F5xx User Manual VDD domain The LDO, which is implemented to supply power for the 1.2V domain, is always enabled after reset. It can be configured to operate in three different status, including in the Sleep mode (full power on), in the Deep-sleep mode (on or low power), and in the Standby mode (power off).
Page 120 GD32F5xx User Manual Figure 4-3. Waveform of the BOR 100mV hyst RSTTEMPO BOR Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register(PMU_CS), indicates if V is higher or lower than the LVD threshold.
Page 121 GD32F5xx User Manual Figure 4-4. Waveform of the LVD threshold threshold 100mV hyst LVD output Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply is implemented to achieve better performance of analog circuits.
Page 122 GD32F5xx User Manual High-driver mode If the 1.2V power domain runs with high frequency and opens many functions, it is recommended to enter high-driver mode. The following steps are needed when using high- driver mode.  IRC16M or HXTAL must be selected as system clock. ...
Page 123 GD32F5xx User Manual Deep-sleep mode ® The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex -M33. In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC16M, IRC48M, HXTAL and PLLs are disabled. The contents of SRAM and registers are preserved. The LDO can operate normally or in low power mode depending on the LDOLP bit in the PMU_CTL register.
Page 124 GD32F5xx User Manual mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. Before entering the Standby mode, it is necessary to set the ® SLEEPDEEP bit in the Cortex -M33 System Control Register, and set the STBMOD bit in the PMU_CTL register, and clear WUF bit in the PMU_CS register.
Page 125 GD32F5xx User Manual 4.4. Register definition PMU base address: 0x4000 7000 Control register (PMU_CTL) 4.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register has to be accessed by word(32-bit). LDEN[1:0] Reserved HDEN LDOVS[1:0] Reserved LDNP LDLP...
Page 126 GD32F5xx User Manual 11: LDO output voltage high mode(1.2V) 13:12 Reserved Must be kept at reset value. LDNP Low-driver mode when use normal power LDO 0: Normal-driver when use normal power LDO 1: Low-driver mode enabled when LDEN is 11 and use normal power LDO LDLP Low-driver mode when use low power LDO.
Page 127 GD32F5xx User Manual 0: The LDO operates normally during the Deep-sleep mode 1: The LDO is in low power mode during the Deep-sleep mode Control and status register (PMU_CS) 4.4.2. Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) This register has to be accessed by word(32-bit).
Page 128 GD32F5xx User Manual in Backup SRAM will be lost. 0: Backup SRAM LDO closed 1: Open the Backup SRAM LDO WUPEN WKUP Pin (PA0) enable 0: Disable WKUP pin (PA0) function 1: Enable WKUP pin (PA0) function If WUPEN is set before entering the Standby mode, a rising edge on the WKUP pin wakes up the system from the Standby mode.
Page 129 GD32F5xx User Manual Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. GD32F5xx reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 130 GD32F5xx User Manual A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset). Figure 5-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have...
Page 131 GD32F5xx User Manual Figure 5-2. Clock tree CK_HXTAL /2 to /31 CK_RTC 32.768 KHz LXTAL OSC (to RTC) RTCSRC[1:0] CK_FWDGT 32 KHz IRC32K (to FWDGT) CK_SYS CK_OUT1 CKOUT1DIV CK_PLLI2SR ÷ 1,2,3,4,5 CK_HXTAL CK_PLLP CKOUT1SEL[1:0] HCLK AHB enable (to AHB bus,Cortex- M33,SRAM,DMA,peripherals) CK_IRC16M CK_CST...
Page 132 GD32F5xx User Manual configurable in the systick control and status register. The ADCs are clocked by the clock of APB2 divided by 2, 4, 6, 8 or by the clock of AHB divided by 5, 6, 10, 20, which defined by ADCCK in ADC_SYNCCTL register. The TIMERs are clocked by the clock divided from CK_AHB.
Page 133 GD32F5xx User Manual Function overview 5.2.3. High speed crystal oscillator (HXTAL) The high speed external crystal oscillator (HXTAL), which has a frequency from 4 to 32 MHz, produces a highly accurate clock source for use as the system clock. A crystal with a specific frequency must be connected and located close to the two HXTAL pins.
Page 134 GD32F5xx User Manual Internal 16M RC oscillators (IRC16M) The internal 16M RC oscillator, IRC16M, has a fixed frequency of 16 MHz and is the default clock source selection for the CPU when the device is powered up. The IRC16M oscillator provides a lower cost type clock source as no external components are required.
Page 135 GD32F5xx User Manual the PLL becomes stable. The PLLI2S can be switched on or off by using the PLLI2SEN bit in the RCU_CTL register. The PLLI2SSTB flag in the RCU_CTL register will indicate if the PLLI2S clock is stable. An interrupt can be generated if the related interrupt enable bit, PLLI2SSTBIE, in the RCU_INT register, is set as the PLLI2S becomes stable.
Page 136 GD32F5xx User Manual HXTAL clock monitor (CKM) The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit, CKMEN, in the control register (RCU_CTL). This function should be enabled after the HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is detected, the HXTAL will be automatically disabled.
Page 137 GD32F5xx User Manual TIMER4_IRMP TIMER10_IRMP register and ITI1_RMP in register for detail. Voltage control The 1.2V domain voltage in Deep-sleep mode can be controlled by DSLPVS[2:0] bit in the Deep-sleep mode voltage register (RCU_DSV). Table 5-3. 1.2V domain voltage selected in deep-sleep mode DSLPVS[2:0] Deep-sleep mode voltage(V) default value...
Page 138 GD32F5xx User Manual 5.3. Register definition RCU base address: 0x4002 3800 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLLSAIS PLLSAIE PLLI2SST PLLI2SE HXTALBP HXTALST HXTALE...
Page 139 GD32F5xx User Manual Set by hardware to indicate if the PLL output clock is stable and ready for use. 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock.
Page 140 GD32F5xx User Manual to 16 MHz ± 1%. Reserved Must be kept at reset value. IRC16MSTB IRC16M Internal 16MHz RC Oscillator stabilization flag Set by hardware to indicate if the IRC16M oscillator is stable and ready for use. 0: IRC16M oscillator is not stable 1: IRC16M oscillator is stable IRC16MEN Internal 16MHz RC oscillator enable...
Page 141 GD32F5xx User Manual 0011: CK_PLLQ = CK_PLLVCO / 3 0100: CK_PLLQ = CK_PLLVCO / 4 … 1111: CK_PLLQ = CK_PLLVCO / 15 Reserved Must be kept at reset value. PLLSEL PLL clock source selection Set and reset by software to control the PLL clock source. 0: IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S 1: HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S 21:18...
Page 142 GD32F5xx User Manual 111111111: Reserved PLLPSC[5:0] The PLL VCO source clock prescaler Set and reset by software when the PLL is disable. These bits used to generate the clock of PLL VCO source clock (CK_PLLVCOSRC), PLLSAI VCO source clock (CK_PLLSAIVCOSRC), or PLLI2S VCO source clock (CK_PLLI2SVCOSRC) from PLL source clock (CK_PLLSRC) which described in PLLSEL in RCU_PLL register.
Page 143 GD32F5xx User Manual 26:24 CKOUT0DIV[2:0] The CK_OUT0 divider which the CK_OUT0 frequency can be reduced see bits 22:21 of RCU_CFG0 for CK_OUT0 0xx: The CK_OUT0 is divided by 1 100: The CK_OUT0 is divided by 2 101: The CK_OUT0 is divided by 3 110: The CK_OUT0 is divided by 4 111: The CK_OUT0 is divided by 5 I2SSEL...
Page 144 GD32F5xx User Manual Reserved Must be kept at reset value. AHBPSC[3:0] AHB prescaler selection Set and reset by software to control the AHB clock division ratio 0xxx: CK_SYS selected 1000: (CK_SYS / 2) selected 1001: (CK_SYS / 4) selected 1010: (CK_SYS / 8) selected 1011: (CK_SYS / 16) selected 1100: (CK_SYS / 64) selected 1101: (CK_SYS / 128) selected...
Page 145 GD32F5xx User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag. 0: Not reset CKMIF flag 1: Reset CKMIF flag PLLSAISTBIC PLLSAI stabilization interrupt clear Write 1 by software to reset the PLLSAISTBIF flag.
Page 146 GD32F5xx User Manual PLLSAISTBIE PLLSAI stabilization interrupt enable Set and reset by software to enable/disable the PLLSAI stabilization interrupt. 0: Disable the PLLSAI stabilization interrupt 1: Enable the PLLSAI stabilization interrupt PLLI2SSTBIE PLLI2S stabilization interrupt enable Set and reset by software to enable/disable the PLLI2S stabilization interrupt. 0: Disable the PLLI2S stabilization interrupt 1: Enable the PLLI2S stabilization interrupt PLLSTBIE...
Page 147 GD32F5xx User Manual PLLI2SSTBIF PLLI2S stabilization interrupt flag Set by hardware when the PLLI2S is stable and the PLLI2SSTBIE bit is set. Reset when setting the PLLI2SSTBIC bit by software. 0: No PLLI2S stabilization interrupt generated 1: PLLI2S stabilization interrupt generated PLLSTBIF PLL stabilization interrupt flag Set by hardware when the PLL is stable and the PLLSTBIE bit is set.
Page 148 GD32F5xx User Manual USBHSR ENETRS DMA1RS DMA0RS Reserved Reserved Reserved IPARST Reserved Reserved CRCRST Reserved PIRST PHRST PGRST PFRST PERST PDRST PCRST PBRST PARST Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. USBHSRST USBHS reset This bit is set and reset by software. 0: No reset 1: Reset the USBHS 28:26...
Page 149 GD32F5xx User Manual 11:9 Reserved Must be kept at reset value. PIRST GPIO port I reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port I PHRST GPIO port H reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port H PGRST...
Page 150 GD32F5xx User Manual AHB2 reset register (RCU_AHB2RST) 5.3.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved PKCAUR Reserved USBFSRST TRNGRST HAURST CAURST Reserved DCIRST Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. USBFSRST USBFS reset This bit is set and reset by software.
Page 151 GD32F5xx User Manual 1: Reset the DCI AHB3 reset register (RCU_AHB3RST) 5.3.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved EXMCRS Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. EXMCRST EXMC reset This bit is set and reset by software.
Page 152 GD32F5xx User Manual 1: Reset the UART7 UART6RST UART6 reset This bit is set and reset by software. 0: No reset 1: Reset the UART6 DACRST DAC reset This bit is set and reset by software. 0: No reset 1: Reset the DAC PMURST PMU reset This bit is set and reset by software.
Page 153 GD32F5xx User Manual 0: No reset 1: Reset the UART4 UART3RST UART3 reset This bit is set and reset by software. 0: No reset 1: Reset the UART3 USART2RST USART2 reset This bit is set and reset by software. 0: No reset 1: Reset the USART2 USART1RST USART1 reset...
Page 154 GD32F5xx User Manual 1: Reset the I2C3 Reserved Must be kept at reset value. TIMER13RST TIMER13 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER13 TIMER12RST TIMER12 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER12 TIMER11RST...
Page 155 GD32F5xx User Manual APB2 reset register (RCU_APB2RST) 5.3.9. Address offset: 0x24 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). TIMER10 TIMER9R TIMER8 Reserved TLIRST Reserved SAIRST SPI5RST SPI4RST Reserved SYSCFG USART5 USART0 TIMER7R TIMER0 Reserved SPI3RST SPI0RST SDIORST Reserved...
Page 156 GD32F5xx User Manual TIMER9RST TIMER9 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER9 TIMER8RST TIMER8 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER8 Reserved Must be kept at reset value.
Page 157 GD32F5xx User Manual 0: No reset 1: Reset the USART0 Reserved Must be kept at reset value. TIMER7RST TIMER7 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER7 TIMER0RST TIMER0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 AHB1 enable register (RCU_AHB1EN)
Page 158 GD32F5xx User Manual ENETRXEN Ethernet RX clock enable This bit is set and reset by software. 0: Disabled Ethernet RX clock 1: Enabled Ethernet RX clock ENETTXEN Ethernet TX clock enable This bit is set and reset by software. 0: Disabled Ethernet TX clock 1: Enabled Ethernet TX clock ENETEN Ethernet clock enable...
Page 159 GD32F5xx User Manual 0: Disabled CRC clock 1: Enabled CRC clock 11:9 Reserved Must be kept at reset value. PIEN GPIO port I clock enable This bit is set and reset by software. 0: Disabled GPIO port I clock 1: Enabled GPIO port I clock PHEN GPIO port H clock enable This bit is set and reset by software.
Page 160 GD32F5xx User Manual 1: Enabled GPIO port A clock AHB2 enable register (RCU_AHB2EN) 5.3.11. Address offset: 0x34 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved USBFSEN TRNGEN HAUEN CAUEN PKCAUEN Reserved DCIEN Bits Fields Descriptions...
Page 161 GD32F5xx User Manual 0: Disabled DCI clock 1: Enabled DCI clock AHB3 enable register (RCU_AHB3EN) 5.3.12. Address offset: 0x38 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved EXMCEN Bits Fields Descriptions 31:1 Reserved Must be kept at reset value.
Page 162 GD32F5xx User Manual 1: Enabled UART7 clock UART6EN UART6 clock enable This bit is set and reset by software. 0: Disabled UART6 clock 1: Enabled UART6 clock DACEN DAC clock enable This bit is set and reset by software. 0: Disabled DAC clock 1: Enabled DAC clock PMUEN PMU clock enable...
Page 163 GD32F5xx User Manual 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software. 0: Disabled UART3 clock 1: Enabled UART3 clock USART2EN USART2 clock enable This bit is set and reset by software. 0: Disabled USART2 clock 1: Enabled USART2 clock USART1EN...
Page 164 GD32F5xx User Manual 1: Enabled I2C3 clock Reserved Must be kept at reset value. TIMER13EN TIMER13 clock enable This bit is set and reset by software. 0: Disabled TIMER13 clock 1: Enabled TIMER13 clock TIMER12EN TIMER12 clock enable This bit is set and reset by software. 0: Disabled TIMER12 clock 1: Enabled TIMER12 clock TIMER11EN...
Page 165 GD32F5xx User Manual APB2 enable register (RCU_APB2EN) 5.3.14. Address offset: 0x44 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). TIMER10 TIMER9E TIMER8 Reserved TLIEN Reserved SAIEN SPI5EN SPI4EN Reserved SYSCFG USART5 USART0 TIMER7E TIMER0 Reserved SPI3EN SPI0EN...
Page 166 GD32F5xx User Manual TIMER9EN TIMER9 clock enable This bit is set and reset by software. 0: Disabled TIMER9 clock 1: Enabled TIMER9 clock TIMER8EN TIMER8 clock enable This bit is set and reset by software. 0: Disabled TIMER8 clock 1: Enabled TIMER8 clock Reserved Must be kept at reset value.
Page 167 GD32F5xx User Manual Reserved Must be kept at reset value. USART5EN USART5 clock enable This bit is set and reset by software. 0: Disabled USART5 clock 1: Enabled USART5 clock USART0EN USART0 clock enable This bit is set and reset by software. 0: Disabled USART0 clock 1: Enabled USART0 clock Reserved...
Page 168 GD32F5xx User Manual This bit is set and reset by software. 0: Disabled USBHS clock when sleep mode 1: Enabled USBHS clock when sleep mode ENETPTPSPEN Ethernet PTP clock enable when sleep mode This bit is set and reset by software. 0: Disabled Ethernet PTP clock when sleep mode 1: Enabled Ethernet PTP clock when sleep mode ENETRXSPEN...
Page 169 GD32F5xx User Manual BKPSRAMSPEN BKPSRAM clock enable when sleep mode This bit is set and reset by software. 0: Disabled BKPSRAM clock when sleep mode 1: Enabled BKPSRAM clock when sleep mode SRAM1SPEN SRAM1 clock enable when sleep mode This bit is set and reset by software. 0: Disabled SRAM1 clock when sleep mode 1: Enabled SRAM1 clock when sleep mode SRAM0SPEN...
Page 170 GD32F5xx User Manual 1: Enabled GPIO port F clock when sleep mode PESPEN GPIO port E clock enable when sleep mode This bit is set and reset by software. 0: Disabled GPIO port E clock when sleep mode 1: Enabled GPIO port E clock when sleep mode PDSPEN GPIO port D clock enable when sleep mode This bit is set and reset by software.
Page 171 GD32F5xx User Manual 0: Disabled USBFS clock when sleep mode 1: Enabled USBFS clock when sleep mode TRNGSPEN TRNG clock enable when sleep mode This bit is set and reset by software. 0: Disabled TRNG clock when sleep mode 1: Enabled TRNG clock when sleep mode HAUSPEN HAU clock enable when sleep mode This bit is set and reset by software.
Page 172 GD32F5xx User Manual EXMCSPEN EXMC clock enable when sleep mode This bit is set and reset by software. 0: Disabled EXMC clock when sleep mode 1: Enabled EXMC clock when sleep mode APB1 sleep mode enable register (RCU_APB1SPEN) 5.3.18. Address offset: 0x60 Reset value: 0xF6FE FDFF This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 173 GD32F5xx User Manual 1: Enabled CAN1 clock when sleep mode CAN0SPEN CAN0 clock enable when sleep mode This bit is set and reset by software. 0: Disabled CAN0 clock when sleep mode 1: Enabled CAN0 clock when sleep mode Reserved Must be kept at reset value.
Page 174 GD32F5xx User Manual 0: Disabled SPI2 clock when sleep mode 1: Enabled SPI2 clock when sleep mode SPI1SPEN SPI1 clock enable when sleep mode This bit is set and reset by software. 0: Disabled SPI1 clock when sleep mode 1: Enabled SPI1 clock when sleep mode I2C5SPEN I2C5 clock enable when sleep mode This bit is set and reset by software.
Page 175 GD32F5xx User Manual 1: Enabled TIMER6 clock when sleep mode TIMER5SPEN TIMER5 clock enable when sleep mode This bit is set and reset by software. 0: Disabled TIMER5 clock when sleep mode 1: Enabled TIMER5 clock when sleep mode TIMER4SPEN TIMER4 clock enable when sleep mode This bit is set and reset by software.
Page 176 GD32F5xx User Manual This bit is set and reset by software. 0: Disabled TLI clock when sleep mode 1: Enabled TLI clock when sleep mode 25:23 Reserved Must be kept at reset value. SAISPEN SAI clock enable when sleep mode This bit is set and reset by software.
Page 177 GD32F5xx User Manual 1: Enabled SPI3 clock when sleep mode SPI0SPEN SPI0 clock enable when sleep mode This bit is set and reset by software. 0: Disabled SPI0 clock when sleep mode 1: Enabled SPI0 clock when sleep mode SDIOSPEN SDIO clock enable when sleep mode This bit is set and reset by software.
Page 178 GD32F5xx User Manual 0: Disabled TIMER0 clock when sleep mode 1: Enabled TIMER0 clock when sleep mode Backup domain control register (RCU_BDCTL) 5.3.20. Address offset: 0x70 Reset value: 0x0000 0000, reset by Backup domain Reset. Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the Backup domain control register (RCU_BDCTL) are only reset after a Backup domain Reset.
Page 179 GD32F5xx User Manual Reserved Must be kept at reset value. LXTALDRI LXTAL drive capability Set and reset by software. Backup domain reset resets this value. 00: lower driving capability (reset value) edium low driving capability 10: Medium high driving capability 11: higher driving capability Note: The LXTALDRI is not in bypass mode.
Page 180 GD32F5xx User Manual 0: No Low-power management reset generated 1: Low-power management reset generated WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No window watchdog reset generated 1: Window watchdog reset generated FWDGTRSTF Free watchdog timer reset flag...
Page 181 GD32F5xx User Manual Set by hardware to indicate if the IRC32K output clock is stable and ready for use. 0: IRC32K is not stable 1: IRC32K is stable IRC32KEN IRC32K enable Set and reset by software. 0: Disable IRC32K 1: Enable IRC32K PLL clock spread spectrum control register (RCU_PLLSSCTL) 5.3.22.
Page 182 GD32F5xx User Manual 12:0 MODCNT These bits configure PLL spread spectrum modulation profile amplitude and frequency. The following criteria must be met: MODSTEP*MODCNT≤2 PLLI2S register (RCU_PLLI2S) 5.3.23. Address offset: 0x84 Reset value: 0x2400 3000 To configure the PLLI2S clock, refer to the following formula: CK_PLLI2SVCOSRC = CK_PLLSRC / PLLPSC CK_PLLI2SVCO = CK_PLLI2SVCOSRC ×...
Page 183 GD32F5xx User Manual RCU_PLLI2S register. 0000: Reserved 0001: Reserved 0010: CK_PLLI2SQ = CK_PLLI2SVCO / 2 0011: CK_PLLI2SQ = CK_PLLI2SVCO / 3 0100: CK_PLLI2SQ = CK_PLLI2SVCO / 4 … 1111: CK_PLLI2SQ = CK_PLLI2SVCO / 15 23:15 Reserved Must be kept at reset value. 14:6 PLLI2SN[8:0] The PLLI2S VCO clock multiplication factor...
Page 184 GD32F5xx User Manual Reserved PLLSAIR[2:0] PLLSAIQ[3:0] Reserved PLLSAIP[1:0] Reserved PLLSAIN[8:0] Reserved Bits Fields Descriptions Reserved Must be kept at reset value. 30:28 PLLSAIR[2:0] The PLLSAI R output frequency division factor from PLLSAI VCO clock Set and reset by software when the PLLSAI is disable. These bits used to generate PLLSAI R output clock (CK_PLLSAIR) from PLLSAI VCO clock (CK_PLLSAIVCO).
Page 185 GD32F5xx User Manual 11 : CK_PLLSAIP = CK_PLLSAIVCO / 8 Reserved Must be kept at reset value. 14:6 PLLSAIN[8:0] The PLLSAI VCO clock multiplication factor Set and reset by software (only use word/half-word write) when the PLLSAI is disable. These bits used to generate PLLSAI VCO clock (CK_PLLSAIVCO) from PLLSAI VCO source clock (CK_PLLSAIVCOSRC).
Page 186 GD32F5xx User Manual 0b100(CK_APBx CK_AHB/2), TIMER clock equal CK_AHB(CK_TIMERx = CK_AHB). Or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2). 1: If APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB).
Page 187 GD32F5xx User Manual Reserved Reserved I2C5SEL[1:0] I2C4SEL[1:0] I2C3SEL[1:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. I2C5SEL[1:0] I2C5 clock source selection Set and reset by software to control the I2C5 clock source. 00: CK_APB1 selected as I2C5 source clock 01: CK_PLLSAIR selected as I2C5 source clock 10: CK_IRC16M selected as I2C5 source clock 11: No select...
Page 188 GD32F5xx User Manual Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register These bits are load automatically at power on. 23:18 Reserved Must be kept at reset value. IRC48MSTB Internal 48MHz RC oscillator clock stabilization Flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use.
Page 189 GD32F5xx User Manual IRC48MS IRC48MS Reserved Reserved Reserved TBIE TBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization interrupt clear Write 1 by software to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag 1: Reset IRC48MSTBIF flag 21:15 Reserved...
Page 190 GD32F5xx User Manual This bit is set and reset by software. 0: No reset 1: Reset IREF unit 30:28 Reserved Must be kept at reset value. CTCRST CTC reset This bit is set and reset by software. 0: No reset 1: Reset CTC 26:0 Reserved...
Page 191 GD32F5xx User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) IREF CTCSP Reserved Reserved SPEN Reserved Bits Fields Descriptions IREFSPEN IREF interface clock enable when sleep mode This bit is set and reset by software. 0: Disabled IREF clock when sleep mode 1: Enabled IREF clock when sleep mode 30:28 Reserved...
Page 192 GD32F5xx User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved DSLPVS[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. DSLPVS[2:0] Deep-sleep mode voltage select These bits are set and reset by software. 000: The core voltage is default value in Deep-sleep mode 001: The core voltage is (default value-0.1)V in Deep-sleep mode(customers are not recommended to use it)
Page 193 GD32F5xx User Manual Clock trim controller (CTC) 6.1. Overview The clock trim controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trims the frequency of the IRC48M which is based on an external accurate reference signal source. It can adjust the calibration value to provide a precise IRC48M clock automatically or manually.
Page 194 GD32F5xx User Manual Figure 6-1．Block diagram of CTC PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM Reference sync pulse generator 6.3.1.
Page 195 GD32F5xx User Manual reloads the RLVALUE and starts down-counting again. If no REF sync pulse is detected, the counter down-counts to zero, and then up-counts to 128 x CKLIM (defined in CTC_CTL1 register), and then stops until next REF sync pulse is detected. If any REF sync pulse is detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 196 GD32F5xx User Manual CTC_STAT register is set, an interrupt will be generated if – When the CKOKIF in CKOKIE bit in CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register is set, the TRIMVALUE in CTC_CTL0 – register is not changed. ...
Page 197 GD32F5xx User Manual 6.4. Register definition CTC base address: 0x4000 6C00 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit). Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 198 GD32F5xx User Manual trim counter. When this bit is set, the CTC_CTL1 register cannot be modified. 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE Expected reference (EREFIF) interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable...
Page 199 GD32F5xx User Manual 00: GPIO (CTC_SYNC) selected 01: LXTAL clock selected 10: Reserved 11: Reserved Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software. 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8...
Page 200 GD32F5xx User Manual REFCAP bits. REFDIR CTC trim counter direction When a reference sync pulse occurs during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register is overflow...
Page 201 GD32F5xx User Manual This bit is set by hardware when an error occurs. If any error of TRIMERR, REFMISS or CKERR occurs, this bit will be set. When the ERRIE in CTC_CTL0 register is set, an interrupt occurs. This bit is cleared by writing 1 to ERRIC bit in CTC_INTC register.
Page 202 GD32F5xx User Manual This bit is written by software and read as 0. Write 1 to clear EREFIF bit in CTC_STAT register. Writing 0 has no effect. ERRIC ERRIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear ERRIF, TRIMERR, REFMISS and CKERR bits in CTC_STAT register.
Page 203 GD32F5xx User Manual Interrupt / event controller (EXTI) 7.1. Overview -M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception ® Cortex and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. More details about NVIC could be referred to Technical Reference Manual of -M33.
Page 204 GD32F5xx User Manual ® Table 7-1. NVIC exception types in Cortex -M33 Vector Exception type priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable...
Page 205 GD32F5xx User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ 16 DMA0 channel5 global interrupt 0x0000_0080 IRQ 17 DMA0 channel6 global interrupt 0x0000_0084 IRQ 18 ADC global interrupt 0x0000_0088 IRQ 19 CAN0 TX interrupt 0x0000_008C IRQ 20 CAN0 RX0 interrupt 0x0000_0090 IRQ 21...
Page 206 GD32F5xx User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ 48 EXMC global interrupt 0x0000_0100 IRQ 49 SDIO global interrupt 0x0000_0104 IRQ 50 TIMER4 global interrupt 0x0000_0108 IRQ 51 SPI2 global interrupt 0x0000_010C IRQ 52 UART3 global interrupt 0x0000_0110 IRQ 53 UART4 global interrupt...
Page 207 GD32F5xx User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ87 SAI global interrupt 0x0000_019C IRQ88 TLI global interrupt 0x0000_01A0 IRQ89 TLI global error interrupt 0x0000_01A4 IRQ90 IPA global interrupt 0x0000_01A8 IRQ91 PKCAU global interrupt 0x0000_01AC IRQ92 I2C3 event interrupt 0x0000_01B0 IRQ93 I2C3 error interrupt...
Page 208 GD32F5xx User Manual 7.4. External interrupt and event block diagram Figure 7-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~25 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 7.5. External Interrupt and Event function overview The EXTI contains up to 26 independent edge detectors and generates interrupts request or event to the processer.
Page 209 GD32F5xx User Manual Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in SYSCFG module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 210 GD32F5xx User Manual EXTI line Source number RTC Alarm USBFS Wakeup Ethernet Wakeup USBHS Wakeup RTC Tamper and TimeStamp event RTC Wakeup I2C3 Wakeup I2C4 Wakeup I2C5 Wakeup...
Page 211 GD32F5xx User Manual 7.6. Register definition EXTI base address: 0x4001 3C00 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8...
Page 212 GD32F5xx User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10...
Page 213 GD32F5xx User Manual This register has to be accessed by word (32-bit). Reserved SWIEV25 SWIEV24 SWIEV23 SWIEV22 SWIEV21 SWIEV20 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:26...
Page 214 GD32F5xx User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 8.1. Overview There are up to 140 general purpose I / O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~ PH15 and PI0 ~ PI11 for the device to implement logic input / output functions.
Page 215 GD32F5xx User Manual drain mode by GPIO output mode registers (GPIOx_OMODE). And the port max speed can be configured by GPIO output speed registers (GPIOx_OSPD). Each port can be configured as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up / pull- down registers (GPIOx_PUD).
Page 216 GD32F5xx User Manual GPIO pin configuration 8.3.1. During or just after the reset period, the alternative functions are all inactive and the GPIO ports are configured into the input floating mode that input disabled without Pull-Up (PU) / Pull-Down (PD) resistors. But the JTAG / Serial-Wired Debug pins are in input PU / PD mode after reset: PA15: JTDI in PU mode.
Page 217 GD32F5xx User Manual Input configuration 8.3.5. When GPIO pin is configured as input:  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors could be chosen.  Every AHB clock cycle the data present on the I / O pin is got to the port input status Register.
Page 218 GD32F5xx User Manual Analog configuration 8.3.7. When GPIO pin is used as analog configuration:  The weak pull-up and pull-down resistors are disabled.  The output buffer is disabled.  The schmitt trigger input is disabled.  The port input status register of this I / O port bit is “0”. Figure 8-4.
Page 219 GD32F5xx User Manual Figure 8-5. Basic structure of Alternate function configuration Output driver Alternate Function Output protect I / O pin Alternate Function Input Input driver GPIO locking function 8.3.9. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD and GPIOx_AFSELz (z=0, 1).
Page 220 GD32F5xx User Manual 8.4. Register definition GPIOA base address: 0x4002 0000 GPIOB base address: 0x4002 0400 GPIOC base address: 0x4002 0800 GPIOD base address: 0x4002 0C00 GPIOE base address: 0x4002 1000 GPIOF base address: 0x4002 1400 GPIOG base address: 0x4002 1800 GPIOH base address: 0x4002 1C00 GPIOI base address: 0x4002 2000 Port control register (GPIOx_CTL, x = A…I)
Page 221 GD32F5xx User Manual Refer to CTL0[1:0] description. 23:22 CTL11[1:0] Pin 11 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 21:20 CTL10[1:0] Pin 10 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 19:18 CTL9[1:0] Pin 9 configuration bits...
Page 222 GD32F5xx User Manual 01: GPIO output mode 10: Alternate function mode 11: Analog mode (Input and Output) Port output mode register (GPIOx_OMODE, x = A…I) 8.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved OM15 OM14...
Page 223 GD32F5xx User Manual Refer to OM0 description Pin 8 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 7 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 6 output mode bit These bits are set and cleared by software.
Page 224 GD32F5xx User Manual OSPD7[1:0] OSPD6[1:0] OSPD5[1:0] OSPD4[1:0] OSPD3[1:0] OSPD2[1:0] OSPD1[1:0] OSPD0[1:0] Bits Fields Descriptions 31:30 OSPD15[1:0] Pin 15 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 29:28 OSPD14[1:0] Pin 14 output max speed bits These bits are set and cleared by software.
Page 225 GD32F5xx User Manual Refer to OSPD0[1:0] description OSPD4[1:0] Pin 4 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD3[1:0] Pin 3 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD2[1:0] Pin 2 output max speed bits...
Page 226 GD32F5xx User Manual 27:26 PUD13[1:0] Pin 13 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description. 25:24 PUD12[1:0] Pin 12 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description. 23:22 PUD11[1:0] Pin 11 pull-up or pull-down bits...
Page 227 GD32F5xx User Manual These bits are set and cleared by software. Refer to PUD0[1:0] description. PUD0[1:0] Pin 0 pull-up or pull-down bits These bits are set and cleared by software. 00: Floating mode, no pull-up and pull-down (reset value) 01: With pull-up mode 10: With pull-down mode 11: Reserved Port input status register (GPIOx_ISTAT, x = A…I)
Page 228 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 OCTLy Pin output control (y=0..15) These bits are set and cleared by software. 0: Pin output low 1: Pin output high Port bit operate register (GPIOx_BOP, x = A…I) 8.4.7.
Page 229 GD32F5xx User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can always be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset.
Page 230 GD32F5xx User Manual Refer to SEL0 [3:0] description. 15:12 SEL3[3:0] Pin 3 alternate function selected These bits are set and cleared by software. Refer to SEL0 [3:0] description. 11:8 SEL2[3:0] Pin 2 alternate function selected These bits are set and cleared by software. Refer to SEL0 [3:0] description.
Page 231 GD32F5xx User Manual These bits are set and cleared by software. Refer to SEL8[3:0] description. 19:16 SEL12[3:0] Pin 12 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description. 15:12 SEL11[3:0] Pin 11 alternate function selected These bits are set and cleared by software.
Page 232 GD32F5xx User Manual 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x = A…I) 8.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved TG15 TG14...
Page 233 GD32F5xx User Manual Cyclic redundancy checks management unit (CRC) 9.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 32 bit CRC code with fixed polynomial. 9.2.
Page 234 GD32F5xx User Manual 9.3. Function overview  CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 235 GD32F5xx User Manual 9.4. Register definition CRC base address: 0x4002 3000 Data register (CRC_DATA) 9.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 236 GD32F5xx User Manual by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 9.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1...
Page 237 GD32F5xx User Manual True random number generator (TRNG) 10.1. Overview The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. 10.2. Characteristics  About 40 periods of TRNG_CLK are needed between two consecutive random numbers ...
Page 238 GD32F5xx User Manual The 32-bit value of LFSR will be transferred into TRNG_DATA register after a sufficient number of seeds have been sent to the LFSR. At the same time, the analog seed and TRNG_CLK clock are monitored. When an analog seed error or a clock error occurs, the corresponding status bit in TRNG_STAT will be set and an interrupt will generate if the TRNGIE bit in TRNG_CTL is set.
Page 239 GD32F5xx User Manual 10.4. Register definition TRNG base address: 0x5006 0800 Control register (TRNG_CTL) 10.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved TRNGEN Reserved Bits Fields Descriptions Must be kept at reset value. 31:4 Reserved TRNGIE...
Page 240 GD32F5xx User Manual Bits Fields Descriptions Must be kept at reset value. 31:7 Reserved SEIF Seed error interrupt flag This bit will be set if more than 64 consecutive same bit or more than 32 consecutive 01(or 10) changing are detected. 0: No fault detected 1: Seed error has been detected.
Page 241 GD32F5xx User Manual Bits Fields Descriptions 31:0 TRNGDATA[31:0] 32-Bit Random data...
Page 242 GD32F5xx User Manual Public Key Cryptographic Acceleration Unit (PKCAU) 11.1. Overview Public key encryption is also called asymmetric encryption, asymmetric encryption algorithms use different keys for encryption and decryption. The Public Key Cryptographic Acceleration Unit (PKCAU) can accelerate RSA (Rivest, Shamir and Adleman), Diffie-Hellmann (DH key exchange) and ECC (elliptic curve cryptography) in GF(p) (Galois domain).
Page 243 GD32F5xx User Manual Figure 11-1. PKCAU module block diagram PKCAU registers Control/status clear PKCAU_CTL Control PKCAU_STAT logic status PKCAU_STATC interrupt PKCAU PKCAU RAM core (3584 bytes) Operands 11.3.1. If the RSA operand size is ROS, the modulus length is ML, then the data size is ROS = (ML/32+1) words.
Page 244 GD32F5xx User Manual Figure 11-2. Flow chart of RSA algorithm Alice Save public Generate key from Bob key pairs message message encryption Public key decryption Private key algorithm from Bob algorithm from Bob ciphertext ciphertext A complete public key crypto system includes key pairs (public and private keys), encryption algorithms and decryption algorithms.
Page 245 GD32F5xx User Manual key. The decryption process is m = c mod n. ECC algorithm 11.3.3. Suppose the message is M, d is the private key, G is the base point of the chosen elliptic curve, Q is a point of the chosen elliptic curve, with a prime order n. The hash function is HASH(), z is the Ln leftmost bits of HASH (M), where Ln is the bit length of the order n.
Page 246 GD32F5xx User Manual ECDSA verification Before verifying the signature, be sure to get the signer's public key, message, and signature. The process to generate ECDSA signature is shown in Figure 11-4. Flow chart of ECDSA verification. Figure 11-4. Flow chart of ECDSA verification start 0<r<n and 0<s<n? Calculate w=s...
Page 247 GD32F5xx User Manual MODSEL[5:0] Operation modes 000001 calculate Montgomery parameter only 000010 modular exponentiation (the Montgomery parameter must be preloaded) 000111 RSA CRT exponentiation 001000 Modular inversion 001001 Arithmetic addition 001010 Arithmetic subtraction 001011 Arithmetic multiplication 001100 Arithmetic comparison 001101 Modular reduction 001110 Modular addition...
Page 248 GD32F5xx User Manual L+ceil(L%32) If A<B, the operation result is “result = A-B+2 ”. Figure 11-6. Arithmetic subtraction PKCAU RAM offset address output offset address input 0x400 0x404 Operand length L 0x408 0x8B4 Operand A 0xA44 Operand B 0xBD0 0xBD0 0≤A<2 , 0≤B<2 , 0≤result<2...
Page 249 GD32F5xx User Manual Arithmetic comparison The arithmetic comparison operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "001100". The operation declaration is shown in Figure 11-8. Arithmetic comparison. If A=B, the operation result is “result = 0x0”; If A>B, the operation result is “result = 0x1”; If A<B, the operation result is “result = 0x2”.
Page 250 GD32F5xx User Manual Figure 11-9. Modular reduction PKCAU RAM Offset address input output Offset address 0x400 Operand length L 0x404 Modulus length M 0x408 0x8B4 Operand A 0xA44 Modulus n 0xBD0 0xBD0 A mod n 0<L≤3136, 0<M≤3136, 0≤A<2 , 0<n<2 , 0≤result<n.
Page 251 GD32F5xx User Manual If A≥B, the operation result is “result = A-B mod n”; If A<B, the operation result is “result = A-B+n mod n”. Figure 11-11. Modular subtraction PKCAU RAM Offset address output input Offset address 0x400 0x404 Modulus length M 0x408 0x8B4 Operand A...
Page 252 GD32F5xx User Manual 0<M≤3136, 1<n<2 (n must be odd integer). Montgomery multiplication Suppose A, B and C are in natural domain. “x” function is Montgomery multiplication operation. The two main uses of this opreation are as follows: 1. Mutual mapping between Montgomery domain and natural domain. Figure 11-13.
Page 253 GD32F5xx User Manual Figure 11-14. Montgomery multiplication PKCAU RAM Offset address output input Offset address 0x400 0x404 Modulus length M 0x408 0x8B4 Operand A 0xA44 0xBD0 Operand B AxB mod n 0xD5C Modulus n 0≤A<n, 0≤B<n, 0<n<2 , 0<M≤3136 (n must be odd integer). Modular exponentiation Normal mode The Modular exponentiation of normal mode operation is selected by configuring...
Page 254 GD32F5xx User Manual in PKCAU_CTL register as "000010". The operation declaration is shown in Figure 11-16. Modular exponentiation of fast mode. The operation result is “result = A mod n”. Figure 11-16. Modular exponentiation of fast mode Offset address input output Offset address 0x400...
Page 255 GD32F5xx User Manual 2． If the modulus n is not prime, only when the greatest common divisor of A and n is 1, the modular inversion output is valid. RSA CRT exponentiation The RSA CRT exponentiation operation is selected by configuring MODSEL[5:0] in PKCAU_CTL register as "000111".
Page 256 GD32F5xx User Manual Table 11-3. Range of parameters used by RSA CRT exponentiation operation Parameters Range 0≤d <2 Operand d 0≤d <2 Operand d 0<q <2 Operand q Input 0<p<2 Prime p 0<q<2 Prime q 0≤A<2 Operand A result = A mod pq 0≤result<pq Output...
Page 257 GD32F5xx User Manual Figure 11-19. Point on elliptic curve Fp check Offset address output input Offset address 0x400 0x400 result 0x404 0x404 Modulus length M 0x408 Sign of curve coefficient 0x40C Curve coefficient |a| 0x460 Curve modulus 0x55C x coordinate of point P 0x5B0 y coordinate of point P 0x7FC...
Page 258 GD32F5xx User Manual Figure 11-20. ECC scalar multiplication of normal mode Offset address output input Offset address 0x400 Length of scalar multiplier k 0x404 Modulus length 0x408 Sign of curve coefficient a 0x40C Curve coefficient |a| 0x460 Curve modulus p 0x508 scalar multiplier k 0x55C...
Page 259 GD32F5xx User Manual Table 11-6. Range of parameters used by ECC scalar multiplication Parameters Range Length of scalar 0<LEN≤640 multiplier k (LEN) 0<M≤640 Modulus length M Sign of curve 0x0: positive coefficient a 0x1: negative input Curve coefficient |a| Absolute value |a|<p Odd prime 0<p≤2 Curve modulus p 0≤k<2...
Page 260 GD32F5xx User Manual Figure 11-22. ECDSA sign PKCAU RAM Offset address output input Offset address 0x400 Curve prime order n length 0x404 Curve modulus p length M 0x408 Sign of curve coefficient a 0x40C Curve coefficient |a| 0x460 Curve modulus p 0x508 Integer k 0x55C...
Page 261 GD32F5xx User Manual Parameters Range 0<r<n Signature part r 0<s<n Signature part s 0x0: no error Signature result: 0x1: Signature part r is 0 ERROR output 0x2: Signature part s is 0 Curve point kG 0≤x <n coordinate x Curve point kG 0≤y <n coordinate y...
Page 262 GD32F5xx User Manual of parameters used by ECDSA verification. Table 11-8. Range of parameters used by ECDSA verification Parameters Range Curve prime order n 0<LEN≤640 length (LEN) Curve modulus p 0<M≤640 length (M) Sign of curve 0x0: positive coefficient a 0x1: negative Curve coefficient |a| Absolute value |a|<p...
Page 263 GD32F5xx User Manual 2. Load the initial data into PKCAU RAM at offset address 0x400; 3. Specify the operation to be performed in MODSEL[5:0] bits in PKCAU_CTL register, then set START bit in PKCAU_CTL register; 4. Wait for the ENDF bit set in PKCAU_STAT register; 5.
Page 264 GD32F5xx User Manual Exponent Operand length (in bits) Mode length (in bits) 1024 2048 3072 13651000 Normal 182783000 3072 Fast 181953000 44905000 Table 11-10. ECC scalar multiplication computation times Modulus length (in bits) Mode Normal 626000 951000 1997000 3617000 5762000 13134000 Fast 623000...
Page 265 GD32F5xx User Manual in PKCAU_STATC register.  End of operation flag (ENDF) When the operation specified in MODSEL[5:0] bits in the PKCAU_CTL register is completed, the ENDF bit will be set. If the ENDIE bit in PKCAU_CTL register is set, an interrupt will be generated.
Page 266 GD32F5xx User Manual 11.4. Register definition PKCAU base address: 0x5006 1000 Control register (PKCAU_CTL) 11.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). ADDRER RAMERR Reserved Reserved ENDIE Reserved PKCAUE Reserved MODSEL[5:0] Reserved START Bits Fields...
Page 267 GD32F5xx User Manual 001010: Arithmetic subtraction 001011: Arithmetic multiplication 001100: Arithmetic comparison 001101: Modular reduction 001110: Modular addition 001111: Modular subtraction 010000: Montgomery multiplication 100000: Montgomery parameter computation then ECC scalar multiplication 100010: ECC scalar multiplication only (Montgomery parameter must be loaded first) 100100: ECDSA sign 100110: ECDSA verification...
Page 268 GD32F5xx User Manual 0: No address error. 1: The accessed address exceeds the expected range of PKCAU RAM, an address error occurs. RAMERR PKCAU RAM error 0: No PKCAU RAM error. 1: When the PKCAU core is using the RAM, AHB accesses the PKCAU RAM, a PKCAU RAM error occurs.
Page 269 GD32F5xx User Manual Software can clear the ENDF bit in PKCAU_STAT by writing 1 to this bit. Reserved Must be kept at reset value. 16:0...
Page 270 GD32F5xx User Manual Hash Acceleration Unit (HAU) 12.1. Overview The hash acceleration unit is used for information security. The secure hash algorithm (SHA- 1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will be computed and the length is 160 / 224 / 256 / 128 bits for a message up to (2 - 1) bits computed by SHA-1, SHA-224, SHA-256 and MD5 algorithms respectively.
Page 271 GD32F5xx User Manual types. Figure 12-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1 word2 word2 WORD 2 word3 word3 WORD 3 (LSB) No swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Half-word swapping Figure 12-2.
Page 272 GD32F5xx User Manual 12.4. HAU core The hash acceleration unit is used to compute condensed information of input messages with secure hash algorithms. The digest result has a length of 160/224/256/128 bits for a message up to (2 -1) bits computed by SHA-1, SHA-224, SHA256 and MD5 algorithms respectively. It can be used to generate or verify the signature of a message with a higher efficiency because of the much simpler of the information.
Page 273 GD32F5xx User Manual set 1 to start the calculation of the digest of the last block. Data Padding Example: The input message is “HAU”, which ASCII hexadecimal code is: 484155 Then the VBL bits in the HAU_CFG register is set as decimal 24 because of the valid bit length.
Page 274 GD32F5xx User Manual CPU is used to transfer data without DMA:  The intermediate block computing can be started when HAU_DI is filled with another new word of the next block.  The last block computing can be started when CALEN bit in the HAU_CFG register is 1. Hash mode 12.4.3.
Page 275 GD32F5xx User Manual 12.5. HAU suspended mode It is possible to suspend HASH or HMAC operation to perform a high-prior task first, then after the high-prior task is finished, resume the suspended operation. When suspending the current task, it is necessary to save the context of the current task from registers to memory, and then the task can be resumed by restoring the context from memory to the HAU registers.
Page 276 GD32F5xx User Manual HAU_CFG and HAU_CTL registers. Resume DMA channel transmission. Reconfigure the DMA channel to transfer data. Resume the message calculation. Set START bit of HAU_CTL register to 1, to restart a new message digest calculation. Resume the previous core state. Restore the content from memory to HAU_CTXS0 ~ HAU_CTXS37 (HAU_CTXS0 ~ HAU_CTXS53 when HMAC operation is to be resumed) registers.
Page 277 GD32F5xx User Manual 12.7. Register definition HAU base address: 0x5006 0400 HAU control register (HAU_CTL) 12.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[1] Reserved Reserved DINE NWIF[3:0] ALGM[0] DATAM[1:0] DMAE START Reserved...
Page 278 GD32F5xx User Manual ALGM[0] Algorithm selection bit 0 This bit and bit 18 of CTL are written by software to select the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: Select SHA-1 algorithm 01: Select MD5 algorithm 10: Select SHA224 algorithm 11: Select SHA256 algorithm HAU mode selection, must be changed when no computation is processing 0: HASH mode selected...
Page 279 GD32F5xx User Manual calculation is in process until it has been finished. This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Message data input When write to these registers, the current content pushed to IN FIFO and new value updates.
Page 280 GD32F5xx User Manual valid 0x1F: Only bits [31:1] of the last data written to HAU_DI after data swapping are valid Note: These bits must be configured before setting the CALEN bit. HAU data output register (HAU_DO0..7) 12.7.4. Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) The data output registers are read only registers.
Page 281 GD32F5xx User Manual DO2[31:16] DO2[15:0] HAU_DO3 Address offset: 0x18 and 0x31C DO3[31:16] DO3[15:0] HAU_DO4 Address offset: 0x1C and 0x320 DO4[31:16] DO4[15:0] HAU_DO5 Address offset: 0x324 DO5[31:16] DO5[15:0] HAU_DO6 Address offset: 0x328 DO6[31:16]...
Page 282 GD32F5xx User Manual DO6[15:0] HAU_DO7 Address offset: 0x32C DO7[31:16] DO7[15:0] Bits Fields Descriptions 31:0 DO0..7[31:0] Message digest result of hash algorithm HAU interrupt enable register (HAU_INTEN) 12.7.5. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CCIE...
Page 283 GD32F5xx User Manual Reset value: 0x0000 0001 This register has to be accessed by word (32-bit). Reserved Reserved BUSY DMAS rc_w0 rc_w0 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing 1: Data block is in process DMAS DMA status 0: DMA is disabled (DMAE = 0) and no transfer is processing...
Page 284 GD32F5xx User Manual the registers to resume the suspended processing.
Page 285 GD32F5xx User Manual Cryptographic Acceleration Unit (CAU) 13.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ...
Page 286 GD32F5xx User Manual  four 32-bit initialization vectors (IV) are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes.  8 * 32-bit input and output FIFO.  Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping.
Page 287 GD32F5xx User Manual Figure 13-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1 word2 word2 WORD 2 word3 word3 WORD 3 (LSB) No swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Half-word swapping Figure 13-2.
Page 288 GD32F5xx User Manual Initialization vectors 13.3.2. The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks. They are independent of plaintext and ciphertext, and the DATAM value will not affect them. Note the initialization vector registers CAU_IV0..1(H / L) can only be written when BUSY is 0, otherwise the write operations are invalid.
Page 289 GD32F5xx User Manual 1. Three same keys The three keys KEY3, KEY2 and KEY1 are completely equal, which means KEY3 = KEY2 = KEY1. FIPS PUB 46-3 – 1999 (and ANSI X9.52 - 1998) refers to this option. It is easy to understand that this mode is equivalent to DES.
Page 290 GD32F5xx User Manual Figure 13-4. DES / TDES ECB encryption CAU_DI Plaintext DATAM SWAP KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES / TDES ECB decryption The 64-bit input ciphertext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and decrypted using KEY3.
Page 291 GD32F5xx User Manual Figure 13-5. DES / TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES / TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 292 GD32F5xx User Manual Figure 13-6. DES / TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES / TDES CBC decryption In DES / TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 293 GD32F5xx User Manual Figure 13-7. DES / TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 13.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 294 GD32F5xx User Manual Figure 13-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 295 GD32F5xx User Manual Figure 13-9. AES ECB decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt SWAP CAU_DO Plaintext AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the AEA and encrypted using the 128-, 192-, 256-bit key.
Page 296 GD32F5xx User Manual Figure 13-10. AES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0..1(H/L) CAU_KEY0..3 AEA, encrypt SWAP CAU_DO Ciphertext AES-CBC mode decryption Similar to that in AES-ECB mode decryption, the key derivation also must be completed first to prepare the decryption keys, the input of the key schedule should be the same to that used in encryption.
Page 297 GD32F5xx User Manual Figure 13-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP CAU_DO Plaintext AES-CTR mode In counter mode, a counter is used in addition with a nonce value to be encrypted and decrypted in AEA, and the result will be used for the XOR operation with the plaintext or the ciphertext.
Page 298 GD32F5xx User Manual Figure 13-13. AES CTR encryption / decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois / counter mode (GCM) can be used to encrypt or authenticate message, and then ciphertext and tag can be obtained.
Page 299 GD32F5xx User Manual can also be used. (i) Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption / decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted / decrypted.
Page 300 GD32F5xx User Manual In this mode, four steps are required to perform an encryption / decryption: 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled.
Page 301 GD32F5xx User Manual (p) Write the 128 bit input into the CAU_DI register, 4 times of write operation to CAU_DI is needed. The input is the A0 value. (q) Wait until the ONE flag is set to 1, and then read CAU_DO 4 times. The output corresponds to the authentication tag.
Page 302 GD32F5xx User Manual Decryption 1. Disable the CAU by resetting the CAUEN bit in the CAU_CTL register. 2. Enable CAU power domain by setting the CORE1WAKE bit in the PMU_CTL1 register, and then enable CAU clock. 3. Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen.
Page 303 GD32F5xx User Manual word is read from the CAU. DMA channel for output data has a higher priority than that channel for input data so that the output FIFO can be empty earlier than that the input FIFO is full. 13.7.
Page 304 GD32F5xx User Manual CCM phase and the key values. When it is CBC, CTR, GCM, GMAC, CCM, CFB or OFB chaining mode, the initialization vectors should also be stored. When it is GCM, GMAC or CCM mode, the context switch CAU_GCMCCMCTXSx (x = 0..7) and CAU_GCMCTXSx (x = 0..7) registers should also be stored.
Page 305 GD32F5xx User Manual 13.9. Register definition CAU base address: 0x5006 0000 Control register (CAU_CTL) 13.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved NBPILB[3:0] ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH Reserved KEYM[1:0] DATAM[1:0] ALGM[2:0] CAUDIR...
Page 306 GD32F5xx User Manual Reading this bit always returns 0 13:10 Reserved Must be kept at reset value. KEYM[1:0] AES key size mode configuration, must be configured when BUSY=0 00: 128-bit key length 01: 192-bit key length 10: 256-bit key length 11: never use DATAM[1:0] Data swapping type mode configuration, must be configured when BUSY=0...
Page 307 GD32F5xx User Manual 1: decryption Reserved Must be kept at reset value. Status register 0 (CAU_STAT0) 13.9.2. Address offset: 0x04 Reset value: 0x0000 0003 This register has to be accessed by word (32-bit). Reserved Reserved BUSY Bits Fields Descriptions 31:5 Reserved Must be kept at reset value.
Page 308 GD32F5xx User Manual Reset value: 0x0000 0000 The data input register is used to transfer plaintext or ciphertext blocks into the input FIFO for processing. The MSB is firstly written into the FIFO and the LSB is the last one. If the CAUEN is 0 and the input FIFO is not empty, when it is read, then the first data in the FIFO is popped out and returned.
Page 309 GD32F5xx User Manual DMA enable register (CAU_DMAEN) 13.9.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DMAOEN DMAIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN DMA output enable 0: DMA for OUT FIFO data is disabled 1: DMA for OUT FIFO data is enabled...
Page 310 GD32F5xx User Manual 1: OUT FIFO interrupt is enable IINTEN IN FIFO interrupt enable 0: IN FIFO interrupt is disable 1: IN FIFO interrupt is enable Status register 1 (CAU_STAT1) 13.9.7. Address offset: 0x18 Reset value: 0x0000 0001 This register has to be accessed by word (32-bit). Reserved Reserved OSTA...
Page 311 GD32F5xx User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. OINTF OUT FIFO enabled interrupt flag 0: OUT FIFO Interrupt not pending 1: OUT FIFO Interrupt pending IINTF IN FIFO enabled interrupt flag 0: IN FIFO Interrupt not pending 1: IN FIFO Interrupt pending when CAUEN is 1 Key registers (CAU_KEY0..3 (H / L)) 13.9.9.
Page 312 GD32F5xx User Manual CAU_KEY0L Address offset: 0x24 Reset value: 0x0000 0000 KEY0L[31:16] KEY0L[15:0] CAU_KEY1H Address offset: 0x28 Reset value: 0x0000 0000 KEY1H[31:16] KEY1H[15:0] CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 KEY1L[31:16] KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0]...
Page 313 GD32F5xx User Manual CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16] KEY3L[15:0] Bits Fields Descriptions KEY0...3(H / L) The key for DES, TDES, AES 31:0 Initial vector registers (CAU_IV0..1 (H / L)) 13.9.10.
Page 314 GD32F5xx User Manual In DES / TDES mode, IV0H is the leftmost bits, and IV0L is the rightmost bits of the initialization vectors. In AES mode, IV0H is the leftmost bits, and IV1L is the rightmost bits of the initialization vectors.
Page 315 GD32F5xx User Manual IV1L[31:16] IV1L[15:0] Bits Fields Descriptions IV0...1(H / L) The initialization vector for DES, TDES, AES 31:0 GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x 13.9.11. = 0..7) Address offset: 0x50 to 0x6C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 316 GD32F5xx User Manual Bits Fields Descriptions 31:0 CTXx[31:0] The internal status of the CAU core. Read and save the register data when a high- priority task is coming to be processed, and restore the saved data back to the registers to resume the suspended processing. Note: These registers are used only when GCM or GMAC mode is selected.
Page 317 GD32F5xx User Manual Direct memory access controller (DMA) 14.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the MCU, thereby increasing system performance by off-loading the MCU from copying large amounts of data and avoiding frequent interrupts to serve peripherals needing more data or having available data.
Page 318 GD32F5xx User Manual  Both DMA and peripheral can be configured as flow controller – DMA: Programmable length of data to be transferred, max to 65535. – Peripheral: The last request signal given to DMA from peripheral determines the end of transfer. ...
Page 319 GD32F5xx User Manual 14.4. Function overview The DMA controller transfers data from one address to another without CPU intervention. It supports multiple data sizes, burst types, address generation algorithm, priority levels and several transfer modes to allow for flexible application by configuring the corresponding bits in DMA registers.
Page 320 GD32F5xx User Manual  Memory to peripheral: read data from memory through AHB master interface for memory, and write data to peripheral through AHB master interface for peripheral; Peripheral to memory: read data from peripheral through AHB master interface for ...
Page 321 GD32F5xx User Manual Table 14-2. Peripheral requests to DMA0 Channel Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 SPI2_RX I2C3_RX SPI2_RX SPI1_RX SPI1_TX SPI2_TX I2C3_TX SPI2_TX I2C0_RX I2C4_RX TIMER6_UP I2C4_TX TIMER6_UP I2C0_RX I2C0_TX I2C0_TX ●...
Page 322 GD32F5xx User Manual channel with lower channel number. Transfer width, burst and counter Transfer width PWIDTH and MWIDTH in the DMA_CHxCTL register indicate the data width of a peripheral and memory transfer seperately. The DMA supports 8-bit, 16-bit and 32-bit transfer width. In multi-data mode, if PWIDTH is not equal to MWIDTH, the DMA can automatically packs/unpacks data to achieve an integrated and correct data transfer operation.
Page 323 GD32F5xx User Manual When configuring the CNT bits, the following rules must be respected to guarantee a good DMA operation: If the circular mode is disabled by clearing the CMEN bit in the DMA_CHxCTL register, the rules to configure the CNT bits in the DMA_CHxCNT register based on the transfer width are listed in the Table 14-4.
Page 324 GD32F5xx User Manual 2. If the If PWIDTH is 8-bit, PBURST is INCR16, MWIDTH is 16-bit and MBURST is INCR4, CNT 16 and ( CNT×1) (2×4) ⁄ ⁄ must be an integer, so the CNT bits must be configured to the multiple of 16. Note: when the switch-buffer mode is enabled by setting the SBMEN bit in the DMA_CHxCTL register, the circular mode is enabled automatically by hardware, and the above rules must also be respected.
Page 325 GD32F5xx User Manual transactions transactions transactions transactions INCR4 ERROR 1 burst transaction ERROR 2 burst transactions INCR8 ERROR ERROR ERROR 1 burst transaction INCR16 ERROR ERROR ERROR ERROR 1 single 2 single 3 single 4 single single transaction transactions transactions transactions 32-bit INCR4...
Page 326 GD32F5xx User Manual Figure 14-4. Data packing/unpacking when PWIDTH = ‘00’  PAIF = 0, MWIDTH = 8-bit read 0xB0[7:0] @0x0 read 0xB8[7:0] @0x8 write 0xB0[7:0] @0x0 write 0xB8[7:0] @0x8 word 4 read 0xB1[7:0] @0x1 read 0xB9[7:0] @0x9 write 0xB1[7:0] @0x1 write 0xB9[7:0] @0x9 read 0xB2[7:0] @0x2 read 0xB10[7:0] @0xA write 0xB2[7:0] @0x2 write 0xB10[7:0] @0xA word 3...
Page 327 GD32F5xx User Manual Figure 14-6. Data packing/unpacking when PWIDTH = ‘10’  PAIF = 1, MWIDTH = 8-bit write 0xB0[7:0] @0x0 write 0xB8[7:0] @0x8 word 4 write 0xB1[7:0] @0x1 write 0xB9[7:0] @0x9 read 0xB3B2B1B0[31:0] @0x0 write 0xB2[7:0] @0x2 write 0xB10[7:0] @0xA word 3 read 0xB7B6B5B4[31:0] @0x4 write 0xB3[7:0] @0x3 write 0xB11[7:0] @0xB...
Page 328 GD32F5xx User Manual DMA_CHxCTL register is cleared. Switch-buffer mode 14.4.5. Similar to circular mode, switch-buffer mode is also implemented to handle continues peripheral requests. The SBMEN bit in the DMA_CHxCTL register is used to enable/disable the switch-buffer mode. When the switch-buffer mode is enabled, the circular mode is automatically enabled immediately after the channel is enabled.
Page 329 GD32F5xx User Manual the transfer flow.  DMA as transfer flow controller: The CNT bits in the DMA_CHxCNT register determine the number of data items to be transferred. The CNT bits must be configured before the channel is enabled.  Peripheral as transfer flow controller: The CNT bits configured in the DMA_CHxCNT register before the channel is enabled have no meaning and these bits are force to ‘0xFFFF’...
Page 330 GD32F5xx User Manual FIFO data and write to the peripheral.  Memory-to-memory mode: Only the multi-data mode is supported. When the channel is enabled, DMA starts several peripheral transfers to fill up the FIFO. During the transmission, the peripheral transfer is initiated once when there is enough space for it in the FIFO.
Page 331 GD32F5xx User Manual the FIFO is not enough for a burst memory transfer, these data items are transferred in single transaction. If the remaining byte number is less than the memory transfer width, these data items are still written in memory transfer width with MSBs filled with zero. The software can read the CNT bits to calculate the number of valid data items in the memory.
Page 332 GD32F5xx User Manual step can be skipped. Configure the memory and peripheral burst types, the target memory buffer, switch- buffer mode, priority of the channel, memory and peripheral transfer width, memory and peripheral address generation algorithm, circular mode, the transfer flow controller in the DMA_CHxCTL register.
Page 333 GD32F5xx User Manual each interrupt, including full transfer finish interrupt, half transfer finish interrupt, transfer access error interrupt, single-data mode exception interrupt, and FIFO error and exception interrupt. A DMA channel interrupt may be produced when any interrupt event occurs on the channel.
Page 334 GD32F5xx User Manual transfer, the current memory and peripheral is completed and the contents of the FIFO are entirely written into the memory in peripheral-to-memory or memory-to-memory mode. When the full transfer finish flag is asserted and the enabled bit for the full transfer finish interrupt is set, an interrupt is generated.
Page 335 GD32F5xx User Manual Error 14.5.3. FIFO error and transfer access error (including the register access error and bus error) can be detected during the DMA transmission, and the transmission can be stopped when one of the errors occurs. FIFO error For a good DMA operation, when the multi-data mode is enabled, the right and wrong configurations of the FIFO counter critical value corresponding with the memory transfer width and memory burst types are listed in...
Page 336 GD32F5xx User Manual and exception interrupt is set, an interrupt is generated. Figure 14-8. System connection of DMA0 and DMA1 Bus matrix Bus matrix FMC_I FMC_I FMC_D FMC_D SRAM0 SRAM0 AHB1 AHB1 EXMC EXMC DMA0 DMA1 memory port memory port AHB2 AHB2 SRAM1...
Page 337 GD32F5xx User Manual 14.6. Register definition DMA0 base address: 0x4002 6000 DMA1 base address: 0x4002 6400 Interrupt flag register 0 (DMA_INTF0) 14.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIF3 HTFIF3 TAEIF3 SDEIF3...
Page 338 GD32F5xx User Manual 0: FIFO error or exception has not occurred on channel x 1: FIFO error or exception has occurred on channel x Interrupt flag register 1 (DMA_INTF1) 14.6.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIF7 HTFIF7...
Page 339 GD32F5xx User Manual Interrupt flag clear register 0 (DMA_INTC0) 14.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTFIFC3 HTFIFC3 TAEIFC3 SDEIFC3 Reserved FEEIFC3 FTFIFC2 HTFIFC2 TAEIFC2 SDEIFC2 Reserved FEEIFC2 Reserved FTFIFC1 HTFIFC1 TAEIFC1 SDEIFC1 Reserved FEEIFC1 FTFIFC0 HTFIFC0 TAEIFC0 SDEIFC0 Reserved FEEIFC0 Bits Fields...
Page 340 GD32F5xx User Manual Reserved FTFIFC5 HTFIFC5 TAEIFC5 SDEIFC5 Reserved FEEIFC5 FTFIFC4 HTFIFC4 TAEIFC4 SDEIFC4 Reserved FEEIFC4 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. Clear bit for full transfer finish flag of channel x (x=4…7) 27/21/11/5 FTFIFCx 0: No effect 1: Clear full transfer finish flag Clear bit for half transfer finish flag of channel x (x=4…7)
Page 341 GD32F5xx User Manual 31:28 Reserved Must be kept at reset value. 27:25 PERIEN[2:0] Peripheral enable Software set and cleare. 000: Enable peripheral 0 001: Enable peripheral 1 010: Enable peripheral 2 011: Enable peripheral 3 100: Enable peripheral 4 101: Enable peripheral 5 110: Enable peripheral 6 111: Enable peripheral 7 These bits can NOT be written when CHEN is ‘1’.
Page 342 GD32F5xx User Manual 0: Disable switch-buffer mode 1: Enable switch-buffer mode This bit can NOT be written when CHEN is ‘1’. 17:16 PRIO[1:0] Priority level Software set and clear. 00: Low 01: Medium 10: High 11: Ultra high These bits can NOT be written when CHEN is ‘1’. PAIF Peripheral address increment fixed Software set and clear.
Page 343 GD32F5xx User Manual PNAGA Next address generation algorithm of peripheral Software set and clear 0: Fixed address mode 1: Increasing address mode This bit can NOT be written when CHEN is ‘1’. CMEN Circular mode enable Software set and clear. 0: Disable circular mode.
Page 344 GD32F5xx User Manual Software set and clear. 0: Disable single data mode exception interrupt 1: Enable single data mode exception interrupt CHEN Channel enable Software set, hardware clear. 0: Disable channel 1: Enable channel When this bit is asserted, the DMA transfer is started. This bit is automaticly cleared when one of the following situations occurs: When the transfer of channel is fully finished.
Page 345 GD32F5xx User Manual Channel x peripheral base address register (DMA_CHxPADDR) 14.6.7. x = 0...7, where x is a channel number Address offset: 0x18 + 0x18 × x Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). PADDR[31:16] PADDR[15:0] Bits Fields...
Page 346 GD32F5xx User Manual These bits can NOT be written when CHEN in the DMA_CHxCTL register is ‘1’ and MBS in the DMA_CHxCTL register is read as ‘0’. When memory 0 is selected as memory transfer area and MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 347 GD32F5xx User Manual Reserved Reserved FEEIE Reserved FCNT[2:0] MDMEN FCCV[1:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. FEEIE Enable bit for FIFO error and exception interrupt Software set and clear. 0: Disable FIFO error and exception interrupt 1: Enable FIFO error and exception interrupt Reserved Must be kept at reset value.
Page 348 GD32F5xx User Manual When MDMEN is configured to ‘0’, these bits has no meaning.
Page 349 GD32F5xx User Manual Image processing accelerator (IPA) 15.1. Overview The IPA provides a configurable and flexible image format conversion from one or two source image to the destination image, with the following four conversion modes:  Copy one source image to the destination image ...
Page 350 GD32F5xx User Manual  Support interrupt enable and clear 15.3. Block diagram Figure 15-1. IPA block diagram AHB slave interface Configuration Background PCE Background Background Destination PCC control state & counter BG pixel management Destination control ARGB8888 state & counter management Alpha channel ARGB8888...
Page 351 GD32F5xx User Manual register, as listed in the Table 15-1. IPA conversion mode  Copy foreground image to the destination image In this mode, the pixel data in the foreground memory are copied to the destination memory without pixel conversion. So the configured pixel format of the foreground and destination images have no specific meaning.
Page 352 GD32F5xx User Manual Conversion operation 15.4.1. An IPA transaction consists of seven operations: Read pixel data from the foreground memory addressed through the IPA_FMADDR. Retrieve the pixel data from the foreground LUT if the foreground pixel format is indirect. Extend the foreground pixel value to a 32-bit value, and calculate the alpha channel value according to the FAVCA bits in the IPA_FPCTL register Read pixel data from the background memory addressed through the IPA_BMADDR.
Page 353 GD32F5xx User Manual determined by the FLPF or BLPF bit in the IPA_FPCTL or IPA_BPCTL register, as listed in Table 15-2. Foreground and background CLUT pixel format. Table 15-2. Foreground and background CLUT pixel format Memory address BLPF/FLPF LUT pixel format base + 0x3 base + 0x2 base + 0x1...
Page 354 GD32F5xx User Manual Memory address BPF[3:0]/FPF[3:0] Pixel format base + 0x3 base + 0x2 base + 0x1 base + 0x0 0111 AL88 [7:0] [7:0] [7:0] [7:0] 1000 [3:0]L [3:0] [3:0]L [3:0] [3:0]L [3:0] [3:0]L [3:0] 1001 [7:0] [7:0] [7:0] [7:0] 1010 [3:0]A [3:0]...
Page 355 GD32F5xx User Manual Figure 15-4. Pixel extension from ‘ARGB1555’ or ‘ARGB4444’ to ‘ARGB8888’  ARGB1555  ARGB8888 A[0] A[0] A[0] A[0] A[0] A[0] A[0] A[0] A[0] R[4] R[3] R[2] R[1] R[0] R[4] R[3] R[2] R[1] R[0] R[4] R[3] R[2] G[4] G[3] G[2] G[1] G[0] G[4] G[3] G[2] G[1] G[0] G[4] G[3] G[2]...
Page 356 GD32F5xx User Manual Blending 15.4.4. When the IPA operates to convert and blend the foreground and background images to the destination image, the foreground and background pixel data after extending are blended by pair to get a 32-bit pixel value. The alpha channel value is blended on the base of the following equations (A is the foreground alpha value, A...
Page 357 GD32F5xx User Manual to the destination image), the DPF bits have no meaning, and the FPF bits in the IPA_FPCTL register determine the bit number per pixel for both the source and destination. As shown in compression, the destination compression is performed by Figure 15-5.
Page 358 GD32F5xx User Manual is completed, as shown in Figure 15-6. Inter timer operation. Figure 15-6. Inter timer operation ITEN = 1'b1 NCCI = B NCCI = A … … Timer counter cmd 1 cmd 2 cmd 3 AHB cmd 2 request time Line mark 15.4.7.
Page 359 GD32F5xx User Manual Only one of the foreground LUT loading, background LUT loading and IPA transfer can be working at a time. For example, when the IPA transfer is ongoing, setting the FLLEN or BLLEN bit has no effect and the FLLEN and BLLEN bit is automatically reset. Configuration 15.4.9.
Page 360 GD32F5xx User Manual Copy the foreground image to the destination image 1. Configure the IPA_FMADDR and IPA_DMADDR register to set the foreground and destination memory base address. 2. Configure the FPF bits in the IPA_FPCTL register to set the foreground pixel format. 3.
Page 361 GD32F5xx User Manual value calculation algorithm and the foreground pixel format. 3. Configure the foreground pre-defined pixel value, including alpha, red, green and blue value in the IPA_FPCTL and IPA_FPV register if the foreground format is not ARGBxxxx type. 4. Configure the BAVCA and BPF bits in the IPA_BPCTL register to set the background alpha value calculation algorithm and the background pixel format.
Page 362 GD32F5xx User Manual When the IPA transfer is enabled: The FMADDR bits in the IPA_FMADDR register must be 32-bit alignment when the FPF bits in the IPA_FPCTL register are ‘ARGB8888’ and be 16-bit alignment when the FPF bits are ‘RGB565’, ‘ARGB1555’, ‘ARGB4444’ or ‘AL88’ . The FLOFF bits in the IPA_FLOFF register must be even when the FPF bits in the IPA_FPCTL register are ‘A4’...
Page 363 GD32F5xx User Manual Table 15-6. IPA interrupt events Flag bit Enable bit Clear bit Interrupt event IPA_INTF IPA_CTL IPA_INTC wrong configuration interrupt WCFIF WCFIE WCFIFC LUT loading finish interrupt LLFIF LLFIE LLFIFC LUT access conflict interrupt LACIF LACIE LACIFC transfer line mark interrupt TLMIF TLMIE TLMIFC...
Page 364 GD32F5xx User Manual Transfer line mark interrupt The transfer line mark interrupt flag is asserted immediately after the last pixel data of the line mark is written into the destination memory. If the LM bits in the IPA_LM register are equal to 0, the transfer line mark interrupt flag will never be asserted during the IPA transmission.
Page 365 GD32F5xx User Manual Figure 15-7. System connection of IPA Bus matrix FMC_I FMC_D SRAM0 AHB1 EXMC Master port AHB2 Foreground SRAM1 B ackground SRAM2 TCMSRAM ADDSRAM APB1 APB2...
Page 366 GD32F5xx User Manual 15.6. Register definition IPA base address: 0x4002 B000 Control register (IPA_CTL) 15.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved PFCM[1:0] Reserved WCFIE LLFIE LACIE TLMIE FTFIE...
Page 367 GD32F5xx User Manual Software set and clear 0: Disable transfer line mark interrupt 1: Enable transfer line mark interrupt FTFIE Enable bit for full transfer finish interrupt Software set and clear 0: Disable full transfer finish interrupt 1: Enable full transfer finish interrupt TAEIE Enable bit for transfer access error interrupt Software set and clear...
Page 368 GD32F5xx User Manual Interrupt flag register (IPA_INTF) 15.6.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved Reserved WCFIF LLFIF LACIF TLMIF FTFIF TAEIF Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 369 GD32F5xx User Manual Interrupt flag clear register (IPA_INTC) 15.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved Reserved WCFIFC LLFIFC LACIFC TLMIFC FTFIFC TAEIFC rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 370 GD32F5xx User Manual Foreground memory base address register (IPA_FMADDR) 15.6.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). FMADDR[31:16] FMADDR[15:0] Bits Fields Descriptions 31:0 FMADDR[31:0] Foreground memory base address These bits must be aligned to 8-bit, 16-bit or 32-bit corresponding with the foreground pixel format.
Page 371 GD32F5xx User Manual These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. Background memory base address register (IPA_BMADDR) 15.6.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). BMADDR[31:16] BMADDR[15:0] Bits...
Page 372 GD32F5xx User Manual will be detected when the transfer is enable. These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. Foreground pixel control register (IPA_FPCTL) 15.6.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). FPDAV[7:0] Reserved FAVCA[1:0]...
Page 373 GD32F5xx User Manual When this bit is enabled, the foreground LUT loading is started. This bit is automatically cleared when one of the following situations occurs: When the TST bit is enabled When the foreground LUT loading is finished When a wrong configuration or a transfer error is detected When the IPA transfer is ongoing or the background LUT is being loaded (TEN bit in the IPA_CTL register or BLLEN bit in the IPA_BPCTL register is ‘1’).
Page 374 GD32F5xx User Manual 31:24 Reserved Must be kept at reset value. 23:16 FPDRV[7:0] Foreground pre-defined red value Software set and clear When the foreground pixel format is A4 or A8, these bits are used as the foreground red value. These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. 15:8 FPDGV[7:0] Foreground pre-defined green value...
Page 375 GD32F5xx User Manual 01: BPDAV[7:0] is selected as the foreground alpha value 10: BPDAV[7:0] multiplied by the alpha data read from background memory or background LUT divided by 255 is selected as the background alpha value 11: Reserved These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. 15:8 BCNP[7:0] Background LUT number of pixel...
Page 376 GD32F5xx User Manual Background pixel value register (IPA_BPV) 15.6.11. Address offset: 0x28 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved BPDRV[7:0] BPDGV[7:0] BPDBV[7:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:16 BPDRV[7:0] Background pre-defined red value...
Page 377 GD32F5xx User Manual Bits Fields Descriptions 31:0 FLMADDR[31:0] Foreground LUT memory base address Software set and clear The address must be aligned to 8-bit, 16-bit or 32-bit corresponding with the foreground LUT pixel format. If foreground LUT pixel format is ARGB8888, these bits must be 32-bit aligned.
Page 378 GD32F5xx User Manual Reserved DPF[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. DPF[2:0] Destination pixel format Software set and clear 000: ARGB8888 001: RGB888 010: RGB565 011: ARGB1555 100: ARGB4444 101~111: Reserved These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. Destination pixel value register (IPA_DPV) 15.6.15.
Page 379 GD32F5xx User Manual These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. 23:16 DPDRV[7:0] Destination pre-defined red value Software set and clear When IPA is configured to fill up destination memory with specific color, these bits are used as the destination red value.
Page 380 GD32F5xx User Manual 31:16 Meaningless These bit can be set and cleared by software, but these bits have no meaning when the destination pixel format is RGB565. 15:11 DPDRV[4:0] Destination pre-defined red value Software set and clear When IPA is configured to fill up destination memory with specific color, these bits are used as the destination red value.
Page 381 GD32F5xx User Manual When IPA is configured to fill up destination memory with specific color, these bits are used as the destination blue value. These bits can NOT be written when TEN in the IPA_CTL register is ‘1’. When the destination pixel format is ARGB4444, the FIFTH row is valid. Bits Fields Descriptions...
Page 382 GD32F5xx User Manual Bits Fields Descriptions 31:0 DMADDR[31:0] Destination memory base address software set and clear The address must be aligned to 8-bit, 16-bit or 32-bit corresponding with the destination pixel format. If the destination pixel format is ARGB8888, these bits must be 32-bit aligned;...
Page 383 GD32F5xx User Manual HEIGHT[15:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:16 WIDTH[13:0] Width of the image to be processed Software set and clear These bits signify the number of pixels per line. If the foreground or background pixel format is A4 or L4, these bits must be configured to be an even number, otherwise a wrong configuration will be detected when the transfer is enable.
Page 384 GD32F5xx User Manual Inter-timer control register (IPA_ITCTL) 15.6.20. Address offset: 0x4C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word (16-bit) and word (32-bit). Reserved NCCI[7:0] Reserved ITEN Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:8 NCCI[7:0] Number of clock cycles interval...
Page 385 GD32F5xx User Manual Debug (DBG) 16.1. Overview The GD32F5xx series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSight module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the -M33.
Page 386 GD32F5xx User Manual enabled. Table 16-1. Pin assignment Debug interface PA15 JTDI PA14 JTCK/SWCLK PA13 JTMS/SWDIO NJTRST JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware).
Page 387 GD32F5xx User Manual mode, the clock of AHB bus and system clock are provided by CK_IRC16M, and the debugger can debug in standby mode. When exit the standby mode, a system reset generated. When DSLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the Deep- sleep mode, the clock of AHB bus and system clock are provided by CK_IRC16M, and the debugger can debug in Deep-sleep mode.
Page 388 GD32F5xx User Manual 16.5. Register definition DBG base address: 0xE0044000 ID code register (DBG_ID) 16.5.1. Address offset: 0x00 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant. Control register 0 (DBG_CTL0) 16.5.2.
Page 389 GD32F5xx User Manual This bit is set and reset by software 0: no effect 1: At the standby mode, the clock of AHB bus and system clock are provided by CK_IRC16M, a system reset generated when exit standby mode. DSLP_HOLD Deep-sleep mode hold bit This bit is set and reset by software 0: no effect...
Page 390 GD32F5xx User Manual 0: no effect 1: hold the I2C2 SMBUS timeout for debug when core halted. I2C1_HOLD I2C1 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C1 SMBUS timeout for debug when core halted. I2C0_HOLD I2C0 hold bit This bit is set and reset by software...
Page 391 GD32F5xx User Manual 1: hold the TIMER 13 counter for debug when core halted. TIMER12_HOLD TIMER 12 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 12 counter for debug when core halted. TIMER11_HOLD TIMER 11 hold bit This bit is set and reset by software...
Page 392 GD32F5xx User Manual This register has to be accessed by word(32-bit) TIMER10 TIMER9_ TIMER8_ Reserved _HOLD HOLD HOLD TIMER7_ TIMER0_ Reserved HOLD HOLD Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. TIMER10_HOLD TIMER 10 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 10 counter for debug when core halted.
Page 393 GD32F5xx User Manual Control register 3 (DBG_CTL3) 16.5.5. Address offset: 0x10 Reset value: 0x0000 0000; power reset only This register has to be accessed by word(32-bit) Reserved Reserved DEVICEID[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. DEVICEID[3:0] deviceid which connect to CPU instanceid These bits can be written and read by software...
Page 394 GD32F5xx User Manual Programmable current reference (IREF) Overview 17.1. A programmable current reference module is included in the MCU. Two different running modes are supplied for user to use current reference, one mode named Low Power Mode (LPM) and another one named High Current Mode (HCM). The difference between two modes is the current step and maximum current.
Page 395 GD32F5xx User Manual Register definition 17.4. IREF base address: 0x4000 C400 Control register (IREF_CTL) 17.4.1. Address offset: 0x300 Reset value: 0x0000 0F00 This register has to be accessed by word (32-bit) Reserved CREN SSEL Reserved CPT[4:0] SCMOD Reserved CSDT[5:0] timer Fields Descriptions 31:16...
Page 396 GD32F5xx User Manual Analog-to-digital converter (ADC) Overview 18.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels and the battery voltage (V ) channel. The 19 ADC sampling channels all support a variety of operation modes.
Page 397 GD32F5xx User Manual – Analog watchdog event. – Overflow event.  Oversampler. 16-bit data register. – Oversampling ratio adjustable from 2x to 256x. – Programmable data shift up to 8-bit. –  Module supply requirements: 2.6V to 3.6V, and typical power supply voltage is 3.3V. ...
Page 398 GD32F5xx User Manual Function overview 18.4. Figure 18-1. ADC module block diagram Trig select Routine sequence Interrupt Interrupt RVOF Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Routine data registers Over ADC_IN15 SAR ADC 6~12bit （16 bits） sampler SENSE REFINT TOVS...
Page 399 GD32F5xx User Manual Set RSTCLB (optional) Set CLB=1 Wait until CLB=0 ADC clock 18.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller. The maximum frequency is 40MHz. ADC clock can be divided and configured by RCU controller.
Page 400 GD32F5xx User Manual ADC_RDATA register, the EOC will be set. An interrupt will be generated if the EOCIE bit is set. Software procedure for single operation mode of a routine channel: Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset Configure RSQ0 with the analog channel number Configure ADC_SAMPTx register...
Page 401 GD32F5xx User Manual Prepare the Direct memory access controller (DMA) module to transfer data from the ADC_RDATA. Set the SWRCST bit, or generate an external trigger for the routine sequence Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers.
Page 402 GD32F5xx User Manual Discontinuous operation mode The discontinuous operation mode will be enabled when DISRC bit in the ADC_CTL0 register is set. In this mode, the ADC performs a short sequence of n conversions (n does not exceed 8) which is a part of the conversions selected in the ADC_RSQ0~ADC_RSQ2 registers. The value of n is configured by the DISNUM[2:0] bits in the ADC_CTL0 register.
Page 403 GD32F5xx User Manual Data storage mode 18.4.7. The alignment of data stored after conversion can be specified by DAL bit in the ADC_CTL1 register. Figure 18-7. Data storage mode of 12-bit resolution Routine channel data D11 D10 DAL=0 D11 D10 DAL=1 Figure 18-8.
Page 404 GD32F5xx User Manual CK_ADC = 40MHz and sample time is 3 cycles, the total conversion time is “3+12” CK_ADC cycles, that means 0.375us. External trigger configuration 18.4.9. The conversion of routine sequence can be triggered by rising/falling edge of external trigger inputs.
Page 405 GD32F5xx User Manual the DMA will transfer the converted data from the ADC_RDATA register to the destination location which is specified by the user. Overflow detection 18.4.11. Overflow detection is enabled when DMA is enabled or EOCM bit in ADC_CTL1 is set. An overflow event occurs when a routine conversion is done before the prior routine data has been read out.
Page 406 GD32F5xx User Manual for the channel. Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the internal temperature sensor output voltage(V ), and get the temperature temperature with the following equation:...
Page 407 GD32F5xx User Manual On-chip hardware oversampling 18.4.15. The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted, and D (n) is the n-th output digital signal of the ADC: Result=...
Page 408 GD32F5xx User Manual processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 18-12. Numerical example with 5-bits shift and rounding Table 18-6. Maximum output results vs N and M Grayed values indicates truncation gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 409 GD32F5xx User Manual the external trigger must be disabled for ADC1 and ADC2. The converted data of routine channel is stored in the ADC sync routine data register (ADC_SYNCDATA). The following modes can be configured in Table 18-7. ADC sync mode table.
Page 410 GD32F5xx User Manual The ADC sync scheme is shown in Figure 18-13. ADC sync block diagram Figure 18-13. ADC sync block diagram Routine Routine data registers （16 bits） channels ADC2 (slave) Routine Routine data registers （16 bits） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO...
Page 411 GD32F5xx User Manual parallel mode is shown in the Figure 18-14. Routine parallel mode on 16 channels . Figure 18-14. Routine parallel mode on 16 channels · · · ADC0 · · · CH14 CH15 · · · ADC1 · · · ·...
Page 412 GD32F5xx User Manual in continuous operation mode. Figure 18-15. Routine follow-up mode on 1 channel in continuous operation mode · · · ADC0 · · · ADC1 · · · ADC2 Routine trigger EOC(ADC0 ) Sample EOC(ADC1) Convert EOC(ADC2) Note: Make sure to trigger the ADCs when none of them is converting (do not trigger ADC0 when some of the conversions are not finished).
Page 413 GD32F5xx User Manual ADC sync DMA mode 1 In ADC sync DMA mode 1, the bitwidth of DMA transfer is 32. One DMA request transfers two data, which are selected from the routine data of the ADCs in turn. For every request, the source address of the DMA channel should be fixed to the ADC_SYNCDATA register, while the content of the ADC_SYNCDATA changes to the data that is to be transferred.
Page 414 GD32F5xx User Manual Register definition 18.7. ADC0 base address: 0x4001 2000 ADC1 base address: 0x4001 2100 ADC2 base address: 0x4001 2200 Status register (ADC_STAT) 18.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ROVF...
Page 415 GD32F5xx User Manual Cleared by software writing 0 to it or by reading the ADC_RDATA register. Analog watchdog event flag 0: No analog watchdog event 1: Analog watchdog event Set by hardware when the converted voltage crosses the values programmed in the ADC_WDLT and ADC_WDHT registers.
Page 416 GD32F5xx User Manual 0: Discontinuous operation mode disable 1: Discontinuous operation mode enable Reserved Must be kept at reset value. WDSC When in scan mode, analog watchdog is effective on a single channel 0: All channels have analog watchdog function 1: A single channel has analog watchdog function Scan mode 0: Scan operation mode disable...
Page 417 GD32F5xx User Manual . ADC2 analog inputs Channel16, Channel17 and Channel18 are internally connected to V SSA. Control register 1 (ADC_CTL1) 18.7.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SWRCST ETMRC[1:0] ETSRC[3:0] Reserved...
Page 418 GD32F5xx User Manual 1111: EXTI line 11 23:12 Reserved Must be kept at reset value. Data alignment 0: LSB alignment 1: MSB alignment EOCM End of conversion mode 0: Only at the end of a sequence of routine conversions, the EOC bit is set. Overflow detection is disabled unless DMA=1.
Page 419 GD32F5xx User Manual Sample time register 0 (ADC_SAMPT0) 18.7.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SPT18[2:0] SPT17[2:0] SPT16[2:0] SPT15[2:1] SPT15[0] SPT14[2:0] SPT13[2:0] SPT12[2:0] SPT11[2:0] SPT10[2:0] Bits Fields Descriptions 31:27 Reserved Must be kept at reset value 26:24...
Page 420 GD32F5xx User Manual Reserved SPT9[2:0] SPT8[2:0] SPT7[2:0] SPT6[2:0] SPT5[2:1] SPT5[0] SPT4[2:0] SPT3[2:0] SPT2[2:0] SPT1[2:0] SPT0[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:27 SPT9[2:0] refer to SPT0[2:0] description 26:24 SPT8[2:0] refer to SPT0[2:0] description 23:21 SPT7[2:0] refer to SPT0[2:0] description 20:18 SPT6[2:0]...
Page 421 GD32F5xx User Manual Reserved WDHT[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDHT[11:0] High threshold for analog watchdog These bits define the high threshold for the analog watchdog. Watchdog low threshold register (ADC_WDLT) 18.7.7. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 422 GD32F5xx User Manual The total number of conversion in routine sequence equals to RL[3:0]+1. 19:15 RSQ15[4:0] refer to RSQ0[4:0] description 14:10 RSQ14[4:0] refer to RSQ0[4:0] description RSQ13[4:0] refer to RSQ0[4:0] description RSQ12[4:0] refer to RSQ0[4:0] description Routine sequence register 1 (ADC_RSQ1) 18.7.9.
Page 423 GD32F5xx User Manual RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ5[4:0] refer to RSQ0[4:0] description 24:20 RSQ4[4:0] refer to RSQ0[4:0] description 19:15 RSQ3[4:0] refer to RSQ0[4:0] description 14:10 RSQ2[4:0] refer to RSQ0[4:0] description RSQ1[4:0] refer to RSQ0[4:0] description RSQ0[4:0]...
Page 424 GD32F5xx User Manual Reserved TOVS OVSS[3:0] OVSR[2:0] Reserved OVSEN Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio(OVSR[2:0]).
Page 425 GD32F5xx User Manual OVSEN Oversampler Enable This bit is set and cleared by software. 0: Oversampler disabled 1: Oversampler enabled Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress). Summary status register (ADC_SSTAT) 18.7.13.
Page 426 GD32F5xx User Manual ROVF0 This bit is the mirror image of the ROVF bit of ADC0 STRC0 This bit is the mirror image of the STRC bit of ADC0 Reserved Must be kept at reset value. EOC0 This bit is the mirror image of the EOC bit of ADC0 WDE0 This bit is the mirror image of the WDE bit of ADC0 Sync control register (ADC_SYNCCTL)
Page 427 GD32F5xx User Manual 3'b111:HCLK div20. 15:14 SYNCDMA[1:0] ADC sync DMA mode selection 00: ADC sync DMA disabled 01: ADC sync DMA mode 0 10: ADC sync DMA mode 1 11: reserved SYNCDDM ADC sync DMA disable mode This bit configures the DMA disable mode for ADC sync mode 0: The DMA engine is disabled after the end of transfer signal from DMA controller is detected.
Page 428 GD32F5xx User Manual SYNCDATA0[15:0] Bits Fields Descriptions 31:16 SYNCDATA1[15:0] Routine data2 in ADC sync mode 15:0 SYNCDATA0[15:0] Routine data1 in ADC sync mode...
Page 429 GD32F5xx User Manual Digital-to-analog converter (DAC) Overview 19.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 430 GD32F5xx User Manual Figure 19-1. DAC block diagram DAC control register DBOFFx EXTI_9 TIMERx_ TRGO SWTRx DAC_ENx buff Control logic Wave OUTx_DH OUTx_DO (optional) 12-bit 12-bit 12-bit 12-bit Table 19-1. DAC I/O description Name Description Signal type Analog power supply Input, analog supply Ground for analog power supply Input, analog supply ground...
Page 431 GD32F5xx User Manual Note: The GPIO pins should be configured to analog mode before enable the DAC module. Function overview 19.3. DAC enable 19.3.1. The DAC can be turned on by setting the DENx bit in the DAC_CTL0 register. A t time WAKEUP is needed to startup the analog DAC submodule.
Page 432 GD32F5xx User Manual generated by setting the SWTRx bits in the DAC_SWT register. DAC conversion 19.3.5. If the external trigger is enabled by setting the DTENx bit in DAC_CTL0 register, the DAC holding data is transferred to the DAC output data (DAC_OUTx_DO) register when the selected trigger event happened.
Page 433 GD32F5xx User Manual Figure 19-3. DAC triangle noise wave (2<<DWBWx)-1 DACx_OUTy_DH value DAC output voltage 19.3.7. The following equation determines the analog output voltage on the DAC pin. *OUTx_DO/4096 (19-1) DAC_OUT REFP The digital input is linearly converted to an analog output voltage and its range is 0 to V REFP.
Page 434 GD32F5xx User Manual on the application scenario.
Page 435 GD32F5xx User Manual Register definition 19.4. DAC0 base address: 0x4000 7400 DACx control register 0 (DAC_CTL0) 19.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DDUDR DDMA Reserved DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 DDUDR...
Page 436 GD32F5xx User Manual 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 23:22 DWM1[1:0] DACx_OUT1 noise wave mode These bits specify the mode selection of the noise wave signal of DACx_OUT1 when external trigger of DACx_OUT1 is enabled (DTEN1=1).
Page 437 GD32F5xx User Manual indicate that unmask LFSR bit [n-1, 0] in LFSR noise mode or the amplitude of the triangle is ((2<<(n-1))-1) in triangle noise mode, where n is the bit width of wave. 0000: The bit width of the wave signal is 1 0001: The bit width of the wave signal is 2 0010: The bit width of the wave signal is 3 0011: The bit width of the wave signal is 4...
Page 438 GD32F5xx User Manual 1: DACx_OUT0 enabled DACx software trigger register (DAC_SWT) 19.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved SWTR1 SWTR0 Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DACx_OUT1 software trigger, cleared by hardware.
Page 439 GD32F5xx User Manual 11:0 OUT0_DH[11:0] DACx_OUT0 12-bit right-aligned data. These bits specify the data that is to be converted by DACx_OUT0. DACx_OUT0 12-bit left-aligned data holding register 19.4.4. (DAC_OUT0_L12DH) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved OUT0_DH[11:0] Reserved...
Page 440 GD32F5xx User Manual DACx_OUT1 12-bit right-aligned data holding register 19.4.6. (DAC_OUT1_R12DH) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT1_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 OUT1_DH[11:0] DACx_OUT1 12-bit right-aligned data.
Page 441 GD32F5xx User Manual DACx_OUT1 8-bit right-aligned data holding register (DAC_OUT1_R8DH) 19.4.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT1_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. OUT1_DH[7:0] DACx_OUT1 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT1.
Page 442 GD32F5xx User Manual DACx concurrent mode 12-bit left-aligned data holding register 19.4.10. (DACC_L12DH) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) OUT1_DH[11:0] Reserved OUT0_DH[11:0] Reserved Bits Fields Descriptions 31:20 OUT1_DH[11:0] DACx_OUT1 12-bit left-aligned data These bits specify the data that is to be converted by DACx_OUT1.
Page 443 GD32F5xx User Manual OUT0_DH[7:0] DACx_OUT0 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT0. DACx_OUT0 data output register (DAC_OUT0_DO) 19.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DO [11:0]...
Page 444 GD32F5xx User Manual DACx status register 0 (DAC_STAT0) 19.4.14. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved DDUDR1 Reserved rc_w1 Reserved DDUDR0 Reserved rc_w1 Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DDUDR1 DACx_OUT1 DMA underrun flag.
Page 445 GD32F5xx User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 446 GD32F5xx User Manual Figure 20-1. Free watchdog timer block diagram The free watchdog timer is enabled by writing the value 0xCCCC to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value 0x000, there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at anytime.
Page 447 GD32F5xx User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[3:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 128 0101 16380.0 1 / 256 0110 32760.0 0111 65520.0 1024 1000 131040.0 2048 1001 262080.0 4096 1010 524160.0 8192 1011 1048320.0 16384 1100 2096640.0 32768...
Page 448 GD32F5xx User Manual Register definition 20.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 449 GD32F5xx User Manual 0000: 1 / 4 0001: 1 / 8 0010: 1 / 16 0011: 1 / 32 0100: 1 / 64 …… 1100: 1 / 16384 1101~1111: 1 / 32768 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 450 GD32F5xx User Manual Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid. This bit is reset by hardware after the update operation of FWDGT_RLD register.
Page 451 GD32F5xx User Manual 20.2. Window watchdog timer (WWDGT) Overview 20.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 452 GD32F5xx User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F, (it implies that the CNT[6] bit should be set).
Page 453 GD32F5xx User Manual Table 20-2. Min / max timeout value at 50 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[4:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 1 / 1 00000 0.082 ms 5.243 ms 1 / 2 00001 0.164 ms 10.486 ms 1 / 4 00010...
Page 454 GD32F5xx User Manual Register definition 20.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 455 GD32F5xx User Manual value PSC[1:0]. PSC[4:0] is the time base of the watchdog counter: 00000: (PCLK1 / 4096) / 1 00001: (PCLK1 / 4096) / 2 00010: (PCLK1 / 4096) / 4 00011: (PCLK1 / 4096) / 8 …… 10001: (PCLK1 / 4096) / 131072 10010: (PCLK1 / 4096) / 262144 10100~11111: Reserved EWIE...
Page 456 GD32F5xx User Manual Real time clock (RTC) 21.1. Overview The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. Working in power saving mode and smart wakeup is software configurable.
Page 457 GD32F5xx User Manual 21.3. Function overview Block diagram 21.3.1. Figure 21-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre (Default 1 Hz) IRC32K 15-bit...
Page 458 GD32F5xx User Manual Clock source and prescalers 21.3.2. RTC unit has three independent clock sources: LXTAL, IRC32K and HXTAL with divided by 2~31(configured in RCU_CFG register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions.
Page 459 GD32F5xx User Manual If a field is masked, the field is considered as matched in logic. If all the fields have been masked, the Alarm Flag will assert 3 RTC clock later after ALRMxEN is set. Configurable periodic auto-wakeup counter 21.3.5.
Page 460 GD32F5xx User Manual RTC_TIME, RTC_DATE, RTC_CTL, RTC_STAT, RTC_PSC, RTC_WUT, RTC_COSC, RTC_ALRM0TD, RTC_ALRM1TD, RTC_SHIFTCTL, RTC_HRFC, RTC_ALRM0SS, RTC_ALRM1SS. Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps: Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register.
Page 461 GD32F5xx User Manual be equal to or greater than 7 times the RTC clock frequency.APB1 bus clock frequency lower than RTC clock frequency is not allowed in any case whatever happens. When APB1 bus clock frequency is not equal to or greater than 7 times the RTC clock frequency, the calendar reading flow should be obeyed: reading calendar time register and date register twice if the two values are equal, the value can be seen as the correct value...
Page 462 GD32F5xx User Manual reading operation as this: read all calendar registers continuously, if the last two values are the same, the data is coherent and correct. Resetting the RTC 21.3.8. There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT.
Page 463 GD32F5xx User Manual After writing RTC_SHIFTCTL register, the SOPF bit in RTC_STAT will be set at once. When shift operation is complete, SOPF bit is cleared by hardware. System reset does not affect SOPF bit. Shift operation only works correctly when REFEN=0. Software must not write to RTC_SHIFTCTL if REFEN=1.
Page 464 GD32F5xx User Manual Coarse digital calibration can be used to add or mask ck_apre clock cycles at the output of the asynchronous prescaler. When COSD=0, 2 ck_apre cycles are added every minute for the first 2xCOSS minutes. The effect of such configuration will make calendar to be updated sooner. When COSD=1, 1 ck_apre cycle is removed every minute for the first 2xCOSS minutes.
Page 465 GD32F5xx User Manual reduced by up to 487.1PPM. To increase the RTC frequency the FREQI bit can be set. If FREQI bit is set, there will be 512 additional cycles to be added during period time which means every 211/210/29(32/16/8 seconds) RTC clock insert one cycle.
Page 466 GD32F5xx User Manual the measure is within 0.477PPM (0.5 RTCCLK cycles over 32s)  When the calibration period is 16 seconds(by setting CWND16 bit) In this configuration, CMSK[0] is fixed to 0 by hardware. Using exactly 16s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 0.954PPM (0.5 RTCCLK cycles over 16s) ...
Page 467 GD32F5xx User Manual These registers are only reset by detected tamper event and backup domain reset. Tamper detection function initialization RTC tamper detection function can be independently enabled on tamper input pin by setting corresponding TPxEN bit. Tamper detection configuration is set before enable TPxEN bit. When the tamper event is detected, the corresponding flag (TPxF) will assert.
Page 468 GD32F5xx User Manual Calibration clock output 21.3.15. Calibration clock can be output on the PC13 if COEN bit is set to 1. When the COS bit is set to 0(this is default) and asynchronous prescaler is set to 0x7F(FACTOR_A), the frequency of RTC_CALIB is frtcclk/64.When the RTCCLK is 32.768KHz, RTC_CALIB output is corresponding to 512Hz.It’s recommend to using rising edge of RTC_CALIB output for there may be a light jitter on falling edge.
Page 469 GD32F5xx User Manual Table 21-2 RTC interrupts control Exit Exit Deep- Exit Interrupt Event flag Control Bit Sleep sleep Standby Alarm 0 ALRM0F ALRM0IE Y(*) Y(*) Alarm 1 ALRM1F ALRM1IE Y(*) Y(*) Wakeup WTIE Y(*) Y(*) Timestamp TSIE Y(*) Y(*) Tamper 0 TP0F TPIE...
Page 470 GD32F5xx User Manual 21.4. Register definition RTC base address: 0x4000 2800 Time register (RTC_TIME) 21.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state This register has to be accessed by word (32-bit) Reserved HRT[1:0]...
Page 471 GD32F5xx User Manual This register has to be accessed by word (32-bit) Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0]...
Page 472 GD32F5xx User Manual 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output 0x2: Enable alarm1 flag output 0x3: Enable wakeup flag output OPOL Output polarity This bit is used to invert output RTC_ALARM...
Page 473 GD32F5xx User Manual 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function WTEN Auto-wakeup timer function enable 0: Disable function 1: Enable function ALRM1EN Alarm-1 function enable 0: Disable alarm function 1: Enable alarm function ALRM0EN Alarm-0 function enable 0: Disable alarm function...
Page 474 GD32F5xx User Manual 0x3:RTC Clock divided by 2 0x4:0x5: ck_spre (default 1Hz) clock 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. Status register (RTC_STAT) 21.4.4. Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0. Others are not affected Backup domain reset value: 0x0000 0007 This register is writing protected except RTC_STAT[14:8].
Page 475 GD32F5xx User Manual Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0. This flag must be cleared at least 1.5 RTC Clock periods before WTF is set to 1 again. ALRM1F Alarm-1 occurs flag Set to 1 by hardware when current time/date matches the time/date of alarm 1 setting value.
Page 476 GD32F5xx User Manual ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset. 0: Alarm registers programming is not allowed 1: Alarm registers programming is allowed ALRM0WF Alarm 0 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM0EN bit has reset.
Page 477 GD32F5xx User Manual WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits. Note: This configure case is forbidden: WTRV=0x0000 with WTCS[2:0]=0b011. This register can be written only when WTWF=1.
Page 478 GD32F5xx User Manual 0x02:-4 PPM(approximate value) … 0x1F:-63 PPM(approximate value) Alarm 0 time and date register (RTC_ALRM0TD) 21.4.8. Address offset: 0x1C System reset: not effect Backup domain reset value: 0x0000 0000 This register is write protected and can only be written in initialization state This register has to be accessed by word (32-bit) MSKD DOWS...
Page 479 GD32F5xx User Manual 14:12 MNT[2:0] Minutes tens in BCD code 11:8 MNU[3:0] Minutes units in BCD code MSKS Alarm second mask bit 0: Not mask second field 1: Mask second field SCT[2:0] Second tens in BCD code SCU[3:0] Second units in BCD code Alarm 1 time and date register (RTC_ALRM1TD) 21.4.9.
Page 480 GD32F5xx User Manual 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit 0: Not mask minutes field 1: Mask minutes field 14:12 MNT[2:0] Minutes tens in BCD code 11:8 MNU[3:0] Minutes units in BCD code MSKS Alarm second mask bit 0: Not mask second field 1: Mask second field SCT[2:0]...
Page 481 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler. Second fraction value is calculated by the below formula: Second fraction = ( FACTOR_S - SSC ) / ( FACTOR_S + 1 ) Shift function control register (RTC_SHIFTCTL) 21.4.12.
Page 482 GD32F5xx User Manual This register will record the calendar time when TSF is set to 1. Reset TSF bit will also clear this register. This register has to be accessed by word (32-bit) Reserved HRT[1:0] HRU[3:0] Reserved MNT[2:0] MNU[3:0] Reserved SCT[2:0] SCU[3:0] Bits...
Page 483 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:13 DOW[2:0] Days of the week MONT Month tens in BCD code 11:8 MONU[3:0] Month units in BCD code Reserved Must be kept at reset value. DAYT[1:0] Day tens in BCD code DAYU[3:0]...
Page 484 GD32F5xx User Manual FREQI CWND8 CWND16 Reserved CMSK[8:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. FREQI Increase RTC frequency by 488.5PPM 0: No effect 1: One RTCCLK pulse is inserted every 2 pulses. This bit should be used in conjunction with CMSK bit. If the input clock frequency is 32.768KHz, the number of RTCCLK pulses added during 32s calibration window is (512 * FREQI) - CMSK CWND8...
Page 485 GD32F5xx User Manual RTC_ALARM Output Type 0: Open-drain output type 1: Push-pull output type TSSEL Timestamp input selection: 0: Timestamp function input from PC13 1: Timestamp function input from PI8 TP0SEL Tamper 0 function input selection 0: Tamper 0 function input from PC13 1: Tamper 0 function input from PI8.
Page 486 GD32F5xx User Manual 0:No effect 1:TSF is set when tamper event detected even TSEN=0 Reserved Must be kept at reset value. TP1EG Tamper 1 event trigger edge If tamper detection is in edge mode(FLT =0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event If tamper detection is in level mode(FLT !=0): 0: Low level triggers a tamper detection event...
Page 487 GD32F5xx User Manual Reserved SSC[14:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched. 0x1: SSC[0] is to be compared and all others are ignored 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored...
Page 488 GD32F5xx User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched. 0x1: SSC[0] is to be compared and all others are ignored 0x2: SSC[1:0] is to be compared and all others are ignored 0x3: SSC[2:0] is to be compared and all others are ignored...
Page 489 GD32F5xx User Manual in power saving mode because they can powered-on by VBAT. Tamper detection flag TPxF assertion will reset these registers.
Page 490 GD32F5xx User Manual Timer (TIMERx) Table 22-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0 / 7 TIMER1~4 TIMER8 / 11 TIMER9 / 10 / 12 / 13 TIMER5 / 6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit...
Page 491 GD32F5xx User Manual Only update events will generate DMA request. Note that TIMER5/6 do not have DMA configuration registers. 22.1. Advanced timer (TIMERx, x=0, 7) Overview 22.1.1. The advanced timer module (Timer0&Timer7) is a four-channel timer that supports both input capture and output compare.
Page 492 GD32F5xx User Manual Function overview 22.1.3. Block diagram provides details of the internal configuration of Figure 22-1. Advanced timer block diagram the advanced timer. Figure 22-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0...
Page 493 GD32F5xx User Manual Figure 22-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 494 GD32F5xx User Manual Figure 22-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 495 GD32F5xx User Manual counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Figure 22-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear...
Page 496 GD32F5xx User Manual Figure 22-5. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 497 GD32F5xx User Manual counter behavior in different clock frequencies when TIMERx_CAR=0x99. Figure 22-6. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF)
Page 498 GD32F5xx User Manual Figure 22-7. Timing chart of down counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF)
Page 499 GD32F5xx User Manual behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 22-8. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured...
Page 500 GD32F5xx User Manual of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow.
Page 501 GD32F5xx User Manual Figure 22-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 502 GD32F5xx User Manual Figure 22-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Prescaler Register Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 503 GD32F5xx User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: if you want to generate an Interrupt or DMA request, you can set CHxG by software directly.
Page 504 GD32F5xx User Manual Figure 22-13. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 505 GD32F5xx User Manual Figure 22-14. EAPWM timechart Figure 22-15. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Composite PWM mode In the Composite PWM mode (CHxCPWMEN = 1’b1, CHxMS[2:0] = 3’b000 and CHxCOMCTL = 4’b0110 or 4’b0111), the PWM signal output in channel x (x=0..3) is composited by CHxVAL and CHxCOMVAL_ADD bits.
Page 506 GD32F5xx User Manual The PWM period is determined by (CARL + 0x0001) and the PWM pulse width is determined by the following table. Table 22-2.The Composite PWM pulse width Condition Mode PWM pulse width (CARL + 0x0001) + PWM mode 0 CHxVAL <...
Page 507 GD32F5xx User Manual Figure 22-16. Channel x output PWM with (CHxVAL < CHxCOMVAL_ADD) CARL CHxCOMVAL_ ADD=CARL CHxCOMVAL_ CHxVAL CHxVAL PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF...
Page 508 GD32F5xx User Manual CARL CHxVAL = CARL CHxVAL CHxCOMVAL_ADD CHxCOMVAL_ADD PWM MODE 1 PWM MODE 1 OxCPRE OxCPRE PWM MODE 0 PWM MODE 0 OxCPRE OxCPRE Interrupt signal Interrupt signal CHxIF CHxIF CHxCOMADDIF CHxCOMADDIF CARL CHxVAL CHxCOMVAL_ADD = 0 PWM MODE 1 OxCPRE PWM MODE 0 OxCPRE...
Page 509 GD32F5xx User Manual next counter next counter period period If more than one channels are configured in composite PWM mode, it is possible to fix an offset for the channel x match edge of each pair with respect to other channels. This behavior is useful in the generation of lighting PWM control signals where it is desirable that edges are not coincident with each other pair to help eliminate noise generation.
Page 510 GD32F5xx User Manual 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 511 GD32F5xx User Manual Table 22-3. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 512 GD32F5xx User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels.
Page 513 GD32F5xx User Manual HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 514 GD32F5xx User Manual 0 and the counter-period value. Therefore, TIMERx_CAR register must be configured before the counter starts to count. Table 22-4. Counting direction in different quadrature decoder mode CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling Quadrature decoder mode 0 CI1FE1=1 Down SMC[2:0]=3’b000...
Page 515 GD32F5xx User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. show how to connect. And we can see Figure 22-26. Hall sensor is used to BLDC motor we need two timers. First TIMER_in (Advanced/GeneralL0 TIMER) should accept three HALL sensor signals.
Page 516 GD32F5xx User Manual Figure 22-27. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 517 GD32F5xx User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection 3'b110 (event 100: CI0F_ED If you choose the ETIF, For the ETIF, configure mode) 101: CI0FE0 configure the ETP for Filter by ETFC and 110: CI1FE1 polarity selection and Prescaler by ETPSC.
Page 518 GD32F5xx User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection trigger input. Figure 22-30. Event mode TIMER_CK ETIFP CNT_REG TRGIF Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0.
Page 519 GD32F5xx User Manual example. Figure 22-31. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG OxCPRE Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt.
Page 520 GD32F5xx User Manual Figure 22-32. Timer0 master/slave mode timer example TRGS TIMER0 TIMER 4 Master ITI0 TRGO Prescaler Counter mode control TIMER 1 Master TRGO ITI1 Prescaler Counter mode control TIMER 2 Master ITI2 TRGO Prescaler Counter mode control Trigger selection TIMER 3 Master...
Page 521 GD32F5xx User Manual in Master/Slave mode. Do as follow: 1. Configure Timer2 slave mode to get the input trigger from CI0 (TRGS=3’b100 in the TIMER2_SMCFG register). 2. Configure Timer2 in event mode (SMC=3’b110 in the TIMER2_SMCFG register). 3. Configure the Timer2 in Master/Slave mode by writing MSM=1 (TIMER2_SMCFG register).
Page 522 GD32F5xx User Manual TIMERx_DMATB is only a buffer; timer will map the TIMERx_DMATB to an internal register, appointed by the field of DMATA in TIMERx_DMACFG . If the field of DMATC in TIMERx_DMACFG is 0(1 transfer), then the timer’s DMA request is finished. While if TIMERx_DMATC is not 0, such as 3( 4 transfers), then timer will send 3 more requests to DMA, and DMA will access timer’s registers DMATA+0x4, DMATA+0x8, DMATA+0xc at the next 3 accesses to TIMERx_DMATB.
Page 523 GD32F5xx User Manual Register definition 22.1.4. TIMER0 base address: 0x4001 0000 TIMER7 base address: 0x4001 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 524 GD32F5xx User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or decoder mode, this bit is read only. Single pulse mode.
Page 525 GD32F5xx User Manual Reserved ISO3N ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ISO3N Idle state of channel 3 complementary output Refer to ISO0N bit ISO3 Idle state of channel 3 output Refer to ISO0 bit...
Page 526 GD32F5xx User Manual Master timer generate a reset the UPG bit in the TIMERx_SWEVG register is set 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output.
Page 527 GD32F5xx User Manual This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 528 GD32F5xx User Manual EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 529 GD32F5xx User Manual 010: Quadrature decoder mode 1.The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level. 011: Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other. 100: Restart mode.
Page 530 GD32F5xx User Manual Note: This bit just used in composite PWM mode. 27:15 Reserved Must be kept at reset value. TRGDEN Trigger DMA request enable 0: Disabled 1: Enabled CMTDEN Commutation DMA request enable 0: Disabled 1: Enabled CH3DEN Channel 3 capture/compare DMA request enable 0: Disabled 1: Enabled CH2DEN...
Page 531 GD32F5xx User Manual 0: Disabled 1: Enabled CH1IE Channel 1 capture/compare interrupt enable 0: Disabled 1: Enabled CH0IE Channel 0 capture/compare interrupt enable 0: Disabled 1: Enabled UPIE Update interrupt enable 0: Disabled 1: Enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 532 GD32F5xx User Manual 27:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag Refer to CH0OF description CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a...
Page 533 GD32F5xx User Manual This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs. If Channel0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 534 GD32F5xx User Manual 27:8 Reserved Must be kept at reset value. BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 535 GD32F5xx User Manual at the same time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CH1COM CH0COM Reserved Reserved...
Page 536 GD32F5xx User Manual Refer to CH0COMSEN description CH1COMFEN Channel 1 output compare fast enable Refer to CH0COMFEN description CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset).
Page 537 GD32F5xx User Manual details. If configured in PWM mode, the O0CPRE level changes only when the output compare mode is adjusted from “Timing” mode to “PWM” mode or the comparison result changes. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00(COMPARE MODE).
Page 538 GD32F5xx User Manual Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal.
Page 539 GD32F5xx User Manual This register has to be accessed by word (32-bit). CH3COM CH2COM Reserved Reserved ADDSEN ADDSEN Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 540 GD32F5xx User Manual 01: Channel 3 is programmed as input mode, IS3 is connected to CI3FE3 10: Channel 3 is programmed as input mode, IS3 is connected to CI2FE3 11: Channel 3 is programmed as input mode, IS3 is connected to ITS. Note: When CH3MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 541 GD32F5xx User Manual When this bit is set, the shadow register of TIMERx_CH2CV register, which updates at each update event will be enabled. 0: Channel 2 output compare shadow disable 1: Channel 2 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00.
Page 542 GD32F5xx User Manual Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH2CAPFLT [3:0] Times...
Page 543 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3NP Channel 3 complementary output polarity Refer to CH0NP description CH3NEN Channel 3 complementary output enable Refer to CH0NEN description CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable...
Page 544 GD32F5xx User Manual 11 or 10. CH0NEN Channel 0 complementary output enable When channel 0 is configured in output mode, setting this bit enables the complementary output in channel0. 0: Channel 0 complementary output disabled 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal...
Page 545 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 546 GD32F5xx User Manual This bit-filed specifies the auto reload value of the counter. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 547 GD32F5xx User Manual shadow register updates every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1...
Page 548 GD32F5xx User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Channel 3 capture/compare value register (TIMERx_CH3CV) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3VAL[15:0] Bits...
Page 549 GD32F5xx User Manual - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input (asynchronous).
Page 550 GD32F5xx User Manual 1: “off-state” enabled. No matter the CHxEN/CHxNEN bits, the channels are “off- state”. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. PROT[1:0] Complementary register protect control This bit-filed specifies the write protection property of registers. 00: protect disable.
Page 551 GD32F5xx User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value.
Page 552 GD32F5xx User Manual CH0COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0COMVAL_ADD Additional compare value of channel 0 [15:0] When channel 0 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 553 GD32F5xx User Manual CH2COMVAL_ADD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2COMVAL_ADD Additional compare value of channel 2 [15:0] When channel 2 is configured in output mode, this bit-field contains value to be compared to the counter. When the corresponding shadow register is enabled, the shadow register updates by every update event.
Page 554 GD32F5xx User Manual Reserved Bits Fields Descriptions CH3CPWMEN Channel 3 composite PWM mode enable 0: Disabled 1: Enabled CH2CPWMEN Channel 2 composite PWM mode enable 0: Disabled 1: Enabled CH1CPWMEN Channel 1 composite PWM mode enable 0: Disabled 1: Enabled CH0CPWMEN Channel 0 composite PWM mode enable 0: Disabled...
Page 555 GD32F5xx User Manual This bit-field set and reset by software 1: If POEN and IOS is 0, the output disabled 0: No effect...
Page 556 GD32F5xx User Manual 22.2. General level0 timer (TIMERx, x=1, 2, 3, 4) Overview 22.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 557 GD32F5xx User Manual Figure 22-34. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection Trigger Selector&Counter TIMER_CK DMA REQ/ACK ETIFP...
Page 558 GD32F5xx User Manual Figure 22-35. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111(external clock mode 0). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 559 GD32F5xx User Manual Figure 22-36. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 560 GD32F5xx User Manual Figure 22-37. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 561 GD32F5xx User Manual Figure 22-38. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 562 GD32F5xx User Manual Figure 22-39. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 22-40.
Page 563 GD32F5xx User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting mode and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 564 GD32F5xx User Manual Figure 22-41. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Input capture and output compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 565 GD32F5xx User Manual Figure 22-42. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Prescaler Register Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 566 GD32F5xx User Manual TIMERx_DMAINTEN. Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 567 GD32F5xx User Manual Figure 22-43. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 568 GD32F5xx User Manual Figure 22-44. EAPWM timechart Figure 22-45. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 569 GD32F5xx User Manual is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content. With regard to a more detail description refer to the relative bit definition.
Page 570 GD32F5xx User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection rising trigger input. Figure 22-46. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Pause mode TI0S=0(Non-xor) TRGS[2:0]=3’b1 The counter can [CH0NP==0, CH0P==0] Filter is bypass in this be paused when no inverted.
Page 571 GD32F5xx User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 22-48. Event mode TIMER_CK ETIFP CNT_REG TRGIF Single pulse mode Single pulse mode. Refer to Timers interconnection Refer to Advanced timer (TIMERx, x=0, 7) Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module.
Page 572 GD32F5xx User Manual Register definition 22.2.4. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0]...
Page 573 GD32F5xx User Manual 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down...
Page 574 GD32F5xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 575 GD32F5xx User Manual Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved...
Page 576 GD32F5xx User Manual The external trigger can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 577 GD32F5xx User Manual These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 578 GD32F5xx User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 579 GD32F5xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value.
Page 580 GD32F5xx User Manual This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs. If Channel0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV.
Page 581 GD32F5xx User Manual This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 582 GD32F5xx User Manual CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 583 GD32F5xx User Manual 0: Channel 0 output compare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 584 GD32F5xx User Manual CH2CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear.
Page 585 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable...
Page 586 GD32F5xx User Manual 101: Force high. O2CPRE is forced to high level. 110: PWM mode 0. When counting up, O2CPRE is high when the counter is smaller than TIMERx_CH2CV, and low otherwise. When counting down, O2CPRE is low when the counter is larger than TIMERx_CH2CV, and high otherwise. 111: PWM mode 1.
Page 587 GD32F5xx User Manual Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability.
Page 588 GD32F5xx User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions...
Page 589 GD32F5xx User Manual 11 or 10. Reserved Must be kept at reset value. CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 590 GD32F5xx User Manual 15:0 CNT[31:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Counter register (TIMERx_CNT) (x=2, 3) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CNT[15:0] Bits...
Page 591 GD32F5xx User Manual Counter auto reload register (TIMERx_CAR) (x=1, 4) Address offset: 0x2C Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). CARL[31:16] CARL[15:0] Bits Fields Descriptions 31:0 CARL[31:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter auto reload register (TIMERx_CAR) (x=2, 3) Address offset: 0x2C Reset value: 0x0000 FFFF...
Page 592 GD32F5xx User Manual CH0VAL[15:0] Bits Fields Descriptions 31:0 CH0VAL[31:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 593 GD32F5xx User Manual CH1VAL[15:0] Bits Fields Descriptions 31:0 CH1VAL[31:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 594 GD32F5xx User Manual CH2VAL[15:0] Bits Fields Descriptions 31:0 CH2VAL[31:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 595 GD32F5xx User Manual CH3VAL[15:0] Bits Fields Descriptions 31:0 CH3VAL[31:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 596 GD32F5xx User Manual Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value.
Page 597 GD32F5xx User Manual Reserved Reserved ITI1_RMP Reserved Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:10 ITI1_RMP Internal trigger input1 remap 00:TIMER7_TRGO 01:Ethernet PTP 10:USB FS SOF 11:USB HS SOF Reserved Must be kept at reset value. Input remap register (TIMERx_IRMP) (x=4) Address offset: 0x50 Reset value: 0x0000 0000...
Page 598 GD32F5xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 599 GD32F5xx User Manual 22.3. General level1 timer (TIMERx, x=8, 11) Overview 22.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 600 GD32F5xx User Manual Function overview 22.3.3. Block diagram provides details on the internal Figure 22-49. General level1 timer block diagram configuration of the general level1 timer. Figure 22-49. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0...
Page 601 GD32F5xx User Manual Figure 22-50. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 602 GD32F5xx User Manual Figure 22-51. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 603 GD32F5xx User Manual Figure 22-52. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 22-53.
Page 604 GD32F5xx User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 605 GD32F5xx User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 606 GD32F5xx User Manual Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN. The timechart below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 22-55.
Page 607 GD32F5xx User Manual Figure 22-56. EAPWM timechart Figure 22-57. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 608 GD32F5xx User Manual setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 609 GD32F5xx User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 22-58. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Pause mode TI0S=0(Non-xor) TRGS[2:0]=3’b1 The counter can [CH0NP==0, CH0P==0] Filter is bypass in this be paused when no inverted.
Page 610 GD32F5xx User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 22-60. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 611 GD32F5xx User Manual Figure 22-61. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG OxCPRE Timers interconnection Refer to Advanced timer (TIMERx, x=0, 7) Timer debug mode When the Cortex ® -M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL2 register set to 1, the TIMERx counter stops.
Page 612 GD32F5xx User Manual Register definition 22.3.4. TIMER8 base address: 0x4001 4000 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits...
Page 613 GD32F5xx User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 614 GD32F5xx User Manual synchronize the counter. 000: ITI0 001: ITI1 010: ITI2 011: ITI3 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode.
Page 615 GD32F5xx User Manual 1: enabled Reserved Must be kept at reset value. CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000...
Page 616 GD32F5xx User Manual trigger input can generates a trigger event. 0: No trigger event occurred. 1: Trigger interrupt occurred. Reserved Must be kept at reset value. Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software.
Page 617 GD32F5xx User Manual Channel 1’s capture or compare event generation CH1G Refer to CH0G description Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware.
Page 618 GD32F5xx User Manual This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 619 GD32F5xx User Manual When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison.
Page 620 GD32F5xx User Manual 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 621 GD32F5xx User Manual CH1EN Channel 1 capture/compare function enable Refer to CH1EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 622 GD32F5xx User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 623 GD32F5xx User Manual 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 624 GD32F5xx User Manual When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 625 GD32F5xx User Manual 22.4. General level2 timer (TIMERx, x=9, 10, 12, 13) Overview 22.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 626 GD32F5xx User Manual Figure 22-62. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector...
Page 627 GD32F5xx User Manual Figure 22-63. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 628 GD32F5xx User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 629 GD32F5xx User Manual Figure 22-66. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 630 GD32F5xx User Manual Figure 22-67. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling Capture Clock Prescaler Register Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal First, the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 631 GD32F5xx User Manual software directly.  Channel output compare function In channel output compare function, the TIMERx can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter matches the value in the CHxVAL register of an output compare channel, the channel (n) output can be set, cleared, or toggled based on CHxCOMCTL.
Page 632 GD32F5xx User Manual Figure 22-68. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 633 GD32F5xx User Manual Timers interconnection Refer to Advanced timer (TIMERx, x=0, 7) Timer debug mode When the Cortex -M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL2 ® register set to 1, the TIMERx counter stops.
Page 634 GD32F5xx User Manual Register definition 22.4.4. TIMER9 base address: 0x4001 4400 TIMER10 base address: 0x4001 4800 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0]...
Page 635 GD32F5xx User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 636 GD32F5xx User Manual CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 637 GD32F5xx User Manual Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 638 GD32F5xx User Manual Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 639 GD32F5xx User Manual compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise.
Page 640 GD32F5xx User Manual filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH0CAPFLT [3:0] Times...
Page 641 GD32F5xx User Manual Reserved.. CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together with CH0P, this bit is used to...
Page 642 GD32F5xx User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 643 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 644 GD32F5xx User Manual 31:2 Reserved Must be kept at reset value. ITI1_RMP Internal trigger input1 remap 00: Based on GPIO setting 01: Based on GPIO setting 10: HXTAL_DIV(Clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) 11: Based on GPIO setting Configuration register (TIMERx_CFG ) Address offset: 0xFC...
Page 645 GD32F5xx User Manual 22.5. Basic timer (TIMERx, x=5, 6) Overview 22.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 646 GD32F5xx User Manual counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 22-70. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler...
Page 647 GD32F5xx User Manual Figure 22-71. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 648 GD32F5xx User Manual Figure 22-72. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 649 GD32F5xx User Manual Figure 22-73. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 650 GD32F5xx User Manual Register definition 22.5.4. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields...
Page 651 GD32F5xx User Manual The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 652 GD32F5xx User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled...
Page 653 GD32F5xx User Manual Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared.
Page 654 GD32F5xx User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 655 GD32F5xx User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 23.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK1 or PCLK2) to produce a dedicated baud rate lock for the USART transmitter and receiver.
Page 656 GD32F5xx User Manual – Character mode (T=0) – Block mode (T=1) – Direct and inverse convention  Multiprocessor communication – Enter into mute mode if address match does not occur – Wake up from mute mode by idle frame or address match detection ...
Page 657 GD32F5xx User Manual Figure 23-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address Transmitter Transimit clock...
Page 658 GD32F5xx User Manual STB[1:0] stop bit length (bit) usage description Smartcard mode for receiving Normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 659 GD32F5xx User Manual of the TX pin can be configured by the TINV bit in the USART_CTL3 register. Clock pulses can be output through the CK pin. After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing.
Page 660 GD32F5xx User Manual communication is selected (DENT=1), this bit can also be cleared by writing 0 directly. USART receiver 23.3.4. After power on, the USART receiver can be enabled by the follow procedure: Set the UEN bit in USART_CTL0 to enable the USART. Write the WL bit in USART_CTL0 to set the data bits length.
Page 661 GD32F5xx User Manual Figure 23-4. Receiving a frame bit by oversampling method (OSB=0) one frame bit RX pin oversampling 8 mode sample bits oversampling 16 mode sample bits If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame.
Page 662 GD32F5xx User Manual Figure 23-5. Configuration step when use DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 663 GD32F5xx User Manual Figure 23-6. Configuration step when use DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 664 GD32F5xx User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared by reading the USART_DATA register.
Page 665 GD32F5xx User Manual address flag is low, the frame is treaded as a data frame. If the LSB 4 bits of an address frame are the same as the ADDR[3:0] bits in the USART_CTL1 register, the hardware will clear the RWU bit and exit the mute mode.
Page 666 GD32F5xx User Manual Figure 23-10. Break frame occurs during a frame frame0 frame1 frame2 RX pin 1 frame time FERR data0 data1 data2 USART_DATA LBDF Synchronous mode 23.3.9. The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1.
Page 667 GD32F5xx User Manual Figure 23-12. 8-bit format USART synchronous waveform (CLEN=1) Idle frame data (8bit) Idle CK pin (CPL=0, CPH=0) CK pin(CPL=1, CPH=0) CK pin (CPL=0, CPH=1) CK pin (CPL=1, CPH=1) Start Master data output bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7...
Page 668 GD32F5xx User Manual logic ‘0’. The pulse width should be 3/16 of a bit period. The IrDA could not detect any pulse if the pulse width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times PSC clock.
Page 669 GD32F5xx User Manual smartcard, the TX pin must be configured as open drain mode, and an external pull-up resistor will be needed, which drives a bidirectional line that is also driven by the smartcard. The data frame consists of 1 start bit, 9 data bits (1 parity bit included) and 1.5 stop bits. The 0.5 stop bit may be configured for a receiver.
Page 670 GD32F5xx User Manual Block (T=1) mode In block (T=1) mode, the NKEN bit in the USART_CTL2 register should be cleared to deactivate the NACK transmission. When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. This timeout period is expressed in baud time units.
Page 671 GD32F5xx User Manual and DINV bits in USART_CTL3 should be set. USART interrupts 23.3.13. The USART interrupt events and flags are listed in Table 23-3. USART interrupt requests. Table 23-3. USART interrupt requests Interrupt event Event flag Enable Control bit Transmit data buffer empty TBEIE CTS toggled flag...
Page 672 GD32F5xx User Manual Figure 23-16. USART interrupt mapping diagram RTIE EBIE IDLEF IDLEIE ORERR RBNEIE PERR PEIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT RBNE RBNEIE TCIE TBEIE CTSF CTSIE...
Page 673 GD32F5xx User Manual 23.4. Register definition USART0 base address: 0x4001 1000 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 USART5 base address: 0x4001 1400 UART6 base address: 0x4000 7800 UART7 base address: 0x4000 7C00 Status register 0 (USART_STAT0) 23.4.1.
Page 674 GD32F5xx User Manual transmit shift register. An interrupt occurs if the TBEIE bit in USART_CTL0 is set. This bit is cleared when the software write transmit data to the USART_DATA register. 0: Transmit data buffer is not empty. 1: Transmit data buffer is empty. Transmission complete.
Page 675 GD32F5xx User Manual 1: The USART has detected a noise error. FERR Frame error flag This bit is set when the RX pin is detected low during the stop bits of a receive frame. An interrupt occurs if the ERRIE bit in USART_CTL2 is set. Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one.
Page 676 GD32F5xx User Manual The software must not write this register when the USART is enabled (UEN=1). This register has to be accessed by word (32-bit). Reserved INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions Must be kept at reset value. 31:16 Reserved 15:4 INTDIV[11:0] Integer part of baud-rate divider.
Page 677 GD32F5xx User Manual 1: 9 Data bits Wakeup method in mute mode 0: wake up by idle frame. 1: wake up by address match. PCEN Parity check function enable. 0: Disable parity check function. 1: Enable parity check function. Parity mode 0: Even parity 1: Odd parity PERRIE...
Page 678 GD32F5xx User Manual Software can set this bit to make the USART work in mute mode and reset this bit to wake up the USART. In wake up by idle frame mode (WM=0), this bit can be reset by hardware when an idle frame has been detected.
Page 679 GD32F5xx User Manual This bit reserved for UART3/4/6/7. CK polarity This bit specifies the polarity of the CK pin in synchronous mode. 0: The CK pin is in low state when the USART is in idle state. 1: The CK pin is in high state when the USART is in idle state. This bit is reserved for UART3/4/6/7.
Page 680 GD32F5xx User Manual Reserved CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields Descriptions Must be kept at reset value. 31:12 Reserved One sample bit method. This bit selects the sample method. When this bit is set, the USART get only one sample for a data bit instead of 3 samples per bit.
Page 681 GD32F5xx User Manual NKEN NACK enable in Smartcard mode This bit enables the NACK transmission when parity error occurs in smartcard mode. 0: Disable NACK transmission 1: Enable NACK transmission This bit is reserved for UART3/4/6/7. HDEN Half-duplex enable This bit enables the half-duplex USART mode. 0: Disable Half duplex mode 1: Enable half duplex mode IRLP...
Page 682 GD32F5xx User Manual TC flag assertion time is delayed by GUAT[7:0] baud clock cycles. These bits are not available for UART3/4/6/7. PSC[7:0] When the USART IrDA low-power mode is enabled, these bits specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the low-power frequency.
Page 683 GD32F5xx User Manual DINV Data bit level inversion. This bit specifies the polarity of the data bits in transmission and reception. 0: Data bit signal values are not inverted. 1: Data bit signal values are inverted. This bit field cannot be written when the USART is enabled (UEN=1). TINV TX pin level inversion This bit specifies the polarity of the TX pin.
Page 684 GD32F5xx User Manual Receiver timeout register (USART_RT) 23.4.9. Address offset: 0x84 Reset value: 0x0000 0000 This register is not available for UART3/4/6/7. This register has to be accessed by word (32-bit). BL[7:0] RT[23:16] RT[15:0] Bits Fields Descriptions 31:24 BL[7:0] Block length These bits specify the block length in smartcard T=1 reception.
Page 685 GD32F5xx User Manual This register has to be accessed by word(32-bit). Reserved Reserved Reserved Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Busy flag This bit is set when the USART is receiving a data frame. 0: USART reception path is idle. 1: USART reception path is working.
Page 686 GD32F5xx User Manual rc_w0 Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. EPERR Early parity error flag. This flag will be set as soon as the parity bit has been detected, which is before RBNE flag. This flag is cleared by writing 0. 0: No parity error is detected 1: Parity error is detected Reserved...
Page 687 GD32F5xx User Manual Inter-integrated circuit interface (I2C) Inter-integrated circuit interface (I2Cx, x=0, 1, 2) 24.1. Overview 24.1.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL.
Page 688 GD32F5xx User Manual Figure 24-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Analog Digital Noise Noise Filter Filter Shift Register SCL Controller Data Register Analog Digital Noise Noise Filter Filter SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags...
Page 689 GD32F5xx User Manual Data validation The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW (see Figure 24-2.
Page 690 GD32F5xx User Manual Figure 24-4. Clock synchronization Arbitration Arbitration, like synchronization, is part of the protocol where more than one master is used in the system. Slaves are not involved in the arbitration procedure. A master may start a transfer only if the bus is free. Two masters may generate a START signal within the minimum hold time of the START signal which results in a valid START signal on the bus.
Page 691 GD32F5xx User Manual An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation. Figure 24-6. I2C communication flow with 7-bit address Figure 24-7. I2C communication flow with 10-bit address (Master Transmit) Slave address byte1 Start Slave address byte2...
Page 692 GD32F5xx User Manual First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus. After receiving a START signal followed by a matched address, either in 7-bit format or in 10-bit format, the I2C hardware sets the ADDSEND bit in I2C_STAT0 register, which should be monitored by software either by polling or interrupt.
Page 693 GD32F5xx User Manual Figure 24-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 694 GD32F5xx User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 24-10.
Page 695 GD32F5xx User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 696 GD32F5xx User Manual reception and then sending a STOP signal on I2C bus. So, special attention should be paid to ensure the correct ending of data reception. Two solutions for master receiving are provided here for applications: Solution A and B. Solution A requires the software’s quick response to I2C events, while Solution B doesn’t.
Page 697 GD32F5xx User Manual Figure 24-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 698 GD32F5xx User Manual If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 699 GD32F5xx User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 700 GD32F5xx User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 701 GD32F5xx User Manual analog block that can suppress spikes with length up to 50ns. The analog noise filter, which is enabled by default, can be disabled by setting the AFD bit in the I2C_FCTL register. The digital noise filter is a digital block lies inside the I2C digital logic. It suppresses spikes with length up to (DF+1) PCLK cycles on the SCL / SDA inputs.
Page 702 GD32F5xx User Manual devices must reset in order to solve the problem. Slave devices are not allowed to hold the clock low too long.  Packet error checking SMBus 2.0 and 1.1 allow Packet Error Checking (PEC). In that mode, a PEC byte is appended at the end of each transaction.
Page 703 GD32F5xx User Manual Table 24-2. Event status flags Event Flag Name Description SBSEND START signal sent (master) ADDSEND Address sent or received ADD10SEND Header of 10-bit address sent STPDET STOP signal detected Byte transmission completed I2C_DATA is empty when transmitting RBNE I2C_DATA is not empty when receiving SAM_V mode rxframe pin rising edge is detected...
Page 704 GD32F5xx User Manual Register definition 24.1.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 I2C2 base address: 0x4000 5C00 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved...
Page 705 GD32F5xx User Manual being received. PECTRANS bit indicates that the current receiving byte is a PEC byte 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0...
Page 706 GD32F5xx User Manual 1: SMBus mode I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved DMALST...
Page 707 GD32F5xx User Manual RBNE=1 if BUFIE=1. ERRIE Error interrupt enable 0: Error interrupt is disabled 1: Error interrupt is enabled, which means that interrupt will be generated when BERR, LOSTARB, AERR, OUERR, PECERR, SMBTO or SMBALT flag is asserted. Reserved Must be kept at reset value.
Page 708 GD32F5xx User Manual Slave address register 1 (I2C_SADDR1) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN...
Page 709 GD32F5xx User Manual Reserved LOSTAR ADD10S ADDSEN SMBALT SMBTO Reserved PECERR OUERR AERR BERR RBNE Reserved STPDET SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0.
Page 710 GD32F5xx User Manual 0: No arbitration lost 1: Arbitration lost occurs and the I2C block changes back to slave mode. BERR Bus error A bus error occurs when an unexpected START or STOP signal on I2C bus This bit is set by hardware and cleared by writing 0. 0: No bus error 1: A bus error detected I2C_DATA is empty during transmitting...
Page 711 GD32F5xx User Manual 0: BTC not asserted 1: BTC asserted ADDSEND Address is sent and ACK is received in master mode or address is received and matches its own address in slave mode. This bit is set by hardware and cleared by reading I2C_STAT0 and reading I2C_STAT1.
Page 712 GD32F5xx User Manual 1: SMBus host header is detected DEFSMB Default address of SMBus device This bit is cleared by hardware after a STOP or a START signal or I2CEN=0. 0: The default address has not been received for SMBus device 1: The default address has been received for SMBus device RXGC General call address (0x00) received.
Page 713 GD32F5xx User Manual FAST I2C speed selection in master mode 0: Standard speed 1: Fast speed DTCY Duty cycle in fast mode 0: T high 1: T =16/9 high 13:12 Reserved Must be kept at reset value. 11:0 CLKC[11:0] I2C clock control in master mode In standard speed mode: T =CLKC*T high...
Page 714 GD32F5xx User Manual Reserved Reserved DF[3:0] Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. Analog noise filter disable 0: Enable analog noise filter 1: Disable analog noise filter DF[3:0] Digital noise filter The Digital noise filter can filter spikes with the maximum length of DF [3:0] PCLK1 cycles on the input pins: SCL and SDA.
Page 715 GD32F5xx User Manual 11:10 Reserved Must be kept at reset value. Level of rxframe signal Level of txframe signal RFRIE Rxframe rise interrupt enable 0: Rxframe rise interrupt disabled 1: Rxframe rise interrupt enabled RFFIE Rxframe fall interrupt enable 0: Rxframe fall interrupt disabled 1: Rxframe fall interrupt enabled TFRIE Txframe rise interrupt enable...
Page 716 GD32F5xx User Manual Inter-integrated circuit interface (I2Cx, x=3, 4, 5) 24.2. Overview 24.2.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 717 GD32F5xx User Manual Figure 24-14. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter...
Page 718 GD32F5xx User Manual  <t I2CCLK HIGH with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters DNF[3:0]×t Analog filter delay is maximum 260ns. Digital filter delay is I2CCLK The period of PCLK clock match the conditions as follows:...
Page 719 GD32F5xx User Manual Figure 24-16. START and STOP signal Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. It operates in slave mode by default. When it generates a START signal, the interface automatically switches from slave to master.
Page 720 GD32F5xx User Manual Figure 24-18. I2C communication flow with 7-bit address (Master Transmit) Figure 24-19. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent. When HEAD10R=0, the complete 10 bit address read sequence must be executed with START + header of 10-bit address in write direction + slave address byte 2 + RESTART + header of 10-bit address in read direction, as is shown in...
Page 721 GD32F5xx User Manual and enabled when ANOFF is 0. It can suppress spikes with a pulse width up to 50ns in fast mode and fast mode plus. The digital noise filter can be used by configuring the DNF [3:0] bit in I2C_CTL0 register. The level of the SCL or the SDA will not be changed if the level is stable for no more than DNF[3:0]×t .
Page 722 GD32F5xx User Manual effects t . The total delay of SDA output is t + {[SDADELY * (PSC+1) + 1] * t HD;DAT I2CCLK SYNC1 depends on SCL falling slope, the delay of analog filter, the delay of digital filter and SYNC1 delay of SCL synchronization to I2CCLK clock.
Page 723 GD32F5xx User Manual a software reset is generated, the SCL and SDA are released. The communication control bits and status bits come back to the reset value. Software reset have no effect on configuration registers. The impacted register bits are START, STOP, NACKEN in I2C_CTL1 register, I2CBSY, TBE, TI, RBNE, ADDSEND, NACK, TCR, TC, STPDET, BERR, LOSTARB and OUERR in I2C_STAT register.
Page 724 GD32F5xx User Manual Figure 24-25. Data reception SCL Stretch data2 data1 Shift register RBNE read data0 read data1 data0 data1 data2 I2C_RDATA  Reload and automatic end mode In order to manage byte transfer and to shut down the communication in modes as is shown Table 24-6.
Page 725 GD32F5xx User Manual I2C_SADDR1 register should be set when the corresponding address is used. 7-bit address or 10-bit address can be programmed in ADDRESS[9:0] in I2C_SADDR0 register by configuring the ADDFORMAT bit in 7-bit address or 10-bit address. The ADDM [6:0] in I2C_CTL2 register defines which bits of ADDRESS[7:1] are compared with an incoming address byte, and which bits are ignored.
Page 726 GD32F5xx User Manual In slave receiving mode, the slave byte control mode can be enabled by setting the SBCTL bit in the I2C_CTL0 register to allow byte ACK control. When SS=1, the slave byte control mode is not allowed. When using slave byte control mode, the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register.
Page 727 GD32F5xx User Manual Figure 24-26. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1 Configure ADDRESS[9:0], ADDFORMAT and ADDRESSEN in I2C_SADDR0, ADDRESS2[7:1], ADDMSK2[2:0] and ADDRESS2EN in I2C_SADDR1, ADDM[6:0] in I2C_CTL2...
Page 728 GD32F5xx User Manual When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine. So the first byte to be sent must be programmed in the I2C_TDATA register previously. ...
Page 729 GD32F5xx User Manual Figure 24-28. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 730 GD32F5xx User Manual Figure 24-29. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 731 GD32F5xx User Manual mode, the HEAD10R bit must be configured to decide whether the complete address sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register. If the number of bytes to be transferred is equal to or greater than 255, BYTENUM[7:0] should be configured as 0xFF.
Page 732 GD32F5xx User Manual bit in I2C_CTL1 can be set to generate a STOP signal automatically. When AUTOEND is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signal by setting the STOP bit in the I2C_CTL1 register. Or generate a RESTART signal to start a new transfer.
Page 733 GD32F5xx User Manual Figure 24-32. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 734 GD32F5xx User Manual Figure 24-33. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 735 GD32F5xx User Manual Figure 24-34. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 736 GD32F5xx User Manual  Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 737 GD32F5xx User Manual after the EXTOEN bit is set, the BUSTOB[11:0] cannot be changed. If the SCL stretching time of the SMBus peripheral is greater than (BUSTOB+1)*2048*t and within the timeout I2CCLK interval described in the bus idle detection section, the TIMEOUT bit in the I2C_STAT register will be set.
Page 738 GD32F5xx User Manual the TIMEOUT flag will be set in the I2C_STAT register.  SMBus slave mode The SMBus receiver must be able to NACK each command or data it receives. For ACK control in slave mode, slave byte control mode can be enabled by setting SBCTL bit in I2C_CTL0 register.
Page 739 GD32F5xx User Manual  SMBus master receiver and slave transmitter If the SMBus master is required to receive PEC at the end of bytes transfer, automatic end mode can be enabled. Before sending a START signal on the bus, PECTRANS bit must be set and slave addresses must be programmed.
Page 740 GD32F5xx User Manual Use DMA for data transfer As is shown in I2C slave mode and I2C master mode, each time TI or RBNE is asserted, software should write or read a byte, this may cause CPU’s high overload. The DMA controller can be used to process TI and RBNE flag: each time TI or RBNE is asserted, DMA controller does a read or write operation automatically.
Page 741 GD32F5xx User Manual I2C debug mode When the microcontroller enters the debug mode (Cortex®-M33 core halted), the SMBus timeout either continues to work normally or stops, depending on the I2Cx_HOLD configuration bits in the DBG module.
Page 742 GD32F5xx User Manual Register definition 24.2.4. I2C3 base address: 0x4000 8000 I2C4 base address: 0x4000 8400 I2C5 base address: 0x4000 8800 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SMBALT SMBDAE SMBHAE...
Page 743 GD32F5xx User Manual 0: Slave won’t response to a General Call 1: Slave will response to a General Call WUEN Wakeup from power saving mode enable This bit is cleared when mcu wakeup from power saving mode. 0: Wakeup from power saving mode disable. 1: Wakeup from power saving mode enable.
Page 744 GD32F5xx User Manual TCIE Transfer complete interrupt enable 0: Transfer complete interrupt is disabled 1: Transfer complete interrupt is enabled STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled 1: Stop detection (STPDET) interrupt is enabled NACKIE Not acknowledge received interrupt enable 0: Not acknowledge (NACK) received interrupt is disabled 1: Not acknowledge (NACK) received interrupt is enabled...
Page 745 GD32F5xx User Manual Set by software. Cleared by hardware in the following cases: When PEC byte is transferred or ADDSEND bit is set or STOP signal is detected or I2CEN=0. 0: Don’t transfer PEC value 1: Transfer PEC Note: This bit has no effect when RELOAD=1, or SBCTL=0 in slave mode. AUTOEND Automatic end mode in master mode 0: TC bit is set when the transfer of BYTENUM[7:0] bytes is completed.
Page 746 GD32F5xx User Manual 0: START will not be sent 1: START will be sent HEAD10R 10-bit address header executes read direction only in master receive mode 0: The 10 bit master receive address sequence is START + header of 10-bit address (write) + slave address byte 2 + RESTART + header of 10-bit address (read).
Page 747 GD32F5xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address 1: 10-bit address Note: When ADDRESSEN is set, this bit should not be written.
Page 748 GD32F5xx User Manual 10:8 ADDMSK2[2:0] ADDRESS2[7:1] mask Defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don’t care). 000: No mask, all the bits must be compared. n (001~110): ADDRESS2[n:0] is masked. Only ADDRESS2[7:n+1] are compared. 111: ADDRESS2[7:1] are masked.
Page 749 GD32F5xx User Manual configuring these bits. And during t , the SCL line is stretched low in master SDADELY mode and in slave mode when SS = 0. = SDADELY x t SDADELY 15:8 SCLH[7:0] SCL high period SCL high period can be generated by configuring these bits. =(SCLH+1)*t SCLH Note: These bits can only be used in master mode.
Page 750 GD32F5xx User Manual than t when TOIDLE =1, a timeout error is detected. IDLE 0: SCL timeout detection is disabled 1: SCL timeout detection is enabled 14:13 Reserved Must be kept at reset value. TOIDLE Idle clock timeout detection 0: BUSTOA is used to detect SCL low timeout 1: BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle Note: This bit can be written only when TOEN =0.
Page 751 GD32F5xx User Manual 0: No I2C communication. 1: I2C communication active. Reserved Must be kept at reset value. SMBALT SMBus Alert When SMBHAEN=1, SMBALTEN=1, and a SMBALERT event (falling edge) is detected on SMBA pin, this bit will be set by hardware. It is cleared by software by setting the SMBALTC bit.
Page 752 GD32F5xx User Manual This bit is set by hardware when RELOAD=1 and data of BYTENUM[7:0] bytes have been transferred. It is cleared by software when BYTENUM[7:0] is written to a non- zero value. 0: When RELOAD=1, transfer of BYTENUM[7:0] bytes is not completed 1: When RELOAD=1, transfer of BYTENUM[7:0] bytes is completed Transfer complete in master mode This bit is set by hardware when RELOAD=0, AUTOEND=0 and data of...
Page 753 GD32F5xx User Manual I2C_TDATA is empty during transmitting This bit is set by hardware when the I2C_TDATA register is empty. It is cleared when the next data to be sent is written in the I2C_TDATA register. This bit can be set by software in order to empty the I2C_TDATA register.
Page 754 GD32F5xx User Manual Software can clear the NACK bit of I2C_STAT by writing 1 to this bit. ADDSENDC ADDSEND flag clear Software can clear the ADDSEND bit of I2C_STAT by writing 1 to this bit. Reserved Must be kept at reset value. PEC register (I2C_PEC) Address offset: 0x20 Reset value: 0x0000 0000...
Page 755 GD32F5xx User Manual Transmit data register (I2C_TDATA) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value Control register 2 (I2C_CTL2) Address offset: 0x90 Reset value: 0x0000 0000...
Page 756 GD32F5xx User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 25.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 757 GD32F5xx User Manual  Transmission and reception using DMA 25.3. SPI block diagram Figure 25-1. Block diagram of SPI SYSCLK MOSI TX Buffer MISO RX Buffer 25.4. SPI signal description Normal configuration (Not Quad-SPI Mode) 25.4.1. Table 25-1. SPI signal description Pin Name Direction Description...
Page 758 GD32F5xx User Manual NSSDRV=0, it is NSS input, suitable for multi-master application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration 25.4.2. SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI5).
Page 759 GD32F5xx User Manual Figure 25-2. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[0] D[2] D[4] D[5] D[1] D[6] D[7] LF=1 FF16=0 MISO D[2] D[6] D[1] D[5] D[7] D[0] D[3]...
Page 760 GD32F5xx User Manual Table 25-3. NSS function in slave mod Mode Register configuration Description MSTMOD = 0 SPI slave gets NSS level from NSS Slave hardware NSS mode SWNSSEN = 0 pin. SPI slave NSS level is determined by MSTMOD = 0 the SWNSS bit.
Page 761 GD32F5xx User Manual Mode Register configuration Description MSTMOD = 1 SWNSSEN = 1 The slave can use hardware or SWNSS = 1 software NSS mode. NSSDRV: Don’t care SPI operation modes 25.5.3. Table 25-5. SPI operation modes Mode Description Register Configuration Data Pin Usage MSTMOD = 1 RO = 0...
Page 762 GD32F5xx User Manual Mode Description Register Configuration Data Pin Usage bidirectional connection RO = 0 MISO: Transmission BDEN = 1 BDOEN = 1 MSTMOD = 0 Slave Reception with RO = 0 MOSI: Not used bidirectional connection BDEN = 1 MISO: Reception BDOEN = 0 Figure 25-4.
Page 763 GD32F5xx User Manual Figure 25-7. A typical bidirectional connection SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC[2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 764 GD32F5xx User Manual empty) flag is set after the first bit of this frame is transmited. After TBE flag is set, which means the transmit buffer is empty, the application should write SPI_DATA register again if it has more data to transmit. In master mode, software should write the next data into SPI_DATA register before the transmission of current data frame is completed if it desires to generate continuous transmission.
Page 765 GD32F5xx User Manual Figure 25-8. Timing diagram of TI master mode with discontinuous transfer Figure 25-9. Timing diagram of TI master mode with continuous transfer sample MOSI D[7] D[1] D[0] D[7] D[6] D[2] D[6] D[5] D[4] D[3] D[2] D[5] D[4] D[3] D[1] D[0]...
Page 766 GD32F5xx User Manual +5*T (25-1) pclk For example, if PSC[2:0] = 010, T is 9*Tpclk. In slave mode, the slave also monitors the NSS signal and sets an error flag FE if it detects an incorrect NSS behavior, for example: toggles at the middle bit of a byte. Quad-SPI mode operation sequence The Quad-SPI mode is designed to control quad SPI flash.
Page 767 GD32F5xx User Manual Figure 25-11. Timing diagram of quad write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 768 GD32F5xx User Manual Figure 25-12. Timing diagram of quad read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7]...
Page 769 GD32F5xx User Manual SPI_CTL0 register are cleared. DMA function 25.5.4. The DMA function frees the application from data writing and reading process during transfer, thus improve the system efficiency. DMA function in SPI is enabled by setting DMATEN and DMAREN bits in SPI_CTL1 register. To use DMA function, application should first correctly configure DMA modules, then configure SPI module according to the initialization sequence, at last enable SPI.
Page 770 GD32F5xx User Manual transmit buffer by writing the SPI_DATA register.  Receive buffer not empty flag (RBNE) This bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register. ...
Page 771 GD32F5xx User Manual interrupt Flag Description Clear Method enable bit register, then write SPI_CTL0 register. Read SPI_DATA register, then RXORERR Rx Overrun Error read SPI_STAT register. CRCERR CRC error Write 0 to CRCERR bit FERR TI Mode Format Error Write 0 to FERR bit 25.7.
Page 772 GD32F5xx User Manual SPI0, SPI3 and SPI4, MCK shares the same pin with SPI_MISO. In SPI1 and SPI2, MCK has a dedicated pin. MCK is an optional signal for I2S interface. It produces a frequency rate equal to 256 x Fs, and Fs is the audio sampling frequency. 25.9.
Page 773 GD32F5xx User Manual Figure 25-15. I2S Philips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation the transmission of to or from the SPI_DATA register is needed to complete a frame.
Page 774 GD32F5xx User Manual bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits: D[23:8], and the second one should be a 16-bit data. The higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value.
Page 775 GD32F5xx User Manual Figure 25-24. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 25-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 25-26. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 25-27.
Page 776 GD32F5xx User Manual MSB justified standard are exactly the same. In the case that the channel length is greater than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below.
Page 777 GD32F5xx User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 778 GD32F5xx User Manual (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure25-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 25-40.
Page 779 GD32F5xx User Manual (DTLEN=00, CHLEN=0, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16 bits I2S_SD Figure 25-44. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK 13 bits I2S_WS 32 bits I2S_SD Figure 25-45.
Page 780 GD32F5xx User Manual Figure 25-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16-bit data 16-bit 0 I2S_SD I2S clock 25.9.2. Figure 25-50. Block diagram of I2S clock generator 8-bit I2SCLK Configurable...
Page 781 GD32F5xx User Manual Table 25-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) The source of I2S clock can be either from PLLI2S or an external I2S_CKIN pin, and this is programmable in RCU.
Page 782 GD32F5xx User Manual  Step 1: Configure the DIV[7:0] bits, the OF bit, and the MCKOEN bit in the SPI_I2SPSC register, in order to define the I2S bitrate and whether I2S_MCK needs to be provided or not.  Step 2: Configure the CKPL in the SPI_I2SCTL register, in order to define the idle state clock polarity.
Page 783 GD32F5xx User Manual loaded into the receive buffer (RBNE goes high). The data should be read from the SPI_DATA register, when the RBNE flag is high. After a read operation to the SPI_DATA register, the RBNE flag goes low. It is mandatory to read the SPI_DATA register before the end of the next reception.
Page 784 GD32F5xx User Manual the TRANS flag is low. I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The difference between them is described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 785 GD32F5xx User Manual 25.10. I2S interrupts Status flags 25.10.1. There are four status flags implemented in the SPI_STAT register, including TBE, RBNE, TRANS and I2SCH. The user can use them to fully monitor the state of the I2S bus.  Transmit buffer empty flag (TBE) This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register.
Page 786 GD32F5xx User Manual Table 25-10. I2S interrupt Interrupt Flag Name Description Clear Method Enable bit Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not empty Read SPI_DATA register RBNEIE TXURERR Transmission underrun error Read SPI_STAT register Read SPI_DATA register and RXORERR Reception overrun error ERRIE...
Page 787 GD32F5xx User Manual 25.11. Register definition I2S1_add base address: 0x4000 3400 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 I2S2_add base address: 0x4000 4000 SPI0 base address: 0x4001 3000 SPI3 base address: 0x4001 3400 SPI4 base address: 0x4001 5000 SPI5 base address: 0x4001 5400 Control register 0 (SPI_CTL0) 25.11.1.
Page 788 GD32F5xx User Manual 1: CRC calculation is enabled. CRCNT CRC next transfer 0: Next transfer is Data 1: Next transfer is CRC value (TCR) When the transfer is managed by DMA, CRC value is transferred by hardware. This bit should be cleared. In full-duplex or transmit-only mode, set this bit after the last data is written to SPI_DATA register.
Page 789 GD32F5xx User Manual MSTMOD Master mode enable 0: Slave mode 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle 1: CLK pin is pulled high when SPI is idle CKPH Clock phase selection 0: Capture the first data at the first clock transition.
Page 790 GD32F5xx User Manual NSSDRV Drive NSS output 0: NSS output is disabled. 1: NSS output is enabled. If the NSS pin is configured as output, the NSS pin is pulled low in master mode when SPI is enabled. If the NSS pin is configured as input, the NSS pin should be pulled high in master mode, and this bit has no effect.
Page 791 GD32F5xx User Manual 1: SPI or I2S is currently transmitting and/or receiving a frame This bit is set and cleared by hardware. RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register.
Page 792 GD32F5xx User Manual Data register (SPI_DATA) 25.11.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register...
Page 793 GD32F5xx User Manual default value is 0007h. RX CRC register (SPI_RCRC) 25.11.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 794 GD32F5xx User Manual 31:16 Reserved Must be kept at reset value. 15:0 TCRC[15:0] TX CRC register When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the transmitted bytes and saves them in TCR register. If the Data frame format is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value in TCRC[7:0].When the Data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC[15:0].
Page 795 GD32F5xx User Manual This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. PCMSMOD PCM frame synchronization mode 0: Short frame synchronization 1: long frame synchronization This bit has a meaning only when PCM standard is used. This bit should be configured when I2S mode is disabled.
Page 796 GD32F5xx User Manual This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved Reserved MCKOEN DIV[7:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: I2S_MCK output is disabled 1: I2S_MCK output is enabled This bit should be configured when I2S mode is disabled.
Page 797 GD32F5xx User Manual IO23_DRV Drive IO2 and IO3 enable 0: IO2 and IO3 are not driven in single wire mode 1: IO2 and IO3 are driven to high in single wire mode This bit is only available in SPI5. Quad-SPI mode read select. 0: SPI is in quad wire write mode 1: SPI is in quad wire read mode This bit should be only be configured when SPI is not busy (TRANS bit cleared).
Page 798 GD32F5xx User Manual Serial Audio Interface (SAI) Overview 26.1. The Serial Audio Interface (SAI) is designed to target a wide range of commonly used audio protocols, both in mono and stereo modes, such as I2S, PCM/DSP, AC’97, LSB or MSB- justified and TDM.
Page 799 GD32F5xx User Manual Function overview 26.3. Block diagram 26.3.1. Figure 26-1. block diagram MCLK2PAD0 SCK2PAD0 SAI_CK0 domain FS_SYNC_OUT SAI_CK0 Clock Divider Logic 0 SCK2REG0 SCK_SYNC_OUT PCLK domain DMA_TX_REQ0 SAI_B0 DMA_RX_REQ0 DMA_IF Compan SAI_B1 SYNC SAI_INTR0 Ctrl Interrupt_IF FIFO0 SAI_B0DATA Finite State Machine SAI_B0STAT SCK0 SAI_B0INTEN...
Page 800 GD32F5xx User Manual mode for external DAC/ADC operations. There is one exception that, when SAI is configured in AC’97 protocol, FS is forced to be an output, independent of master/slave configurations. The Serial Data (SD) IO pin is configured as output in transition and input in reception. The IO Management block controls the IO pins of each audio sub-block, when the two sub- blocks are declared synchronous with each other, FS, SCK and MCLK can be shared, those pins of the synchronous sub-block are freed and can be used as general purpose IO.
Page 801 GD32F5xx User Manual SAI_CK (26-3) MDIV × (MOSPR + 1) × 256 When BYPASS is set, the master clock (MCLK) is turned off with a fixed output value of 0, while the bit clock (SCK) is linked directly to SAI_CK. In addition, there is no restriction on the frame length value as long as the frame length is bigger or equal to 8.
Page 802 GD32F5xx User Manual slave will not receive the complete data from the master. Transmitter When the audio sub-block is configured as transmitter, serial data (SD) is an output. If the FIFO is still empty after the audio sub-block is enabled, a 0 value is sent, and the underrun flag (OUERR) is raised.
Page 803 GD32F5xx User Manual Frame configuration 26.3.5. Frame synchronization Frame synchronization is the coordination signal between master and slave to initiate a transfer. A number of parameters were implemented to manipulate with its waveform. Frame synchronization advancement Frame synchronization active edge could be aligned with the start of the first bit of the first slot, or one bit clock (SCK) cycle in advance, depending on the control field FSOST in SAI_BxFCFG register.
Page 804 GD32F5xx User Manual Frame synchronization function Frame synchronization function definition is configured though the FSFUNC in SAI_BxFCFG register. Two specific function could be selected, when FSFUNC is set to 1, FS not only represent frame start, but also channel number identification, in this case, frame active width (FSAWD + 1) should be configured to half of the frame width, as shown in Figure 26-5 FS function, otherwise the audio sub-block behavior is not guaranteed.
Page 805 GD32F5xx User Manual (SLOTAV) in SAI_BxSCFG register. SLOTAV is a 16-bits wide control field, and each bit controls the corresponding slot’s activation status. The logical division of slots could be shown in the Figure 26-6 Slot activation. Figure 26-6 Slot activation Bit Clock (SCK) Frame Synchronization...
Page 806 GD32F5xx User Manual Serial data output management on inactive slots Serial data (SD) output behavior in the vicinity of inactive slots could be set according to the management policy defined in the serial data output mode (SDOM) bit in SAI_BxSCFG register, either SAI releases or drives a 0 value to the output.
Page 807 GD32F5xx User Manual Figure 26-11 SD output management Bit Clock (SCK) Frame Synchronization (FS) Active High Unique Offset Region Treatment Serial Data (SD) Offset Free Offset Free Offset Free Region Region Region Region Region Region Logical Slot Slot 0 Slot 1 Slot 2 Slot 3 Slot 4...
Page 808 GD32F5xx User Manual Table 26-2 FIFO request generation conditions Transmitter: OPTMOD[0] = 0 Receiver: OPTMOD[0] = 1 FIFO FIFO FFTH FIFO Status FFSTAT FFTH FIFO Status FFSTAT Threshold Threshold Empty = 000 Empty = 000 Empty = 000 Not Empty ≥...
Page 809 GD32F5xx User Manual Figure 26-13 AC'97 slot partition Bit Clock (SCK) FS Assert 1 Cycle Before Frame Synchronization (FS) Logical Slot Slot 0 Slot 1 Slot 12 Slot 2…11 Division FS Active Width (16-Bits) Slot 0 (16-Bits) Slot 1 (20-Bits) Slot 12 (20-Bits) Frame Width (256 Bits) give an overview of AC’97 slot partition.
Page 810 GD32F5xx User Manual STATUS ADDR read port MSBs echo register address; LSBs indicate which slots request data STATUS DATA read port 16-bit command register read data PCM L&R ADC record 16-, 18- or 20-bit PCM data from Left and Right inputs Modem Line 1 ADC 16-bit modem data from modem Line 1 input Dedicated Microphone ADC...
Page 811 GD32F5xx User Manual The data filling of SPDIF data transmission in the SAI_BxDATA register should follow: SAI_BxDATA[26:24] contains the channel status bit, user bit and validity bit, SAI_BxDATA[23:0] contains the 24-bit data of the channel under consideration. Note: If the data size is 20/16 bits, the data should be mapped to SAI_BxDATA[23:4] / SAI_BxDATA [23:8].
Page 812 GD32F5xx User Manual Mute 26.3.12. Users could set the mute property anywhere during an on-going frame through the MT bit in the SAI_BxCFG1 register, but mute will only take effect on the state of the next frame. When the SAI audio sub-block is configured as transmitter and mute is configured, data is still read from the FIFO, put into the shift register as usual when mute take effect at next frame, the only difference is that the SD output if forced to a specific value determined by the mute value (MTVAL) configuration also located in the SAI_BxCFG1 register.
Page 813 GD32F5xx User Manual Forced to 0 Forced to 0 >2 Compander 26.3.13. Compander is simply a system in which information is first compressed, transmitted through a bandwidth limited channel, and expanded in the receiving end. It is frequently used to reduce the bandwidth requirement for transmitting telephone quality speech, by reducing the 13-bitto 8-bit code words.
Page 814 GD32F5xx User Manual Table 26-8 A-law encoding Linear Input Data A-law Encoded Output After the input data is encoded through the logic defined in the table, an inversion pattern is applied to the 8-bit code to increase the density of transitions on the transmission line, a benefit to hardware performance.
Page 815 GD32F5xx User Manual 4. The inversion pattern is applied to all bits in the 8-bit code. illustrate Mu-law encoding algorithm. The sign bit S of Table 26-10 Mu-law encoding the linear input data takes on the opposite value from the sign bit of the encode data. Table 26-10 Mu-law encoding Linear Input Data Mu-law Encoded output...
Page 816 GD32F5xx User Manual IO management 26.3.15. IO management module is connected to both SAI audio sub-blocks, it is the only medium where they are connected. When audio sub-block is configured synchronous with the other sub-block through the synchronization mode (SYNCMOD) bit in SAI_BxCFG0 register, FS, SCK and MCLK pin could be shared, those pins of the synchronous sub-block are freed and left as general purpose IOs.
Page 817 GD32F5xx User Manual Error flags 26.3.18. Clock error configuration detection Clock error configuration detection mechanism in enabled only when the audio sub-block is configured as master and clock divider bypass (BYPASS) is set. In this operating mode, users have to guarantee that the frame length (FWD+1) equals the results of an exponential function of base 2 within 8- and 256-bits range, otherwise the clock error flag (CKERR) will be set in the status register SAI_BxSTAT.
Page 818 GD32F5xx User Manual 1. Audio sub-block should be disabled, users must wait for the SAIEN control field of the corresponding sub-block is completely disabled. 2. The internal FIFO should be flushed by setting the FLUSH control field. 3. Enable the audio sub-block again by setting SAIEN. 4.
Page 819 GD32F5xx User Manual Figure 26-19 Frame synchronization postponed detection Bit Clock (SCK) FSAW+1 = (FW+1) / 2 Frame Synchronization (FS) n = (FW+1)/2 Logical Slot FSPDET bi t 1 bi t 2 bi t 3 bi t n Division FIFO overrun or underrun detection FIFO overrun and underrun flag (OUERR) ccupies the same bit in status register SAI_BxSTAT since each audio sub-block can be configured into either transmitter or receiver.
Page 820 GD32F5xx User Manual Table 26-12 Interrupt control Interrupt Interrupt Interrupt Enable Interrupt Clear Interrupt raise condition source partition Control Control FFREQ Request OPTMOD = Any FFREQIE Read/Write SAI_BxDATA MTDET Mute OPTMOD = Receiver MTDETIE MTDETC CKERR Error OPTMOD = Master; BYPASS = 1 CKERRIE CKERRC ACNRDY...
Page 821 GD32F5xx User Manual Register definition 26.4. SAI base address: 0x4001 5800 Synchronize configuration register (SAI_SYNCFG) 26.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved SYNO[1:0] Reserved SYNI[1:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 822 GD32F5xx User Manual SAMPED SHIFTDI Reserved ODRIV MONO SYNCMOD[1:0] DATAWD[2:0] Reserved PROT[1:0] OPTMOD[1:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. MCLKEN The master clock enable 0: The master clock is enable 1: The master clock is enabled independently of SAIEN bit MOSPR The master clock oversampling rate.
Page 823 GD32F5xx User Manual Note: This control field has to be set after SAI configuration but before SAI sub- block enabled. MONO Stereo and Mono mode selection. 0: Stereo mode. 1: Mono mode. Mono mode requires slot number equals to 2, in transmitter mode, the first slots data is copied to the second slot, while in receiver mode, the second slot’s data is ignored.
Page 824 GD32F5xx User Manual Note: In case AC’97 protocol is selected, only 16- or 20-bits is viable, otherwise audio sub-block’s behavior is not guaranteed. Reserved Must be kept at reset value. PROT[1:0] Protocol selection. 00: Polymorphic. 01: SPDIF. 10: AC’97. 10: Reserved. Polymorphic configuration allows the user to tweak with all the frame and slot configuration options to form his protocol of choice suck as I2S, LSB/MSB justified, TDM, PCM/DSP and so on.
Page 825 GD32F5xx User Manual ITU-T G.711 defines two main compansion algorithm, the Mu-law and A-law, which encode 13- and 12-bits signed linear PCM respectively to logarithmic 8-bit samples. The former gives more resolution to higher range signals while the later provides more quantization levels at lower signal levels.
Page 826 GD32F5xx User Manual frame of a continuous transfer, whether the offset section of the first slot is released or not depends on the last slot of the previous frame. If the last slot is active, then the offset section is driven, otherwise it is released. Note: If data offset plus data width is still lower than the slot width, than the space between the last bit of data and the end of slot is known as the empty section.
Page 827 GD32F5xx User Manual Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. FSOST Frame synchronization offset. 0: FS active edge asserted at the beginning of the first bit of the first slot. 1: FS active edge asserted one bit cycle before normal FS when FSOST is 0. Note: This control field must be configured before the audio sub-block is enabled, and it is meaningless when protocol is set to AC’97 or SPDIF.
Page 828 GD32F5xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SLOTAV[15:0] Reserved SLOTNUM[3:0] SLOTWD[1:0] Reserved DATAOST[4:0] Bits Fields Descriptions 31:16 SLOTAV[15:0] Slot activation vector. 0: Slot inactive. 1: Slot active. Each bit in the SLOTAV vector is aligned to the slot number from 0 to 15, if SLOTNUM is less than 15, the unaligned vector bits is ignored.
Page 829 GD32F5xx User Manual Note: This control field is meaningless in AC’97 mode. Block x interrupt enable register (SAI_BxINTEN) (x = 0,1) 26.4.6. Address offset: 0x14 + 0x20 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FSPDETI FSADETI...
Page 830 GD32F5xx User Manual 1: Interrupt enabled. An interrupt is generated if FFREQ and FFREQIE are both set. Note: When the audio sub-block is configured as receiver, OPTMOD must be set before FFREQIE is enabled to guarantee no false FIFO request is generated since the sub-block is transmitter after reset.
Page 831 GD32F5xx User Manual where different evaluation standards is present according to audio sub-blocks operating mode. In case OPTMOD is configured as receiver: 000: Empty. 001: Empty <FIFO_Level<= 1/4_Full. 010: 1/4_Full <FIFO_Level<= 1/2_Full. 011: 1/2_Full <FIFO_Level<= 3/4_Full. 100: 3/4_Full <FIFO_Level< Full 101: Full.
Page 832 GD32F5xx User Manual 0: No FIFO request. 1: FIFO write or read request. FIFO request could generate an interrupt if FFREQIE is set. The request type depend on audio sub-block configuration, if OPTMOD is configured as transmitter and all conditions met, write request in generated, else if receiver mode is selected, read request is generated.
Page 833 GD32F5xx User Manual FSPDET FSADET ACNRDY Reserved Reserved ERRCKC MTDETC OUERRC Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. FSPDETC Frame synchronization postponed detection interrupt clear. Writing 1 clears FSPDET flag. Note: This control field is not used in AC’97 or SPDIF mode. Note: This field always reads as 0.
Page 834 GD32F5xx User Manual DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] Data. Write and read operations are performed on the FIFO directly.
Page 835 GD32F5xx User Manual Digital camera interface (DCI) 27.1. Overview DCI is a parallel interface to capture video or picture from a camera. It supports various color space such as YUV / RGB, as well as compression format such as JPEG. 27.2.
Page 836 GD32F5xx User Manual signal (DCI_HSYNC or DCI_VSYNC). DCI uses embedded sync detection module to extract synchronization information from pixel data, and then recover horizontal and vertical synchronization signals. The window timing module performs image cutting function. This module calculates a pixel’s position using synchronization signals either from DCI interface or embedded sync detection module and then decides whether this pixel data needs to be received according to the configuration of DCI_CWSPOS and DCI_CWSZ registers.
Page 837 GD32F5xx User Manual JPEG mode DCI supports JPEG video/picture compression format in hardware synchronization mode. In JPEG mode (JM bit in DCI_CTL is set), the DCI_VSYNC is used to indicate start of a new frame, and DCI_HSYNC is used as stream data valid signal. Figure 27-3.
Page 838 GD32F5xx User Manual is captured completely, while in continuous mode, DCI prepares to capture the next frame. The DCI capture frequency is defined by FR[1:0] bits in continuous mode. For example, if FR[1:0]=00, DCI captures each frame, and if FR[1:0]=01, DCI only captures every alternate frame.
Page 839 GD32F5xx User Manual Table 27-2. Memory view in byte padding mode D3[7:0] D2[7:0] D1[7:0] D0[7:0] D7[7:0] D6[7:0] D5[7:0] D4[7:0] Half-word padding mode Half-word padding is used if data width of DCI interface is configured into 10/12/14. In this mode each pixel data is extended into 16-bits length by filling zero at higher position, so the 32-bits width data buffer is able to hold two pixel data.
Page 840 GD32F5xx User Manual 27.7. Register definition DCI base address: 0x5005 0000 Control register (DCI_CTL) 27.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved DCIEN Reserved DCIF[1:0] FR[1:0] WDEN SNAP Bits Fields Descriptions 31:15...
Page 841 GD32F5xx User Manual 1: High level during blanking period Clock Polarity Selection 0: Capture at falling edge 1: Capture at rising edge Embedded Synchronous Mode 0: Embedded synchronous mode is disabled 1: Embedded synchronous mode is enabled JPEG Mode 0: JPEG mode is disabled 1: JPEG mode is enabled WDEN Window Enable...
Page 842 GD32F5xx User Manual 0: Not in vertical blanking period 1: In vertical blanking period HS line status 0: Not in horizontal blanking period 1: In horizontal blanking period Status register1 (DCI_STAT1) 27.7.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ESEF...
Page 843 GD32F5xx User Manual Interrupt enable register (DCI_INTEN) 27.7.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ELIE VSIE ESEIE OVRIE EFIE Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. ELIE End of Line Interrupt Enable 0: End of line flag won’t generate interrupt...
Page 844 GD32F5xx User Manual Reserved ELIF VSIF ESEIF OVRIF EFIF Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. ELIF End of line interrupt flag VSIF Vsync interrupt flag ESEIF Embedded synchronous error interrupt flag OVRIF FIFO overrun interrupt flag EFIF End of frame interrupt flag Interrupt flag clear register (DCI_INTC)
Page 845 GD32F5xx User Manual Synchronization codes register (DCI_SC) 27.7.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) FE[7:0] LE[7:0] LS[7:0] FS[7:0] Bits Fields Descriptions 31:24 FE[7:0] Frame end code in embedded synchronous mode 23:16 LE[7:0] Line end code in embedded synchronous mode...
Page 846 GD32F5xx User Manual Cropping window start position register (DCI_CWSPOS) 27.7.9. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved WVSP[12:0] Reserved WHSP[13:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value. 28:16 WVSP[12:0] Window Vertical Start Position...
Page 847 GD32F5xx User Manual WHSZ=x means x+1 pixels clock in a line DATA register (DCI_DATA) 27.7.11. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) DT3[[7:0] DT2[7:0] DT1[7:0] DT0[7:0] Bits Fields Descriptions 31:24 DT3[7:0] Pixel data 3 23:16 DT2[7:0]...
Page 848 GD32F5xx User Manual TFT-LCD interface (TLI) 28.1. Overview The TLI (TFT-LCD Interface) module handles the synchronous LCD interface and provides pixel data, clock and timing signals for passive LCD display. It supports a wide variety of displays with fully programmable timing parameters. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display.
Page 849 GD32F5xx User Manual Figure 28-1. TLI module block diagram 28.4. Signal description TLI provides a 24-bit RGB Parallel display interface, which is shown in table below. Table 28-1. Pins of display interface provided by TLI Direction Name Width Description Output Horizontal Synchronous Output Vertical Synchronous...
Page 850 GD32F5xx User Manual VTSZ VASZ VBPSZ VPSZ HTSZ HASZ HBPSZ HPSZ PIXCLK RED[7:0], GREEN[7:0], BLUE[7:0] Pixel DMA function 28.5.2. Following the configuration of Register module, the Pixel DMA reads pixel data from memory to the pixel buffer in internal PPU (Pixel Process Unit) continuously. After enabled, the Pixel DMA begins to fetch pixel data from system and push these data into the pixel buffer in PPU as long as the pixel buffer is not full.
Page 851 GD32F5xx User Manual Pixel formats 28.5.3. The Pixel DMA pushes pixel data into PPU in word format and PPU (Pixel Process Unit) is responsible for converting various pixel formats into an internal ARGB8888 format. TLI supports up to eight pixel formats as shown in the table below. The PPF[2:0] in TLI_LxPPF register defines the pixel format.
Page 852 GD32F5xx User Manual parameters defined by TLI_LxHPOS and TLI_LxVPOS registers. These window parameters define a window inside the layer. The pixel inside the window will keep its original value, while the pixel outside will be replaced with a default pixel defined in TLI_LxDC register. The blending units first blends Layer0 and BG Layer into a temporary layer, and then blends Layer1 and the temporary layer into destination layer.
Page 853 GD32F5xx User Manual Dithering function 28.5.6. The dithering module adds a 2-bit pseudo-random value to each pixel channel. This function is able to make the image smoother when 18-bits interface is used to display a 24-bit data. Application may switch on this function using DFEN bit in TLI_CTL register. 28.6.
Page 854 GD32F5xx User Manual 28.7. Register definition TLI base address: 0x4001 6800 Synchronous pulse size register (TLI_SPSZ) 28.7.1. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved HPSZ[11:0] Reserved VPSZ[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value.
Page 855 GD32F5xx User Manual 27:16 HBPSZ[11:0] Size of the horizontal back porch plus synchronous pulse The HBPSZ value should be configured to the pixels number of horizontal back porch and synchronous pulse minus 1. 15:12 Reserved Must be kept at reset value. 11:0 VBPSZ[11:0] Size of the vertical back porch plus synchronous pulse...
Page 856 GD32F5xx User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:16 HTSZ[11:0] Horizontal total size of the display, including active area, back porch, synchronous pulse and front porch The HTSZ value should be configured to the pixels number of horizontal active area width plus back porch, front porch and synchronous pulse minus 1.
Page 857 GD32F5xx User Manual 27:17 Reserved Must be kept at reset value. DFEN Dither function enable 0: Dither function disable 1: Dither function enable Reserved Must be kept at reset value. 14:12 RDB[2:0] Red channel dither bits number Fixed to 2, read only Reserved Must be kept at reset value.
Page 858 GD32F5xx User Manual This bit is set by software and cleared by hardware after reloading 0: Reload disable 1: The layer configuration will be reloaded into core after this bit sets Background color register (TLI_BGC) 28.7.7. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 859 GD32F5xx User Manual 0: Transaction error flag won’t generate an interrupt 1: Transaction error flag will generate an interrupt FEIE FIFO error interrupt enable 0: FIFO error flag won’t generate an interrupt 1: FIFO error flag will generate an interrupt LMIE Line mark interrupt enable 0: Line mark flag won’t generate an interrupt...
Page 860 GD32F5xx User Manual Interrupt flag clear register (TLI_INTC) 28.7.10. Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved LCRC Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. LCRC Layer configuration reloaded flag clear Write 1 to clear layer configuration reloaded flag Transaction error flag clear...
Page 861 GD32F5xx User Manual Current pixel position register (TLI_CPPOS) 28.7.12. Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). HPOS[15:0] VPOS[15:0] Bits Fields Descriptions 31:16 HPOS[15:0] Horizontal position Horizontal position of the current displayed pixel 15:0 VPOS[15:0] Vertical position...
Page 862 GD32F5xx User Manual 0: VPOS in TLI_CPPOS register is not between the VBPSZ in TLI_BPSZ register and VASZ in TLI_ASZ register. 1: VPOS in TLI_CPPOS register is between the VBPSZ in TLI_BPSZ register and VASZ in TLI_ASZ register. Layer x control register (TLI_LxCTL) (x = 0, 1) 28.7.14.
Page 863 GD32F5xx User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:16 WRP[11:0] Window right position 15:12 Reserved Must be kept at reset value. 11:0 WLP[11:0] Window left position Layer x vertical position parameters register (TLI_LxVPOS) (x = 0, 1) 28.7.16.
Page 864 GD32F5xx User Manual 23:16 CKEYR[7:0] Color key red 15:8 CKEYG[7:0] Color key green CKEYB[7:0] Color key blue If the pixel RGB value in a layer equals the value in TLI_LxCKEY, the pixel RGB value is reset to 0. That means these pixels is transparent to other layers. Layer x packeted pixel format register (TLI_LxPPF) (x = 0, 1) 28.7.18.
Page 865 GD32F5xx User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. SA[7:0] Specified alpha The Alpha value used for blending Layer x default color register (TLI_LxDC) (x = 0, 1) 28.7.20. Address offset: 0x9C + 0x80 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 866 GD32F5xx User Manual 31:11 Reserved Must be kept at reset value. 10:8 ACF1[2:0] Alpha calculation factor 1 of blending method 000: Reserved 001: Reserved 010: Reserved 011: Reserved 100: normalization Specified Alpha 101: Reserved 110: normalization Pixel Alpha x normalization Specified Alpha 111:Reserved Reserved Must be kept at reset value.
Page 867 GD32F5xx User Manual This register has to be accessed by word(32-bit) Reserved STDOFF[13:0] Reserved FLL[13:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:16 STDOFF[13:0] Frame buffer stride offset This value defines the bytes number from start of a line to the start of next line 15:14 Reserved Must be kept at reset value.
Page 868 GD32F5xx User Manual TG[7:0] TB[7:0] Bits Fields Descriptions 31:24 TADD[7:0] Look up table write address The entry at this address in LUT will be updated with the value of RED, GREEN and BLUE written 23:16 TR[7:0] Red channel of a LUT entry 15:8 TG[7:0] Green Channel of a LUT entry...
Page 869 GD32F5xx User Manual Secure digital input/output interface (SDIO) 29.1. Introduction The secure digital input/output interface (SDIO) defines the SD/SD I/O /MMC CE-ATA card host interface, which provides command/data transfer between the APB2 system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC), and CE-ATA devices. The supported SD memory card and SD I/O card system specifications are defined in the SD card Association website at www.sdcard.org.
Page 870 GD32F5xx User Manual Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
Page 871 GD32F5xx User Manual has an optional busy before it is ready to receive the data. Figure 29-2. SDIO multiple blocks read operation Figure 29-3. SDIO multiple blocks write operation Command Response Command Response Host to Device Device to Host Host to Device Device to Host DATA BLOCK CRC DATA BLOCK CRC...
Page 872 GD32F5xx User Manual Figure 29-5. SDIO sequential write operation 29.4. SDIO functional description The following figure shows the SDIO structure. There have two main parts:  The SDIO adapter block consists of control unit which manage clock, command unit which manage command transfer, data unit which manage data transfer. ...
Page 873 GD32F5xx User Manual SDIO_CLK: The SDIO_CLK is the clock provided to the card. Each cycle of this signal directs a one bit transfer on the command line (SDIO_CMD) and on all the data lines (SDIO_DAT). The SDIO_CLK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3.31, between 0 and 48 MHz for a Multimedia Card V4.2, or between 0 and 25 MHz for an SD/SD I/O card.
Page 874 GD32F5xx User Manual SDIO_CLK on/off depending on the system bus is very busy or not. When the FIFO cannot receive or transmit data, the host will stop the SDIO_CLK and freeze SDIO state machines to avoid the corresponded error. Only state machines are frozen, the APB2 interface is still alive. So, the FIFO can access by APB2 bus.
Page 875 GD32F5xx User Manual Note: The command timeout has a fixed value of 64 SDIO_CLK clock periods. CS_Receive Receive the response and check the CRC. → 1.Response Received in CE-ATA mode and CS_Waitcompl interrupt disabled and wait for CE-ATA Command Completion signal enabled →...
Page 876 GD32F5xx User Manual → 1.Data transfer ended DS_Idle → 2.DSM disabled DS_Idle → 3.Data FIFO empty flag is deasserted DS_Send DS_Send Transmit data to the card. → 1.Data block transmitted DS_Busy → 2.DSM disabled DS_Idle → 3.Data FIFO underrun error occurs DS_Idle →...
Page 877 GD32F5xx User Manual The interrupt logic generates interrupt when at least one of the selected status flags is high. An interrupt enable register is provided to allow the logic to generate a corresponding interrupt. The DMA interface provides a method for fast data transfers between the SDIO data FIFO and memory.
Page 878 GD32F5xx User Manual a 32-bit wide, 32-word deep data buffer. The transmit FIFO is used when write data to card and TXRUN in SDIO_STAT register is 1. The data to be transferred is written to transmit FIFO by APB2 bus, the data unit in SDIO adapter read data from transmit FIFO, and then send the data to card.
Page 879 GD32F5xx User Manual is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The host can use CMD3 to ask the card to publish a new relative address (RCA). Note: The default value of the RCA register is 0x0001(MMC) or 0x0000(SD/SD I/O).
Page 880 GD32F5xx User Manual Table 29-2. Command format [45:40] [39:8] [7:1] Bit position Width ‘0’ ‘1’ ‘1’ Value Description start bit transmission bit command index argument CRC7 end bit A command always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (host = 1).
Page 881 GD32F5xx User Manual Table 29-3. Card command classes (CCCs) Card command class(CCC) Supported Class command description CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28...
Page 882 GD32F5xx User Manual CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC.CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card.
Page 883 GD32F5xx User Manual Response type argument Abbreviation Description index format Asks the card, in idle state, to [31:0] SEND_OP_CON send its Operating Conditions CMD1 without busy Register contents response on the CMD line. Asks any card to send the CID numbers on the CMD line (any CMD2 [31:0] stuff bits...
Page 884 GD32F5xx User Manual Response type argument Abbreviation Description index format Addressed card sends its card- [31:16] RCA CMD9 SEND_CSD specific data (CSD) on the CMD [15:0] stuff bits line. Addressed card sends its card [31:16] RCA CMD10 SEND_CID identification (CID) on CMD the [15:0] stuff bits line.
Page 885 GD32F5xx User Manual Response type argument Abbreviation Description index format BLOCK_LEN_ERROR bit. In the case of a Standard Capacity SD and MMC, this command reads a block of the size selected [31:0] data READ_SINGLE_B CMD17 adtc SET_BLOCKLEN command. address LOCK In the case of a High Capacity Card, block length is fixed 512 Bytes...
Page 886 GD32F5xx User Manual Response type argument Abbreviation Description index format Defines the number of blocks which are going to be transferred [31:16] set to 0 in the immediately succeeding SET_BLOCK_ CMD23 [15:0] number multiple block read or write COUNT of blocks command.
Page 887 GD32F5xx User Manual Table 29-8. Erase commands (class 5) Response type argument Abbreviation Description index format [31:0] data ERASE_WR_BLK Sets the address of the first write CMD32 address _START block to be erased.(SD) Sets the address of the last write [31:0] data ERASE_WR_BLK CMD33...
Page 888 GD32F5xx User Manual Response type argument Abbreviation Description index format bits. Note: 1. High Capacity SD Memory Card does not support these three commands. Table 29-10. Lock card (class 7) Response type argument Abbreviation Description index format See description in Table 29-5.
Page 889 GD32F5xx User Manual Response type argument Abbreviation Description index format data block from the card for general purpose/application specific command. The host sets RD/WR=1 for reading data from the card and sets to 0 for writing data to the card. [31] WR [23:18] Address R1(read)/...
Page 890 GD32F5xx User Manual Response type argument Abbreviation Description index format [26] Stuff Bits function, including [25:9] Register common I/O area (CIA). This Address command reads or writes 1 [8] Stuff Bits byte using only [7:0] Write command/response pair. Data/Stuff Bits common use is to initialize registers or monitor status values for I/O functions.
Page 891 GD32F5xx User Manual Response type argument Abbreviation Description index format [3:0] function group 1 for access mode Responses 29.5.3. All responses are sent on the CMD line. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type.
Page 892 GD32F5xx User Manual R1 (normal response command) Code length is 48 bits. The bits 45:40 indicate the index of the command to be responded to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits.
Page 893 GD32F5xx User Manual Width ‘0’ ‘0’ ‘111111’ ‘1111111’ ‘1’ Value transmission start bit reserved reserved end bit description register R4 (Fast I/O) For MMC only. Code length 48 is bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its contents. The status bit in the argument is set if the operation was successful.
Page 894 GD32F5xx User Manual winning card or of May be used for IRQ the host data For SD I/O only. The SDIO card's response to CMD52 and CMD53 is R5. If the communication between the card and host is in the 1-bit or 4-bit SD mode, the response shall be in a 48-bit response (R5).
Page 895 GD32F5xx User Manual mode is SDIO or SPI, when card reset and initialize. 1-bit data packet format After card reset and initialize, only DAT0 pin is used to transfer data. And other pin can be used freely. Figure 29-9. 1-bit data bus width, Figure 29-10. 4-bit data bus width Figure 29-11.
Page 896 GD32F5xx User Manual Two status fields of the card 29.5.5. The SD Memory supports two status fields and others just support the first one: Card Status: Error and state information of a executed command, indicated in the response SD Status: Extended status field of 512 bits that supports special features of the SD Memory Card and future Application-Specific features.
Page 897 GD32F5xx User Manual Bits Identifier Type Value Description Clear Condition ’0’= no error BLOCK_LEN_ERROR The transferred block length is ’1’= error not allowed for this card, or the number of transferred bytes does not match the block length. ’0’= no error ERASE_SEQ_ERROR An error in the sequence of ’1’= error...
Page 898 GD32F5xx User Manual Bits Identifier Type Value Description Clear Condition copy (set original) permanent WP(unprotected) bits was made. ’0’= not protected WP_ERASE_SKIP Set when only partial address ’1’= protected space was erased due to existing write protected blocks or the temporary or permanent write protected card...
Page 899 GD32F5xx User Manual Bits Identifier Type Value Description Clear Condition ’1’= error sequence authentication process. Reserved for application specific commands. [1:0] Reserved for manufacturer test mode. Note: 18, 17, 7 bits are only for MMC. 14, 3 bits are only for SD memory. SD status register The SD Status contains status bits that are related to the SD Memory Card proprietary features and may be used for future application-specific usage.
Page 900 GD32F5xx User Manual Bits Identifier Type Value Description Clear Condition 448] ED_AREA area [447: SPEED_CLASS Speed class of the (See below) 440] card [439: PERFORMANCE_M Performance (See below) 432] move indicated by 1 [MB/s] step. [431: AU_SIZE Size of AU (See below) 428] [427:...
Page 901 GD32F5xx User Manual 00h: Class 0 01h: Class 2 02h: Class 4 03h: Class 6 04h: Class 10 05h–FFh: Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm and the value can be set by 1 [MB/sec] step. If the card does not move useing RUs, Pm should be considered as infinity.
Page 902 GD32F5xx User Manual 64 MB The maximum AU size, depends on the card capacity, is defined in Table 29-26. AU_SIZE field. The card can set any AU size specified in Table 29-27. Maximum AU size that is less than or equal to the maximum AU size. The card should set smaller AU size as possible. Table 29-27.
Page 903 GD32F5xx User Manual If ERASE_SIZE field is set to 0, this field shall be set to 0. ERASE_OFFSET This 2-bit field indicates the T and one of four values can be selected. This field is OFFSET meaningless if ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 29-30.
Page 904 GD32F5xx User Manual The SEND_OP_COND (CMD1 for MMC), SD_SEND_OP_COND (ACMD41 for SD memory), IO_SEND_OP_COND (CMD5 for SD I/O) command is designed to provide hosts with a mechanism to identify and reject cards which do not match the V range desired by the host. This is accomplished by the host sending the required V voltage window as the operand of this command.
Page 905 GD32F5xx User Manual – If ATA mode is supported, the CPU should select the ATA mode by setting the ATA bit (bit 4) in the EXT_CSD register slice 191(CMD_SET) to activate the ATA command set. The CPU selects the command set using the SWITCH (CMD6) command. –...
Page 906 GD32F5xx User Manual indicates whether the card can accept new data or whether the write process is still in progress). The host may deselect the card by issuing CMD7 (to select a different card) which will displace the card into the Disconnect State and release the DAT line without interrupting the write operation.
Page 907 GD32F5xx User Manual Blocks will be continuously transferred until a STOP_TRANSMISSION command (CMD12) is issued. The stop command has an execution delay due to the serial command transmission. The data transfer stops after the end bit of the stop command. When the last block of user area is read using CMD18, the host should ignore OUT_OF_RANGE error that may occur even the sequence is correct.
Page 908 GD32F5xx User Manual set. Note that the stream write command works only on a 1 bit bus configuration (on DAT0). If CMD20 is issued in other bus configurations, it is regarded as an illegal command. In order to sustain data transfer in stream mode of the card, the time it takes to receive the data (defined by the bus clock rate) must be less than the time it takes to program it into the main memory field (defined by the card in the CSD register).
Page 909 GD32F5xx User Manual main memory field (defined by the card in the CSD register). Therefore, the maximum clock frequency for stream read operation is given by the following formula: READ_BL_LEN -100*NSAC max read frequence = min (TRAN_SPEED, (28-3) TAAC*R2W_FACTOR TRAN_SPEED: Max bus clock frequency. READ_BL_LEN: Max read data block length.
Page 910 GD32F5xx User Manual protected blocks shall be erased. The WP_ERASE_SKIP status bit in the status register shall be set. As described above for block write, the card will indicate that an erase is in progress by holding DAT0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card.
Page 911 GD32F5xx User Manual The Password Card Lock/Unlock protection is described in Card Lock/Unlock operation. Card Lock/Unlock operation 29.6.9. The password protection feature enables the host to lock a card while providing a password, which later will be used for unlocking the card. The password and its size are kept in a 128- bit PWD and 8-bit PWD_LEN registers, respectively.
Page 912 GD32F5xx User Manual a password change, it contains the old password followed by the new password. Setting the password  Select a card (CMD7), if not previously selected.  Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the new password.
Page 913 GD32F5xx User Manual If the PWD content is equal to the sent password, then the card will be locked and the card- locked status bit will be set in the status register. If the password is not correct, then the LOCK_UNLOCK_FAILED error bit will be set in the status register.
Page 914 GD32F5xx User Manual SDIO_DAT[2] show the Read Wait mode about stop the SDIO_CLK and use SDIO_DAT[2]. Figure 29-12. Read wait control by stopping SDIO_CLK Figure 29-13. Read wait operation using SDIO_DAT[2] SDIO_CLK CMD52 DAT[3:0] Read data 1a Read data 1b 2 CLK 2 CLK DAT1...
Page 915 GD32F5xx User Manual checks the status of the request with a read and determines that the bus has now been released (BS=0). At this time, a read to function 2 is started. Once that single block read is completed, the resume is issued to function, causing the data transfer to resume (DF=1). Figure 29-14.
Page 916 GD32F5xx User Manual data transaction read cycles. Figure 29-15. Read Interrupt cycle timing Figure 29-16. Write interrupt cycle timing SDIO_CLK Command write data Response Command write data DAT0 Data DAT1 Data 2 CLK DAT1(mode) interrupt data interrupt When transferring multiple blocks of data in the 4-bit SD mode, a special definition of the interrupt period is required.
Page 917 GD32F5xx User Manual Figure 29-18. Multiple block 4-Bit write interrupt cycle timing CE-ATA specific operations 29.7.2. The CE-ATA device supports these specific operations: Receive command completion signal Send command completion disable signal The SDIO supports these operations only when SDIO_CMDCTL[14] is set. Command completion signal CE-ATA defines a command completion signal that the device uses to notify the host upon normal ATA command completion or when ATA command termination has occurred due to...
Page 918 GD32F5xx User Manual Figure 29-19. The operation for command completion disable signal...
Page 919 GD32F5xx User Manual 29.8. Register definition SDIO base address: 0x4001 2C00 Power control register (SDIO_PWRCTL) 29.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. PWRCTL[1:0] SDIO power control bits.
Page 920 GD32F5xx User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division between the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL 30:15 Reserved Must be kept at reset value. HWCLKEN Hardware Clock Control enable bit If this bit is set, hardware controls the SDIO_CLK on/off depending on the system...
Page 921 GD32F5xx User Manual Command argument register (SDIO_CMDAGMT) 29.8.3. Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits...
Page 922 GD32F5xx User Manual NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used when CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
Page 923 GD32F5xx User Manual Command index response register (SDIO_RSPCMDIDX) 29.8.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RSPCMDIDX[5:0] Last response command index Read-only bits field.
Page 924 GD32F5xx User Manual Register Short response Long response SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 Data timeout register (SDIO_DATATO) 29.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits...
Page 925 GD32F5xx User Manual starts, the data counter loads this register and starts decrement. If block data transfer selected, the content of this register must be a multiple of the block Note: size (refer to SDIO_DATACTL). The data timer register and the data length register must be updated before being written to the data control register when need a data transfer.
Page 926 GD32F5xx User Manual 0101: block size = 2 = 32 bytes 0110: block size = 2 = 64 bytes 0111: block size = 2 = 128 bytes 1000: block size = 2 = 256 bytes 1001: block size = 2 = 512 bytes 1010: block size = 2 = 1024 bytes...
Page 927 GD32F5xx User Manual Bits Fields Descriptions 31:25 Reserved Must be kept at reset value. 24:0 DATACNT[24:0] Data count value Read-only bits field. When these bits are read, the number of remaining data bytes to be transferred is returned. Status register (SDIO_STAT) 29.8.11.
Page 928 GD32F5xx User Manual Transmit FIFO is full Receive FIFO is half full: at least 8 words can be read in the FIFO Transmit FIFO is half empty: at least 8 words can be written into the FIFO RXRUN Data reception in progress TXRUN Data transmission in progress CMDRUN...
Page 929 GD32F5xx User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag. 21:11 Reserved Must be kept at reset value.
Page 930 GD32F5xx User Manual This register has to be accessed by word(32-bit) ATAENDI SDIOINTI RXDTVA TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE CMDRUN DTBLKE CMDSEN CMDREC DTTMOU CMDTMO DTCRCE CCRCER RFHIE TFHIE RXRUNIE TXRUNIE STBITEIE DTENDIE RXOREIE TXUREIE NDIE UTIE RRIE Bits Fields Descriptions 31:24...
Page 931 GD32F5xx User Manual Write 1 to this bit to enable the interrupt. DTBLKENDIE Data block end interrupt enable Write 1 to this bit to enable the interrupt. STBITEIE Start bit error interrupt enable Write 1 to this bit to enable the interrupt. DTENDIE Data end interrupt enable Write 1 to this bit to enable the interrupt.
Page 932 GD32F5xx User Manual 31:24 Reserved Must be kept at reset value. 23:0 FIFOCNT[23:0] FIFO counter. These bits define the remaining number words to be written or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is word- aligned or SDIO_DATALEN[24:2]+1 if SDIO_DATALEN is not word-aligned) when DATAEN is set, and start count decrement when a word write to or read from the FIFO.
Page 933 GD32F5xx User Manual External memory controller (EXMC) 30.1. Overview The external memory controller EXMC, is used to access a variety of external memories. By configuring the related registers, it can automatically convert AMBA memory access protocol into a specific memory access protocol, such as SRAM, PSRAM, ROM and NOR Flash. Users can also adjust the timing parameters in the configuration registers to improve memory access efficiency.
Page 934 GD32F5xx User Manual Figure 30-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NOR- SDRAM NAND-Flash/PC Card Flash/PSRAM Controller Controller Controller NAND NOR/PSRAM PC Card Shared NOR/ PSRAM/ SDRAM Pins /NAND Pins Pins...
Page 935 GD32F5xx User Manual External device address mapping 30.3.3. Figure 30-2. EXMC memory banks Address Banks Supported memory type 0x6000 0000 NOR/PSRAM Bank0(4x64M) SQPI-PSRAM 0x6FFF FFFF 0x7000 0000 Bank1(256M) 0x7FFF FFFF NAND 0x8000 0000 Bank2(256M) 0x8FFF FFFF 0x9000 0000 Bank3(256M) PC Card 0x9FFF FFFF 0xC000 0000 SDRAM Device0...
Page 936 GD32F5xx User Manual four regions. Figure 30-3. Four regions of bank0 address mapping HADDR[27:26] Address Regions Supported memory type 0x60000000 NOR/PSRAM0 Region0 SQPI-PSRAM 0x63FF FFFF 0x64000000 Region1 NOR/PSRAM1 0x67FF FFFF 0x68000000 NOR/PSRAM2 Region2 0x6BFF FFFF 0x6C000000 Region3 NOR/PSRAM3 0x6FFF FFFF HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency.
Page 937 GD32F5xx User Manual EXMC Memory Memory Space Address Bank 0x7000_0000 Common Memory Space 0x73FF_FFFF Bank1 0x7800_0000 Attribute Memory Space 0x7BFF_FFFF 0x8000_0000 Common Memory Space 0x83FF_FFFF Bank2 0x8800_0000 Attribute Memory Space 0x8BFF_FFFF 0x9000_0000 Common Memory Space 0x93FF_FFFF 0x9800_0000 Bank3 Attribute Memory Space 0x9BFF_FFFF 0x9C00_0000...
Page 938 GD32F5xx User Manual  When HADDR [17:16] = 01, the command area is selected.  When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as follows. ...
Page 939 GD32F5xx User Manual Maximum memory Memory width Internal bank Row address Column address capacity 256 Mbytes: 32-bit HADDR[27:26] HADDR[25:13] HADDR[12:2] 4 x 8K x 2K x 4 NOR/PSRAM controller 30.3.4. NOR/PSRAM memory controller controls bank0, which is designed to support NOR Flash, PSRAM, SRAM, ROM and honeycomb RAM external memory.
Page 940 GD32F5xx User Manual Table 30-3. PSRAM non-muxed signal description EXMC Pin Direction Mode Functional description EXMC_CLK Output Sync Clock signal for sync EXMC_A[25:0] Output Async/Sync Address Bus EXMC_D[15:0] Input/output Async/Sync Data Bus EXMC_NE[x] Output Async/Sync Chip selection, x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE...
Page 941 GD32F5xx User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Async Use of byte lanes Async EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses PSRAM Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync...
Page 942 GD32F5xx User Manual Parameter Function Access mode Unit DLAT Data latency Sync EXMC_CLK BUSLAT Bus latency Async/Sync read HCLK DSET Data setup time Async HCLK AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 30-7. EXMC_timing models Timing Extend Write timing...
Page 943 GD32F5xx User Manual when NOR flash synchronous access is performed, EXMC_CLK will be generated. If CCK is set to 1, EXMC_CLK will be generated unconditionally whether the NOR flash is accessed in synchronous or asynchronous mode. Asynchronous access timing diagram Mode 1 - SRAM/CRAM Figure 30-7.
Page 944 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value NRWTEN Depends on user NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN No effect Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx...
Page 945 GD32F5xx User Manual Figure 30-10. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET HCLK) (WDSET HCLK) The different between mode A and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode A write timing configuration is independent of its read configuration.
Page 946 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30...
Page 947 GD32F5xx User Manual Figure 30-12. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET HCLK) (DSET HCLK) Figure 30-13. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 948 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value NREN Depends on memory NRTP 0x2, NOR Flash NRMUX NRBKEN EXMC_SNTCFGx(Read and write in mode 2,read in mode B) 31-30 Reserved 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to...
Page 949 GD32F5xx User Manual Figure 30-14. Mode C read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time (ASET HCLK) (DSET HCLK) Figure 30-15. Mode C write access Address (EXMC_A[25:0]) Chip Enable...
Page 950 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN Depends on memory NRTP 0x2, NOR Flash NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 29-28 ASYNCMOD Mode C:0x2 27-24 DLAT 23-20...
Page 951 GD32F5xx User Manual Figure 30-16. Mode D read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time (ASET HCLK) (AHLD HCLK) (DSET HCLK) Figure 30-17.
Page 952 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value NREN Depends on memory Depends on memory NRTP Depends on memory NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 29-28 ASYNCMOD Mode D:0x3 Don’t care 27-24 DLAT 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge...
Page 953 GD32F5xx User Manual Figure 30-18. Multiplex mode read access Address Address[25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Mux Address[15:0] Memory Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time (ASET HCLK) (AHLD HCLK) (DSET HCLK) Figure 30-19.
Page 954 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value NREN Depends on memory NRTP 0x2:NOR Flash NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT No effect 23-20 CKDIV No effect Minimum time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user(DSET HCLK for...
Page 955 GD32F5xx User Manual Figure 30-20. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Output Enable (EXMC_NOE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 4 HCLK Figure 30-21.
Page 956 GD32F5xx User Manual For specification of NOR Flash includes the EXMC_NADV cycle, their relationship should be: NOR Flash latency=DLAT+3 (30-7) Note: During read access, the data latency is determined by both DLAT in the EXMC_SNTCFGx register and LATDEC in the EXMC_SNLATDECx registers. For details, see SRAM/NOR flash data latency decrease registers (EXMC_SNLATDECx) (x=0, 1, 2, 2.
Page 957 GD32F5xx User Manual Read timing of synchronous multiplexed burst mode - NOR, PSRAM (CRAM) Figure 30-22. Read timing of synchronous multiplexed burst mode HCLK Clock (EXMC_CLK) Address Address[25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Wait (EXMC_NWAIT)
Page 958 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1,EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge 15-8 DSET No effect AHLD No effect ASET No effect EXMC_SNLATDECx 31-3 Reserved...
Page 959 GD32F5xx User Manual Bit Position Bit Name Reference Setting Value NRWTCFG 0x0(Here must be zero) WRAPEN NTWTPOL Depends on memory SBRSTEN No effect Reserved NREN NRTP NRMUX 0x1, Depends on users NRBKEN EXMC_SNTCFGx(Write) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1,EXMC_CLK=2HCLK...
Page 960 GD32F5xx User Manual Set address bit number by the ADRBIT bit, and set command bit number by CMDBIT bit. 2. Read/Write operation Three modes of memory access are supported, SPI, QPI, and SQPI. Access mode should be configured before read/write operation. Read/write command mode is set by the RMODE bit and WMODE bit.
Page 961 GD32F5xx User Manual the clock, chip-enable, and 4 bits data IO lines. As shown in the diagram below, the command is first sent serially through the data[0] output line, which sets the external memory operating mode, and then the 4 data IO lines output the parallel address and read/write datas. The following SQPI-PSRAM waveforms are configured with: ADRBIT[4:0] = 24, CMDBIT[1:0] = 1 (can be different)
Page 962 GD32F5xx User Manual NAND flash or PC card controller 30.3.5. EXMC has partitioned Bank1 and Bank2 as NAND Flash access field, bank3 as PC Card access field. Each bank has its own set of control register for access timing configuration. 8- and 16-bit NAND Flash and 16-bit PC Card are supported.
Page 963 GD32F5xx User Manual Memory Mode AHB transaction size Comments Async Automatically split into 2 EXMC Async accesses Async Automatically split into 4 EXMC Async accesses Async Async Not support this operation 16-bit Async NAND/PC Card Async Async Automatically split into 2 EXMC Async accesses NAND flash or PC card controller timing...
Page 964 GD32F5xx User Manual controller Clock (EXMC_CLK) Address (EXMC_A[25:0]) Chip Enable (EXMC_NCE) EXMC_NREG EXMC_NIORD EXMC_NIOWR EXMC_NWR EXMC_NOE Write Data Read Data Valid COMSETx + 1 HCLK COMHLDx HCLK COMHIZx HCLK COMWAITx + 1 HCLK NAND Flash operation When EXMC sends command or address to NAND Flash, it needs to use the command latch signal (A [16]) or address latch signal (EXMC_A [17]), namely, the CPU needs to perform write operation in particular address.
Page 965 GD32F5xx User Manual Taking TOSHIBA128 M x 8 bit NAND Flash as an example: Figure 30-28. Access to none "NCE don’t care" NAND Flash Chip Enable (EXMC_NCE) Command Latch Enable (EXMC_A[16]) Address Latch Enable (EXMC_A[17]) Write Enable (EXMC_NWE) Output Enable (EXMC_NOE) Data CMD 0...
Page 966 GD32F5xx User Manual PC/CF card access EXMC Bank3 is used exclusively for PC/CF Card, both memory and IO mode access are supported. This bank is divided further into three sub spaces, memory, attribute and IO space. EXMC_NCE3_0 and EXMC_NCE3_1 are the byte select signals, when only EXMC_NCE3_0 is active (Low), the lower byte or upper byte is selected depending on the EXMC_A[0], while only EXMC_NCE3_1 is active (Low), the upper byte is selected which is not supported, when both of these signals are active, 16-bit operation is performed.
Page 967 GD32F5xx User Manual SDRAM controller 30.3.6. Characteristics  Two independent SDRAM devices  8-,16- or 32-bit data bus width  Up to 13-bits Row Address, 11-bits Column Address and 2-bits internal banks address  Supported memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB) and 4x16Mx8bit (64 MB) ...
Page 968 GD32F5xx User Manual SDRAM control register EXMC_SDCTLx. Due to the volatile nature of SDRAM, periodic refresh cycle is necessary to maintain the stored information. Two refresh mode could be selected, self-refresh and auto-refresh mode. Self-refresh mode is typically set in low power mode when EXMC is suspended, refresh is provided by the SDRAM and timed by its internal counter.
Page 969 GD32F5xx User Manual Figure 30-29. SDRAM controller block diagram D[31:0] WADDR FIFO NBL[3:0] WDATA REFRESH SDCK FIFO TIMER GENERATOR ref_req ref_ok RADDR FIFO AHBS_IF_MEM ack_req ack_ok RDATA SDNE[1:0] FIFO EXTERNAL COMMAND SDRAM rw_req TIMERS ACTIVE rw_ok CACHE SIGNAL pre_req ADDRESS GENERATOR DECODE pre_ok...
Page 970 GD32F5xx User Manual A[n] A[10] A[m] Command Self-refresh when SDCKE = 0 Mode Mode Load mode register SDRAM controller operation sequence IO configuration SDRAMC IO port must be configured first to interface with external SDRAM, otherwise it is left as general purpose IOs, and could be utilized by other modules. IO ports related to SDRAM operations are summarized in the following table Table 30-22.
Page 971 GD32F5xx User Manual programed in EXMC_SDTCFG0, those corresponding bit position in EXMC_SDTCFG1 are reserved. Enable SDCLK: SDCLK enable command should be issued to the corresponding SDRAM devices, this is done by writing 0b001 to the CMD bits in the EXMC_SDCMD register, DS0 and DS1 selected which device will accept the command and start receiving EXMC_SDCLK.
Page 972 GD32F5xx User Manual Activate The activate command activates an idle bank. It presents a 2-bit bank address EXMC_A[15:14] and a 13-bit row address EXMC_A[12:0], and causes a read of that row into the bank’s array of 16,384 column sense amplifiers. This also known as opening the row. This operation has the side effect of refreshing the dynamic memory storage cells of that row.
Page 973 GD32F5xx User Manual Figure 30-30. Burst read operation Clock (EXMC_SDCLK) Address (EXMC_A[12:0]) Bank Address bank bank (EXMC_A[15:14]) Chip Enable (EXMC_SDNEx) Row Address Strobe (EXMC_NRAS) Column Address Strobe (EXMC_NCAS) Write Enable (EXMC_SDNWE) Data Data Data Data Data Data Data Data Data (EXMC_D[31:0]) RCD = 3 CL = 3...
Page 974 GD32F5xx User Manual The following diagram Figure 30-32. Burst write operation shows a write burst access to an inactive row, a row activation command is issued before write access. If write operations were performed on an active row, row address strobe is not necessary, only column address strobe is needed.
Page 975 GD32F5xx User Manual Figure 30-34. Read access when FIFO hit (BRSTRD=1) specify the Read FIFO operation. Figure 30-33. Read access when FIFO not hit (BRSTRD=1, CL=2, SDCLK=2, PIPED=2) AHB Master IF Read @0x0 Data0 @0x0 Data1 Data2 Data3 @0x4 @0x8 @0xC Read FIFO Data1 @0x4...
Page 976 GD32F5xx User Manual up this record and decide whether to generate the Active/Precharge commands or not. Before read/write operation, the targeted row must be activated, the value of EXMC_A[15:14] selects the bank, and EXMC_A[12:0] select the row. The selected row remains active until a precharge command is issued.
Page 977 GD32F5xx User Manual Precharge the current active row. Next row’s activation. Read/write access. Precharge delay (PRD) and row to column delay (RCD) are added according to their configuration in EXMC_SDTCFGx register, other timing parameters should be configured as SDRAM specification requires. When this boundary happens to be at the end of a bank, two cases are possible: When the current bank is not the last bank, the activation of the first row of the next bank is performed, and this supports all row, column, and bus width configuration.
Page 978 GD32F5xx User Manual If an auto-refresh request occurs when the SDRAM controller is in power-down mode, the SDRAM controller returns to normal mode, issues the Precharge all and Auto-Refresh command sequence, and enters power-down mode again automatically. Figure 30-38. Process for power-down entry and exit Clock (EXMC_SDCLK) Clock Enable...
Page 979 GD32F5xx User Manual 30.4. Register definition EXMC base address: 0xA000 0000 NOR/PSRAM controller registers 30.4.1. SRAM/NOR flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, 3) Reset value: 0x0000 30DA This register has to be accessed by word (32-bit).
Page 980 GD32F5xx User Manual EXMODEN Extended mode enable 0: Disable extended mode 1: Enable extended mode NRWTEN NWAIT signal enable For flash memory access in burst mode, this bit enables/disables wait-state insertion to the NWAIT signal. 0: Disable NWAIT signal 1: Enable NWAIT signal Write enable 0: Disable write in the bank by the EXMC, otherwise an AHB error is reported 1: Enable write in the bank by the EXMC (default after reset)
Page 981 GD32F5xx User Manual 1: Enable address/data multiplexing function NRBKEN NOR region enable 0: Disable the corresponding memory bank 1: Enable the corresponding memory bank SRAM/NOR flash timing configuration registers (EXMC_SNTCFGx) (x=0, 1, 2, 3) Address offset: 0x04 + 8 * x, (x = 0, 1, 2, 3) Reset value: 0x0FFF FFFF This register has to be accessed by word(32-bit) Reserved...
Page 982 GD32F5xx User Manual 0x0: Bus latency = 0 * HCLK period 0x1: Bus latency = 1 * HCLK period …… 0xF: Bus latency = 15 * HCLK period 15:8 DSET[7:0] Data setup time This field is meaningful only in asynchronous access. 0x00: Reserved 0x01: Data setup time = 1 * HCLK period ……...
Page 983 GD32F5xx User Manual 29:28 WASYNCMOD[1:0] Asynchronous access mode The bits are valid only when the EXMEN bit in the EXMC_SNCTLx register is 1. 00: Mode A access 01: Mode B access 10: Mode C access 11: Mode D access 27:20 Reserved Must be kept at reset value.
Page 984 GD32F5xx User Manual This register is meaningful only in synchronous access. This register has to be accessed by word(32-bit) Reserved Reserved LATDEC[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. LATDEC[2:0] Data latency decrease for NOR Flash. Only valid in synchronous read access. This field is used to adjust read access time along with DLAT.
Page 985 GD32F5xx User Manual 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0] ALE to RE delay 0x0: ALE to RE delay = 1 * HCLK ……...
Page 986 GD32F5xx User Manual NAND flash/PC card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1,2, and 3) Reset value: 0x0000 0042 (for bank1 and bank2), 0x0000 0040 (for bank3) This register has to be accessed by word(32-bit) Reserved Reserved FFEPT...
Page 987 GD32F5xx User Manual NAND flash/PC card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFFFFFFFF These operations applicable to common memory space for 16-bit PC Card, CF card and NAND Flash.
Page 988 GD32F5xx User Manual 0x00: COMSET = 1 * HCLK …… 0xFE: COMSET = 255 * HCLK 0xFF: Reserved NAND flash/PC card attribute space timing configuration registers (EXMC_NPATCFGx) (x=1, 2, 3) Address offset: 0x4C + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFFFFFFFF It is used for 8-bit accesses to the attribute memory space of the PC Card or to access the NAND Flash for the last address write access if another timing must be applied.
Page 989 GD32F5xx User Manual 0xFE: ATTWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: ATTWAIT = Reserved ATTSET[7:0] Attribute memory setup time Define the time to build address before sending command 0x00: ATTSET = 1 * HCLK …… 0xFE: ATTSET = 255 * HCLK 0xFF: Reserved PC card I/O space timing configuration register (EXMC_PIOTCFG3) Address offset: 0xB0...
Page 990 GD32F5xx User Manual IOSET[7:0] IO space setup time Define the time to build address before sending command 0x00: IOSET = 1 * HCLK …… 0xFF: IOSET = 256 * HCLK NAND flash ECC registers (EXMC_NECCx) (x=1, 2) Address offset: 0x54+0x20 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 991 GD32F5xx User Manual Reserved PIPED[1:0] BRSTRD SDCLK[1:0] WPEN CL[1:0] SDW[1:0] RAW[1:0] CAW[1:0] Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. 14:13 PIPED[1:0] Pipeline delay These bits specify the delay for reading data after CAS latency in HCLK clock cycles.
Page 992 GD32F5xx User Manual Number of banks This bit specifies the number of internal banks. 0: 2 internal Banks 1: 4 internal Banks SDW[1:0] SDRAM data bus width. These bits specify the SDRAM memory data width. 00: 8 bits 01: 16 bits 10: 32 bits 11: reserved RAW[1:0]...
Page 993 GD32F5xx User Manual Bits Fields Descriptions 0x0: 1 cycle. 0x1: 2 cycles ..0xF: 16 cycles 23:20 RPD[3:0] Row precharge delay These bits specify the delay between a precharge command and the next command in SDRAM memory clock cycle unit. 0x0: 1 cycle 0x1: 2 cycles ..
Page 994 GD32F5xx User Manual Bits Fields Descriptions 0x0: 1 cycle 0x1: 2 cycles ..0xF: 16 cycles XSRD[3:0] Exit self-refresh delay These bits specify the delay from a self-refresh command to an activate command in SDRAM memory clock cycle unit. 0x0: 1 cycle 0x1: 2 cycles ……...
Page 995 GD32F5xx User Manual 0x0: 1 Auto-refresh cycle 0x1: 2 Auto-refresh cycles ..0xE: 15 Auto-refresh cycles 0xF: Reserved Device select 0 This bit indicates whether the SDRAM Device0 is selected or not. 0: SDRAM Device0 is not selected 1: SDRAM Device0 is selected Device select 1 This bit indicates whether the SDRAM Device1 is selected or not.
Page 996 GD32F5xx User Manual 31:15 Reserved Must be kept at reset value. REIE Refresh error interrupt enable 0: Disable 1: Enable. An interrupt is generated if REIF bit of the status register is set 13:1 ARINTV[12:0] Auto-refresh interval This bit field specifies the interval of two successive auto-refresh commands in memory clock cycle unit.
Page 997 GD32F5xx User Manual 00: Normal status 01: Self-refresh status 10: Power-down status REIF Refresh error interrupt flag 0: No refresh error 1: A refresh error occurred. An interrupt is generated when REIE = 1. SDRAM read sample control register (EXMC_SDRSCTL) Address offset: 0x180 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 998 GD32F5xx User Manual This register has to be accessed by word (32-bit) IDL[1:0] ADRBIT[4:0] Reserved CMDBIT[1:0] Reserved Bits Fields Descriptions Read data sample polarity. 0: Sample data at rising edge(default) 1: Sample data at falling edge. 30:29 IDL[1:0] SPI PSRAM ID Length. 00:64-bit 01:32-bit 10:16-bit...
Page 999 GD32F5xx User Manual RDID Reserved RMODE[1:0] RWAITCYCLE[3:0] RCMD[15:0] Bits Fields Descriptions RDID Send SPI Read ID Command, command code and mode come from RCMD and RMODE. 30:22 Reserved Must be kept at reset value. 21:20 RMODE[1:0] SPI PSRAM read command mode 00: Not SPI mode 01: SPI mode 10: SQPI mode...
Page 1000 GD32F5xx User Manual 21:20 WMODE[1:0] SPI PSRAM write command mode 00: Not SPI mode 01: SPI mode 10: SQPI mode 11: QPI mode 19:16 WWAITCYCLE[3:0] SPI write wait cycle number after address phase 15:0 WCMD[15:0] SPI write command for AHB write transfer Note: Before write 1 to SC bit, you must ensure it is cleared and after set SC to 1, you must wait SC cleared.

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