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Manuals and User Guides for GigaDevice Semiconductor GD32H75E. We have
1
GigaDevice Semiconductor GD32H75E manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32H75E User Manual (1632 pages)
Arm Cortex-M7 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 13 MB
Table of Contents
Table of Contents
2
List of Figures
29
List of Tables
41
System and Memory Architecture
46
Arm ® Cortex ® -M7 Processor
46
System Architecture
47
Figure 1-1. the Structure of the Cortex
47
Table 1-1. the Interconnection Relationship of the Interconnect Matrix
48
Figure 1-2. the System Architecture of GD32H75E Devices
49
Bus Matrix Region 0
50
Bus Matrix Region 1
50
Figure 1-3. Bus Matrix Region 0
50
Bus Matrix Region 2
51
Figure 1-4. Bus Matrix Region 1
51
Figure 1-5. Bus Matrix Region 2
51
Memory Map
52
Table 1-2. Memory Map of GD32H75E Devices
52
On-Chip SRAM Memory
60
Figure 1-6. Block Digram of AXI SRAM Controller
60
Figure 1-7. Block Digram of RAM Shared by ITCM/DTCM/AXI SRAM
61
Table 1-3. Configuration of ITCM/DTCM/AXI SRAM
61
On-Chip Flash Memory Overview
62
Boot Configuration
62
Table 1-4. Boot Mode Selection
62
System Configuration Controller (SYSCFG)
63
Table 1-5. Details of Boot Mode
63
Timer Break Input Lock
64
AXI Interconnect Matrix (AXIIM)
64
Characteristics
64
Function Overview
64
Figure 1-8. Block Diagram of AXI Interconnect Matrix
64
Table 1-6. Configuration of Asibs
65
Table 1-7. Configuration of Amibs
65
System Configuration Registers
66
Peripheral Mode Configuration Register (SYSCFG_PMCFG)
66
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
67
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
69
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
70
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
71
Lockup Control Register (SYSCFG_LKCTL)
72
I/O Compensation Control Register (SYSCFG_CPSCTL)
74
I/O Compensation Cell Code Configuration Register (SYSCFG_CPSCCCFG)
75
Timer Input Selection Register 0 (SYSCFG_TIMERCISEL0)
75
Timer Input Selection Register 1 (SYSCFG_TIMERCISEL1)
77
Timer Input Selection Register 2 (SYSCFG_TIMERCISEL2)
78
Timer Input Selection Register 3 (SYSCFG_TIMERCISEL3)
79
Timer Input Selection Register 5 (SYSCFG_TIMERCISEL5)
80
Timer Input Selection Register 6 (SYSCFG_TIMERCISEL6)
82
CPU ICACHE Error Status Register(SYSCFG_CPUICAC)
84
CPU DCACHE Error Status Register (SYSCFG_CPUDCAC)
84
FPU Interrupt Enable Register (SYSCFG_FPUINTEN)
85
SRAM Configuration Register 0 (SYSCFG_SRAMCFG0)
86
SRAM Configuration Register 1 (SYSCFG_SRAMCFG1)
86
Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=0, 7)
87
Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=0, 7)
89
Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=0, 7)
91
Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=1, 2, 3, 4, 22, 23)
92
Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=1, 2, 3, 4, 22, 23)
95
Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=1, 2, 3, 4, 22, 23)
97
Timerx Configuration Register 0 (Syscfg_Timerxcfg0, X=14, 40, 41, 42, 43, 44)
98
Timerx Configuration Register 1 (Syscfg_Timerxcfg1, X=14, 40, 41, 42, 43, 44)
100
Timerx Configuration Register 2 (Syscfg_Timerxcfg2, X=14, 40, 41, 42, 43, 44)
101
User Configuration Register (SYSCFG_USERCFG)
102
AXI Interconnect Registers
103
AXI Peripheral ID4 Register (AXI_PERIPH_ID4)
103
AXI Peripheral ID0 Register (AXI_PERIPH_ID0)
103
AXI Peripheral ID1 Register (AXI_PERIPH_ID1)
104
AXI Peripheral ID2 Register (AXI_PERIPH_ID2)
104
AXI Peripheral ID3 Register (AXI_PERIPH_ID3)
105
AXI Componet ID0 Register (AXI_COMP_ID0)
105
AXI Componet ID1 Register (AXI_COMP_ID1)
106
AXI Componet ID2 Register (AXI_COMP_ID2)
106
AXI Componet ID3 Register (AXI_COMP_ID3)
106
AXI Master Port X Bus Matrix Issuing Functionality Control Register (Axi_Mpxbm_Iss_Ctl)
107
AXI Master Port X Bus Matrix Functionality Control Register (Axi_Mpxbm_Ctl)
107
AXI Master Port X Long Burst Functionality Control Register (Axi_Mpx_Lb_Ctl)
108
AXI Master Port X Issuing Functionality Control Register (Axi_Mpx_Iss_Ctl)
108
AXI Slave Port X Functionality Control Register (Axi_Spx_Ctl)
109
AXI Slave Port X AHB Issuing Functionality Control Register (Axi_Spx_Ahbiss_Ctl)
109
AXI Slave Port X Read QOS Control Register (Axi_Spx_Rdqos_Ctl)
110
AXI Slave Port X Write QOS Control Register (Axi_Spx_Wrqos_Ctl)
111
AXI Slave Port X Issuing Functionality Control Register (Axi_Spx_Iss_Ctl)
111
Device Electronic Signature
112
Memory Density Information
112
Unique Device ID (96 Bits)
112
RAM ECC Monitor Unit (RAMECCMU)
114
Characteristics
114
Function Overview
114
Figure 2-1. Block Architecture of RAMECCMU
114
Table 2-1. RAMECC Monitor X Unit for Region 0 (X=0
115
Table 2-2. RAMECC Monitor X Unit for Region 1 (X=0
115
Register Definition
116
RAMECCMU Global Interruput Register (RAMECCMU_INT)
116
RAMECCMU Monitor X Control Register (Rameccmu_Mxctl)
116
Flash Memory Controller (FMC)
121
Flash Memory Architecture
121
Figure 3-1. FMC Block Diagram
121
Table 3-1. GD32H75E Base Address and Size for Flash Memory
122
Read Operations
122
Sector Erase
124
Figure 3-2. Proccess of Sector Erase Operation
124
Mass Erase
125
Figure 3-3. Process of Typical Mass Erase Operation
126
Figure 3-4. Process of Protection-Removed Mass Erase Operation
127
Figure 3-5. Proccess of Program Operation
129
Option Bytes Description
130
Table 3-2. Option Byte
131
Table 3-3. WP Bit for Sectors Protected
134
Security Protection
134
Table 3-4. SPC Protection Level Configuration
136
Table 3-5. DCRP Area Configuration
137
Table 3-6. Secure User Area Configuration
139
Figure 3-6. Memory Architecture in Standard Mode and Secure Mode
140
Table 3-7. Function Resetandinitializesecureareas
141
Table 3-8. Function Exitsecurearea
141
Error Description
142
Table 3-9 FMC Interrupt Requests
144
Register Definition
145
Function Overview
164
Figure 4-1. Block Diagram of EFUSE Controller
164
Table 4-1. System Parameters
167
Read Operation
168
Program Operation
169
Table 4-2. EFUSE Interrupt Requests
170
Figure 4-2 EFUSE Interrupt Mapping Diagram
171
Register Definition
172
Figure 5-1. Power Supply Overview
183
Backup Domain
184
Figure 5-2. Waveform of the Backup Domain Voltage Thresholds
185
Figure 5-3. Waveform of the por / PDR
186
Figure 5-4. Waveform of the BOR
186
Figure 5-5. Waveform of the LVD Threshold
187
Figure 5-6. Waveform of the VAVD Threshold
188
Figure 5-7. Temperature Thresholds
189
Power Domain
189
Power Supply
189
Figure 5-8. LDO Supplies for 0.9V Power Domain
190
Figure 5-9. SMPS Supplies for 0.9V Power Domain
190
Figure 5-10. SMPS Supplies for LDO, LDO Supplies for 0.9V Power Domain
191
Figure 5-11. SMPS Supplies for LDO and External, LDO Supplies for 0.9V Power Domain
192
Figure 5-12. SMPS Supplies for External, External Supplies for 0.9V Power Domain
192
Figure 5-13. Bypass
193
Table 5-1. Supply Mode
193
Figure 5-14. Waveform of the VOVD
194
Power-Saving Modes
194
Sleep Mode
194
Deep Sleep Mode
195
Table 5-2. Power Saving Mode Summary
196
Register Definition
197
Reset and Clock Unit (RCU)
206
Reset Control Unit (RCTL)
206
Overview
206
Function Overview
206
Power Reset
206
System Reset
206
Figure 6-1. the System Reset Circuit
207
Backup Domain Reset
207
Clock Control Unit (CCTL)
207
Overview
207
Figure 6-2. Clock Tree
208
Characteristics
210
Function Overview
211
Figure 6-3. HXTAL Clock Source
211
Figure 6-4. HXTAL Clock Source in Bypass Mode
211
Phase Locked Loop (PLL)
213
System Clock (CK_SYS) Selection
214
Clock Output Capability
215
Table 6-1. Clock Output 0 Source Select
215
Table 6-2. Clock Output 1 Source Select
216
Register Definition
217
Control Register (RCU_CTL)
217
PLL0 Register (RCU_PLL0)
219
Clock Configuration Register 0 (RCU_CFG0)
221
Clock Interrupt Register (RCU_INT)
223
AHB1 Reset Register (RCU_AHB1RST)
226
AHB2 Reset Register (RCU_AHB2RST)
227
AHB3 Reset Register (RCU_AHB3RST)
228
AHB4 Reset Register (RCU_AHB4RST)
229
APB1 Reset Register (RCU_APB1RST)
230
APB2 Reset Register (RCU_APB2RST)
234
APB3 Reset Register (RCU_APB3RST)
236
APB4 Reset Register (RCU_APB4RST)
237
AHB1 Enable Register (RCU_AHB1EN)
238
AHB2 Enable Register (RCU_AHB2EN)
239
AHB3 Enable Register (RCU_AHB3EN)
240
AHB4 Enable Register (RCU_AHB4EN)
241
APB1 Enable Register (RCU_APB1EN)
243
APB2 Enable Register (RCU_APB2EN)
246
APB3 Enable Register (RCU_APB3EN)
248
APB4 Enable Register (RCU_APB4EN)
249
AHB1 Sleep Mode Enable Register (RCU_AHB1SPEN)
250
AHB2 Sleep Mode Enable Register (RCU_AHB2SPEN)
251
AHB3 Sleep Mode Enable Register (RCU_AHB3SPEN)
252
AHB4 Sleep Mode Enable Register (RCU_AHB4SPEN)
254
APB1 Sleep Mode Enable Register (RCU_APB1SPEN)
255
APB2 Sleep Mode Enable Register (RCU_APB2SPEN)
258
APB3 Sleep Mode Enable Register (RCU_APB3SPEN)
261
APB4 Sleep Mode Enable Register (RCU_APB4SPEN)
261
Backup Domain Control Register (RCU_BDCTL)
262
Reset Source/Clock Register (RCU_RSTSCK)
264
PLL Clock Additional Control Register (RCU_PLLADDCTL)
266
PLL1 Register (RCU_PLL1)
268
PLL2 Register (RCU_PLL2)
270
Clock Configuration Register 1 (RCU_CFG1)
272
Clock Configuration Register 2 (RCU_CFG2)
274
Clock Configuration Register 3 (RCU_CFG3)
276
PLL All Configuration Register (RCU_PLLALL)
277
PLL0 Fraction Configuration Register (RCU_PLL0FRA)
279
PLL1 Fraction Configuration Register (RCU_PLL1FRA)
279
PLL2 Fraction Configuration Register (RCU_PLL2FRA)
280
Additional Clock Control Register 0 (RCU_ADDCTL0)
281
Additional Clock Control Register 1(RCU_ADDCTL1)
282
Additional Clock Interrupt Register (RCU_ADDINT)
283
Clock Configuration Register 4 (RCU_CFG4)
285
USB Clock Control Register (RCU_USBCLKCTL)
285
Table 19-2
286
PLLUSB Configuration Register (RCU_PLLUSBCFG)
288
APB2 Additional Reset Register (RCU_ADDAPB2RST)
289
APB2 Additional Enable Register (RCU_ADDAPB2EN)
290
APB2 Additional Sleep Enable Register (RCU_ADDAPB2SPEN)
291
Clock Configuration Register 5 (RCU_CFG5)
291
Clock Trim Controller (CTC)
294
Overview
294
Characteristics
294
Function Overview
294
Figure 7-1. CTC Overview
294
REF Sync Pulse Generator
295
CTC Trim Counter
295
Frequency Evaluation and Automatically Trim Process
296
Figure 7-2. CTC Trim Counter
296
Software Program Guide
297
Register Definition
299
Control Register 0 (CTC_CTL0)
299
Control Register 1 (CTC_CTL1)
300
Status Register (CTC_STAT)
301
Interrupt Clear Register (CTC_INTC)
303
Interrupt / Event Controller (EXTI)
305
Overview
305
Characteristics
305
Interrupts Function Overview
305
Table 8-1. NVIC Exception Types in Cortex ® -M7
306
Table 8-2. Interrupt Vector Table
306
External Interrupt and Event (EXTI) Block Diagram
311
Figure 8-1. Block Diagram of EXTI
311
External Interrupt and Event Function Overview
312
Hardware Trigger
312
Software Trigger
312
Table 8-3. EXTI Source
313
Register Definition
314
Interrupt Enable Register 0 (EXTI_INTEN0)
314
Event Enable Register 0 (EXTI_EVEN0)
314
Rising Edge Trigger Enable Register 0 (EXTI_RTEN0)
314
Function Overview
320
Figure 9-1. TRIGSEL Main Composition Example
321
Table 9-1. Trigger Input Bit Fields Selection
321
Table 9-2. TRIGSEL Input and Output Mapping
325
Register Definition
331
Function Overview
362
Figure 10-1. Basic Structure of a Standard I/O Port Bit
363
Table 10-1. GPIO Configuration Table
363
GPIO Pin Configuration
364
Alternate Functions (AF)
365
Additional Functions
365
Figure 10-2. Input Configuration
365
Output Configuration
365
Figure 10-3. Output Configuration
366
Figure 10-4. Analog Configuration
366
Figure 10-5. Alternate Function Configuration
367
Figure 10-6. Analog Configuration for ADC
368
Input Filtering
368
Figure 10-7. Filtering Using the Sampling Window
369
Figure 10-8. Input Filtering Clock Cycle
371
Register Definition
372
Figure 11-1. Block Diagram of CRC Calculation Unit
389
Function Overview
389
Register Definition
391
Figure 12-1. TRNG Block Diagram
394
Post Processing
395
Table 12-1. ALGO Configurations
396
Operation Flow
398
Error Flags
398
Figure 13-1. TMU Block Diagram
405
Table 13-1. Input Data Configuration
406
Table 13-2. Output Data Configuration
407
Table 13-3. TMU Mode Configuration
407
Table 13-4. Mode 0 Description
407
Table 13-5. Mode 1 Description
409
Table 13-6. Mode 2 Description
410
Table 13-7. Mode 3 Description
411
Table 13-8. Mode 4 Description
412
Table 13-9. Mode 5 Description
412
Table 13-10. Mode 6 Description
413
Table 13-11. Mode 7 Description
414
Table 13-12. Mode 8 Description
415
Table 13-13. Recommended Scaling Factors in Mode 8
415
Table 13-14. Mode 9 Description
415
Table 13-15. Recommended Scaling Factors in Mode 9
416
Table 13-16. Precision Vs. Number of Iterations
416
Direct Memory Access Controller (DMA)
423
Function Overview
424
Figure 14-1. Block Diagram of DMA
424
Figure 14-2. Data Stream for Three Transfer Modes
425
Table 14-1. Transfer Mode
425
Figure 14-3. Handshake Mechanism
426
Data Process
426
Table 14-2. CNT Configuration
428
Table 14-3. FIFO Counter Critical Value Configuration Rules
429
Figure 14-4. Data Packing/Unpacking When PWIDTH = '00
430
Figure 14-5. Data Packing/Unpacking When PWIDTH = '01
431
Figure 14-6. Data Packing/Unpacking When PWIDTH = '10
431
Address Generation
431
Circular Mode
432
Figure 14-7. DMA Operation of Switch-Buffer Mode
433
Transfer Operation
433
Error Detection
435
Channel Configuration
435
Table 14-4. DMA Interrupt Events
436
Bus Error
439
Figure 14-8. System Connection of DMA0 and DMA1
440
DMA Request Mapping
440
Register Definition
441
Function Overview
453
Figure 15-1. Block Diagram of MDMA
453
Table 15-1. Transfer Mode
453
Figure 15-2. Connections of the Four Modes
454
Table 15-2. MDMA Hardware Request Sources
454
Figure 15-3. Word, Halfword, Byte Order Exchange
456
Figure 15-4. Data Padding and Alignment (Source Greater than Destination)
456
Figure 15-5. Data Padding and Alignment (Source Less than Destination)
457
Figure 15-6. Data Packing / Unpacking
458
Table 15-3. Source and Destination Address Generation Configuration
459
Transfer Modes
459
Block Transfer Mode
460
Table 15-4. Update Mode of Source and Destination Address
461
Table 15-5. Register Link Address
461
Transfer Status
462
Transfer Complete
462
Transfer Interrupt
462
Table 15-6. MDMA Error Flags
462
Table 15-7. MDMA Interrupt Events
463
Figure 15-7. MDMA Interrupt Logic
464
Register Definition
465
Figure 16-1. Block Diagram of DMAMUX
480
Signal Description
480
Function Overview
481
Figure 16-2. Synchronization Mode
482
Figure 16-3. Event Generation
483
Trigger Overrun
484
Channel Configurations
484
Table 16-1. Interrupt Events
485
Table 16-2. Request Multiplexer Input Mapping
486
Table 16-3. Trigger Input Mapping
491
Table 16-4. Synchronization Input Mapping
492
Register Definition
494
Request Multiplexer Channel X Configuration Register (Dmamux_Rm_Chxcfg)
494
Request Multiplexer Channel Interrupt Flag Register (DMAMUX_RM_INTF)
495
Request Multiplexer Channel Interrupt Flag Clear Register (DMAMUX_RM_INTC)
495
Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
496
Request Generator Channel Interrupt Flag Register (DMAMUX_RG_INTF)
497
Rquest Generator Channel Interrupt Flag Clear Register (DMAMUX_RG_INTC)
497
Debug (DBG)
499
Overview
499
JTAG / SW Function Overview
499
Switch JTAG or SW Interface
499
Pin Assignment
499
Jtag
500
Figure 17-1. Block Diagram of JTAG Unit
500
Table 17-1. Pin Assignment
500
Debug Reset
502
JEDEC-106 ID Code
502
Debug Hold Function Overview
502
Debug Support for Power Saving Mode
502
Debug Support for TIMER, I2C, WWDGT, FWDGT, RTC and CAN
502
Register Definition
504
ID Code Register (DBG_ID)
504
Control Register0 (DBG_CTL0)
504
Control Register1 (DBG_CTL1)
505
Control Register2 (DBG_CTL2)
506
Control Register3 (DBG_CTL3)
507
Control Register4 (DBG_CTL4)
509
Analog-To-Digital Converter (ADC)
511
Overview
511
Characteristics
511
Pins and Internal Signals
512
Figure 18-1. ADC Module Block Diagram
512
Table 18-1. ADC Internal Input Signals
512
Table 18-2. ADC Input Pins Definition
512
Function Overview
513
Foreground Calibration Function
513
Dual Clock Domain Architecture
514
ADC Enable
514
Single-Enden and Differential Input Channels
514
Table 18-3. ADC Differential Channel Pin Matching
515
Routine Sequence
516
Operation Modes
516
Figure 18-2. Single Operation Mode
516
Figure 18-3. Continuous Operation Mode
517
Figure 18-4. Scan Operation Mode, Continuous Disable
518
Figure 18-5. Scan Operation Mode, Continuous Enable
518
Figure 18-6. Discontinuous Operation Mode
519
Conversion Result Threshold Monitor Function
519
Analog Watchdog
519
Data Storage Mode
520
Sample Time Configuration
520
Figure 18-7. 14-Bit Data Storage Mode
520
Figure 18-8. 12-Bit Data Storage Mode
520
Figure 18-9. 6-Bit Data Storage Mode
520
External Trigger Configuration
521
Table 18-4. Trigger Source for Routine Channels for ADC0/ADC1/ADC2
521
DMA Request
521
Overflow Detection
521
Battery Voltage Monitoring
523
Table 18-5. T CONV Timings Depending on Resolution for ADC0 and ADC1
524
Table 18-6. T CONV Timings Depending on Resolution for ADC2
524
Figure 18-11. 20-Bit to 16-Bit Result Truncation (for 12Bit ADC)
525
Figure 18-12. Numerical Example with 5-Bits Shift and Rounding (for 12Bit ADC)
526
Figure 18-13. 14Bit ADC Oversampling with 10Bits Right Shift
526
Figure 18-14. Numerical Example for 14Bit ADC Oversampling with 10Bits Right Shift
526
Table 18-7. some Examples Show the Maximum Output Results for N and M Combimations
526
Table 18-8. ADC Sync Mode Table
527
Figure 18-15. ADC Sync Block Diagram
528
Free Mode
528
Figure 18-16. Routine Parallel Mode on 16 Channels
528
Figure 18-17. Routine Follow-Up Mode on 1 Channel in Continuous Operation Mode
529
ADC Interrupts
530
Register Definition
531
Digital-To-Analog Converter (DAC)
556
Figure 19-1. DAC Block Diagram
556
Table 19-1. DAC I/O Description
557
Function Description
558
Table 19-3. Triggers of DAC
558
Figure 19-2. DAC LFSR Algorithm
559
Figure 19-3. DAC Triangle Noise Wave
560
DAC Output Voltage
560
Normal Mode
562
Figure 19-4. DAC Sample and Keep
563
Table 19-4. Formula of Sample and Refresh Time
563
Standby Mode
564
Figure 20-1. Free Watchdog Block Diagram
580
Table 20-1. Min/Max FWDGT Timeout Period at 32Khz (IRC32K)
581
Figure 20-2. Window Watchdog Timer Block Diagram
586
Figure 20-3. Window Watchdog Timing Diagram
587
Table 20-2. Min-Max Timeout Value at 150 Mhz
588
Real Time Clock (Rtc)
591
Figure 21-1. Block Diagram of RTC
592
RTC Initialization and Configuration
594
RTC Register Write Protection
594
Calendar Initialization and Configuration
595
Daylight Saving Time
595
Resetting the RTC
597
RTC Reference Clock Detection
598
RTC Smooth Digital Calibration
598
Verifying the RTC Calibration
599
Re-Calibration On-The-Fly
600
Time-Stamp Function
600
Tamper Detection
600
Timestamp on Tamper Event
601
Calibration Clock Output
602
Alarm Output
602
Table 21-1 RTC Pin Configuration and Function
603
Table 21-2 RTC Power Saving Mode Management
603
Table 21-3 RTC Interrupts Control
604
Register Definition
605
Table 22-1. Timers (Timerx) Are Divided into Five Sorts
624
Figure 22-1. Advanced Timer Block Diagram
627
Table 22-2. Advanced Timer Channel Description
627
Clock Selection
627
Figure 22-2. Normal Mode, Internal Clock Divided by 1
628
Clock Prescaler
629
Up Counting Mode
629
Figure 22-3. Counter Timing Diagram with Prescaler Division Change from 1 to 2
629
Figure 22-4. Timing Diagram of up Counting Mode, PSC=0/2
630
Figure 22-5. Timing Diagram of up Counting Mode, Change Timerx_Car Ongoing
631
Figure 22-6. Timing Diagram of down Counting Mode, PSC=0/2
631
Figure 22-7. Timing Diagram of down Counting Mode, Change Timerx_Car Ongoing
632
Figure 22-8. Timing Diagram of Center-Aligned Counting Mode
633
Figure 22-9. Repetition Counter Timing Diagram of Center-Aligned Counting Mode
635
Figure 22-10. Repetition Counter Timing Diagram of up Counting Mode
635
Figure 22-11. Repetition Counter Timing Diagram of down Counting Mode
636
Capture/Compare Channels
636
Figure 22-12. Input Capture Logic for Channel 0
637
Figure 22-13. Input Capture Logic for Multi Mode Channel 0
637
Output Compare Mode
638
Figure 22-14. Output Compare Logic (When Mchxmsel = 2'00, X=0, 1, 2, 3)
638
Figure 22-15. Output Compare Logic (When Mchxmsel = 2'11, X=0,1,2,3)
639
Figure 22-16. Output-Compare in Three Modes
641
Figure 22-17. Timing Diagram of EAPWM
641
Figure 22-18. Timing Diagram of CAPWM
641
Table 22-3.The Composite PWM Pulse Width
643
Figure 22-19. Channel X Output PWM with (Chxval < Chxcomval_Add)
644
Figure 22-20. Channel X Output PWM with (Chxval = Chxcomval_Add)
644
Figure 22-21. Channel X Output PWM with (Chxval > Chxcomval_Add)
644
Figure 22-22. Channel X Output PWM with Chxval or Chxcomval_Add Exceeds CARL
645
Figure 22-23. Channel X Output PWM Duty Cycle Changing with Chxcomval_Add
645
Figure 22-24. Four Channels Outputs in Composite PWM Mode
646
Figure 22-25. Chx_O Output with a Pulse in Edge-Aligned Mode (Chxompsel≠2'B00)
647
Figure 22-26. Chx_O Output with a Pulse in Center-Aligned Mode (Chxompsel≠2'B00)
647
Table 22-4. Complementary Outputs Controlled by Parameters (Mchxmsel =2'B11)
649
Figure 22-27. Complementary Output with Dead Time Insertion
650
Figure 22-28. BREAK0 Function Logic Diagram
651
Figure 22-29. BREAK1 Function Logic Diagram
652
Figure 22-30. Output Behavior of the Channel in Response to BREAK0 (the Break Input High Active and IOS=1)
652
Figure 22-31. Output Behavior of the Channel Outputs with the BREAK0 and BREAK1
653
Table 22-5. Output Behavior of the Channel in Response to a BREAK0 and BREAK1 (the Break Input Is High Active)
653
Table 22-6. Break Function Input Pins Locked/ Released Conditions
654
Figure 22-32. Brkinx (X=0
655
Quadrature Decoder
655
Figure 22-33. Example of Counter Operation in Decoder Interface Mode
656
Figure 22-34. Example of Decoder Interface Mode with CI0FE0 Polarity Inverted
656
Table 22-7. Counting Direction in Different Quadrature Decoder Signals
656
Figure 22-35. Quadrature Decoder Signal Disconnection Detection Block Diagram
657
Figure 22-36. Example of Counter Operation in Non-Quadrature Decoder Mode 0 with
657
Figure 22-37. Example of Counter Operation in Non-Quadrature Decoder Mode 1 with CH0P=0
658
Table 22-8. the Counter Operation in in Non-Quadrature Decoder Mode 1
658
Figure 22-38. Hall Sensor Is Used for BLDC Motor
659
Figure 22-39. Hall Sensor Timing between Two Timers
660
Table 22-9. Examples of Slave Mode
660
Figure 22-40. Restart Mode
661
Figure 22-41. Pause Mode
662
Figure 22-42. Event Mode
662
Figure 22-43. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
663
Figure 22-44. Delayable Single Pulse Mode with Timerx_Chxcv=0X00, Timerx_Car=0X60
664
Figure 22-45. Trigger Mode of TIMER0 Controlled by Enable Signal of TIMER2
665
Figure 22-46. Trigger Mode of TIMER0 Controlled by Update Signal of TIMER2
666
Figure 22-47. Pause Mode of TIMER0 Controlled by Enable Signal of TIMER2
666
Figure 22-48. Pause Mode of TIMER0 Controlled by O0CPRE Signal of TIMER2
667
Figure 22-49. Trigger TIMER0 and TIMER2 by the CI0 Signal of TIMER2
668
Figure 22-50. General Level 0 Timer Block Diagram
739
Clock Selection
740
Figure 22-51. Normal Mode, Internal Clock Divided by 1
741
Figure 22-52. Counter Timing Diagram with Prescaler Division Change from 1 to 2
742
Figure 22-53. Timing Chart of up Counting Mode, PSC=0/2
742
Figure 22-54. Timing Chart of up Counting, Change Timerx_Car Ongoing
743
Figure 22-55. Timing Chart of down Counting Mode, PSC=0/2
744
Figure 22-56. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
745
Figure 22-57. Timing Chart of Center-Aligned Counting Mode
746
Capture/Compare Channels
746
Figure 22-58. Input Capture Logic
747
Figure 22-59. Output Compare Logic (X=0,1,2,3)
748
Figure 22-60. Output-Compare under Three Modes
749
Figure 22-61. Timing Chart of EAPWM
749
Figure 22-62. Timing Chart of CAPWM
749
Table 22-10.The Composite PWM Pulse Width
751
Figure 22-63. Channel X Output PWM with (Chxval < Chxcomval_Add)
752
Figure 22-64. Channel X Output PWM with (Chxval = Chxcomval_Add)
752
Figure 22-65. Channel X Output PWM with (Chxval > Chxcomval_Add)
752
Figure 22-66. Channel X Output PWM with Chxval or Chxcomval_Add Exceeds CARL
753
Figure 22-67. Channel X Output PWM Duty Cycle Changing with Chxcomval_Add
753
Figure 22-68. Four Channels Outputs in Composite PWM Mode
754
Figure 22-69. Chx_O Output with a Pulse in Edge-Aligned Mode (Chxompsel≠2'B00)
755
Figure 22-70. Chx_O Output with a Pulse in Center-Aligned Mode (Chxompsel≠2'B00)
755
Figure 22-71. Example of Counter Operation in Decoder Interface Mode
757
Figure 22-72. Example of Decoder Interface Mode with CI0FE0 Polarity Inverted
757
Table 22-11. Counting Direction in Different Quadrature Decoder Signals
757
Figure 22-73. Quadrature Decoder Signal Disconnection Detection Block Diagram
758
Figure 22-74. Example of Counter Operation in Non-Quadrature Decoder Mode 0 with
758
Figure 22-75. Example of Counter Operation in Non-Quadrature Decoder Mode 1 with CH0P=0
759
Table 22-12. the Counter Operation in in Non-Quadrature Decoder Mode 1
759
Table 22-13. Examples of Slave Mode
760
Figure 22-76. Restart Mode
761
Figure 22-77. Pause Mode
761
Figure 22-78. Event Mode
761
Figure 22-79. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X60
763
Figure 22-80. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
764
Figure 22-81. General Level3 Timer Block Diagram
798
Figure 22-82. Normal Mode, Internal Clock Divided by 1
800
Figure 22-83. Counter Timing Diagram with Prescaler Division Change from 1 to 2
801
Figure 22-84. Timing Diagram of up Counting Mode, PSC=0/2
801
Figure 22-85. Timing Diagram of up Counting Mode, Change Timerx_Car on the Go
802
Figure 22-86. Repetition Timechart for Up-Counter
803
Figure 22-87. Input Capture Logic for Channel 0
804
Figure 22-88. Input Capture Logic for Multi Mode Channel 0
804
Figure 22-89. Output Compare Logic (When Mchxmsel = 2'00, X=0)
805
Figure 22-90. Output Compare Logic (When Mchxmsel = 2'11, X=0)
806
Figure 22-91. Output Compare Logic (X=1)
806
Figure 22-92. Output-Compare in Three Modes
808
Figure 22-93. PWM Mode Timechart
808
Table 22-14.The Composite PWM Pulse Width
810
Figure 22-94. Channel X Output PWM with (Chxval < Chxcomval_Add)
811
Figure 22-95. Channel X Output PWM with (Chxval = Chxcomval_Add)
811
Figure 22-96. Channel X Output PWM with (Chxval > Chxcomval_Add)
811
Figure 22-97. Channel X Output PWM with Chxval or Chxcomval_Add Exceeds CARL
812
Figure 22-98. Channel X Output PWM Duty Cycle Changing with Chxcomval_Add
812
Figure 22-99. Chx_O Output with a Pulse in Edge-Aligned Mode (Chxompsel =2'B00)
813
Table 22-15. Complementary Outputs Controlled by Parameters (Mchxmsel =2'B11)
816
Figure 22-100. Complementary Output with Dead-Time Insertion
817
Figure 22-101. BREAK0 Function Logic Diagram
818
Figure 22-102. Output Behavior of the Channel in Response to BREAK0 (the Break Input High Active and IOS=1)
818
Figure 22-103. BRKIN0 Pin Logic with BREAK0 Function
820
Table 22-16. Break Function Input Pins Locked/ Released Conditions
820
Table 22-17. Slave Mode Example Table
820
Figure 22-104. Restart Mode
821
Figure 22-105. Pause Mode
821
Figure 22-106. Event Mode
822
Single Pulse Mode
822
Figure 22-107. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
823
Figure 22-108. Delayable Single Pulse Mode Timerx_Chxcv=0X00, Timerx_Car=0X60
824
Figure 22-109. General Level4 Timer Block Diagram
859
Figure 22-110. Normal Mode, Internal Clock Divided by 1
861
Figure 22-111. Counter Timing Diagram with Prescaler Division Change from 1 to 2
861
Figure 22-112. Timing Diagram of up Counting Mode, PSC=0/2
862
Figure 22-113. Timing Diagram of up Counting Mode, Change Timerx_Car on the Go
863
Figure 22-114. Repetition Timechart for Up-Counter
864
Figure 22-115. Input Capture Logic for Channel 0
865
Figure 22-116. Input Capture Logic for Multi Mode Channel 0
865
Figure 22-117. Output Compare Logic (When Mchxmsel = 2'00, X=0)
866
Figure 22-119. Output-Compare in Three Modes
868
Figure 22-118. Output Compare Logic (When Mchxmsel = 2'11, X=0)
869
Figure 22-120. PWM Mode Timechart
869
Table 22-18. Complementary Outputs Controlled by Parameters (Mchxmsel =2'B11)
870
Figure 22-121. Complementary Output with Dead-Time Insertion
872
Figure 22-122. BREAK0 Function Logic Diagram
873
Figure 22-123. Output Behavior of the Channel in Response to BREAK0 (the Break Input High Active and IOS=1)
873
Table 22-19. Break Function Input Pins Locked/ Released Conditions
874
Figure 22-124. BRKIN0 Pin Logic with BREAK0 Function
875
Figure 22-125. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
875
Figure 22-126. Basic Timer Block Diagram
903
Figure 22-127. Normal Mode, Internal Clock Divided by 1
904
Figure 22-128. Counter Timing Diagram with Prescaler Division Change from 1 to 2
904
Figure 22-129. Timing Chart of up Counting Mode, PSC=0/2 (Timerx, X=5,6)
905
Figure 22-130. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing (Timerx, X=5,6)
905
Universal Synchronous / Asynchronous Receiver
915
Function Overview
917
Table 23-1. Description of USART Important Pins
917
Figure 23-1. USART Module Block Diagram
917
Figure 23-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
918
Table 23-2. Configuration of Stop Bits
918
Baud Rate Generation
918
USART Transmitter
919
Figure 23-3. USART Transmit Procedure
920
USART Receiver
920
Figure 23-4. Oversampling Method of a Receive Frame Bit (OSB = 0)
921
Figure 23-5. Configuration Step When Using DMA for USART Transmission
922
Figure 23-6. Configuration Step When Using DMA for USART Reception
923
Figure 23-7. Hardware Flow Control between Two Usarts
923
Figure 23-8. Hardware Flow Control
924
LIN Mode
925
Figure 23-9. Break Frame Occurs During Idle State
926
Figure 23-10. Break Frame Occurs During a Frame
926
Synchronous Mode
926
Figure 23-11. Example of USART in Synchronous Mode
927
Figure 23-12. 8-Bit Format USART Synchronous Waveform (CLEN = 1)
927
Figure 23-13. Irda SIR ENDEC Module
928
Figure 23-14. Irda Data Modulation
928
Figure 23-15. ISO7816-3 Frame Format
929
Direct and Inverse Convention
931
Modbus Communication
931
Figure 23-16. USART Receive FIFO Structure
932
Figure 23-17. USART Transmitter FIFO Structure
932
Wakeup from Deep-Sleep Mode
932
USART Interrupts
933
Table 23-3. USART Interrupt Requests
933
Figure 23-18. USART Interrupt Mapping Diagram
934
Register Definition
935
Inter-Integrated Circuit Interface (I2C)
959
Function Overview
959
Figure 24-1. I2C Module Block Diagram
959
Table 24-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
960
Clock Requirements
960
Figure 24-2. Data Validation
961
Figure 24-3. START and STOP Condition
962
Figure 24-4. I2C Communication Flow with 10-Bit Address (Master Transmit)
962
Figure 24-5. I2C Communication Flow with 7-Bit Address (Master Transmit)
963
Figure 24-6. I2C Communication Flow with 7-Bit Address (Master Receive)
963
Figure 24-7. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)
963
Figure 24-8. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)
963
Noise Filter
964
Figure 24-9. Data Hold Time
964
Figure 24-10. Data Setup Time
965
Table 24-2. Data Setup Time and Data Hold Time
966
Data Transfer
966
Data Transmission
966
Figure 24-11. Data Transmission
967
Figure 24-12. Data Reception
967
Table 24-3. Communication Modes to be Shut down
967
I2C Slave Mode
968
Slave Byte Control Mode
969
Figure 24-13. I2C Initialization in Slave Mode
970
Figure 24-14. Programming Model for Slave Transmitting When SS=0
971
Figure 24-15. Programming Model for Slave Transmitting When SS=1
972
Figure 24-16. Programming Model for Slave Receiving
973
I2C Master Mode
973
Figure 24-17. I2C Initialization in Master Mode
974
Figure 24-18. Programming Model for Master Transmitting (N<=255)
975
Figure 24-19. Programming Model for Master Transmitting (N>255)
976
Figure 24-20. Programming Model for Master Receiving (N<=255)
977
Figure 24-21. Programming Model for Master Receiving (N>255)
978
Smbus Protocol
978
Address Resolution Protocol
979
Host Notify Protocol
979
Time-Out Feature
979
Packet Error Checking
980
Smbus Alert
980
Bus Idle Detection
980
Smbus Slave Mode
981
Figure 24-22. Smbus Master Transmitter and Slave Receiver Communication Flow
982
Figure 24-23. Smbus Master Receiver and Slave Transmitter Communication Flow
982
Table 24-4. I2C Error Flags
983
Table 24-5. I2C Interrupt Events
983
I2C Debug Mode
984
Register Definition
985
Serial Peripheral Interface/Inter-IC Sound (SPI/I2S)
999
SPI Characteristics
999
SPI Block Diagram
1000
Figure 25-1. Block Diagram of SPI
1000
Table 25-1. SPI Signal Description
1001
Quad-SPI Configuration
1001
Table 25-2. Quad-SPI Signal Description
1001
Figure 25-2. SPI Timing Diagram in Normal Mode
1002
Table 25-3. MISO / MISO Signal Switching Description
1002
Figure 25-3. SPI3 / 4 Timing Diagram in Quad-SPI Mode (CKPL = 1, CKPH = 1, LF = 0)
1003
Figure 25-4. SPI Data Frame Right-Aligned Diagram
1003
Figure 25-5. SPI Data and Clock Transmission Path Diagram
1004
Figure 25-6. SPI Master Rx Delay Configuration Diagram
1004
Figure 25-7. SPI Slave Rx Delay Configuration Diagram
1005
Rxfifo and Txfifo
1005
Table 25-4. the Maxinum Number of Data Frame Stored in SPIX FIFO
1005
Data Packing
1006
Table 25-5. NSS Function in Slave Mode
1008
Figure 25-8. NSS Signal Delay Timing Diagram (MSSD[3:0] = 0011 (3 X Tclk), MDFD = 0011 (3 X Tclk))
1009
Table 25-6. NSS Function in Master Mode
1009
Figure 25-9. NSS Interlaced Pulses Timing Diagram (MSSD[3:0] = 0011 (3 X Tclk), MDFD = 0011 (3 X Tclk))
1010
Table 25-7. SPI Operation Modes
1010
Figure 25-10. a Typical Full-Duplex Connection
1011
Figure 25-11. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
1012
Figure 25-12. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
1012
Figure 25-13. a Typical Bidirectional Connection
1012
Figure 25-14. Timing Diagram of TI Master Mode with Discontinuous Transfer
1015
Figure 25-15. Timing Diagram of TI Master Mode with Continuous Transfer
1015
Figure 25-16. Timing Diagram of TI Slave Mode
1016
Figure 25-17. Timing Diagram of Quad Write Operation in Quad-SPI Mode
1017
Figure 25-18. Timing Diagram of Quad Read Operation in Quad-SPI Mode
1018
CRC Function
1019
SPI Interrupts
1020
Status Flags
1020
Error Conditions
1021
Table 25-8. SPI Interrupt Requests
1022
I2S Block Diagram
1023
Figure 25-19. Block Diagram of I2S
1023
Figure 25-20. I2S Philips Standard Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 0)
1025
Figure 25-21. I2S Philips Standard Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 1)
1025
Figure 25-22. I2S Philips Standard Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 0)
1025
Figure 25-23. I2S Philips Standard Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 1)
1025
Figure 25-24. I2S Philips Standard Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 0)
1025
Figure 25-25. I2S Philips Standard Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 1)
1025
Figure 25-26. I2S Philips Standard Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 0)
1026
Figure 25-27. I2S Philips Standard Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 1)
1026
Figure 25-28. MSB Justified Standard Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 0)
1026
Figure 25-29. MSB Justified Standard Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 1)
1026
Figure 25-30. MSB Justified Standard Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 0)
1026
Figure 25-31. MSB Justified Standard Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 1)
1026
Figure 25-32. MSB Justified Standard Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 0)
1027
Figure 25-33. MSB Justified Standard Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 1)
1027
Figure 25-34. MSB Justified Standard Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 0)
1027
Figure 25-35. MSB Justified Standard Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 1)
1027
Figure 25-36. LSB Justified Standard Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 0)
1028
Figure 25-37. LSB Justified Standard Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 1)
1028
Figure 25-38. LSB Justified Standard Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 0)
1028
Figure 25-39. LSB Justified Standard Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 1)
1028
Figure 25-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 0)
1028
Figure 25-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 1)
1029
Figure 25-42. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 0)
1029
Figure 25-44. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 0)
1029
Figure 25-45. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 1)
1029
Figure 25-46. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 0)
1030
Figure 25-47. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 1)
1030
Figure 25-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 0)
1030
Figure 25-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 0, CKPL = 1)
1030
Figure 25-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 0)
1030
Figure 25-51. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 10, CHLEN = 1, CKPL = 1)
1030
Figure 25-52. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 0)
1031
Figure 25-53. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 01, CHLEN = 1, CKPL = 1)
1031
Figure 25-54. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 0)
1031
Figure 25-55. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN = 00, CHLEN = 1, CKPL = 1)
1031
Figure 25-56. Block Diagram of I2S Clock Generator
1032
Table 25-9. I2S Bitrate Calculation Formulas
1032
Table 25-10. Audio Sampling Frequency Calculation Formulas
1032
Table 25-11. the Maxinum Number of Data Frame Stored in I2SX FIFO
1033
Operation
1033
Table 25-12. Direction of I2S Interface Signals for each Operation Mode
1033
Table 25-13. I2S Interrupt
1037
Register Definition
1038
Function Overview
1057
Table 26-1 OSPIM Matrix Mapping
1058
Register Definition
1058
Table 27-1 OSPI Signal Description
1060
Figure 27-1 OSPI Octal Communication Mode Block Diagram
1062
Figure 27-2 OSPI Quad Communication Mode Block Diagram
1063
Figure 27-3 OSPI Command Format in Octal Mode
1064
Figure 27-4 OSPI Command Format in Quad Mode
1064
Instruction Phase
1064
Address Phase
1065
Alternate-Bytes Phase
1065
Data Phase
1066
Figure 27-5 CSN and SCK Behavior
1066
Operating Modes
1066
Error Management
1070
Table 27-2 OSPI Interrupt Requests
1071
Register Definition
1072
Function Overview
1092
Figure 28-1. the EXMC Block Diagram
1093
Bus Interface
1093
External Device Address Mapping
1095
Figure 28-2. EXMC Memory Banks
1095
Table 28-1. EXMC Bank Mapping
1095
NOR/PSRAM Address Mapping
1096
Figure 28-3. Four Regions of Bank0 Address Mapping
1096
Figure 28-4. NAND Address Mapping
1097
Figure 28-5. Diagram of Bank2 Common Space
1098
SDRAM Address Mapping
1098
Figure 28-6. SDRAM Address Mapping
1099
Table 28-2. SDRAM Mapping
1099
Table 28-3. nor Flash Interface Signals Description
1099
Table 28-4. PSRAM Non-Muxed Signal Description
1100
Table 28-5. EXMC Bank 0 Supports All Transactions
1100
Table 28-6. nor / PSRAM Controller Timing Parameters
1102
Table 28-7. EXMC Timing Models
1102
Figure 28-7. Mode 1 Read Access
1103
Figure 28-8. Mode 1 Write Access
1104
Table 28-8. Mode 1 Related Registers Configuration
1104
Figure 28-9. Mode a Read Access
1105
Figure 28-10. Mode a Write Access
1105
Table 28-9. Mode a Related Registers Configuration
1105
Figure 28-11. Mode 2/B Read Access
1107
Figure 28-12. Mode 2 Write Access
1107
Figure 28-13. Mode B Write Access
1107
Table 28-10. Mode 2/B Related Registers Configuration
1108
Figure 28-14. Mode C Read Access
1109
Figure 28-15. Mode C Write Access
1109
Table 28-11. Mode C Related Registers Configuration
1109
Figure 28-16. Mode D Read Access
1111
Figure 28-17. Mode D Write Access
1111
Table 28-12. Mode D Related Registers Configuration
1111
Figure 28-18. Multiplex Mode Read Access
1112
Figure 28-19. Multiplex Mode Write Access
1113
Table 28-13. Multiplex Mode Related Registers Configuration
1113
Figure 28-20. Read Access Timing Diagram under Async-Wait Signal Assertion
1114
Figure 28-21. Write Access Timing Diagram under Async-Wait Signal Assertion
1115
Figure 28-22. Read Timing of Synchronous Multiplexed Burst Mode
1117
Table 28-14. Timing Configurations of Synchronous Multiplexed Read Mode
1117
Figure 28-23. Write Timing of Synchronous Multiplexed Burst Mode
1118
Table 28-15. Timing Configurations of Synchronous Multiplexed Write Mode
1118
Table 28-16. 8-Bit or 16-Bit NAND Interface Signal
1119
Table 28-17. Bank2 of EXMC Support the Memory and Access Mode
1120
Figure 28-24. Access Timing of Common Memory Space of NAND Flash Controller
1121
Table 28-18. NAND Flash Programmable Parameters
1121
NAND Flash Pre-Wait Functionality
1122
Figure 28-25. Access to None "NCE Don't Care" NAND Flash
1122
SDRAM Controller
1123
Figure 28-26. SDRAM Controller Block Diagram
1125
Table 28-19. SDRAM Command Truth Table
1126
Table 28-20. IO Definition of SDRAM Controller
1126
Controller Initialization
1126
Figure 28-27. Burst Read Operation
1129
Figure 28-28. Data Sampling Clock Delay Chain
1129
Figure 28-29. Burst Write Operation
1130
Figure 28-30. Read Access When FIFO Not Hit (BRSTRD=1, CL=2, SDCLK=2, PIPED=2)
1130
Figure 28-31. Read Access When FIFO Hit (BRSTRD=1)
1131
Figure 28-32. Cross Boundary Read Operation
1132
Figure 28-33. Cross Boundary Write Operation
1132
Low Power Modes
1133
Figure 28-34. Process for Self-Refresh Entry and Exit
1133
Figure 28-35. Process for Power-Down Entry and Exit
1134
Register Definition
1135
NOR/PSRAM Controller Registers
1135
NAND Flash Controller Registers
1140
Function Overview
1153
Figure 29-1.Precision Reference Connection
1153
Table 29-1. VREF Modes
1153
Register Definition
1155
Figure 30-1. LPDTS Block Diagram
1157
Table 30-1. LPDTS Signals
1158
Figure 30-2. Method for Different REF_CLK
1159
Table 30-2. Sampling Time Configuration
1159
Trigger Input
1160
Table 30-3. Trigger Configuration
1160
Table 30-4. Temperature Sensor Behavior in Low-Power Modes
1161
Table 30-5. Temperature Sensor Behavior in Low-Power Modes
1162
Figure 31-1. Block Diagram of EDOUT
1170
Figure 31-2. ABZ-Phase Output Waveforms
1171
Operation Guidance
1172
Figure 31-3. Example of the Settings of EDOUT and the AB-Phase and Z-Phase Output
1173
Controller Area Network (CAN)
1179
Figure 32-1. CAN Module Block Diagram
1180
Table 32-1. Mailbox Descriptor with 64 Byte Payload
1181
Table 32-2. Data Bytes for DLC
1183
Table 32-3. Mailbox Rx CODE
1183
Table 32-4. Mailbox Tx CODE
1184
Mailbox Number
1186
Table 32-5. Mailbox Size
1186
Table 32-6. Rx FIFO Descriptor
1186
Communication Modes
1192
Inactive Mode
1192
Monitor Mode
1193
Transmit Process
1194
Arbitration Process
1195
Table 32-7. Mailbox Arbitration Value(32 Bit) When Local Priority Disabled
1196
Table 32-8. Mailbox Arbitration Value(35 Bit) When Local Priority Enabled
1197
Data Reception
1198
Mailbox Reception
1198
Matching Process
1201
Table 32-9. Rx Mailbox Matching
1203
Table 32-10. Rx FIFO Matching
1204
Wakeup Interrupt
1206
Figure 32-2. Transmitter Delay
1211
Communication Parameters
1214
Figure 32-3. CAN Bit Time
1214
Table 32-11. Interrupt Events
1217
CAN Registers
1220
Table 32-12. Rx FIFO Filter Element Number
1231
Comparator (CMP)
1249
Function Overview
1249
Figure 33-1. CMP Block Diagram
1250
Table 33-1. CMP Inputs and Outputs Summary
1251
Figure 33-2. CMP Hysteresis
1252
Figure 33-3. the CMP Outputs Signal Blanking
1253
Register Definition
1254
Function Overview
1262
Figure 34-1. HPDF Block Diagram
1262
Table 34-1. HPDF Pins Definition
1262
Table 34-2. HPDF Internal Signal
1263
Table 34-3. SPI Interface Clock Configuration
1265
Figure 34-2. the Sequence Diagram of SPI Data Transmission
1266
Figure 34-3. the Sequence Diagram of Manchester Data Transmission
1267
Figure 34-4. Manchester Synchronous Sequence Diagram
1267
Figure 34-5. Clock Loss Detection Timing Diagram
1270
Figure 34-6. Channel Pins Redirection
1271
Table 34-4. Parallel Data Packed Mode
1274
Table 34-5. Trigger Signal of Inserted Group
1276
Digital Filter
1277
Table 34-6. the Relationship between the Maximum Output Resolution and Oversampling Filtering of Sincx Filtering
1277
Table 34-7. Relationship between the Maximum Output Resolution and IOR, SFOR, SFO of the Integrator
1278
Table 34-8. Features of Threshold Monitor Working Mode
1278
Figure 34-7. HPDF Module External Input Data Processing Flow
1281
Table 34-9. Maximum Output Rate
1282
Figure 34-8. HPDF Interrupt Logic Diagram
1283
Table 34-10. HPDF Interrupt Event
1283
Register Definition
1284
Function Overview
1304
General Description
1304
Figure 35-1 FAC Structure Diagram
1305
Input Buffers
1306
Figure 35-2 Input Buffer Area
1306
Figure 35-3 Circular Input Buffer Area
1307
Figure 35-4 Circular Input Buffer Operation
1308
Figure 35-5 Circular Output Buffer
1308
Figure 35-6 Circular Output Buffer Area
1309
Initialization Functions
1309
Filter Functions
1310
Figure 35-7 the Structure of FIR Filter Function
1311
Figure 35-8 the Structure of IIR Filter
1312
FIR Filters
1313
Table 35-1 IEEE 32-Bit Single Precision Floating-Point Format
1313
Register Definition
1317
Figure 36-1. USBHS Block Diagram
1325
Table 36-1. USBHS Signal Description
1325
Table 36-2. USBHS Supported Speeds
1326
Figure 36-2. Connection Using Internal Embedded PHY with Host or Device Mode
1327
Figure 36-3. Connection Using Internal Embedded PHY with OTG Mode
1328
Figure 36-4. Connection Using External ULPI PHY
1328
USB Host Function
1328
Figure 36-5. State Transition Diagram of Host Port
1329
USB Device Function
1331
Figure 36-6. Host Mode FIFO Space in SRAM
1335
Figure 36-7. Host Mode FIFO Access Register Map
1335
Figure 36-8. Device Mode FIFO Space in SRAM
1336
Figure 36-9. Device Mode FIFO Access Register Map
1337
Host Mode
1338
Device Mode
1342
Table 36-3. USBHS Global Interrupt
1345
Register Definition
1346
Device Control and Status Registers
1389
Enable Register
1398
Figure 37-1. Bus Architecture of ESC
1420
Table 37-1. Memory Map
1421
Table 37-2. Alignment of Valid Data
1424
Figure 37-2 Efuse Controller Block Diagram
1426
Power Management Unit (PMU)
1437
Function Overview
1437
Figure 37-3. PME Interrupt Pending
1438
Table 37-3. Power Saving Mode Summary
1439
Figure 37-4. Clock Tree
1446
Figure 37-5. HXTAL Clock Source
1447
Interrupt Controller (INTC)
1454
Figure 37-6. Block Diagram of Interrupt
1455
Software Interrupt
1455
Timer Interrupt
1456
General-Purpose I/Os (GPIO)
1462
Function Overview
1462
Table 37-4. GPIO Configuration Table
1463
Figure 37-7. Port Line PHYS
1464
Figure 37-8. Basic Structure of Analog Configuration
1465
Figure 37-9. Basic Structure of Alternate Function Configuration
1465
Clock Source
1476
Figure 37-10. Basic Timer Block Diagram
1476
Figure 37-11. Timing Chart of down Counting Mode
1477
Figure 37-12. FRC Block Diagram
1479
Figure 37-13. Block Diagram of PDI Wrapper
1481
Figure 37-14. Block Diagram of SPI
1482
Table 37-5. 4-Wire Mode
1482
Table 37-6. 6-Wire Mode
1482
Table 37-7. OSPI 8-Line Mode
1483
Operation Description
1484
Table 37-8. SPI Instructions
1485
Table 37-9. QSPI Instruction
1486
Table 37-10. OSPI Instruction
1486
Figure 37-15. Enable QSPI
1487
Figure 37-16. Enable OSPI
1487
Figure 37-17. SPI MODE RESET SPI
1488
Figure 37-18. QSPI MODE RESET QSPI
1488
Figure 37-19. OSPI MODE RESET OSPI
1488
Figure 37-20. SPI READ
1490
Figure 37-21. QSPI READ
1490
Figure 37-22. OSPI READ
1490
Figure 37-23. SPI DUAL OUTPUT READ
1492
Figure 37-24. SPI QUAD OUTPUT READ
1493
Figure 37-25. SPI DUAL I/O READ
1494
Figure 37-26. SPI QUAD I/O READ
1495
Figure 37-27. SPI WRITE
1496
Figure 37-28. QSPI WRITE
1496
Figure 37-29. OSPI WRITE
1496
Figure 37-30. SPI DUAL DATA WRITE
1498
Figure 37-31. SPI QUAD DATA WRITE
1499
Figure 37-32. SPI DUAL ADDRESS / DATA WRITE
1501
Figure 37-33. SPI QUAD ADDRESS / DATA WRITE
1501
Ethernet PHYS
1503
Figure 37-34.PHY Functional Block Diagram
1504
Functional Overview
1504
Operation Mode
1504
MII Interface
1504
Loopback Modes
1505
LED Modes
1505
Figure 37-35. LED Connect Diagram
1506
LED Interface
1506
Figure 37-36. 100Base-TX LPI
1507
MDIO Registers
1535
Figure 37-37. Ethercat System Block Diagram
1553
Function Overview
1555
Table 37-11. Pdis for Ethercat
1555
Table 37-12. Registers Affected by PDI Register Function Acknowledge by Write
1556
Distributed Clocks
1559
Ethercat State Machine
1559
Figure 37-38. Ethercat State Machine
1560
Figure 37-39. EEPROM Layout
1560
Figure 37-40. PDI Interrupt Masking and Interrupt Signals
1562
Figure 37-41. Ethercat Interrupt Masking
1563
Table 38-1. List of Abbreviations Used in Register
1629
Table 38-2. List of Terms
1629
Table 39-1. Revision History
1631
Important Notice
1632
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