GigaDevice Semiconductor GD32E23 Series User Manual

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GigaDevice Semiconductor Inc.

GD32E23x

Arm

Cortex

-M23 32-bit MCU

User Manual

Revision 1.5

(Jul. 2022)

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Summary of Contents for GigaDevice Semiconductor GD32E23 Series

Page 1 GigaDevice Semiconductor Inc. GD32E23x ® ® Cortex -M23 32-bit MCU User Manual Revision 1.5 (Jul. 2022)
Page 2: Table Of Contents
GD32E23x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................13 List of Table ........................19 1. System and memory architecture ................ 21 ® ® 1.1. Cortex -M23 processor ................... 21 1.2. System architecture ....................22 1.3.
Page 3 GD32E23x User Manual 2.3.11. Page erase/Program protection .................... 52 2.3.12. Security protection ........................ 52 2.4. Register definition ..................... 54 2.4.1. Wait state register (FMC_WS) ....................54 2.4.2. Unlock key register (FMC_KEY) ................... 54 2.4.3. Option byte unlock key register (FMC_OBKEY) ..............55 2.4.4.
Page 4 GD32E23x User Manual 4.3.9. Backup domain control register (RCU_BDCTL) ..............94 4.3.10. Reset source /clock register (RCU_RSTSCK) ..............96 4.3.11. AHB reset register (RCU_AHBRST)..................97 4.3.12. Configuration register 1 (RCU_CFG1) ................. 98 4.3.13. Configuration register 2 (RCU_CFG2) ................. 99 4.3.14. Control register 1 (RCU_CTL1) ..................
Page 5 GD32E23x User Manual 6.4.5. Port input status register (GPIOx_ISTAT, x=A..C,F) ............125 6.4.6. Port output control register (GPIOx_OCTL, x=A..C,F) ............126 6.4.7. Port bit operate register (GPIOx_BOP, x=A..C,F)............... 126 6.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ............. 127 6.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C) ........128 6.4.10.
Page 6 GD32E23x User Manual 9. Debug (DBG) ......................153 9.1. Overview ........................153 9.2. SW function overview ..................... 153 9.2.1. Pin assignment ........................153 9.3. Debug hold function overview ................153 9.3.1. Debug support for power saving mode ................153 9.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT ..........
Page 7 GD32E23x User Manual 10.5.10. Routine data register (ADC_RDATA) .................. 179 10.5.11. Oversampling control register (ADC_OVSAMPCTL) ............180 Comparator (CMP) .................... 182 11.1. Introduction ......................182 11.2. Main features ......................182 11.3. Function description .................... 182 11.3.1. CMP clock and reset ......................183 11.3.2.
Page 8 GD32E23x User Manual 13.3.12. Tamper detection ........................ 208 13.3.13. Calibration clock output ...................... 209 13.3.14. Alarm output ........................209 13.3.15. RTC power saving mode management ................210 13.3.16. RTC interrupts ........................210 13.4. Register definition ....................212 13.4.1. Time register (RTC_TIME) ....................212 13.4.2.
Page 9 GD32E23x User Manual 14.4. General level3 timer (TIMERx, x=14) ..............348 14.4.1. Overview ..........................348 14.4.2. Characteristics ........................348 14.4.3. Block diagram ........................348 14.4.4. Function overview ....................... 349 14.4.5. TIMERx registers(x=14) ...................... 366 14.5. General level4 timer (TIMERx, x=15, 16) ............. 386 14.5.1.
Page 10 GD32E23x User Manual 16.3.15. Wakeup from Deep-sleep mode ..................445 16.3.16. USART interrupts ........................ 446 16.4. Register definition ....................448 16.4.1. Control register 0 (USART_CTL0) ..................448 16.4.2. Control register 1 (USART_CTL1) ..................450 16.4.3. Control register 2 (USART_CTL2) ..................453 16.4.4.
Page 11 GD32E23x User Manual 17.4.9. Rise time register (I2C_RT) ....................493 17.4.10. SAM control and status register (I2C_SAMCS) ..............493 17.4.11. Fast mode plus configure register (I2C_FMPCFG) ............494 Serial peripheral interface/Inter-IC sound (SPI/I2S) ........496 18.1. Overview ....................... 496 18.2. Characteristics .....................
Page 12 GD32E23x User Manual 19.3. Function overview ....................543 19.3.1. Enable OPA ........................543 19.3.2. Combinatorial work with ADC ..................... 543 19.3.3. Use SW when enabled OPA ....................543 Appendix ......................544 20.1. List of abbreviations used in register ..............544 20.2.
Page 13: List Of Figures
GD32E23x User Manual List of Figures ® Figure 1-1. The structure of the Cortex -M23processor ............22 Figure 1-2. Series system architecture of GD32E23x series ..........23 Figure 2-1. Process of page erase operation ................46 Figure 2-2. Process of the mass erase operation ..............47 Figure 2-3.
Page 14 GD32E23x User Manual Figure 14-1. Advanced timer block diagram ................234 Figure 14-2. Timing chart of internal clock divided by 1 ............235 Figure 14-3. Timing chart of PSC value change from 0 to 2 ..........236 Figure 14-4. Timing chart of up counting mode, PSC=0/2 ........... 237 Figure 14-5.
Page 15 GD32E23x User Manual Figure 14-44. General level2 timer block diagram ..............329 Figure 14-45. Timing chart of internal clock divided by 1 ............ 330 Figure 14-46. Timing chart of PSC value change from 0 to 2 ..........331 Figure 14-47. Timing chart of up counting mode, PSC=0/2 ..........332 Figure 14-48.
Page 16 GD32E23x User Manual Figure 15-1. IFRP output timechart 1 ..................427 Figure 15-2. IFRP output timechart 2 ..................428 Figure 15-3. IFRP output timechart 3 ..................428 Figure 16-1. USART module block diagram ................431 Figure 16-2. USART character frame (8 bits data and 1 stop bit) ........432 Figure 16-3.USART transmit procedure .................
Page 17 GD32E23x User Manual Figure 18-10. A typical bidirectional connection ..............504 Figure 18-11. Timing diagram of TI master mode with discontinuous transfer ....507 Figure 18-12. Timing diagram of TI master mode with continuous transfer ...... 507 Figure 18-13. Timing diagram of TI slave mode ..............508 Figure 18-14.
Page 18 GD32E23x User Manual Figure 18-46. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ......................522 Figure18-47. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ......................523 Figure 18-48. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ......................
Page 19: List Of Table
GD32E23x User Manual List of Table Table 1-1.Memory map of GD32E23x series ................24 Table 1-2. Flash module organization ..................26 Table1-3. Boot modes ......................... 27 Table 2-1. Base address and size for flash memory ............... 42 Table 2-2. The relation between WSCNT and AHB clock frequency ........43 Table 2-3.
Page 20 GD32E23x User Manual Table 17-3. Error flags....................... 483 Table 18-1. SPI signal description ................... 497 Table 18-2. Quad-SPI signal description ................498 Table 18-3. NSS function in slave mode ................. 501 Table 18-4. NSS function in master mode ................502 Table 18-5.
Page 21: System And Memory Architecture
GD32E23x User Manual System and memory architecture ® The GD32E23x series are 32-bit general-purpose microcontrollers based on the Arm Cortex ® -M23 processor. The Cortex ® -M23 processor includes AHB buses. All memory accesses of the Cortex ® -M23 processor are executed on the AHB buses according to the different purposes and the target memory spaces.
Page 22: System Architecture
GD32E23x User Manual ® Figure 1-1. The structure of the Cortex -M23processor Nested Data Vectored IRQ interface Cortex-M23 Watchpoint Interrupt Processor core And Trace Controller (DWT) (NVIC) Breakpoint Processor Unit Romtable Bus Matrix Single Wire Debug Single-cycle IO port AHB Master interface 1.2.
Page 23: Memory Map
GD32E23x User Manual Figure 1-2. Series system architecture of GD32E23x series 1.2V TPIU GPIO Ports AHB2: Fma x = 72MHz POR/PDR A, B, C, F ARM Cortex-M23 Processor SRAM : 72MHz SRAM Controller Flash Fmax: 72MHz Flash Memory Memory NVIC Controller HXTAL 4-32MHz...
Page 24: Table 1-1.Memory Map Of Gd32E23X Series
GD32E23x User Manual Code, SRAM, peripheral, and other pre-defined regions. Each peripheral of either type is allocated 1KB of space. This allows simplifying the address decoding for each peripheral. Table 1-1.Memory map of GD32E23x series Pre-defined ADDRESS Peripherals Regions 0xE000 0000 - 0xE00F FFFF Cortex M23 internal peripherals External Device 0xA000 0000 - 0xDFFF FFFF...
Page 25 GD32E23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF SYSCFG + CMP 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved...
Page 26: On-Chip Sram Memory
GD32E23x User Manual Pre-defined ADDRESS Peripherals Regions Aliased to Flash or 0x00000000 - 0x0000FFFF system memory 1.3.1. On-chip SRAM memory The GD32E23x series contain up to 8KB of on-chip SRAM which starts at the address 0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) accesses. In order to increase memory robustness, parity check is supported.
Page 27: Boot Configuration
GD32E23x User Manual memory can be programmed word (32 bits) or double-word (64 bits) at a time. Each page of the flash memory can be erased individually. The whole flash memory space except information blocks can be erased at a time. 1.4.
Page 28: System Configuration Registers (Syscfg)
GD32E23x User Manual 1.5. System configuration registers (SYSCFG) SYSCFG base address: 0x4001 0000 1.5.1. System configuration register 0 (SYSCFG_CFG0) For GD32E230xx devices Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the nBOOT1 option bit after reset) PB9_HC Reserved Reserved...
Page 29 GD32E23x User Manual 0: not remap (USART0_RX DMA requests are mapped on DMA channel 2) 1: remap (USART0_RX DMA requests are mapped on DMA channel 4) USART0_TX_DMA_ USART0_TX DMA request remapping enable 0: not remap (USART0_TX DMA requests are mapped on DMA channel 1) 1: remap (USART0_TX DMA requests are mapped on DMA channel 3) ADC_DMA_RMP ADC DMA request remapping enable...
Page 30 GD32E23x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value Reserved Must be kept at reset value 18:13 Reserved Must be kept at reset value TIMER16_DMA_RM Timer 16 DMA request remapping enable 0: not remap (TIMER16_CH1 and TIMER16_UP DMA requests are mapped on DMA channel 0) 1: remap (TIMER16_CH1 and TIMER16_UP DMA requests are mapped on DMA channel 1)
Page 31: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32E23x User Manual 11: Boot from the embedded SRAM 1.5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0) Address offset: 0x08 Reset value: 0x0000 0000 Reserved EXTI3_SS [3:0] EXTI2_SS [3:0] EXTI1_SS [3:0] EXTI0_SS [3:0] Bits Fields Descriptions 31:16 Reserved must be kept at reset value 15:12 EXTI3_SS EXTI 3 sources selection...
Page 32: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32E23x User Manual X110: reserved X111: reserved EXTI0_SS EXTI 0 sources selection X000: PA0 pin X001: PB0 pin X010: reserved X011: reserved X100: reserved X101: PF0 pin X110: reserved X111: reserved 1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved EXTI7_SS [3:0]...
Page 33: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32E23x User Manual X110: reserved X111: reserved EXTI5_SS EXTI 5 sources selection X000: PA5 pin X001: PB5 pin X010: reserved X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved EXTI4_SS EXTI 4 sources selection X000: PA4 pin X001: PB4 pin X010: reserved X011: reserved X100: reserved...
Page 34 GD32E23x User Manual X100: reserved X101: reserved X110: reserved X111: reserved 11:8 EXTI10_SS EXTI 10 sources selection X000: PA10 pin X001: PB10 pin X010: reserved X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved EXTI9_SS EXTI 9 sources selection X000: PA9 pin X001: PB9 pin X010: reserved...
Page 35: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32E23x User Manual 31:16 Reserved Must be kept at reset value 15:12 EXTI11_SS EXTI 11 sources selection X000: PA11 pin X001: PB11 pin X010: reserved X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved 11:8 EXTI10_SS EXTI 10 sources selection X000: PA10 pin X001: PB10 pin X010: reserved...
Page 36 GD32E23x User Manual Reset value: 0x0000 0000 Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI15_SS EXTI 15 sources selection X000: PA15 pin X001: PB15 pin X010: PC15 pin X011: reserved X100: reserved X101: reserved...
Page 37 GD32E23x User Manual X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved For GD32E231xx devices Address offset: 0x14 Reset value: 0x0000 0000 Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI15_SS EXTI 15 sources selection...
Page 38: System Configuration Register 2 (Syscfg_Cfg2)
GD32E23x User Manual X100: reserved X101: reserved X110: reserved X111: reserved EXTI12_SS EXTI 12 sources selection X000: PA12 pin X001: PB12 pin X010: reserved X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved 1.5.6. System configuration register 2 (SYSCFG_CFG2) Address offset: 0x18 Reset value: 0x0000 0000 Reserved...
Page 39: Irq Latency Register (Syscfg_Cpu_Irq_Lat)
GD32E23x User Manual and LVDT[2:0] in the PWR_CTL register are read only. SRAM_PARITY_ SRAM parity check error lock ERROR_LOCK This bit is set by software and cleared by a system reset. 0: The SRAM parity check error is disconnected from the break input of TIMER0/14/15/16.
Page 40: Memory Density Information
GD32E23x User Manual device ID. It is stored in the information block of the Flash memory. The 96-bit unique device ID is unique for any device. It can be used as serial numbers, or part of security keys, etc. 1.6.1. Memory density information Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user.
Page 41 GD32E23x User Manual This register has to be accessed by word(32-bit) UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7B4 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit) UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits...
Page 42: Flash Memory Controller (Fmc)
GD32E23x User Manual Flash memory controller (FMC) 2.1. Overview The Flash Memory Controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored in the 64K bytes of the flash. It also provides page erase, mass erase, and word/double word program for flash memory.
Page 43: Read Operations
GD32E23x User Manual Block Name Address size(bytes) Page 63 0x0800 FC00 - 0x0800 FFFF Information Block Boot Loader 0x1FFF EC00 - 0x1FFF F7FF Option byte Block Option byte 0x1FFF F800 - 0x1FFF F80F One-time program OTP bytes 0x1FFF_7000~0x1FFF_73FF Block The Information Block stores the bootloader - this block cannot be programmed or Note: erased by user.
Page 44: Unlock The Fmc_Ctl Register
GD32E23x User Manual Current buffer: The current buffer is always enabled. Each time read from flash memory, 64-bit data will be get and store in current buffer. The CPU only need 32-bit or 16-bit in each read operation. So in the case of sequential code, the next data can get from current buffer without repeat fetch from flash memory.
Page 45 GD32E23x User Manual  Write the page erase command into PER bit in FMC_CTL register.  Send the page erase command to the FMC by setting the START bit in FMC_CTL register.  Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_STAT register.
Page 46: Mass Erase
GD32E23x User Manual Figure 2-1. Process of page erase operation Start Is the LK bit 0 Unlock the FMC_CTL Is the BUSY bit 0 Set the FMC_ADDR, PER bit Send the command to FMC by setting START bit Is the BUSY bit 0 Finish 2.3.5.
Page 47: Main Flash Programming
GD32E23x User Manual When the operation is executed successfully, an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. Since all flash data will be reset to a value of 0xFFFF FFFF, the mass erase operation can be implemented using a program that runs in SRAM or by using the debugging tool to access the FMC registers directly.
Page 48 GD32E23x User Manual  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished. ...
Page 49: Otp Programming
GD32E23x User Manual The DBUS write is not alignment. If DBUS program is 32-bit and the PGW bit is set to 1(64-bit program to flash memory), the second DBUS write must double-word alignment and belong to same double-word address. If DBUS program is 16-bit and the PGW bit is set to 0(32-bit program to flash memory), the second DBUS write must word alignment and belong to same word address.
Page 50: Option Byte Erase
GD32E23x User Manual only be programed once and cannot be erased. Note: It must ensure the OTP programming sequence completely without any unexpected interrupt, such as system reset or power down. If unexpected interrupt occurs, there is very little probability of corrupt the data stored in flash memory. 2.3.8.
Page 51: Option Byte Description
GD32E23x User Manual  Read and verify the flash memory if required using a DBUS access. When the operation is executed successfully, an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. Note that before the word/half word programming operation you should check the address that it has been erased.
Page 52: Page Erase/Program Protection
GD32E23x User Manual Address Name Description 1: Software free watchdog timer 0x1fff f803 OB_USER_N OB_USER complement value 0x1fff f804 OB_DATA[7:0] user defined data bit 7 to 0 0x1fff f805 OB_DATA_N[7:0] OB_DATA complement value bit 7 to 0 0x1fff f806 OB_DATA[15:8] user defined data bit 15 to 8 0x1fff f807 OB_DATA_N[15:8]...
Page 53 GD32E23x User Manual No protection: when setting OB_SPC byte and its complement value to 0xA55A, no protection performed. The main flash and option bytes block are accessible by all operations. Protection level low: when setting OB_SPC byte and its complement value to any value except 0xA55A or 0xCC33, protection level low performed.
Page 54: Register Definition
GD32E23x User Manual 2.4. Register definition FMC base address: 0x4002 2000 2.4.1. Wait state register (FMC_WS) Address offset: 0x00 Reset value: 0x0000 0030 This register has to be accessed by word(32-bit) Reserved Reserved PFEN Reserved WSCNT[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value Program width to flash memory...
Page 55: Option Byte Unlock Key Register (Fmc_Obkey)
GD32E23x User Manual KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] FMC_CTL unlock registers These bits are only be written by software Write KEY[31:0] with key to unlock FMC_CTL register. 2.4.3. Option byte unlock key register (FMC_OBKEY) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) OBKEY[31:16] OBKEY[15:0]...
Page 56: Control Register (Fmc_Ctl)
GD32E23x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value ENDF End of operation flag bit When the operation executed successfully, this bit is set by hardware. The software can clear it by writing 1. WPERR Erase/Program protection error flag bit When erasing/programming on protected pages, this bit is set by hardware.
Page 57 GD32E23x User Manual This bit is set or cleared by software. 0: No interrupt generated by hardware 1: End of operation interrupt enable Reserved Must be kept at reset value ERRIE Error interrupt enable bit This bit is set or cleared by software. 0: No interrupt generated by hardware 1: Error interrupt enable OBWEN...
Page 58: Address Register (Fmc_Addr)
GD32E23x User Manual 1: Main flash page program command 2.4.6. Address register (FMC_ADDR) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) ADDR[31:16] ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash command address bits These bits are set by software. ADDR bits are the address of flash erase command 2.4.7.
Page 59: Write Protection Register (Fmc_Wp)
GD32E23x User Manual OBERR Option byte read error bit. This bit is set by hardware when the option byte and its complement byte do not match, and the option byte set 0xFF. 2.4.8. Write protection register (FMC_WP) Address offset: 0x20 Reset value: 0x0000 XXXX This register has to be accessed by word(32-bit) Reserved...
Page 60: Power Management Unit (Pmu)
GD32E23x User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32E23x series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 61: Backup Domain
GD32E23x User Manual Figure 3-1. Power supply overview Backup Domain 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD PB15 WKUPN NRST WKUPF SLEEPING Cortex-M23 FWDGT SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V IRC28M PLLs LVD: Low Voltage Detector...
Page 62: Vdd / V Dda
GD32E23x User Manual When the Backup domain is supplied by V pin is connected to V ), the following functions are available:  PC13 can be used as GPIO or RTC function pin described in the Real-time clock(RTC).  PC14 and PC15 can be used as either GPIO or LXTAL Crystal oscillator pins. Note: For GD32E231 series, no PC13 pin.
Page 63: Figure 3-2. Waveform Of The Por / Pdr
GD32E23x User Manual Figure 3-2. Waveform of the POR / PDR 40mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register (PMU_CS), indicates if V is higher or lower than the LVD threshold.
Page 64: 1.2V Power Domain
GD32E23x User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC conversion accuracy, the independent power supply V implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 65: Table 3-1. Power Saving Mode Summary
GD32E23x User Manual exits from the lowest priority ISR. Deep-sleep mode ® The Deep-sleep mode is based on the SLEEPDEEP mode of the Cortex -M23. In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC8M, IRC28M, HXTAL and PLLs are disabled.
Page 66 GD32E23x User Manual Mode Sleep Deep-sleep Standby On (normal power On (normal or low power LDO Status mode) mode) SLEEPDEEP = 1 SLEEPDEEP = 1 Configuration SLEEPDEEP = 0 STBMOD = 0 STBMOD = 1, WURST=1 Entry WFI or WFE WFI or WFE WFI or WFE Any interrupt from EXTI...
Page 67: Pmu Registers
GD32E23x User Manual 3.4. PMU registers PMU base address: 0x4000 7000 3.4.1. Control register (PMU_CTL) Address offset: 0x00 Reset value: 0x0000 4000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). Reserved LDOVS[1:0] Reserved BKPWEN LVDT[2:0] LVDEN...
Page 68: Control And Status Register (Pmu_Cs)
GD32E23x User Manual Note: When LVD_LOCK bit is set to 1 in the SYSCFG_CFG2 register, LVDEN and LVDT[2:0] are read only. STBRST Standby Flag Reset 0: No effect 1: Reset the standby flag This bit is always read as 0. WURST Wakeup Flag Reset 0: No effect...
Page 69 GD32E23x User Manual WKUP pin6 wakes up the system from the power saving mode. As the WKUP pin6 is active high, the WKUP pin6 is internally configured to input pull down mode. And set this bit will trigger a wakeup event when the input is already high. WUPEN5 WKUP Pin5 (PB5) Enable 0: Disable WKUP pin5 function...
Page 70 GD32E23x User Manual RTC Tamper event, RTC alarm event，RTC Time Stamp event This bit is cleared only by a POR / PDR or by setting the WURST bit in the PMU_CTL register. For GD32E231xx devices Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit).
Page 71 GD32E23x User Manual set this bit will trigger a wakeup event when the input is already high. Reserved Must be kept at reset value. LVDF Low Voltage Detector Status Flag 0: Low Voltage event has not occurred (V is higher than the specified LVD threshold) 1: Low Voltage event occurred (V is equal to or lower than the specified LVD...
Page 72: Reset And Clock Unit (Rcu)
GD32E23x User Manual Reset and clock unit (RCU) 4.1. Reset control unit (RCTL) 4.1.1. Overview GD32E23x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, resets the full system except the backup domain during a power up.
Page 73: Clock Control Unit (Cctl)
GD32E23x User Manual A system reset resets the processor core and peripheral IP components except for the SW-DP controller and the backup domain. A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset). Figure 4-1.
Page 74: Figure 4-2. Clock Tree
GD32E23x User Manual Figure 4-2. Clock tree CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable (to FMC) (by hardware) HCLK CK_IRC8M AHB enable (to AHB bus,Cortex-M23,SRAM,DMA) 8 MHz CK_CST ×2,3,4 CK_PLL CK_SYS CK_AHB IRC8M …,32 Prescaler ÷ 8 72 MHz max 72 MHz max (to Cortex-M23 SysTick) ÷...
Page 75: Characteristics
GD32E23x User Manual 4.2.2. Characteristics  4 to 32 MHz High speed crystal oscillator (HXTAL)  Internal 8 MHz RC oscillator (IRC8M)  Internal 28 MHz RC oscillator (IRC28M)  32.768 KHz Low speed crystal oscillator (LXTAL)  Internal 40 KHz RC oscillator (IRC40K) ...
Page 76 GD32E23x User Manual Internal 8 MHz RC Oscillator (IRC8M) The internal 8 MHz RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up. The IRC8M oscillator provides a lower cost type clock source as no external components are required.
Page 77: Table 4-1. Clock Source Select
GD32E23x User Manual Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the backup domain control r2egister(RCU_BDCTL). The CK_LXTAL is equal to the external clock which drives the OSC32IN pin. Internal 40 KHz RC Oscillator (IRC40K) The internal 40 KHz RC Oscillator has a frequency of about 40 kHz and is a low power clock source for the real time clock circuit or the free watchdog timer.
Page 78: Table 4-2. Core Domain Voltage Selected In Deep-Sleep Mode
GD32E23x User Manual Clock Source Selection bits Clock Source CK_IRC8M CK_HXTAL CK_PLL or CK_PLL/2 The CK_OUT frequency can be reduced by a configurable binary divider, controlled by the CKOUTDIV[2:0] bits, in the configuration register 0(RCU_CFG0). Deep-sleep mode clock control When the MCU is in Deep-sleep mode, the USART0 can wake up the MCU, when their clock is provided by LXTAL clock and LXTAL clock is enable.
Page 79: Register Definition
GD32E23x User Manual 4.3. Register definition RCU base address: 0x4002 1000 4.3.1. Control register 0 (RCU_CTL0) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTALB HXTALST HXTALE Reserved PLLSTB PLLEN...
Page 80: Configuration Register 0 (Rcu_Cfg0)
GD32E23x User Manual state. HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0. 0: Disable the HXTAL Bypass mode 1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock.
Page 81 GD32E23x User Manual PLLPRE PLLDV CKOUTDIV[2:0] PLLMF[4] CKOUTSEL[2:0] Reserved PLLMF[3:0] PLLSEL ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions PLLDV The CK_PLL divide by 1 or 2 for CK_OUT 0: CK_PLL divide by 2 for CK_OUT 1: CK_PLL divide by 1 for CK_OUT 30:28 CKOUTDIV[2:0] The CK_OUT divider which the CK_OUT frequency can be reduced...
Page 82 GD32E23x User Manual 00010: (PLL source clock x 4) 00011: (PLL source clock x 5) 00100: (PLL source clock x 6) 00101: (PLL source clock x 7) 00110: (PLL source clock x 8) 00111: (PLL source clock x 9) 01000: (PLL source clock x 10) 01001: (PLL source clock x 11) 01010: (PLL source clock x 12) 01011: (PLL source clock x 13)
Page 83 GD32E23x User Manual clock prescaler. Set and cleared by software. 000: (CK_APB2 / 2) selected 001: (CK_ APB2 / 4) selected 010: (CK_ APB2 / 6) selected 011: (CK_ APB2 / 8) selected 100: (CK_AHB / 3) selected 101: (CK_ AHB / 5) selected 110: (CK_ AHB / 7) selected 111: (CK_ AHB / 9) selected 13:11...
Page 84: Interrupt Register (Rcu_Int)
GD32E23x User Manual Set by software to select the CK_SYS source. Because the change of CK_SYS has inherent latency, software should read SCSS to confirm whether the switching is complete or not. The switch will be forced to IRC8M when leaving Deep-sleep and Standby mode or by HXTAL clock monitor when the HXTAL failure is detected and the HXTAL is selected as the clock source of CK_SYS or PLL.
Page 85 GD32E23x User Manual HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by software to reset the HXTALSTBIF flag. 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC IRC8M stabilization interrupt clear Write 1 by software to reset the IRC8MSTBIF flag. 0: Not reset IRC8MSTBIF flag 1: Reset IRC8MSTBIF flag LXTALSTBIC...
Page 86 GD32E23x User Manual 0: Disable the IRC40K stabilization interrupt 1: Enable the IRC40K stabilization interrupt CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck. Reset by software when setting the CKMIC bit. 0: Clock operating normally 1: HXTAL clock stuck Reserved Must be kept at reset value...
Page 87: Apb2 Reset Register (Rcu_Apb2Rst)
GD32E23x User Manual 0: No IRC40K stabilization clock ready interrupt generated 1: IRC40K stabilization interrupt generated 4.3.4. APB2 reset register (RCU_APB2RST) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) TIMER16 TIMER15 TIMER14 Reserved USART0...
Page 88: Apb1 Reset Register (Rcu_Apb1Rst)
GD32E23x User Manual 0: No reset 1: Reset the SPI0 TIMER0RST TIMER0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 Reserved Must be kept at reset value ADCRST ADC reset This bit is set and reset by software. 0: No reset 1: Reset the ADC Reserved...
Page 89 GD32E23x User Manual I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset I2C0 20:18 Reserved Must be kept at reset value USART1RST USART1 reset This bit is set and reset by software.
Page 90: Ahb Enable Register (Rcu_Ahben)
GD32E23x User Manual 1: Reset TIMER2 timer Reserved Must be kept at reset value 4.3.6. AHB enable register (RCU_AHBEN) Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved PFEN Reserved. PCEN PBEN PAEN Reserved...
Page 91: Apb2 Enable Register (Rcu_Apb2En)
GD32E23x User Manual 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value FMCSPEN FMC clock enable This bit is set and reset by software to enable/disable FMC clock during Sleep mode. 0: Disabled FMC clock during Sleep mode 1: Enabled FMC clock during Sleep mode Reserved Must be kept at reset value...
Page 92 GD32E23x User Manual 1: Enabled DBGMCU clock 21:19 Reserved Must be kept at reset value TIMER16EN TIMER16 timer clock enable This bit is set and reset by software. 0: Disabled TIMER16 timer clock 1: Enabled TIMER16 timer clock TIMER15EN TIMER15 timer clock enable This bit is set and reset by software.
Page 93: Apb1 Enable Register (Rcu_Apb1En)
GD32E23x User Manual 1: Enabled System configuration and comparator clock 4.3.8. APB1 enable register (RCU_APB1EN) Address offset:0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) USART1 Reserved PMUEN Reserved I2C1EN I2C0EN Reserved Reserved WWDGT TIMER13E TIMER5E TIMER2E...
Page 94: Backup Domain Control Register (Rcu_Bdctl)
GD32E23x User Manual This bit is set and reset by software. 0: Disabled SPI1 clock 1: Enabled SPI1 clock 13:12 Reserved Must be kept at reset value WWDGTEN Window watchdog timer clock enable This bit is set and reset by software. 0: Disabled Window watchdog timer clock 1: Enabled Window watchdog timer clock 10:9...
Page 95 GD32E23x User Manual LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LXTALDRI[1:0] LXTALEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by software.
Page 96: Reset Source /Clock Register (Rcu_Rstsck)
GD32E23x User Manual 0: Disable LXTAL 1: Enable LXTAL 4.3.10. Reset source /clock register (RCU_RSTSCK) Address offset: 0x24 Reset value: 0x0C00 0000, reset flags reset by power reset only, other reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGT RSTFC...
Page 97: Ahb Reset Register (Rcu_Ahbrst)
GD32E23x User Manual Set by hardware when a power reset generated. Reset by writing 1 to the RSTFC bit. 0: No power reset generated 1: Power reset generated EPRSTF External pin reset flag Set by hardware when an external pin generated. Reset by writing 1 to the RSTFC bit.
Page 98: Configuration Register 1 (Rcu_Cfg1)
GD32E23x User Manual Reserved PFRST Reserved PCRST PBRST PARST Reserved Reserved Bits Fields Descriptions 31:23 Reserved Must be kept at reset value PFRST GPIO port F reset This bit is set and reset by software. 0: No reset GPIO port F 1: Reset GPIO port F 21:20 Reserved...
Page 99: Configuration Register 2 (Rcu_Cfg2)
GD32E23x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value PREDV[3:0] CK_HXTAL divider previous PLL This bit is set and reset by software. These bits can be written when PLL is disable Note: The bit 0 of PREDV is same as bit 17 of RCU_CFG0, so modifying bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1.
Page 100: Control Register 1 (Rcu_Ctl1)
GD32E23x User Manual IRC28MDIV IRC28M divider or not 0: IRC28M /2 used as ADC clock 1: IRC28M used as ADC clock 15:9 Reserved Must be kept at reset value ADCSEL CK_ADC clock source selection This bit is set and reset by software. 0: CK_ADC select CK_IRC28M 1: CK_ADC select CK_APB2 which is divided by 2,4,6,8 or.
Page 101: Voltage Key Register (Rcu_Vkey)
GD32E23x User Manual IRC28MSTB IRC28M Internal 28M RC oscillator stabilization Flag Set by hardware to indicate if the IRC28M oscillator is stable and ready for use. 0: IRC28M oscillator is not stable 1: IRC28M oscillator is stable IRC28MEN IRC28M Internal 28M RC oscillator enable Set and reset by software.
Page 102 GD32E23x User Manual These bits is set and reset by software 00 : The core voltage is 1.0V in Deep-sleep mode 01 : The core voltage is 0.9V in Deep-sleep mode 10 : The core voltage is 0.8V in Deep-sleep mode 11 : The core voltage is 1.2V in Deep-sleep mode...
Page 103: Interrupt/Event Controller (Exti)
GD32E23x User Manual Interrupt/event controller (EXTI) 5.1. Overview Cortex-M23 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the Technical Reference Manual of Cortex-M23 for more details about NVIC.
Page 104: Table 5-1. Nvic Exception Types In Cortex-M23
GD32E23x User Manual types. Table 5-1. NVIC exception types in Cortex-M23 Vector Exception Type Priority (a) Vector Address Description Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt 0x0000_000C All class of fault HardFault 0x0000_0010 4-10 Reserved -0x0000_002B System service call via SWI Programmable 0x0000_002C SVCall...
Page 105 GD32E23x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 18 Reserved 0x0000_0088 IRQ 19 TIMER13 global interrupt 0x0000_008C IRQ 20 TIMER14 global interrupt 0x0000_0090 IRQ 21 TIMER15 global interrupt 0x0000_0094 TIMER16 global interrupt 0x0000_0098 IRQ 22 I2C0 event interrupt 0x0000_009C IRQ 23...
Page 106: External Interrupt And Event (Exti) Block Diagram
GD32E23x User Manual 5.4. External interrupt and event (EXTI) block diagram Figure 5-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~27 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 5.5. External interrupt and Event function overview The EXTI contains up to 21 independent edge detectors and generates interrupts request or event to the processer.
Page 107 GD32E23x User Manual EXTI Line Source Number PA0 / PB0 / PF0 PA1 / PB1 / PF1 PA2 / PB2 PA3 / PB3 PA4 / PB4 PA5 / PB5 PA6 / PB6 / PF6 PA7 / PB7 / PF7 PA8 / PB8 PA9 / PB9 PA10 / PB10 PA11 / PB11...
Page 108 GD32E23x User Manual EXTI Line Source Number PA10 / PB10 PA11 / PB11 PA12 / PB12 PA13 / PB13 PA14 / PB14 / PC14 PA15 / PB15 / PC15 RTC Alarm Reserved RTC Tamper and Timestamp Reserved CMP output Reserved Reserved Reserved USART0 Wakeup...
Page 109: Register Definition
GD32E23x User Manual 5.6. Register definition EXTI base address: 0x4001 0400 5.6.1. Interrupt enable register (EXTI_INTEN) Address offset: 0x00 Reset value: 0x0F94 0000 This register has to be accessed by word (32-bit) Reserved INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8...
Page 110: Rising Edge Trigger Enable Register (Exti_Rten)
GD32E23x User Manual 1: Event from Linex is enabled 5.6.3. Rising edge trigger enable register (EXTI_RTEN) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved RTEN21 Reserved RTEN19 Reserved RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12...
Page 111: Software Interrupt Event Register (Exti_Swiev)
GD32E23x User Manual Bits Fields Descriptions 31: 22 Reserved Must be kept at reset value FTENx Falling edge trigger enable (x=21) 0: Falling edge of Linex is invalid 1: Falling edge of Linex is valid as an interrupt/event request Reserved Must be kept at reset value FTENx Falling edge trigger enable (x=19)
Page 112: Pending Register (Exti_Pd)
GD32E23x User Manual Reserved Must be kept at reset value 17: 0 SWIEVx Interrupt/Event software trigger (x=0..17) 0: Deactivate the EXTIx software interrupt/event request 1: Activate the EXTIx software interrupt/event request 5.6.6. Pending register (EXTI_PD) Address offset: 0x14 Reset value: undefined This register has to be accessed by word (32-bit) Reserved PD21...
Page 113: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32E23x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 6.1. Overview There are up to 39 general purpose I/O pins, (GPIO), named PA0 ~ PA15 and PB0 ~ PB15, PC13 ~ PC15, PF0 ~ PF1, PF6 ~ PF7 for the GD32E230xx device to implement logic input/output functions.
Page 114: Gpio Pin Configuration
GD32E23x User Manual and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 6-1. GPIO configuration table PAD TYPE CTLn PUDn Floating GPIO Pull-up INPUT Pull-down Floating Push-pull Pull-up GPIO Pull-down OUTPUT Floating Open-drain Pull-up Pull-down Floating AFIO Pull-up INPUT Pull-down...
Page 115: Alternate Functions (Af)
GD32E23x User Manual ports are configured as the input floating mode that input disabled without pull-up(PU)/pull-down(PD) resistors. But the Serial-Wired Debug pins are configured as AF PU/PD mode after reset: PA14: SWCLK in AF pull-down mode PA13: SWDIO in AF pull-up mode The GPIO pins can be configured as inputs or outputs.
Page 116: Output Configuration
GD32E23x User Manual Figure 6-2. Basic structure of Input configuration shows the input configuration of the GPIO pin. Figure 6-2. Basic structure of Input configuration 6.3.5. Output configuration When GPIO pin is configured as output:  The schmitt trigger input is activated. ...
Page 117: Alternate Function (Af) Configuration
GD32E23x User Manual  The output buffer is disabled.  The schmitt trigger input is de-activated.  Read access to the port input status register gets the value “0”. Figure 6-4. Basic structure of Analog configuration shows the analog configuration of the GPIO pin.
Page 118: Gpio Locking Function
GD32E23x User Manual 6.3.8. GPIO locking function The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD, GPIOx_AFSELy(y=0,1). It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK). When the special LOCK sequence has been applied on a port bit, it is no longer able to modify the value of the port bit until the next reset.
Page 119: Register Definition
GD32E23x User Manual 6.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOF base address: 0x4800 1400 6.4.1. Port control register (GPIOx_CTL, x=A..C,F) Address offset: 0x00 Reset value: 0x2800 0000 for port A; 0x0000 0000 for others. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) CTL15[1:0] CTL14[1:0]...
Page 120: Port Output Mode Register (Gpiox_Omode, X=A
GD32E23x User Manual These bits are set and cleared by software. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 15:14 CTL7[1:0] Pin 7 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 13:12 CTL6[1:0]...
Page 121 GD32E23x User Manual Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value OM15 Pin 15 output mode bit These bits are set and cleared by software. Refer to OM0 description OM14 Pin 14 output mode bit These bits are set and cleared by software.
Page 122: Port Output Speed Register (Gpiox_Ospd, X=A
GD32E23x User Manual Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 3 output mode bit These bits are set and cleared by software.
Page 123 GD32E23x User Manual Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 25:24 OSPD12[1:0] Pin 12 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 23:22 OSPD11[1:0]...
Page 124: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32E23x User Manual OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits These bits are set and cleared by software. x0: Output max speed 2M (reset value) 01: Output max speed 10M 11: Output max speed 50M 6.4.4.
Page 125: Port Input Status Register (Gpiox_Istat, X=A
GD32E23x User Manual Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 17:16 PUD8[1:0] Pin 8 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 15:14 PUD7[1:0]...
Page 126: Port Output Control Register (Gpiox_Octl, X=A
GD32E23x User Manual Reset value: 0x0000 XXXX This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT 0 Bits...
Page 127: Port Configuration Lock Register (Gpiox_Lock, X=A,B)
GD32E23x User Manual CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit 15:0...
Page 128: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A,B,C)
GD32E23x User Manual These bits are set and cleared by software. 0: Port configuration not locked 1: Port configuration locked 6.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C) Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) SEL7[3:0] SEL6[3:0] SEL5[3:0]...
Page 129: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A,B,C)
GD32E23x User Manual These bits are set and cleared by software. 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected 0100: AF4 selected (Port A,B only) 0101: AF5 selected (Port A,B only) 0110: AF6 selected (Port A,B only) 0111: AF7 selected (Port A,B only) 1000 ~ 1111: Reserved 6.4.10.
Page 130: Bit Clear Register (Gpiox_Bc, X=A
GD32E23x User Manual 11:8 SEL10[3:0] Pin 10 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description SEL9[3:0] Pin 9 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description SEL8[3:0] Pin 8 alternate function selected These bits are set and cleared by software.
Page 131 GD32E23x User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved TG15 TG14 TG13 TG12 TG11 TG10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 Port toggle bit y(y=0..15) These bits are set and cleared by software.
Page 132: Cyclic Redundancy Checks Management Unit (Crc)
GD32E23x User Manual Cyclic redundancy checks management unit (CRC) 7.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial.
Page 133: Function Overview
GD32E23x User Manual 7.3. Function overview  CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 134 GD32E23x User Manual is unavailable. It is strongly recommend resetting the CRC management unit after change the PS[1:0] bits or polynomial.
Page 135: Register Definition
GD32E23x User Manual 7.4. Register definition CRC base address: 0x4002 3000 7.4.1. Data register (CRC_DATA) Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit) DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 136: Control Register (Crc_Ctl)
GD32E23x User Manual Software writes and reads. These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will generate no effect to the byte. 7.4.3. Control register (CRC_CTL) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 137: Initialization Data Register (Crc_Idata)
GD32E23x User Manual 7.4.4. Initialization data register (CRC_IDATA) Address offset: 0x10 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit) IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value.
Page 138: Direct Memory Access Controller (Dma)
GD32E23x User Manual Direct memory access controller (DMA) 8.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 139: Block Diagram
GD32E23x User Manual 8.3. Block diagram Figure 8-1. Block diagram of DMA AHB slave interface Configuration … Channel 4 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 140: Table 8-1. Dma Transfer Operation
GD32E23x User Manual Suppose DMA_CHxCNT is 4, and both PNAGA and MNAGA are set. The DMA transfer operations for each combination of PWIDTH and MWIDTH are shown in the Table 8-1. DMA transfer operation. Table 8-1. DMA transfer operation Transfer size Transfer operations Source Destination...
Page 141: Peripheral Handshake
GD32E23x User Manual The CNT bits in the DMA_CHxCNT register control how many data to be transmitted on the channel and must be configured before enable the CHEN bit in the register. During the transmission, the CNT bits indicate the remaining number of data items to be transferred. The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.
Page 142: Arbitration
GD32E23x User Manual 8.4.3. Arbitration When two or more requests are received at the same time, the arbiter determines which request is served based on the priorities of channels. There are two-stage priorities, including the software priority and the hardware priority. The arbiter determines which channel is selected to respond according to the following priority rules: –...
Page 143: Channel Configuration
GD32E23x User Manual 8.4.7. Channel configuration When starting a new DMA transfer, it is recommended to respect the following steps: 1. Read the CHEN bit and judge whether the channel is enabled or not. If the channel is enabled, clear the CHEN bit by software. When the CHEN bit is read as ‘0’, configuring and starting a new DMA transfer is allowed.
Page 144: Dma Request Mapping
GD32E23x User Manual Figure 8-3. DMA interrupt logic FTFIFx FTFIEx HTFIFx CHxINTF HTFIEx ERRIFx ERRIEx Note: “x” indicates channel number (x=0…4). 8.4.9. DMA request mapping Several requests from peripherals may be mapped to one DMA channel. They are logically ORed before entering the DMA. For details, see the Figure 8-4.
Page 145: Figure 8-4. Dma Request Mapping
GD32E23x User Manual Figure 8-4. DMA request mapping Hardware priority TIMER16_CH0 high Channel 0 TIMER16_UP MEMTOMEM0 SPI/I2S0_RX USART0_TX I2C0_TX TIMER0_CH0 Channel 1 TIMER2_CH2 TIMER16_CH0 TIMER16_UP SPI/I2S0_TX USART0_RX T2C0_RX TIMER0_CH1 TIMER2_CH3 Channel 2 TIMER2_UP TIMER5_UP TIMER15_CH0 TIMER15_UP SPI1_RX USART0_TX USART1_TX I2C1_TX TIMER0_CH3 TIMER0_TRIG Channel 3...
Page 146 GD32E23x User Manual ● ● ● ● TIMER5 TIMER5_UP TIMER14_CH TIMER14_UP TIMER14_TRI ● ● ● ● TIMER14 TIMER14_CO TIMER14_CH TIMER15_CH0 TIMER15_CH0 ● ● ● TIMER15 TIMER15_UP TIMER15_UP TIMER16_CH0 TIMER16_CH0 ● ● ● TIMER16 TIMER16_UP TIMER16_UP 1. When the corresponding remapping bit in the SYSCFG_CFG0 register is cleared, the request is mapped on the channel.
Page 147: Register Definition
GD32E23x User Manual 8.5. Register definition DMA base address: 0x4002 0000 8.5.1. Interrupt flag register (DMA_INTF) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved ERRIF4 HTFIF4 FTFIF4 GIF4 ERRIF3 HTFIF3 FTFIF3 GIF3 ERRIF2 HTFIF2 FTFIF2...
Page 148: Channel X Control Register (Dma_Chxctl)
GD32E23x User Manual This register has to be accessed by word(32-bit) Reserved ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0 Bits Fields Descriptions 31:20 Reserved Must be kept at reset value 19/15/11/7/3 ERRIFCx Clear bit for error flag of channel x (x=0…4)
Page 149 GD32E23x User Manual Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’.
Page 150: Channel X Counter Register (Dma_Chxcnt)
GD32E23x User Manual Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Software set and cleared 0: Disable the channel error interrupt 1: Enable the channel error interrupt...
Page 151: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32E23x User Manual is read-only, and decreases after each DMA transfer. If the register is zero, no transaction can be issued whether the channel is enabled or not. Once the transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode.
Page 152 GD32E23x User Manual These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these bits are ignored.
Page 153: Debug (Dbg)
GD32E23x User Manual Debug (DBG) Overview 9.1. The GD32E23x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm Cortex-M23.
Page 154: Debug Support For Timer, I2C, Rtc, Wwdgt And Fwdgt
GD32E23x User Manual When the DSLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set, and entering the Deep-sleep mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in Deep-sleep mode. When the SLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set, and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode.
Page 155: Register Definition
GD32E23x User Manual 9.4. Register definition DBG base address: 0x4001 5800 9.4.1. ID code register (DBG_ID) Address offset: 0x00 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by software, These bits are unchanged constant 9.4.2.
Page 156 GD32E23x User Manual This bit is set and reset by software 0: no effect 1: hold the TIMER 5 counter for debugging when the core is halted 18:17 Reserved Must be kept at reset value I2C1_HOLD I2C1 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C1 SMBUS timeout for debugging when the core is halted I2C0_HOLD...
Page 157: Control Register 1 (Dbg_Ctl1)
GD32E23x User Manual This bit is set and reset by software 0: no effect 1: In the Deep-sleep mode, the clock of AHB bus and system clock are provided by CK_IRC8M SLP_HOLD Sleep mode hold bit This bit is set and reset by software 0: no effect 1: In the sleep mode, the clock of AHB is on.
Page 158 GD32E23x User Manual Reserved Must be kept at reset value...
Page 159: Analog To Digital Converter (Adc)
GD32E23x User Manual Analog to digital converter (ADC) 10.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 10 external channels and 2 internal channels. The 12 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment or the most significant bit alignment.
Page 160: Pins And Internal Signals
GD32E23x User Manual – Programmable data shift up to 8-bits.  ≤V ≤V Channel input range: V 10.3. Pins and internal signals Figure 10-1. ADC module block diagram shows the ADC block diagram. Table 10-1. ADC internal input signals Table 10-2. ADC input pins definition give the ADC internal signals and pins description.
Page 161: Function Overview
GD32E23x User Manual 10.4. Function overview Figure 10-1. ADC module block diagram Trig select DMA request routine sequence Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO ADC_IN9 Over routine data registers SAR ADC 6~12-bit （16 bits） sampler SENSE REFINT...
Page 162: Dual Clock Domain Architecture
GD32E23x User Manual Wait for CLB =0. 10.4.2. Dual clock domain architecture The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock, which can be asynchronous and independent from the APB clock. Application can reduce PLCK frequency for low power operation while still keeping optimum ADC performance.
Page 163: Figure 10-3. Continuous Operation Mode
GD32E23x User Manual Software procedure for single operation mode of a routine channel: Make sure the DISRC, SM bits in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset; Configure RSQ0 with the analog channel number. Configure the ADC_SAMPTx register. Configure the ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 164: Figure 10-4. Scan Operation Mode, Continuous Disable
GD32E23x User Manual Scan operation mode The scan operation mode will be enabled when the SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in the routine sequence till the end of the sequence, once the corresponding software trigger or external trigger is active.
Page 165: Conversion Result Threshold Monitor Function
GD32E23x User Manual the ADC_CTL0 register. When the corresponding software trigger or external trigger is active, samples converts next channels configured ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set.
Page 166: Figure 10-7. Data Storage Mode Of 12-Bit Resolution
GD32E23x User Manual mode of 12-bit resolution, Figure 10-8. Data storage mode of 10-bit resolution, Figure 10-9. Data storage mode of 8-bit resolution Figure 10-10. Data storage mode of 6-bit resolution. Figure 10-7. Data storage mode of 12-bit resolution Figure 10-8. Data storage mode of 10-bit resolution Figure 10-9.
Page 167: Sample Time Configuration
GD32E23x User Manual 10.4.8. Sample time configuration The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn [2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. A different sampling time can be specified for each channel. For 12-bit resolution, the total sampling and conversion time is “sampling time + 12.5”...
Page 168: Programmable Resolution (Dres) - Fast Conversion Mode
GD32E23x User Manual The output voltage of the temperature sensor changes linearly with temperature. Because there is an offset, which is up to 45° C and varies from chip to chip due to the chip production process variation, the internal temperature sensor is more appropriate to detect temperature variations than absolute temperature.
Page 169: Figure 10-11. 20-Bit To 16-Bit Result Truncation
GD32E23x User Manual It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. The on-chip hardware oversampling circuit is enabled by OVSEN bit in the ADC_OVSAMPCTL register.It provides a result with the following form, where N and M can be adjusted, and D (n) is the n-th output digital signal of the ADC: n=N−1...
Page 170: Table 10-5. Maximum Output Results For N And M Combimations (Grayed Values Indicates Truncation)
GD32E23x User Manual Figure 10-12. A numerical example with 5-bit shifting and rounding Table 10-5. Maximum output results for N and M combimations (grayed values indicates truncation) below gives the data format for the various N and M combinations, and the raw conversion data equals 0xFFF. Table 10-5.
Page 171: Adc Interrupts
GD32E23x User Manual The oversampling configuration can only be changed when ADCON is reset. Make sure configuring the oversampling before setting ADCON to 1. 10.4.14. ADC interrupts The interrupt can be produced on one of the events:  End of conversion for routine sequence. ...
Page 172: Register Definition
GD32E23x User Manual 10.5. Register definition ADC base address: 0x4001 2400 10.5.1. Status register (ADC_STAT) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved STRC Reserved rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:5 Reserved...
Page 173 GD32E23x User Manual This register has to be accessed by word(32-bit). Reserved DRES [1:0] RWDEN Reserved DISNUM [2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL [4:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value 25:24 DRES[1:0] ADC resolution 00: 12bit 01: 10bit...
Page 174: Control Register 1 (Adc_Ctl1)
GD32E23x User Manual 0: Interrupt disable 1: Interrupt enable WDCHSEL[4:0] Analog watchdog channel select 00000: ADC channel 0 00001: ADC channel 1 00010: ADC channel 2 …… 01000: ADC channel 8 01001: ADC channel9 01010: ADC channel 16 01011: ADC channel 17 Other values are reserved.
Page 175: Sample Time Register 0 (Adc_Sampt0)
GD32E23x User Manual 000: TIMER0 CH0 001: TIMER0 CH1 010: TIMER0 CH2 011: reserved 100: TIMER2 TRGO 101: TIMER14 CH0 110: EXTI line 11 111: SWRCST 16:12 Reserved Must be kept at reset value Data alignment 0: LSB alignment 1: MSB alignment 10:9 Reserved Must be kept at reset value...
Page 176: Sample Time Register 1 (Adc_Sampt1)
GD32E23x User Manual Reserved SPT17[2:0] SPT16[2:0] Reserved Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:21 SPT17[2:0] Refer to SPT16[2:0] description 20:18 SPT16[2:0] Channel sampling time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles 100: channel sampling time is 41.5 cycles...
Page 177: Watchdog Low Threshold Register (Adc_Wdlt)
GD32E23x User Manual 17:15 SPT5[2:0] Refer to SPT0[2:0] description 14:12 SPT4[2:0] Refer to SPT0[2:0] description 11:9 SPT3[2:0] Refer to SPT0[2:0] description SPT2[2:0] Refer to SPT0[2:0] description SPT1[2:0] Refer to SPT0[2:0] description SPT0[2:0] Channel sampling time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles...
Page 178: Routine Sequence Register 1 (Adc_Rsq1)
GD32E23x User Manual RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:20 RL[3:0] Routine sequence length The total number of conversion in routine sequence equals to RL[3:0] +1. 19:15 RSQ15[4:0] Refer to RSQ0[4:0] description 14:10 RSQ14[4:0] Refer to RSQ0[4:0] description...
Page 179: Routine Sequence Register 2 (Adc_Rsq2)
GD32E23x User Manual 10.5.9. Routine sequence register 2 (ADC_RSQ2) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RSQ5[4:0] RSQ4[4:0] RSQ3[4:1] RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:25 RSQ5[4:0] Refer to RSQ0[4:0] description...
Page 180: Oversampling Control Register (Adc_Ovsampctl)
GD32E23x User Manual 10.5.11. Oversampling control register (ADC_OVSAMPCTL) Address offset: 0x80 Reset value: 0x0000_0000 This register has to be accessed by word(32-bit). Reserved Reserved TOVS OVSS[3:0] OVSR[2:0] Reserved OVSEN Bits Fields Descriptions 31:10 Reserved Must be kept at reset value TOVS Triggered Oversampling This bit is set and cleared by software.
Page 181 GD32E23x User Manual 101: 64x 110: 128x 111: 256x Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress). Reserved Must be kept at reset value OVSEN Oversampling enable This bit is set and cleared by software.
Page 182: Comparator (Cmp)
GD32E23x User Manual Comparator (CMP) 11.1. Introduction The general purpose comparator can work either standalone (all terminal are available on I/Os) or together with the timers. 11.2. Main features  Rail-to-rail comparators  Configurable hysteresis  Configurable speed and consumption ...
Page 183: Cmp Clock And Reset
GD32E23x User Manual Figure 11-1. CMP block diagram Note: V is 1.2V. REFINT 11.3.1. CMP clock and reset The CMP clock is synchronous with the PCLK. The CMP share common reset and clock enable bits with SYSCFG. 11.3.2. CMP I/O configuration These pins must be configured in analog mode before they are selected as CMP inputs.
Page 184: Cmp Hysteresis
GD32E23x User Manual 11.3.4. CMP hysteresis In order to avoid spurious output transitions that caused by the noise signal, a programmable hysteresis is designed to force the hysteresis value by using external components. This function could be shut down if it is unnecessary. Figure 11-2.
Page 185: Cmp Registers
GD32E23x User Manual 11.4. CMP registers CMP base address：0x4001 001C 11.4.1. Control/status register (CMP_CS) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CMPLK CMPO CMPHST[1:0] CMPPL CMPOSEL[2:0] Reserved CMPMSEL[2:0] CMPM[1:0] CMPSW CMPEN rw/r rw/r...
Page 186 GD32E23x User Manual 001: TIMER0 break input 010: TIMER0 channel0 input capture 011: TIMER0 OCPRE_CLR input 100: Reserved 101: Reserved 110: TIMER2 channel0 input capture 111: TIMER2 OCPRE_CLR input Reserved Must be kept at reset value CMPMSEL[2:0] CMP_IM input selection These bits are used to select the source connected to the CMP_IM input of the CMP.
Page 187: Watchdog Timer (Wdgt)
GD32E23x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 188: Figure 12-1. Free Watchdog Block Diagram
GD32E23x User Manual Figure 12-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at any time.
Page 189: Table 12-1. Min/Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32E23x User Manual Table 12-1. Min/max FWDGT timeout period at 40 kHz (IRC40K) Min timeout (ms) RL[11:0]= Max timeout (ms) RL[11:0]= Prescaler divider PSC[2:0] bits 0x000 0xFFF 1 / 4 0.025 409.525 1 / 8 0.025 819.025 1 / 16 0.025 1638.025 1 / 32...
Page 190: Register Definition
GD32E23x User Manual 12.1.4. Register definition FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 191 GD32E23x User Manual bit in the FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until...
Page 192 GD32E23x User Manual Status register (FWDGT_STAT) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter window value update. When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 193 GD32E23x User Manual this register. The WUD bit in the FWDGT_STAT register must be reset in order to be able to change the reload value. These bits are write protected. Write 5555h in the FWDGT_CTL register before writing these bits. If several window values are used by the application, it is mandatory to wait until WUD bit has been reset before changing the window value.
Page 194: Window Watchdog Timer (Wwdgt)
GD32E23x User Manual 12.2. Window watchdog timer (WWDGT) 12.2.1. Overview The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 195: Figure 12-2. Window Watchdog Timer Block Diagram
GD32E23x User Manual Figure 12-2. Window watchdog timer block diagram The watchdog is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 196: Figure 12-3. Window Watchdog Timing Diagram
GD32E23x User Manual Figure 12-3. Window watchdog timing diagram Calculate the WWDGT timeout by using the formula below. �� × ( �� [ 5: 0 ] + 1 ) × 4096 × 2 (��) (12-1) WWDGT PCLK1 where: : WWDGT timeout WWDGT : APB1 clock period measured in ms PCLK1...
Page 197: Register Definition
GD32E23x User Manual 12.2.4. Register definition WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. WDGTEN Start the Window watchdog timer.
Page 198 GD32E23x User Manual reaches 0x40. It can be cleared by a hardware reset or software clock reset (refer to 4.3.5. APB1 reset register ) . A write operation of 0 has no effect. PSC[1:0] Prescaler. The time base of the watchdog counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4...
Page 199: Real-Time Clock(Rtc)
GD32E23x User Manual Real-time clock(RTC) 13.1. Overview The RTC provides a time which includes hour/minute/second/sub-second and a date including year/month/day/week day. The time and date are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjustment for daylight saving time.
Page 200: Function Overview
GD32E23x User Manual 13.3. Function overview 13.3.1. Block diagram Figure 13-1. Block diagram of RTC ALARM 0 Alarm-0 Flag Alarm-0 logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_spre (Default 1 Hz) IRC40K 15-bit 7-bit ck_apre Digital (Default 256 Hz) Synchronous Asynchronous...
Page 201: Clock Source And Prescalers
GD32E23x User Manual reference clock input: RTC_REFIN(50 or 60 Hz) 13.3.2. Clock source and prescalers RTC unit has three independent clock sources: LXTAL, IRC40K and HXTAL divided by 32. In the RTC unit, there are two prescalers used for implementing the calendar and other functions.
Page 202: Rtc Initialization And Configuration
GD32E23x User Manual If a field is masked, the field is considered as matched in logic. If all the fields have been masked, the Alarm Flag will assert 3 RTC clock later after ALRMxEN (x=0) is set. 13.3.5. RTC initialization and configuration RTC register write protection BKPWEN bit in the PMU_CTL register is cleared in default, so writing to RTC registers needs setting BKPWEN bit ahead of time.
Page 203: Calendar Reading
GD32E23x User Manual S1H and A1H can subtract or add 1 hour to the calendar when the calendar is running.S1H and A1H operation can be tautologically set and DSM bit can be used to recording this adjustment operation. After setting the S1H/A1H, subtracting/adding 1 hour will perform when next second comes.
Page 204: Resetting The Rtc
GD32E23x User Manual after a system reset after an initialization after shift function Especially that software must clear RSYNF bit and wait it asserted before reading calendar register after wakeup from power saving mode. Reading calendar registers under BPSHAD=1 When BPSHAD=1, RSYNF is cleared and maintains as 0 by hardware so reading calendar registers does not care about RSYNF bit.
Page 205: Rtc Shift Function
GD32E23x User Manual 13.3.8. RTC shift function When there is a remote clock with higher degree of precision and RTC 1Hz clock(ck_spre)has an offset (in a fraction of a second) with the remote clock, RTC unit provides a function named shift function to remove this offset and thus make second precision higher.
Page 206: Rtc Smooth Digital Calibration
GD32E23x User Manual the reference clock is detected in the window. When the two clock (ck_spre and reference clock) edges are aligned, this reload operation has no effect for 1Hz clock. But when the two clock edge are not aligned, this reload operation will shift ck_spre clock edge a bit to make the ck_spre(1Hz) clock edge aligned to the reference clock edge.
Page 207 GD32E23x User Manual Calibration when FACTOR_A < 3 When asynchronous prescaler value (FACTOR_A) is set to less than 3, software should not set FREQI bit to 1 when using calibration function. FREQI setting will be ignored when FACTOR_A<3. When the FACTOR_A is less than 3, the FACTOR_S value should be set to a value less than the nominal value.
Page 208: Time-Stamp Function (Only For Gd32E230Xx Devices)
GD32E23x User Manual Write the new value into RTC_HRFC register After 3 ck_apre clocks, the new calibration settings take effect 13.3.11. Time-stamp function (Only for GD32E230xx devices) Time-stamp function is performed on RTC_TS pin and is enabled by control bit TSEN. When a time-stamp event occurs on RTC_TS pin, the calendar value will be saved in time-stamp registers (RTC_DTS/RTC_TTS/RTC_SSTS) and the time-stamp flag (TSF) is set to 1 by hardware.
Page 209: Calibration Clock Output
GD32E23x User Manual Edge detection mode on tamper input detection When FLT bit is set to 0x0, the tamper detection is set to edge detection mode and TPxEG bit determines the rising edge or falling edge is the detecting edge. When tamper detection is under edge detection mode, the internal pull-up resistors on the tamper detection input pin are deactivated.
Page 210: Rtc Power Saving Mode Management
GD32E23x User Manual function will directly output the content of alarm flag in RTC_STAT. The OPOL bit in RTC_CTL can configure the polarity of the alarm output which means that the RTC_ALARM output is the opposite of the corresponding flag bit or not. 13.3.15.
Page 211 GD32E23x User Manual Tamper 1 TP1F TPIE Y(*) Y(*) * Only active when RTC clock source is LXTAL or IRC40K. For GD32E231xx devices Exit Exit Exit Interrupt Event flag Control Bit Sleep Deep-sleep Standby Alarm 0 ALRM0F ALRM0IE Y(*) Y(*) Tamper 1 TP1F TPIE...
Page 212: Register Definition
GD32E23x User Manual 13.4. Register definition RTC base address: 0x4000 2800 13.4.1. Time register (RTC_TIME) Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state This register has to be accessed by word(32-bit) Reserved HRT[1:0]...
Page 213: Control Register (Rtc_Ctl)
GD32E23x User Manual This register has to be accessed by word(32-bit) Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:20 YRT[3:0] Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0]...
Page 214 GD32E23x User Manual 31:24 Reserved Must be kept at reset value COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output 0x2: Reserved 0x3: Reserved...
Page 215 GD32E23x User Manual 1: Enable time-stamp function 10:9 Reserved Must be kept at reset value ALRM0EN Alarm-0 function enable 0: Disable alarm function 1: Enable alarm function Reserved Must be kept at reset value Clock System 0: 24-hour format 1: 12-hour format Note: Can only be written in initialization state BPSHAD Shadow registers bypass control...
Page 216 GD32E23x User Manual Daylight saving mark This bit is flexible used by software. Often can be used to recording the daylight saving hour adjustment. Subtract 1 hour(winter time change) One hour will be subtracted from current time if it is not 0 0: No effect 1: 1 hour will be subtracted at next second change time.
Page 217: Status Register (Rtc_Stat)
GD32E23x User Manual 13.4.4. Status register (RTC_STAT) For GD32E230xx devices Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0. Others are not affected Backup domain reset value: 0x0000 0007 This register is writing protected except RTC_STAT[14:8]. This register has to be accessed by word(32-bit) Reserved SCPF...
Page 218 GD32E23x User Manual Cleared by software writing 0. INITM Enter initialization mode 0: Free running mode 1: Enter initialization mode for setting calendar time/date and prescaler. Counter will stop under this mode. INITF Initialization state flag Set to 1 by hardware, calendar registers and prescaler can be programmed in this state.
Page 219 GD32E23x User Manual Reserved TP1F Reserved ALRM0F INITM INITF RSYNF SOPF Reserved ALRM0WF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value SCPF Smooth calibration pending flag Set to 1 by hardware when software writes to RTC_HRFC without entering initialization mode and set to 0 by hardware when smooth calibration configuration is taken into account.
Page 220: Prescaler Register (Rtc_Psc)
GD32E23x User Manual SOPF Shift function operation pending flag 0:No shift operation is pending 1:Shift function operation is pending Reserved Must be kept at reset value ALRM0WF Alarm 0 configuration can be write flag Set by hardware if alarm register can be written after ALRM0EN bit has reset. 0:Alarm registers programming is not allowed 1:Alarm registers programming is allowed 13.4.5.
Page 221: Write Protection Key Register (Rtc_Wpk)
GD32E23x User Manual MSKM MNT[2:0] MNU[3:0] MSKS SCT[2:0] SCU[3:0] Bits Fields Descriptions MSKD Alarm date mask bit 0:Not mask date/day field 1:Mask date/day field DOWS Day of the week selected 0:DAYU[3:0] indicates the date units 1: DAYU[3:0] indicates the week day and DAYT[1:0] has no means. 29:28 DAYT[1:0] Date tens in BCD code...
Page 222: Sub Second Register (Rtc_Ss)
GD32E23x User Manual This register has to be accessed by word(32-bit) Reserved Reserved WPK[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value WPK[7:0] Key for write protection 13.4.8. Sub second register (RTC_SS) Address offset: 0x28 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1.
Page 223: Time Of Time Stamp Register (Rtc_Tts)
GD32E23x User Manual Reserved SFS[14:0] Bits Fields Descriptions One second add 0:Not add 1 second 1:Add 1 second to the clock/calendar. This bit is jointly used with SFS field to add a fraction of a second to the clock. 30:15 Reserved Must be kept at reset value 14:0...
Page 224: Date Of Time Stamp Register (Rtc_Dts)
GD32E23x User Manual Reserved Must be kept at reset value 14:12 MNT[2:0] Minute tens in BCD code 11:8 MNU[3:0] Minute units in BCD code Reserved Must be kept at reset value SCT[2:0] Second tens in BCD code SCU[3:0] Second units in BCD code 13.4.11.
Page 225: High Resolution Frequency Compensation Register (Rtc_Hrfc)
GD32E23x User Manual This register has to be accessed by word(32-bit) Reserved SSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler when TSF is set to 1. 13.4.13.
Page 226: Tamper Register (Rtc_Tamp)
GD32E23x User Manual Note: When CWND16=1, CMSK[0] are stuck at “0”. 12:9 Reserved Must be kept at reset value CMSK[8:0] Calibration mask number The number of mask pulse out of 2 RTCCLK pulse. This feature will decrease the frequency of calendar with a resolution of 0.9537 PPM.
Page 227 GD32E23x User Manual 0:PC13 is in open-drain output type 1:PC13 is in push-pull output type all RTC alternate functions are disabled and PC13MDE=1: When 0:PC13 output 0 1:PC13 output 1 17:16 Reserved Must be kept at reset value DISPU RTC_TAMPx pull up disable bit 0:Enable inner pull-up before sampling for pre-charge RTC_TAMPx pin 1:Disable pre-charge duration 14:13...
Page 228 GD32E23x User Manual If tamper detection is in edge mode(FLT =0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event If tamper detection is in level mode(FLT !=0): 0: Low level triggers a tamper detection event 1: High level triggers a tamper detection event TP1EN Tamper 1 detection enable...
Page 229 GD32E23x User Manual LXTAL is disable 1:Force PC15 to push-pull output if PC15VAL PC15 Value Only valid when LXTAL is disabled and PC15MDE=1,PC15 output this bit data. PC14MDE PC14 Mode 0:No effect LXTAL is disable 1:Force PC14 to push-pull output if PC14VAL PC14 Value Only valid when LXTAL is disabled and PC14MDE=1,PC14 output this bit data.
Page 230: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32E23x User Manual 0:No effect 1:TSF is set when tamper event detected even TSEN=0 Reserved Must be kept at reset value TP1EG Tamper 1 event trigger edge If tamper detection is in edge mode(FLT =0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event If tamper detection is in level mode(FLT !=0): 0: Low level triggers a tamper detection event...
Page 231: Backup Registers (Rtc_Bkpx) (X=0
GD32E23x User Manual 0x4: SSC[3:0] is to be compared and all others are ignored 0x5: SSC[4:0] is to be compared and all others are ignored 0x6: SSC[5:0] is to be compared and all others are ignored 0x7: SSC[6:0] is to be compared and all others are ignored 0x8: SSC[7:0] is to be compared and all others are ignored 0x9: SSC[8:0] is to be compared and all others are ignored 0xA: SSC[9:0] is to be compared and all others are ignored...
Page 232: Timer (Timerx)
GD32E23x User Manual Timer (TIMERx) Table 14-1. Timers (TIMERx) are devided into six sorts TIMER TIMER0 TIMER2 TIMER13 TIMER14 TIMER15/16 TIMER5 TYPE Advanced General-L0 General-L2 General-L3 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN,...
Page 233: Advanced Timer (Timerx, X=0)
GD32E23x User Manual 14.1. Advanced timer (TIMERx, x=0) 14.1.1. Overview The advanced timer module (TIMER0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The advanced timer has a 16-bit counter that can be used as an unsigned counter.
Page 234: Block Diagram
GD32E23x User Manual 14.1.3. Block diagram Figure 14-1. Advanced timer block diagramprovides details of the internal configuration of the advanced timer. Figure 14-1. Advanced timer block diagram...
Page 235: Function Overview
GD32E23x User Manual 14.1.4. Function overview Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is from module RCU.
Page 236: Figure 14-3. Timing Chart Of Psc Value Change From 0 To 2
GD32E23x User Manual 0x1, 0x2 or 0x3.  SMC1== 1’b1 (external clock mode 1). External input ETI is selected as timer clock source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 237: Figure 14-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E23x User Manual will be generated. In addition, the update events will be generated after (TIMERx_CREP+1) times of overflow events. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode. Whenever, if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update event.
Page 238: Figure 14-5. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32E23x User Manual Timing chart of up counting mode Figure 14-5. , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE)
Page 239: Figure 14-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32E23x User Manual Timing chart of down counting mode, PSC=0/2 Figure 14-6. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Timing chart of down counting mode Figure 14-7.
Page 240 GD32E23x User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting direction and generates an underflow event when the counter counts to 1 in the down-counting direction.
Page 241: Figure 14-8. Timing Chart Of Center-Aligned Counting Mode
GD32E23x User Manual Timing chart of center-aligned counting mode Figure 14-8. TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register.
Page 242: Figure 14-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32E23x User Manual effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overflow.
Page 243: Figure 14-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32E23x User Manual Repetition counter timing chart of down counting mode Figure 14-11. TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare outputs.
Page 244: Figure 14-12. Channel Input Capture Principle
GD32E23x User Manual Channel input capture principle Figure 14-12. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 245: Figure 14-13. Channel Output Compare Principle (With Complementary Output, X=0,1,2)
GD32E23x User Manual Result: When the wanted input signal is captured, TIMERx_CHxCV will be set by counter’s value and CHxIF is asserted. If the CHxIF is 1, the CHxOF will also be asserted. The interrupt and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN.
Page 246: Figure 14-15. Output-Compare In Three Modes
GD32E23x User Manual 1) Configure CHxP=0 (the active level of CHx_O is high, the same as OxCPRE), CHxE=1 (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;...
Page 247: Figure 14-16. Timing Chart Of Eapwm
GD32E23x User Manual Figure 14-15. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bit to 3’b110 (PWM mode 0) or to 3’b 111(PWM mode 1)), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 248 GD32E23x User Manual Figure 14-16. Timing chart of EAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Figure 14-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF...
Page 249: Table 14-2. Complementary Outputs Controlled By Parameters
GD32E23x User Manual original level by configuring the CHxCOMCTL field to 0x00, setting to high by configuring the CHxCOMCTL field to 0x01, setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
Page 250 GD32E23x User Manual Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O = ISOx CHx_ON = ISOxN CHx_O/CHx_ON = LOW CHx_O/CHx_ON output disable. CHx_O = LOW CHx_ON=OxCPRE⊕CHxNP CHx_O output disable. CHx_ON output enable CHx_O=OxCPRE⊕CHxP CHx_ON = LOW CHx_O output enable CHx_ON output disable.
Page 251: Figure 14-18. Complementary Output With Dead Time Insertion
GD32E23x User Manual signal is always inactive (As shown in Figure 14-18. Complementary output with dead time insertion). Figure 14-18. Complementary output with dead time insertion CHxVAL CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime > pulse width Pulse width CHx_O Deadtime CHx_ON Deadtime...
Page 252: Figure 14-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32E23x User Manual Figure 14-19. Output behavior of the channel in response to a break (the break high active) BRKIN OxCPRE = ISOx CHx_O CHxEN: 1 CHxNEN: 1 CHxP : 0 CHxNP : 0 = ISOxN ISOx = ~ISOxN CHx_ON = ISOx CHx_O CHxEN: 1 CHxNEN: 0...
Page 253: Figure 14-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32E23x User Manual SMC [2:0]=3’b011 CI1FE1= Down CI0FE0= Down CI0FE0= Down Note: "-" means "no counting"; "X" means impossible. ”0” means “low level”, ”1” means “high level”. Figure 14-20. Counter behavior with CI0FE0 polarity non-inverted in mode 2 CI0FE0 CI1FE1 TIMERx_CAR 24 25 23 22...
Page 254 GD32E23x User Manual TIMER_out will generate PWM signal to control BLDC motor’s speed based on the ITRx. Then, the feedback circuit is finished, also you change configuration to fit your request. About the TIMER_in, it need have input XOR function, so you can choose from Advanced/GeneralL0 TIMER.
Page 255: Figure 14-23. Hall Sensor Timing Between Two Timers
GD32E23x User Manual Figure 14-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode and event mode which is selected by the SMC[2:0] bits in the TIMERx_SMCFG register.
Page 256: Figure 14-24. Restart Mode
GD32E23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 110: CI1FE1 the trigger source, For the ETIFP, filter 111: ETIFP configure the ETP for can be used by polarity selection and configuring ETFC and inversion. prescaler can be used by configuring ETPSC.
Page 257: Figure 14-26. Event Mode
GD32E23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event mode ETPSC = 1, ETI is The counter will start TRGS[2:0] =3’b111 ETP = 0, the polarity of divided by 2. to count when a rising ETIFP is selected. ETI does not change.
Page 258: Figure 14-28. Timer0 Master/Slave Mode Timer Example
GD32E23x User Manual Figure 14-27. Single pulse mode TIMERx_CHxCV=4, TIMERx_CAR=99 Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt.
Page 259 GD32E23x User Manual Figure 14-28. TIMER0 Master/Slave mode timer example TIMER0 TIMER 14 TRGS Master ITI0 TRG O mode Pre scaler Counter control TIMER 2 Trigger Master ITI2 selection TRG O mode Pre scaler Counter control CI0F_ED CI0FE0 CI1FE1 ETIFP Other interconnection examples: ...
Page 260: Figure 14-29. Triggering Timer0 With Enable Signal Of Timer2
GD32E23x User Manual mode, so Timer0 can not be disabled by Timer2’s disable signal. Do as follow: 1. Configure Timer2 master mode to send its enable signal as trigger output (MMC=3’b001 in the TIMER2_CTL1 register) 2. Configure Timer0 to select the input trigger from Timer2 (TRGS=3’b010 in the TIMERx_SMCFG register).
Page 261: Figure 14-30. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32E23x User Manual Figure 14-30. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event.
Page 262: Timerx Registers(X=0)
GD32E23x User Manual 14.1.5. TIMERx registers(x=0) TIMER0 base address: 0x4001 2C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 263 GD32E23x User Manual After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable.
Page 264 GD32E23x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 265 GD32E23x User Manual 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit.
Page 266 GD32E23x User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 267 GD32E23x User Manual 4’b0010 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 268 GD32E23x User Manual 011: Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other. 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode.
Page 269 GD32E23x User Manual 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable...
Page 270 GD32E23x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description...
Page 271 GD32E23x User Manual Refer to CH0IF description Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
Page 272 GD32E23x User Manual transfer can occur if enabled. 0: No generate a trigger event 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 273 GD32E23x User Manual Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 274 GD32E23x User Manual equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV. 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV.
Page 275 GD32E23x User Manual 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value...
Page 276 GD32E23x User Manual 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection Same as Output compare mode...
Page 277 GD32E23x User Manual Note: When CH3MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. CH2COMCEN Channel 2 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal will be cleared.
Page 278 GD32E23x User Manual CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM1 or PWM2 mode.
Page 279 GD32E23x User Manual 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 280 GD32E23x User Manual Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable...
Page 281 GD32E23x User Manual trigger operation in slave mode. And CIxFE0 will not be inverted. [CH0NP==0, CH0P==1]: CIxFE0’s falling edge is the active signal for capture or trigger operation in slave mode. And CIxFE0 will be inverted. [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode.
Page 282 GD32E23x User Manual PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 283 GD32E23x User Manual Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
Page 284 GD32E23x User Manual CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 285 GD32E23x User Manual Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 286 GD32E23x User Manual Note: This bit is only valid when CHxMS=2’b00. OAEN Output automatic enable 0: The POEN bit can only be set by software. 1: POEN can be set at the next update event, if the break input is not active. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 287 GD32E23x User Manual and the ROS/IOS bits in TIMERx_CCHP register are writing protected. 11: PROT mode 2. In addition of the registers in PROT mode 1, the CHxCOMCTL/ CHxCOMSEN bits in TIMERx_CHCTL0/1 registers (if the related channel is configured in output) are writing protected. This bit-field can be written only once after the reset.
Page 288 GD32E23x User Manual specifies the address you just access. And then the second access to the TIMERx_DMATB, you will access the address of start address + 0x4. DMA transfer buffer register (TIMERx_DMATB) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DMATB[15:0] Bits...
Page 289 GD32E23x User Manual write access ignored 0: No effect OUTSEL The output value selection This bit-field set and reset by software 1: If POEN and IOS is 0, the output disabled 0: No effect...
Page 290: General Level0 Timer (Timerx, X=2)
GD32E23x User Manual 14.2. General level0 timer (TIMERx, x=2) 14.2.1. Overview The general level0 timer module (TIMER2) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level0 timer has a 16-bit counter that can be used as an unsigned counter.
Page 291: Function Overview
GD32E23x User Manual Figure 14-31. General Level 0 timer block diagram 14.2.4. Function overview Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an...
Page 292: Figure 14-32. Timing Chart Of Internal Clock Divided By 1
GD32E23x User Manual alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when theSMC [2:0] == 3’b000.
Page 293: Figure 14-33. Timing Chart Of Psc Value Change From 0 To 2
GD32E23x User Manual is set the SMC [2:0] to 0x7 and the TRGS [2:0] to 0x7 respectively. Note that the ETI signal is derived from the ETI pin sampled by a digital filter. When the clock source is selected to come from the ETI signal, the trigger controller including the edge detection circuitry will generate a clock pulse during each ETI signal rising edge to clock the counter prescaler.
Page 294: Figure 14-34. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E23x User Manual When an update event occurs, all the shadow registers (counter auto reload register, prescaler register) are updated. Figure 14-34. Timing chart of up counting mode, PSC=0/2 Figure 14-35. Timing chart of up counting mode, change TIMERx_CAR on the go.
Page 295: Figure 14-35. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32E23x User Manual Timing chart of up counting mode Figure 14-35. , change TIMERx_CAR on the go. TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE)
Page 296: Figure 14-37. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32E23x User Manual Timing chart of down counting mode Figure 14-36. , PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Timing chart of down counting mode Figure 14-37.
Page 297: Figure 14-38. Timing Chart Of Center-Aligned Counting Mode
GD32E23x User Manual Counter center-aligned counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The TIMER module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting mode and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 298 GD32E23x User Manual Figure 14-38. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Input capture and output compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 299: Figure 14-39. Channel Input Capture Principle
GD32E23x User Manual Channel input capture principle Figure 14-39. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 300: Figure 14-40. Channel Output Compare Principle (X=0,1,2,3)
GD32E23x User Manual value and CHxIF is asserted. If the CHxIF is 1, the CHxOF will also be asserted. The interrupt and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: A DMA request or interrupt is generated by setting CHxG directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 301: Figure 14-41. Output-Compare Under Three Modes
GD32E23x User Manual Step2: Compare mode configuration.  Set the shadow enable mode by CHxCOMSEN.  Set the output mode (set/clear/toggle) by CHxCOMCTL.  Select the active polarity by CHxP.  Enable the output by CHxEN. Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV.
Page 302: Figure 14-42. Timing Chart Of Eapwm
GD32E23x User Manual by TIMERx_CHxCV. Figure 14-42. Timing chart of EAPWM shows the EAPWM output and interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV. Figure 14-43. Timing chart of CAPWM shows the CAPWM output and interrupts waveform.
Page 303 GD32E23x User Manual Figure 14-43. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal As is shown in Figure 14-40. Channel output compare principle (x=0,1,2,3) when TIMERx is configured in compare match output mode,a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal.
Page 304 GD32E23x User Manual Configure the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register, the OxCPRE signal can be forced to 0 when the ETIFP signal derived from the external ETI pin is set to a high level. The OxCPRE signal will not return to its active level until the next update event occurs. Quadrature decoder Refer to Quadrature...
Page 305: Timerx Registers(X=2)
GD32E23x User Manual 14.2.5. TIMERx registers(x=2) TIMER2 base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 306 GD32E23x User Manual After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable.
Page 307 GD32E23x User Manual Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 308 GD32E23x User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 309 GD32E23x User Manual according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level. The filtering capability configuration is as follows: EXTFC[3:0] Times SAMP...
Page 310 GD32E23x User Manual SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level.
Page 311 GD32E23x User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 312 GD32E23x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 313 GD32E23x User Manual mode, this flag is set when a compare event occurs. 0: No Channel 1 interrupt occurred 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG)
Page 314 GD32E23x User Manual if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high. 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by software, and cleared by hardware automatically.
Page 315 GD32E23x User Manual TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 316 GD32E23x User Manual The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the...
Page 317 GD32E23x User Manual 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
Page 318 GD32E23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable...
Page 319 GD32E23x User Manual 110: PWM mode 0. When counting up, O2CPRE is high when the counter is smaller than TIMERx_CH2CV, and low otherwise. When counting down, O2CPRE is low when the counter is larger than TIMERx_CH2CV, and high otherwise. 111: PWM mode 1. When counting up, O2CPRE is low when the counter is smaller than TIMERx_CH2CV, and high otherwise.
Page 320 GD32E23x User Manual 31:16 Reserved Must be kept at reset value 15:12 CH3CAPFLT[3:0] Channel 3 input capture filter control Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the...
Page 321 GD32E23x User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions...
Page 322 GD32E23x User Manual When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 323 GD32E23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved...
Page 324 GD32E23x User Manual This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value.
Page 325 GD32E23x User Manual 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 326 GD32E23x User Manual 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 327 GD32E23x User Manual DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 328: General Level2 Timer (Timerx, X=13)
GD32E23x User Manual 14.3. General level2 timer (TIMERx, x=13) 14.3.1. Overview The general level2 timer module (TIMER13) is a one-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level2 timer has a 16-bit counter that can be used as an unsigned counter.
Page 329 GD32E23x User Manual Figure 14-44. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector...
Page 330: Function Overview
GD32E23x User Manual 14.3.4. Function overview Clock source configuration The general level2 TIMER can only being clocked by the CK_TIMER.  Internal timer clock CK_TIMER which is from module RCU The general level2 TIMER has only one clock source which is the internal CK_TIMER, used to drive the counter prescaler.
Page 331: Figure 14-46. Timing Chart Of Psc Value Change From 0 To 2
GD32E23x User Manual Timing chart of PSC value change from 0 to 2 Figure 14-46. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 332: Figure 14-47. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E23x User Manual Timing chart of up counting mode, PSC=0/2 Figure 14-47. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 14-48.
Page 333: Figure 14-49. Channel Input Capture Principle
GD32E23x User Manual Input capture and output compare channels The general level2 timer has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 334: Figure 14-50. Channel Output Compare Principle
GD32E23x User Manual Step2: Edge selection.(CHxP/CHxNP in TIMERx_CHCTL2). Rising edge, falling edge or both edges (rising and falling edge), choose one by configuring CHxP/CHxNP bits. Step3: Capture source selection (CHxMS in TIMERx_CHCTL0). As soon as selecting one input capture source by CHxMS, the channel must be set to input mode (CHxMS! =0x0) and TIMERx_CHxCV cannot be written any more.
Page 335: Figure 14-51. Output-Compare In Three Modes
GD32E23x User Manual In output compare mode, the TIMERx can generate timed pulses with programmable position, polarity, duration and frequency. When the counter matches the value in the TIMERx_CHxCV register of an output compare channel, the channel (n) output can be set, cleared, or toggled based on CHxCOMCTL.
Page 336: Figure 14-52. Pwm Mode Timechart
GD32E23x User Manual Output PWM function In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers. The period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV. Figure 14-52.
Page 337 GD32E23x User Manual and the TIMERx_CHxCV content. Refer to the definition of relative bit for more details. Another special function of the OxCPRE signal is a forced output which can be achieved by configuring the CHxCOMCTL field to 0x04/0x05. The output can be forced to an inactive/active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV.
Page 338: Timerx Registers(X=13)
GD32E23x User Manual 14.3.5. TIMERx registers(x=13) TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 339 GD32E23x User Manual event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 340 GD32E23x User Manual Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 341 GD32E23x User Manual This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 342 GD32E23x User Manual 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise. 111: PWM mode1.
Page 343 GD32E23x User Manual 31:8 Reserved Must be kept at reset value. CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal.
Page 344 GD32E23x User Manual Reserved Reserved CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, together with CH0P, this bit is used to...
Page 345 GD32E23x User Manual Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter.
Page 346 GD32E23x User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value.
Page 347 GD32E23x User Manual Reserved Reserved CI0_RMP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER13_CH0) 01: Channel 0 input is connected to the RTCCLK 10: Channel 0 input is connected to HXTAL/32 clock 11: Channel 0 input is connected to CKOUTSEL Configuration register (TIMERx_CFG) Address offset: 0xFC...
Page 348: Figure 14-53. General Level3 Timer Block Diagram
GD32E23x User Manual 14.4. General level3 timer (TIMERx, x=14) 14.4.1. Overview The general level3 timer module (TIMER14) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 349 GD32E23x User Manual Figure 14-53. General level3 timer block diagram 14.4.4. Function overview Clock source configuration The clock source of the advanced timer can be either the CK_TIMER or an alternate clock source controlled by SMC bits (TIMERx_SMCFG bit[2:0]).  SMC [2:0] == 3’b000.
Page 350: Figure 14-54. Timing Chart Of Internal Clock Divided By 1
GD32E23x User Manual is from module RCU. The default clock source is the CK_TIMER for driving the counter prescaler when the SMC [2:0] == 3’b000. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. In this mode, the TIMER_CK, which drives counter’s prescaler to count, is equal to CK_TIMER which is from RCU.
Page 351: Figure 14-55. Timing Chart Of Psc Value Change From 0 To 2
GD32E23x User Manual Timing chart of PSC value change from 0 to 2 Figure 14-55. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 352: Figure 14-56. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E23x User Manual Timing chart of up counting mode, PSC=0/2 Figure 14-56. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 14-57.
Page 353: Figure 14-58. Repetition Counter Timing Chart Of Up Counting Mode
GD32E23x User Manual Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register. Counter repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMERx_CREP register.
Page 354: Figure 14-59. Channel Input Capture Principle
GD32E23x User Manual Channel input capture principle Figure 14-59. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 355: Figure 14-60. Channel Output Compare Principle (With Complementary Output, X=0)
GD32E23x User Manual CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 356: Figure 14-62. Output-Compare In Three Modes
GD32E23x User Manual If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(high) level.
Page 357: Figure 14-63. Pwm Mode Timechart
GD32E23x User Manual Figure 14-62. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 358 GD32E23x User Manual Figure 14-63. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 359: Table 14-5. Complementary Outputs Controlled By Parameters
GD32E23x User Manual Table 14-5. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable.
Page 360: Figure 14-64. Complementary Output With Dead-Time Insertion
GD32E23x User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 0.
Page 361: Figure 14-65. Output Behavior In Response To A Break(The Break High Active)
GD32E23x User Manual cannot be set both to active level when break occurs. The break sources are input break pin and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP.
Page 362: Figure 14-66. Restart Mode
GD32E23x User Manual Table 14-6. Slave mode example table Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0] LIST SMC[2:0] choose For the ITIx no filter and 000: ITI0 CI0FE0 CI1FE1, prescaler can be used. 3'b100 (restart 001: ITI1 configure the CHxP and mode) 010: ITI2...
Page 363: Figure 14-67. Pause Mode
GD32E23x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection Figure 14-67. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Exam3 Event mode TI0S=0.(Non-xor) Filter is bypass in this example. TRGS[2:0]=3 counter [CH0NP==0, ’b101 will start CH0P==0] count when a CI0FE0 is the no inverted.
Page 364: Figure 14-69. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32E23x User Manual counter will be stopped and its value held. In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value.
Page 365 GD32E23x User Manual If one more time DMA request event coming, TIMERx will repeat the process as above. Timer debug mode ® When the Cortex -M23 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1, the TIMERx counter stops.
Page 366 GD32E23x User Manual 14.4.5. TIMERx registers(x=14) TIMER14 base address: 0x4001 4000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 367 GD32E23x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 368 GD32E23x User Manual 0: When POEN bit is reset, CH0_O is set low. 1: When POEN bit is reset, CH0_O is set high The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value MMC[2:0]...
Page 369 GD32E23x User Manual After these bits have been written, they are updated based when commutation event coming. When a channel does not have a complementary output, this bit has no effect. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved...
Page 370 GD32E23x User Manual by the internal clock (TIMER_CK) when CEN bit is set high. 001: Reserved 010: Reserved 011: Reserved 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode.
Page 371 GD32E23x User Manual 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH1IE...
Page 372 GD32E23x User Manual 31:11 Reserved Must be kept at reset value CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 373 GD32E23x User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved BRKG TRGG CMTG Reserved CH1G CH0G Bits Fields Descriptions 31:8 Reserved Must be kept at reset value BRKG Break event generation...
Page 374 GD32E23x User Manual This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH0IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 375 GD32E23x User Manual This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 376 GD32E23x User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 377 GD32E23x User Manual 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 378 GD32E23x User Manual Reserved Must be kept at reset value CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable Refer to CH0EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity.
Page 379 GD32E23x User Manual 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value.
Page 380 GD32E23x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 381 GD32E23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 382 GD32E23x User Manual Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by:...
Page 383 GD32E23x User Manual Run mode off-state configure When POEN bit is set, this bit specifies the output state for the channels which has a complementary output and has been configured in output mode. 0: When POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled.
Page 384 GD32E23x User Manual TIMERx_CTL0. 2. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DMATC[4:0] Reserved...
Page 385 GD32E23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 386: Figure 14-70. General Level4 Timer Block Diagram
GD32E23x User Manual 14.5. General level4 timer (TIMERx, x=15, 16) 14.5.1. Overview The general level4 timer module (TIMER15, TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 387 GD32E23x User Manual Figure 14-70. General level4 timer block diagram 14.5.4. Function overview Clock source configuration The general level4 TIMER can only being clocked by the CK_TIMER.  Internal timer clock CK_TIMER which is from module RCU...
Page 388: Figure 14-71. Timing Chart Of Internal Clock Divided By 1
GD32E23x User Manual The general level4 TIMER has only one clock source which is the internal CK_TIMER, used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER which is from Timing chart of internal clock divided by 1 Figure 14-71.
Page 389: Figure 14-72. Timing Chart Of Psc Value Change From 0 To 2
GD32E23x User Manual Timing chart of PSC value change from 0 to 2 Figure 14-72. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 390: Figure 14-73. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E23x User Manual Timing chart of up counting mode, PSC=0/2 Figure 14-73. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 14-74.
Page 391: Figure 14-75. Repetition Counter Timing Chart Of Up Counting Mode
GD32E23x User Manual Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register. Counter repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMERx_CREP register.
Page 392: Figure 14-76. Channel Input Capture Principle
GD32E23x User Manual Channel input capture principle Figure 14-76. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 393: Figure 14-77. Channel Output Compare Principle (With Complementary Output, X=0)
GD32E23x User Manual value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly.
Page 394: Figure 14-78. Output-Compare Under Three Modes
GD32E23x User Manual CHxVAL register of an output compare channel, the channel (n) output can be set, cleared, or toggled based on CHxCOMCTL. When the counter reaches the value in the CHxVAL register, the CHxIF bit is set and the channel (n) interrupt is generated if CHxIE = 1. And the DMA request will be assert, if CHxDEN =1.
Page 395: Figure 14-79. Pwm Mode Timechart
GD32E23x User Manual Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers. The period is determined by TIMERx_CAR and duty cycle is determined by TIMERx_CHxCV. Figure 14-79.
Page 396: Table 14-7. Complementary Outputs Controlled By Parameters
GD32E23x User Manual relative bit definition. Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values.
Page 397 GD32E23x User Manual Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O output enable CHxNP CHx_ON output enable CHx_O = CHxP CHx_ON = CHxNP CHx_O output disable. CHx_ON output disable. CHx_O = CHxP CHx_ON=OxCPRE⊕CHxNP CHx_O output enable CHx_ON output enable CHx_ON = CHxNP CHx_O=OxCPRE⊕CHxP CHx_O output enable...
Page 398: Figure 14-80. Complementary Output With Dead-Time Insertion
GD32E23x User Manual Figure 14-80. Complementary output with dead-time insertion. CHxVAL CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime > pulse width Pulse width CHx_O Deadtime CHx_ON Deadtime Break mode In this mode, the output CHx_O and CHx_ON are controlled by the POEN, IOS and ROS bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs.
Page 399: Figure 14-81. Output Behavior In Response To A Break(The Break High Active)
GD32E23x User Manual Figure 14-81. Output behavior in response to a break(The break high active) BRKIN OxCPRE = ISOx CHx_O CHxEN: 1 CHxNEN: 1 CHxP : 0 CHxNP : 0 ISOx = ~ISOxN = ISOxN CHx_ON = ISOx CHxEN: 1 CHxNEN: 0 CHx_O CHxP: 0 CHxNP : 0...
Page 400 GD32E23x User Manual example. Figure 14-82. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event.
Page 401 GD32E23x User Manual 14.5.5. TIMERx registers(x=15, 16) TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits...
Page 402 GD32E23x User Manual The restart mode generates an update event. 1: This event generates update interrupts or DMA requests: The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable.
Page 403 GD32E23x User Manual 0: When POEN bit is reset, CH0_O is set low. 1: When POEN bit is reset, CH0_O is set high The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value DMAS...
Page 404 GD32E23x User Manual CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved...
Page 405 GD32E23x User Manual software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag When the break input is inactive, the bit is set by hardware. When the break input is inactive, the bit can be cleared by software. 0: No active level break has been detected.
Page 406 GD32E23x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 407 GD32E23x User Manual Reserved CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
Page 408 GD32E23x User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 409 GD32E23x User Manual 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 410 GD32E23x User Manual 0: Channel 0 complementary output disabled 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 411 GD32E23x User Manual 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved PSC[15:0] Bits...
Page 412 GD32E23x User Manual value Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate.
Page 413 GD32E23x User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved POEN OAEN...
Page 414 GD32E23x User Manual This bit can be set to enable the BRKIN and CCS clock failure event inputs. 0: Break inputs disabled 1: Break inputs enabled This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is Run mode off-state configure When POEN bit is set, this bit specifies the output state for the channels which has a complementary output and has been configured in output mode.
Page 415 GD32E23x User Manual 3’b110 (32+ DTCFG[4:0]) * t DTS_CK 3’b111 (32+ DTCFG[4:0]) * t DTS_CK Note: 1. t is the period of DTS_CK which is configured by CKDIV[1:0] in DTS_CK TIMERx_CTL0. 2. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 416 GD32E23x User Manual DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 417: Figure 14-83. Basic Timer Block Diagram
GD32E23x User Manual 14.6. Basic timer (TIMERx, x=5) 14.6.1. Overview The basic timer module (TIMER5) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request. 14.6.2. Characteristics ...
Page 418: Figure 14-84. Timing Chart Of Internal Clock Divided By 1
GD32E23x User Manual counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Timing chart of internal clock divided by 1 Figure 14-84. CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler...
Page 419: Figure 14-85. Timing Chart Of Psc Value Change From 0 To 2
GD32E23x User Manual Timing chart of PSC value change from 0 to 2 Figure 14-85. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 420: Figure 14-86. Timing Chart Of Up Counting Mode, Psc=0/2
GD32E23x User Manual Timing chart of up counting mode, PSC=0/2 Figure 14-86. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 14-87.
Page 421 GD32E23x User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. Once the timer is set to operate in the single pulse mode, it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 422 GD32E23x User Manual 14.6.5. TIMERx registers(x=5) TIMER5 base address: 0x4000 1000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8 Reserved Must be kept at reset value ARSE Auto-reload shadow enable...
Page 423 GD32E23x User Manual The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized. Counter enable 0: Counter disable 1: Counter enable...
Page 424 GD32E23x User Manual This register has to be accessed by word(32-bit) Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. UPIE Update interrupt enable 0: disabled...
Page 425 GD32E23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared.
Page 426 GD32E23x User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 427: Figure 15-1. Ifrp Output Timechart 1
GD32E23x User Manual Infrared ray port (IFRP) 15.1. Overview Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control. There is no register in this module, which is controlled by TIMER15 and TIMER16. You can improve the module's output to high current capacity by set the GPIO pin to Fast Mode.
Page 428: Figure 15-2. Ifrp Output Timechart 2
GD32E23x User Manual Note: IFRP_OUT has one APB clock delay from TIMER16_CH0. Figure 15-2. IFRP output timechart 2 TIMER16_CH0 TIMER15_CH0 IFRP_OUT Note: Carrier (TIMER15_CH0)’s duty cycle can be changed, and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high. Figure 15-3.
Page 429 GD32E23x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 16.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the the UCLK (PCLK1, PCLK2 and CK_USART0 available only for USART0) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 430 GD32E23x User Manual  Parity control – Transmits parity bit – Checks parity of received data byte  LIN break generation and detection  Support IrDA  Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface –...
Page 431: Figure 16-1. Usart Module Block Diagram
GD32E23x User Manual 16.3. Function overview The interface is externally connected to another device by the main pins listed in Table 16-1. Description of USART important pins. Table 16-1. Description of USART important pins Type Description Input Receive data Output I/O Transmit data.
Page 432: Figure 16-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32E23x User Manual Figure 16-2. USART character frame (8 bits data and 1 stop bit) In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 16-2. Configuration of stop bits STB[1:0] stop bit length (bit) usage description...
Page 433 GD32E23x User Manual Get the value of USART_BUAD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). the nearest integer is 6, so 16*0.37=5.92, FRADIV=6 (0x6). USART_BUAD=0x1E6. roundness of Note: If the FRADIV is 16 (overflow), the carry must be added to the integer part.
Page 434: Figure 16-3.Usart Transmit Procedure
GD32E23x User Manual Figure 16-3. USART transmit procedure It It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. The TC bit can be cleared by writing 1 to TCC bit in USART_INTC register.
Page 435: Figure 16-4.Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32E23x User Manual (NERR) status will be generated for the frame. An interrupt will be generated, If the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set. If the OSB bit in USART_CTL2 register is set, the receiver gets only one sample to evaluate a bit value. In this situation, no noisy error will be detected.
Page 436: Figure 16-5. Configuration Step When Using Dma For Usart Transmission
GD32E23x User Manual Figure 16-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 437: Figure 16-6. Configuration Step When Using Dma For Usart Reception
GD32E23x User Manual Figure 16-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 438: Figure16-8. Hardware Flow Control
GD32E23x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 439: Figure 16-9. Break Frame Occurs During Idle State
GD32E23x User Manual The idle frame wake up method is selected by default. When an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode. When it is woken up by an idle frame, the IDLEF bit in USART_STAT will not be set.
Page 440: Figure 16-10. Break Frame Occurs During A Frame
GD32E23x User Manual As shown in Figure 16-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame. Figure 16-10. Break frame occurs during a frame 16.3.9.
Page 441: Figure 16-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32E23x User Manual Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1) 16.3.10. IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 442: Figure 16-14. Irda Data Modulation
GD32E23x User Manual logic ‘0’. The pulse width should be 3/16 of a bit period. The IrDA could not detect any pulse if the pulse width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times of PSC clock.
Page 443: Figure 16-15. Iso7816-3 Frame Format
GD32E23x User Manual that is also driven by the smartcard. Figure 16-15. ISO7816-3 frame format Character (T=0) mode Compared to the timing in normal operation, the transmission time from transmit shift register to the TX pin is delayed by half baud clock, and the TC flag assertion time is delayed by a guard time that is configured by the GUAT[7:0] bits in USART_GP.
Page 444 GD32E23x User Manual timeout interrupt will be generated, if no answer is received from the card before the expiration of this period. If the first character is received before the expiration of the period, it is signaled by the RBNE interrupt. If DMA is used to read from the smartcard in block mode, the DMA must be enabled only after the first character is received.
Page 445: Figure 16-16. Usart Receive Fifo Structure
GD32E23x User Manual To detect the idle line, the RTEN bit in the USART_CTL1 register and the RTIE in the USART_CTL0 register must be set. The USART_RT register must be set to the value corresponding to a timeout of 2 characters time. After the last stop bit is received, when the receive line is idle for this duration, an interrupt will be generated, informing the software that the current block reception is completed.
Page 446: Table 16-3. Usart Interrupt Requests
GD32E23x User Manual WUM bit fields. DMA must be disabled before entering Deep-sleep mode. Before entering Deep-sleep mode, software must check that the USART is not performing a transfer, by checking the BSY flag in the USART_STAT register. The REA bit must be checked to ensure the USART is actually enabled.
Page 447: Figure 16-17. Usart Interrupt Mapping Diagram
GD32E23x User Manual Figure 16-17. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 448 GD32E23x User Manual 16.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 16.4.1. Control register 0 (USART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE DEA[4:0] DED[4:0] OVSMOD...
Page 449 GD32E23x User Manual 1: Oversampling by 8 This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be written when the USART is enabled (UEN=1). AMIE ADDR match interrupt enable 0: Disable ADDR match interrupt 1: Enable ADDR match interrupt Mute mode enable 0: Disable mute mode...
Page 450 GD32E23x User Manual 1: Enable read data register not empty interrupt and overrun error interrupt. An interrupt will occur whenever the ORERR bit is set or the RBNE bit is set in USART_STAT. IDLEIE IDLE line detected interrupt enable 0: Disable IDLE line detected interrupt 1: Enable IDLE line detected interrupt.
Page 451 GD32E23x User Manual only the ADDR[3:0] bits are used to compare. In normal reception, these bits are also used for character detection. The whole received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set on matching. This bit field cannot be written when both reception (REN=1) and USART (UEN=1) are enabled.
Page 452 GD32E23x User Manual 10: 2 Stop bits 11: 1.5 Stop bit This bit field cannot be written when the USART is enabled (UEN=1). CKEN CK pin enable 0: Disable CK pin 1: Enable CK pin This bit field cannot be written when the USART is enabled (UEN=1). Clock polarity 0: Steady low value on CK pin outside transmission window in synchronous mode 1: Steady high value on CK pin outside transmission window in synchronous mode...
Page 453 GD32E23x User Manual This bit field cannot be written when the USART is enabled (UEN=1). Reserved Must be kept at reset value. 16.4.3. Control register 2 (USART_CTL2) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0]...
Page 454 GD32E23x User Manual stop retransmission. This bit is reserved in USART1. Reserved Must be kept at reset value. Driver enable polarity mode 0: DE signal is active high 1: DE signal is active low This bit field cannot be written when the USART is enabled (UEN=1). Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin.
Page 455 GD32E23x User Manual 1: Enable CTS hardware flow control This bit field cannot be written when the USART is enabled (UEN=1). RTSEN RTS enable 0: Disable RTS hardware flow control 1: Enable RTS hardware flow control. Data can be requested only when there is space in the receive buffer This bit field cannot be written when the USART is enabled (UEN=1).
Page 456 GD32E23x User Manual ORERR bit or the NERR bit is set in USART_STAT in multibuffer communication 16.4.4. Baud rate generator register (USART_BAUD) Address offset: 0x0C Reset value: 0x0000 0000 This register cannot be written when the USART is enabled (UEN=1). This register has to be accessed by word (32-bit).
Page 457 GD32E23x User Manual 15:8 GUAT[7:0] Guard time value in smartcard mode This bit field cannot be written when the USART is enabled (UEN=1). PSC[7:0] Prescaler value for dividing the system clock In IrDA low-power mode, the division factor is the prescaler value. 00000000: Reserved - do not program this value 00000001: divides the source clock by 1 00000010: divides the source clock by 2...
Page 458 GD32E23x User Manual In other modes, when REN=0 (receiver disabled) and/or when the EBC bit is written to 1, the block length counter is reset. 23:0 RT[23:0] Receiver timeout threshold These bits are used to specify receiver timeout value in terms of number of baud clocks.
Page 459 GD32E23x User Manual 16.4.8. Status register (USART_STAT) Address offset: 0x1C Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit). Reserved Reserved CTSF LBDF RBNE IDLEF ORERR NERR FERR PERR Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknowledge flag This bit, which is set/reset by hardware, reflects the receive enable state of the USART core logic.
Page 460 GD32E23x User Manual when wakeup on IDLEIE mode is selected. Send break flag 0: No break character is transmitted 1: Break character will be transmitted This bit indicates that a send break character was requested. Set by software, by writing 1 to the SBKCMD bit in the USART_CMD register. Cleared by hardware during the stop bit of break transmission.
Page 461 GD32E23x User Manual 1: A change occurred on the nCTS status line. An interrupt will occur if the CTSIE bit is set in USART_CTL2 Set by hardware when the nCTS input toggles. Cleared by writing 1 to CTSC bit in USART_INTC register. LBDF LIN break detected flag 0: LIN Break is not detected...
Page 462 GD32E23x User Manual ORERR Overrun error 0: No overrun error is detected 1: Overrun error is detected. An interrupt will occur if the RBNEIE bit is set in USART_CTL0. In multibuffer communication, an interrupt will occur if the ERRIE bit is set in USART_CTL2. Set by hardware when the word in the receive shift register is ready to be transferred into the USART_RDATA register while the RBNE bit is set.
Page 463 GD32E23x User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. Wakeup from Deep-sleep mode clear Writing 1 to this bit clears the WUF bit in the USART_STAT register. This bit is reserved in USART1. 19:18 Reserved Must be kept at reset value.
Page 464 GD32E23x User Manual Writing 1 to this bit clears the PERR bit in the USART_STAT register. 16.4.10. Receive data register (USART_RDATA) Address offset: 0x24 Reset value: 0xXXXX XXXX This register has to be accessed by word (32-bit). Reserved Reserved RDATA[8:0] Bits Fields Descriptions...
Page 465 GD32E23x User Manual This register must be written only when TBE bit in USART_STAT register is set. 16.4.12. USART coherence control register (USART_CHC) Address offset: 0xC0 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved EPERR Reserved...
Page 466 GD32E23x User Manual RFFINT Receive FIFO full interrupt flag 14:12 RFCNT[2:0] Receive FIFO counter number Receive FIFO full flag 0: Receive FIFO not full 1: Receive FIFO full Receive FIFO empty flag 0: Receive FIFO not empty 1: Receive FIFO empty RFFIE Receive FIFO full interrupt enable 0: Receive FIFO full interrupt disable...
Page 467: Figure 17-1. I2C Module Block Diagram
GD32E23x User Manual Inter-integrated circuit interface (I2C) 17.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface.I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), PMBus (power management bus) and SAM_V (secure access and control module for...
Page 468: Table 17-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32E23x User Manual Figure 17-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 17-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 469: Figure 17-2. Data Validation
GD32E23x User Manual if the FMPEN bit in I2C_FMPCFG is set. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V 17.3.2.
Page 470: Figure 17-4. Clock Synchronization
GD32E23x User Manual held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time. Figure 17-4. Clock synchronization CLK1 CLK2 17.3.5. Arbitration Arbitration, like synchronization, is part of the protocol where more than one master is used in the system.
Page 471: Figure 17-6. I2C Communication Flow With 7-Bit Address
GD32E23x User Manual if General Call is enabled by software, the I2C slave always responds to a General Call Address (0x00). The I2C block supports both 7-bit and 10-bit address modes. An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation.
Page 472 GD32E23x User Manual mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus.
Page 473 GD32E23x User Manual Figure 17-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 474: Figure 17-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32E23x User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 17-10.
Page 475: Figure 17-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32E23x User Manual I2C_STAT1. Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 476 GD32E23x User Manual Programming model in master receiving mode In master receiving mode, a master is responsible for generating NACK for the last byte reception and then sending a STOP signal on I2C bus. So, special attention should be paid to ensure the correct ending of data reception.
Page 477: Figure 17-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32E23x User Manual Figure 17-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 478 GD32E23x User Manual I2C_STAT1. If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 479: Figure 17-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32E23x User Manual Figure 17-13. Programming model for master receiving mode using solution B (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge...
Page 480 GD32E23x User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 481 GD32E23x User Manual derived from I2C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols.
Page 482: Table 17-2. Event Status Flags
GD32E23x User Manual SMBus alert The SMBus has an extra optional shared interrupt signal called SMBALERT# which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data.
Page 483: Table 17-3. Error Flags
GD32E23x User Manual Event Flag Name Description Byte transmission completed I2C_DATA is empty when transmitting RBNE I2C_DATA is not empty when receiving SAM_V mode rxframe pin rising edge is detected SAM_V mode rxframe pin falling edge is detected SAM_V mode txframe pin rising edge is detected SAM_V mode txframe pin falling edge is detected Table 17-3.
Page 484 GD32E23x User Manual 17.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 17.4.1. Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved SALT...
Page 485 GD32E23x User Manual byte. 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte. ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0.
Page 486 GD32E23x User Manual I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled 17.4.2. Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE...
Page 487 GD32E23x User Manual Reserved Must be kept at reset value. I2CCLK[6:0] I2C peripheral clock frequency I2CCLK[6:0]should be the frequency of input APB1 clock in MHz which is at least 2. 0000000 - 0000001: Not allowed 0000010 - 1001000: 2 MHz~72MHz 1001001 - 1111111: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than...
Page 488 GD32E23x User Manual This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled...
Page 489 GD32E23x User Manual LOSTAR ADD10S ADDSEN SMBALT SMBTO Reserved PECERR OUERR AERR BERR RBNE Reserved STPDET SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode)
Page 490 GD32E23x User Manual 1: A bus error detected I2C_DATA is empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail).
Page 491 GD32E23x User Manual 0: In slave mode, no address is received or the received address does not match witih its own address. In master mode, no address is sent or address has been sent but not received the ACK from slave. 1: In slave mode, address is received and matches witih its own address.
Page 492 GD32E23x User Manual This bit is cleared by hardware after a STOP or a START signal or I2CEN=0. 0: No general call address received 1: General call address received Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver. It is cleared by hardware after a STOP or a START signal or I2CEN=0 or LOSTARB=1.
Page 493 GD32E23x User Manual 13:12 Reserved Must be kept at reset value. 11:0 CLKC[11:0] I2C clock control in master mode In standard speed mode: T =CLKC*T high PCLK1 In fast speed mode or fast mode plus, if DTCY=0: =CLKC*T =2*CLKC*T high PCLK1 PCLK1 In fast speed mode or fast mode plus, if DTCY=1:...
Page 494 GD32E23x User Manual 31:16 Reserved Must be kept at reset value. Rxframe rise flag, cleared by software by writing 0 Rxframe fall flag, cleared by software by writing 0 Txframe rise flag, cleared by software by writing 0 Txframe fall flag, cleared by software by writing 0 11:10 Reserved Must be kept at reset value.
Page 495 GD32E23x User Manual Reserved FMPEN Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. FMPEN Fast mode plus enable. The I2C device supports up to 1MHz when this bit is set.
Page 496 GD32E23x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 18.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 497: Figure 18-1. Block Diagram Of Spi
GD32E23x User Manual  Master clock (MCK) can be output.  Transmission and reception using DMA. 18.3. SPI function overview 18.3.1. SPI block diagram Figure 18-1. Block diagram of SPI SYSCLK MOSI TXBuffer/ TXFIFO MISO RX Buffer/ RXFIFO 18.3.2. SPI signal description Normal configuration (not Quad-SPI mode) Table 18-1.
Page 498: Figure 18-2. Spi0 Timing Diagram In Normal Mode
GD32E23x User Manual Pin name Direction Description NSSDRV=0, it is NSS input, suitable for multi-master application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI1).
Page 499: Figure 18-3. Spi1 Timing Diagram In Normal Mode
GD32E23x User Manual In SPI0 normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits. Data order is configured by LF bit in SPI_CTL0 register, and SPI will send the LSB first if LF=1, or the MSB if LF=0.
Page 500: Figure 18-5. Spi1 Data Frame Right-Aligned Diagram
GD32E23x User Manual Figure 18-5. SPI1 data frame right-aligned diagram 18.3.4. Separate transmission and reception FIFO The separate 32-bit reception FIFO (RXFIFO) and transmission FIFO (TXFIFO) are used in different directions for SPI data transactions, and they can enable the SPI to work in a continuous flow (only available in SPI1).
Page 501: Table 18-3. Nss Function In Slave Mode
GD32E23x User Manual RXFIFO level is less than half of its capacity. The meaning of RXFIFO full is the opposite. If the RXFIFO empty or full appears below and there is no special explanation, the meaning is the same as that described here. Data merging (Only for SPI1) When DZ[3:0] in the SPI_CTL1 register configures the transmission data bit width to be 8 bits or less than 8 bits, by configuring the BYTEN bit in the SPI_CTL1 register to 0, the data...
Page 502: Table 18-4. Nss Function In Master Mode
GD32E23x User Manual (SWNSSEN=1). Then, once the NSS pin (in hardware NSS mode) or the SWNSS bit (in software NSS mode) goes low, the SPI automatically enters slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1).
Page 503 GD32E23x User Manual Mode Description Register configuration Data pin usage BDOEN: Don’t care MSTMOD = 1 Master reception with RO = 1 MOSI: not used unidirectional connection BDEN = 0 MISO: reception BDOEN: Don’t care MSTMOD = 1 Master transmission with RO = 0 MOSI: transmission bidirectional connection...
Page 504: Figure 18-7. A Typical Full-Duplex Connection
GD32E23x User Manual Figure 18-7. A typical full-duplex connection Figure 18-8. A typical simplex connection (Master: receive, Slave: transmit) Figure 18-9. A typical simplex connection (Master: transmit only, Slave: receive) Figure 18-10. A typical bidirectional connection Master Slave MTB/MRB SRB/STB MISO MISO MOSI...
Page 505 GD32E23x User Manual Initialization sequence SPI0: Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 506 GD32E23x User Manual Note: During communication, CKPH, CKPL, MSTMOD, PSC[2:0], LF and DZ[3:0] bits should not be changed. Basic transmission and reception sequence Transmission sequence After the initialization sequence, the SPI is enabled and stays at idle state. In master mode, the transmission starts when the application writes a data into the transmission buffer/TXFIFO.
Page 507: Figure 18-11. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32E23x User Manual mode except that the TBE bit need to be ignored. SPI TI mode SPI TI mode takes NSS as a special frame header flag signal and its operation sequence is similar to normal mode described above. The modes described above (MFD, MTU, MRU, MTB, MRB, SFD, STU, SRU, STB and SRB) are still supported in TI mode.
Page 508: Figure 18-13. Timing Diagram Of Ti Slave Mode
GD32E23x User Manual Figure 18-13. Timing diagram of TI slave mode sample MOSI D[7] D[1] D[6] D[5] D[4] D[3] D[2] D[0] MISO D[5] D[3] D[2] D[0] D[7] D[6] D[4] D[1] In slave TI mode, after the last rising edge of SCK in transfer, the slave begins to transmit the LSB bit of the last data byte, and after a half-bit time, the master begins to sample the line.
Page 509: Figure 18-14. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32E23x User Manual Figure 18-14. Timing diagram of NSS pulse with continuous transmit MOSI MISO Don t Care Don t Care Don t Care 1 SCK Quad-SPI mode operation sequence The Quad-SPI mode is designed to control Quad-SPI Flash. In order to enter Quad-SPI mode, the software should first verify that the TBE bit is set and TRANS bit is cleared, then set QMOD bit in SPI_QCTL register.
Page 510: Figure 18-15. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32E23x User Manual Figure 18-15. Timing diagram of write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 511: Figure 18-16. Timing Diagram Of Read Operation In Quad-Spi Mode
GD32E23x User Manual Figure 18-16. Timing diagram of read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3]...
Page 512 GD32E23x User Manual For SPI1, application can disable the SPI when it doesn’t want to receive data, and then confirm the TRANS=0 and read data until RXLVL[1:0] = 00. TI mode The disabling sequence of TI mode is the same as the sequences described above. NSS pulse mode The disabling sequence of NSSP mode is the same as the sequences described above.
Page 513 GD32E23x User Manual Application can enable the CRC function by setting CRCEN bit in SPI_CTL0 register. The CRC calculators calculate CRC for each bit transmitted and received on lines continuously, and the calculated CRC values can be read from SPI_TCRC and SPI_RCRC registers. To transmit the calculated CRC value, application should set the CRCNT bit in SPI_CTL0 register after the last data is written to the transmission buffer/TXFIFO.
Page 514 GD32E23x User Manual 1/2 of FIFO depth, the software can write the next data to the transmission buffer/TXFIFO by writing the SPI_DATA register.  Reception buffer/RXFIFO not empty flag (RBNE) For SPI0, this bit is set when reception buffer is not empty, which means that one data is received and stored in the reception buffer, and software can read the data by reading the SPI_DATA register.
Page 515: Figure 18-17. Block Diagram Of I2S
GD32E23x User Manual Table 18-6. SPI interrupt requests Interrupt Flag Description Clear method enable bit Transmission buffer/TXFIFO Write SPI_DATA register. TBEIE empty Reception buffer/RXFIFO not RBNE Read SPI_DATA register. RBNEIE empty Read or write SPI_STAT register, CONFERR Configuration fault error then write SPI_CTL0 register.
Page 516: Figure 18-18. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E23x User Manual 18.4.2. I2S signal description There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 517: Figure 18-19. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32E23x User Manual Figure 18-19. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation the transmission of to or from the SPI_DATA register is needed to complete a frame.
Page 518: Figure 18-24. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32E23x User Manual 24-bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits: D[23:8], and the second one should be a 16-bit data. The higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value. In reception mode, if a 24-bit data D[23:0] is received, the first data read from the SPI_DATA register is D[23:8], and the second one is a 16-bit data.
Page 519: Figure 18-28. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32E23x User Manual Figure 18-28. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 18-29. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 520: Figure 18-34. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32E23x User Manual than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below. Figure 18-34.
Page 521: Figure 18-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32E23x User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 522: Figure 18-39. Pcm Standard Short Frame Synchronization Mode Timing Diagram
GD32E23x User Manual Figure 18-42. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure18-43. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 18-44. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 16-bit data...
Page 523: Figure18-47. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32E23x User Manual Figure18-47. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 18-48. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 18-49. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 13 bits...
Page 524: Figure 18-54. Block Diagram Of I2S Clock Generator
GD32E23x User Manual Figure 18-52. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 18-53. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) 18.4.4. I2S clock Figure 18-54. Block diagram of I2S clock generator 8-bit Configurable I2S_MCK...
Page 525: Figure 18-55. I2S Initialization Sequence
GD32E23x User Manual configured according to the formulas listed in Table 18-8. Audio sampling frequency calculation formulas. Table 18-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) 18.4.5.
Page 526 GD32E23x User Manual Figure 18-55. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 527 GD32E23x User Manual I2S master transmission sequence The TBE flag is used to control the transmission sequence. As is mentioned before, the TBE flag indicates that the transmission buffer is empty, and an interrupt will be generated if the TBEIE bit in the SPI_CTL1 register is set. At the beginning, the transmission buffer is empty (TBE is high) and no transmission sequence is processing in the shift register.
Page 528: Figure 18-56. I2S Master Reception Disabling Sequence
GD32E23x User Manual channel length. The sequences for each case are shown as below Figure 18-56. I2S master reception disabling sequence. Figure 18-56. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 &&...
Page 529 GD32E23x User Manual In order to disable I2S, it is mandatory to clear the I2SEN bit after the TBE flag is high and the TRANS flag is low. I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below.
Page 530: Table 18-10. I2S Interrupt
GD32E23x User Manual from 0 to 1. This flag will not generate any interrupt. Error conditions There are three error flags:  Transmission underrun error flag (TXURERR) This situation occurs when the transmission buffer is empty when the valid SCK signal starts in slave transmission mode.
Page 531 GD32E23x User Manual 18.5. Register definition SPI0/I2S0 base address: 0x4001 3000 SPI1 base address: 0x4000 3800 18.5.1. Control register 0 (SPI_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 532 GD32E23x User Manual received. FF16 Data frame format (only for SPI0) 0: 8-bit data frame format 1: 16-bit data frame format CRCL CRC length (only for SPI1) 0: 8-bit crc length. 1: 16-bit crc length. Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN...
Page 533 GD32E23x User Manual 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle. 1: CLK pin is pulled high when SPI is idle. CKPH Clock phase selection 0: Capture the first data at the first clock transition. 1: Capture the first data at the second clock transition.
Page 534 GD32E23x User Manual RXFIFO that generate RBNE. 0: Half-word access, and RBNE is generated when RXLVL >= 2. 1: Byte access, and RBNE is generated when RXLVL >= 1. 11:8 DZ[3:0] Date size (only for SPI1) This field indicates the data size for transfer. 0000: Force to “0111”...
Page 535 GD32E23x User Manual 18.5.3. Status register (SPI_STAT) Address offset: 0x08 Reset value: 0x0000 0002 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved RXORER CONFER TXURER Reserved TXLVL[1:0] RXLVL[1:0] FERR TRANS CRCERR I2SCH RBNE rc_w0 rc_w0 Bits...
Page 536 GD32E23x User Manual 1: SPI or I2S is currently transmitting and/or receiving a frame. This bit is set and cleared by hardware. RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register.
Page 537 GD32E23x User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register. For SPI0, the hardware has two buffers, including transmission buffer and reception buffer.
Page 538 GD32E23x User Manual 15:0 CRCPOLY[15:0] CRC polynomial register This register contains the CRC polynomial and it is used for CRC calculation. The default value is 0007h. 18.5.6. RX CRC register (SPI_RCRC) Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved RCRC[15:0] Bits...
Page 539 GD32E23x User Manual TCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 TCRC[15:0] TX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the transmitted bytes and saves them in TCRC register. For SPI0, if the data frame format is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value in TCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC[15:0].
Page 540 GD32E23x User Manual I2SEN I2S enable 0: Disable I2S 1: Enable I2S This bit is not used in SPI mode. I2SOPMOD[1:0] I2S operation mode 00: Slave transmission mode 01: Slave reception mode 10: Master transmission mode 11: Master reception mode This bit should be configured when I2S mode is disabled.
Page 541 GD32E23x User Manual The channel length must be equal to or greater than the data length. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. 18.5.9. I2S clock prescaler register (SPI_I2SPSC) Address offset: 0x20 Reset value: 0x0000 0002 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 542 GD32E23x User Manual IO23_DR Reserved QMOD Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. IO23_DRV Drive IO2 and IO3 enable 0: IO2 and IO3 are not driven in single wire mode. 1: IO2 and IO3 are driven to high in single wire mode. This bit is only available in SPI1.
Page 543 GD32E23x User Manual Operational amplifiers (OPA) This chapter applies to GD32E231xx devices. 19.1. Overview The two OPAs are low noise, low voltage and low power operational amplifiers with high gain-bandwidth product of 6MHz and slew rate of 5V/μs. The maximum input offset voltage is only 3.5mV and the input common mode range extends beyond the supply rails.
Page 544: Table 20-1. List Of Abbreviations Used In Register
GD32E23x User Manual Appendix 20.1. List of abbreviations used in register Table 20-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit.
Page 545 GD32E23x User Manual 20.3. Available peripherals For availability of peripherals and their number across all MCU series types, refer to the corresponding device data datasheet.
Page 546: Table 21-1. Revision History
GD32E23x User Manual Revision history Table 21-1. Revision history Revision No. Description Date Initial Release Mar.8, 2019 1. Modify access mode and reset value of TIMER register. 2. Delete the I-BUS and D-BUS descriptions in Figure 1-2. Oct.8, 2019 3. Add the descriptions of [31:16] bit domain in TIMERs register. 4.
Page 547 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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