Peripheral Handshake; Arbitration; Figure 9-2. Handshake Mechanism - GigaDevice Semiconductor GD32VF103 User Manual

The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.

If the DMA transmission is not completed when the CHEN bit is cleared, two situations
may be occurred when restart this DMA channel:
–
–

If the DMA transmission has been finished when clearing the CHEN bit, enable the DMA
channel without any register configuration operation will not launch any DMA transfer.
9.4.2.

Peripheral handshake

To ensure a well-organized and efficient data transfer, a handshake mechanism is introduced
between the DMA and peripherals, including a request signal and a acknowledge signal:
–
Request signal asserted by peripheral to DMA controller, indicating that the peripheral is
ready to transmit or receive data
– Acknowledge signal responded by DMA to peripheral, indicating that the DMA controller
has initiated an AHB command to access the peripheral

Figure 9-2. Handshake mechanism

the DMA controller and peripherals.
Figure 9-2. Handshake mechanism
Peripheral
request
DMA
Acknowledge
9.4.3.

Arbitration

When two or more requests are received at the same time, the arbiter determines which
request is served based on the priorities of channels. There are two-stage priorities, including
the software priority and the hardware priority. The arbiter determines which channel is
selected to respond according to the following priority rules:
–
Software priority: Four levels, including low, medium, high and ultra high by configuring
If no register configuration operations of the channel occurs before restart the DMA
channel, the DMA will continue to complete the rest of the transmission.
If any register configuration operations occur, the DMA will restart a new
transmission.
Peripheral is ready to transmit
or receive data, and assert the
request signal to DMA
Wait the DMA bus idle and
other higher priority channels
to have been processed
GD32VF103 User Manual
shows how the handshake mechanism works between
Peripheral releases the
request signal when it receives
the acknowledge signal
Peripheral request
The DMA controller deasserts
the acknowledge signal when
DMA acknowledge
The corresponding channel has
the highest priority and the DMA
controller sents an AHB command
to access the peripheral
Peripheral launches
the next request
Peripheral
it receives low request signal
request
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