GigaDevice Semiconductor GD32F30 Series User Manual

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GigaDevice Semiconductor Inc.

GD32F30x

Arm

Cortex

-M4 32-bit MCU

User Manual

Revision 2.9

( Dec. 2022 )

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Summary of Contents for GigaDevice Semiconductor GD32F30 Series

Page 1 GigaDevice Semiconductor Inc. GD32F30x Cortex -M4 32-bit MCU ® ® User Manual Revision 2.9 ( Dec. 2022 )
Page 2: Table Of Contents
GD32F30x User Manual Table of Contents Table of Contents......................... 2 List of Figures ........................19 List of Table ........................26 1. System and memory architecture ................30 1.1. ® Cortex ® -M4 processor ...................30 1.2. System architecture .....................31 1.3. Memory map.......................34 1.3.1.
Page 3 GD32F30x User Manual 2.4.5. Control register 0(FMC_CTL0) ......................55 2.4.6. Address register 0 (FMC_ADDR0) ..................... 56 2.4.7. Option byte status register (FMC_OBSTAT) ..................57 2.4.8. Erase/Program Protection register (FMC_WP) ................57 2.4.9. Unlock key register 1(FMC_KEY1)..................... 58 2.4.10. Status register 1 (FMC_STAT1) ......................58 2.4.11.
Page 4 GD32F30x User Manual 5.2.1. Overview ..............................80 5.2.2. Characteristics............................82 5.2.3. Function overview........................... 82 5.3. Register definition....................86 5.3.1. Control register (RCU_CTL)......................... 86 5.3.2. Clock configuration register 0 (RCU_CFG0) ..................87 5.3.3. Clock interrupt register (RCU_INT) ....................91 5.3.4. APB2 reset register (RCU_APB2RST) ....................94 5.3.5.
Page 5 GD32F30x User Manual 5.6.14. Additional clock control register (RCU_ADDCTL).................149 5.6.15. Additional clock interrupt register (RCU_ADDINT) ...............150 5.6.16. APB1 additional reset register (RCU_ADDAPB1RST) ..............150 5.6.17. APB1 additional enable register (RCU_ADDAPB1EN) ...............151 6. Clock trim controller (CTC)..................152 6.1. Overview ........................152 6.2.
Page 6 GD32F30x User Manual 8.3.5. Output configuration..........................176 8.3.6. Analog configuration ..........................177 8.3.7. Alternate function (AF) configuration....................177 8.3.8. GPIO locking function ..........................178 8.3.9. GPIO I/O compensation cell.......................178 8.4. Remapping function I/O and debug configuration ............178 8.4.1. Introduction.............................178 8.4.2. Main features ............................179 8.4.3.
Page 7 GD32F30x User Manual 9.4.2. Free data register (CRC_FDATA) .....................210 9.4.3. Control register (CRC_CTL).......................211 Direct memory access controller (DMA) ............212 10.1. Overview ....................... 212 10.2. Characteristics ......................212 10.3. Block diagram ......................213 10.4. Function overview ....................213 10.4.1. DMA operation............................213 10.4.2.
Page 8 GD32F30x User Manual 12.2. Characteristics......................234 12.3. Pins and internal signals ..................235 12.4. Functional overview....................236 12.4.1. Foreground calibration function ......................236 12.4.2. ADC clock ...............................237 12.4.3. ADC enable ............................237 12.4.4. Routine sequence..........................237 12.4.5. Operation modes ..........................237 12.4.6. Conversion result threshold monitor function.................240 12.4.7.
Page 9 GD32F30x User Manual 13.3.2. DAC output buffer ..........................262 13.3.3. DAC data configuration ........................263 13.3.4. DAC trigger.............................263 13.3.5. DAC workflow ............................263 13.3.6. DAC noise wave............................263 13.3.7. DAC output calculate ...........................264 13.3.8. DMA function............................265 13.3.9. DAC concurrent conversion .......................265 13.4. DAC registers......................266 13.4.1.
Page 10 GD32F30x User Manual 15.4. RTC Register ......................290 15.4.1. RTC interrupt enable register(RTC_INTEN)...................290 15.4.2. RTC control register(RTC_CTL)......................290 15.4.3. RTC prescaler high register (RTC_PSCH) ..................291 15.4.4. RTC prescaler low register(RTC_PSCL)..................292 15.4.5. RTC divider high register (RTC_DIVH)....................292 15.4.6. RTC divider low register (RTC_DIVL) ....................292 15.4.7.
Page 11 GD32F30x User Manual 16.5.5. TIMERx registers(x=5, 6) ........................436 Universal synchronous/asynchronous receiver /transmitter (USART) ..441 17.1. Overview ....................... 441 Characteristics ....................441 17.2. 17.3. Function overview ....................442 17.3.1. USART frame format..........................443 17.3.2. Baud rate generation ...........................444 17.3.3. USART transmitter..........................444 17.3.4.
Page 12 GD32F30x User Manual 18.3.8. SCL line stretching..........................483 18.3.9. Use DMA for data transfer ........................484 18.3.10. Packet error checking........................484 18.3.11. SMBus support..........................485 18.3.12. Status, errors and interrupts ......................486 18.4. Register definition ....................488 18.4.1. Control register 0 (I2C_CTL0) ......................488 18.4.2. Control register 1 (I2C_CTL1) ......................490 18.4.3.
Page 13 GD32F30x User Manual 19.5.3. Status register (SPI_STAT) ........................533 19.5.4. Data register (SPI_DATA) ........................534 19.5.5. CRC polynomial register (SPI_CRCPOLY) ..................535 19.5.6. RX CRC register (SPI_RCRC) ......................535 19.5.7. TX CRC register (SPI_TCRC) ......................536 19.5.8. I2S control register (SPI_I2SCTL) ....................537 19.5.9. I2S clock prescaler register (SPI_I2SPSC) ..................538 19.5.10.
Page 14 GD32F30x User Manual 20.8.6. Response register (SDIO_RESPx x=0..3) ..................593 20.8.7. Data timeout register (SDIO_DATATO) ...................594 20.8.8. Data length register (SDIO_DATALEN) ...................594 20.8.9. Data control register (SDIO_DATACTL) ..................595 20.8.10. Data counter register (SDIO_DATACNT)..................596 20.8.11. Status register (SDIO_STAT)......................597 20.8.12. Interrupt clear register (SDIO_INTC) ...................598 20.8.13.
Page 15 GD32F30x User Manual 22.4.5. Receive message FIFO1 register (CAN_RFIFO1) ...............665 22.4.6. Interrupt enable register (CAN_INTEN)...................666 22.4.7. Error register (CAN_ERR) ........................668 22.4.8. Bit timing register (CAN_BT)......................669 22.4.9. Transmit mailbox identifier register (CAN_TMIx) (x = 0…2) ............670 22.4.10. Transmit mailbox property register (CAN_TMPx) (x = 0...2) ..........670 22.4.11.
Page 16 GD32F30x User Manual 23.4.9. MAC remote wakeup frame filter register (ENET_MAC_RWFF)..........745 23.4.10. MAC wakeup management register (ENET_MAC_WUM) .............745 23.4.11. MAC debug register (ENET_MAC_DBG) ...................746 23.4.12. MAC interrupt flag register (ENET_MAC_INTF) ...............748 23.4.13. MAC interrupt mask register (ENET_MAC_INTMSK) .............749 23.4.14. MAC address 0 high register (ENET_MAC_ADDR0H) ............750 23.4.15.
Page 17 GD32F30x User Manual 23.4.51. DMA control register (ENET_DMA_CTL) ...................777 23.4.52. DMA interrupt enable register (ENET_DMA_INTEN) ..............780 23.4.53. DMA missed frame and buffer overflow counter register (ENET_DMA_MFBOCNT)..782 23.4.54. DMA receive state watchdog counter register (ENET_DMA_RSWDC) ......783 23.4.55. DMA current transmit descriptor address register (ENET_DMA_CTDADDR) ....783 23.4.56.
Page 18 GD32F30x User Manual 25.4. Signal description ....................807 25.5. Function overview ....................807 25.5.1. USBFS clocks and working modes ....................807 25.5.2. USB host function ..........................809 25.5.3. USB device function..........................811 25.5.4. OTG function overview ........................812 25.5.5. Data FIFO ...............................813 25.5.6. Operation guide.............................815 25.6.
Page 19: List Of Figures
GD32F30x User Manual List of Figures ® Figure 1-1. The structure of the Cortex -M4 processor ...............31 Figure 1-2. GD32F303 series system architecture ...............33 Figure 1-3. GD32F305 and GD32F307 series system architecture ..........34 Figure 2-1. Process of page erase operation ................46 Figure 2-2.
Page 20 GD32F30x User Manual Figure 12-12. Numerical example with 5-bits shift and rounding ..........244 Figure 12-13. ADC sync block diagram ..................246 Figure 12-14. Routine parallel mode on 10 channels ..............247 Figure 12-16. Routine follow-up fast mode (the CTN bit of ADCs are set) ........247 Figure 12-17.
Page 21 GD32F30x User Manual Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR ongoing ......355 Figure 16-34. Timing chart of down counting mode, PSC=0/2 ............ 356 Figure 16-35. Timing chart of down counting mode, change TIMERx_CAR ongoing ....356 Figure 16-36.
Page 22 GD32F30x User Manual Figure 17-9. Break frame occurs during idle state..............451 Figure 17-10. Break frame occurs during a frame ..............451 Figure 17-11. Example of USART in synchronous mode............451 Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) ......... 452 Figure 17-13.
Page 23 GD32F30x User Manual Figure 19-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ....517 Figure 19-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....517 Figure 19-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ....517 Figure 19-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....518 Figure 19-27.
Page 24 GD32F30x User Manual Figure 19-51. Block diagram of I2S clock generator ..............523 Figure 19-52. I2S initialization sequence .................. 525 Figure 19-53. I2S master reception disabling sequence ............527 Figure 20-1. SDIO “no response” and “no data” operations ............542 Figure 20-2.
Page 25 GD32F30x User Manual Figure 21-23. Access timing of common memory space of PC Card Controller......629 Figure 21-24. Access to none "NCE don’t care" NAND Flash............. 630 Figure 22-1. CAN module block diagram .................. 645 Figure 22-2. Transmission register ..................647 Figure 22-3.
Page 26: List Of Table
GD32F30x User Manual List of Table Table 1-1. The interconnection relationship of the AHB interconnect matrix.........31 Table 1-2. Memory map of GD32F30x devices ................35 Table 1-3. Boot modes ......................39 Table 1-4. Bootloader supported peripherals ................40 Table 2-1. GD32F30x_CL and GD32F30x_HD, GD32F30x_XD base address and size for flash memory ..........................43 Table 2-2.
Page 27 GD32F30x User Manual Table 13-1. DAC I/O description ....................262 Table 13-2. External triggers of DAC ..................263 Table 14-1. Min/max FWDGT timeout period at 40 kHz (IRC40K) ..........276 )..............283 Table 14-2. Min/max timeout value at 60 MHz (f PCLK1 Table 16-1.
Page 28 GD32F30x User Manual Table 20-18. Response R4 for SD I/O..................564 Table 20-19. Response R5 for MMC ..................564 Table 20-20. Response R5 for SD I/O..................565 Table 20-21. Response R6 ....................... 565 Table 20-22. Response R7 ....................... 565 Table 20-23. Card status ......................567 Table 20-24.
Page 29 GD32F30x User Manual ............................719 Table 23-10. Supported time stamp snapshot with PTP register configuration ......764 Table 24-1. USBD signal description ..................787 Table 24-2. Double-buffering buffer flag definition ..............790 Table 24-3. Double buffer usage ....................790 Table 24-4. Reception status encoding ..................802 Table 24-5.
Page 30: System And Memory Architecture
GD32F30x User Manual System and memory architecture The devices of GD32F30x series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M4 processor. The Arm Cortex -M4 processor includes three AHB buses ® ® known as I-Code, D-Code and System buses. All memory accesses of the Arm Cortex processor are executed on the three buses according to the different purposes and the target memory spaces.
Page 31: System Architecture
GD32F30x User Manual ® Figure 1-1. The structure of the Cortex -M4 processor Cortex-M4 processor Cortex-M4 core Interrupts and Nested Power control Vectored Interrupt Controller Floating Point (NVIC) Unit(FPU) Wake-up Interrupt Controller (WIC) Data Flash Patch Memory Watchpoint Breakpoint Protection And Trace (FPB) Unit(MPU)
Page 32 GD32F30x User Manual IBUS DBUS SBUS DMA0 DMA1 ENET APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including IBUS, DBUS, SBUS, DMA0, DMA1 and ENET. IBUS is the instruction bus of the ®...
Page 33: Figure 1-2. Gd32F303 Series System Architecture
GD32F30x User Manual Figure 1-2. GD32F303 series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus ARM Cortex-M4 Memory Memory Controller Processor : 120MHz Dbus Fmax:120MHz SDIO 1.2V NVIC Master AHB Peripherals Slave 8MHz SRAM GP DMA 12 chs SRAM Controller Master Slave...
Page 34: Memory Map
GD32F30x User Manual Figure 1-3. GD32F305 and GD32F307 series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M4 Memory Controller : 120MHz Processor Dbus Fmax:120MHz USBFS 1.2V NVIC Master Slave AHB Peripherals 8MHz GP DMA 12 chs SRAM SRAM Controller...
Page 35: Table 1-2. Memory Map Of Gd32F30X Devices
GD32F30x User Manual ® which is the maximum address range of the Cortex -M4 since the bus address width is 32- ® bit. Additionally, a pre-def ined memory map is provided by the Cortex -M4 processor to reduce the software complexity of repeated implementation of different device vendors. In the ®...
Page 36 GD32F30x User Manual Pre-defined Address Peripherals Regions 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF SDIO 0x4001 7C00 - 0x4001 7FFF Reserved...
Page 37 GD32F30x User Manual Pre-defined Address Peripherals Regions 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF CAN1 0x4000 6400 - 0x4000 67FF...
Page 38: Bit-Banding
GD32F30x User Manual Pre-defined Address Peripherals Regions 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF B000 - 0x1FFF F7FF Boot loader 0x1FFF 7A10 - 0x1FFF AFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 0000 - 0x1FFF 77FF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved...
Page 39: On-Chip Sram Memory
GD32F30x User Manual bit_word_addr = 0x2200 0000 + (0x200 * 32)+ (7 * 4)= 0x2200 401C (1-2) Writing to address 0x2200 401C will cause bit 7 of address 0x2000 0200 change while a read to address 0x2200 401C will return 0x01 or 0x00 according to the value of bit 7 at the SRAM address 0x2000 0200.
Page 40: Device Electronic Signature
GD32F30x User Manual of -stack value f rom address 0x0000 0000 and the base address of boot code f rom 0x0000 0004 in sequence. Then, it starts executing code from the base address of boot code. Due to the selected boot source, either the main f lash memory (original memory space beginning at 0x0800 0000) or the system memory (HD series original memory space beginning at 0x1FFF F000, please ref er to Table 2-1.
Page 41: Memory Density Information
GD32F30x User Manual Memory density information 1.5.1. Base address: 0x1FFF F7E0 The value is f actory programmed and can never be altered by user. SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on -chip SRAM density of the device in Kbytes. Example: 0x0008 indicates 8 Kbytes.
Page 42: System Configuration Registers
GD32F30x User Manual Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is f actory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID 1.6. System configuration registers Base address: 0x4002 103C Reset value: 0x0000 0000 Reserved...
Page 43: Flash Memory Controller (Fmc)
GD32F30x User Manual Flash memory controller (FMC) 2.1. Introduction The f lash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the f irst 256K bytes of the f lash.
Page 44: Read Operations
GD32F30x User Manual flash memory size Block Name Address Range (bytes) Page 0 0x0800 0000 - 0x0800 07FF Page 1 0x0800 0800 - 0x0800 0FFF Page 2 0x0800 1000 - 0x0800 17FF Main Flash Block Page 255 0x0807 F800 - 0x0807 FFFF Page 256 0x0808 0000 - 0x0808 0FFF Page 257...
Page 45: Page Erase
GD32F30x User Manual For the GD32F30x_CL and GD32F30x_XD, the FMC_CTL0 register is used to configure the operations to bank0 and the option bytes block, while FMC_CTL1 register is used to configure the program and erase operations to bank1. The lock/unlock mechanism of FMC_CTL1 register is similar to FMC_CTL0 register.
Page 46: Mass Erase
GD32F30x User Manual Figure 2-1. Process of page erase operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish For the GD32F30x_CL and GD32F30x_XD, FMC_STAT0 ref lects the operation status of...
Page 47: Figure 2-2. Process Of Mass Erase Operation
GD32F30x User Manual Set MER bit in FMC_CTL0 register if erase Bank0 only. Set MER bit in FMC_CTL1 register if erase Bank1 only. Set MER bits in in FMC_CTL0 register and FMC_CTL1 register if erase entire flash; Send the mass erase command to the FMC by setting the START bit in FMC_CTL register;...
Page 48: Main Flash Programming
GD32F30x User Manual Main flash programming 2.3.6. The FMC provides a 32-bit word/16-bit half word/bit programming function which is used to modify the main f lash memory contents. The f ollowing steps show the register access sequence of the word programming operation. Unlock the FMC_CTLx registers if necessary;...
Page 49: Option Bytes Erase
GD32F30x User Manual Figure 2-3. Process of word program operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish For the GD32F30x_CL and GD32F30x_XD, the program procedure applied to bank1 is similar to the procedure applied to bank0.
Page 50: Option Bytes Modify
GD32F30x User Manual Read and verify the Flash memory if required using a DBUS access. When the operation is executed successful, the ENDF in FMC_STAT0 register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL0 register is set. Option bytes modify 2.3.8.
Page 51: Page Erase/Program Protection
GD32F30x User Manual Address Name Description 0x1fff f802 USER [7:4]: reserved [3]: BB 0: boot from bank1 or bank0 if bank1 is void, when configured boot from main memory 1: boot from bank0, when configured boot from main memory [2]: nRST_STDBY 0: generator a reset instead of entering standby mode 1: no reset when entering standby mode [1]: nRST_DPSLP...
Page 52: Security Protection
GD32F30x User Manual protected pages. If the page erase or program command is sent to the FMC on a protected page, the WPERR bit in the FMC_STATx registers will then be set by the FMC. If the WPERR bit is set and the ERRIE bit is also set to 1 to enable the corresponding interrupt, then the Flash operation error interrupt will be triggered by the FMC to draw the attention of the CPU.
Page 53: Fmc Registers
GD32F30x User Manual 2.4. FMC registers FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value.
Page 54: Option Byte Unlock Key Register (Fmc_Obkey)
GD32F30x User Manual Write KEY[31:0] with keys to unlock FMC_CTL0 register. Option byte unlock key register (FMC_OBKEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_ CTL0 option bytes operation unlock register These bits are only be written by software.
Page 55: Control Register 0(Fmc_Ctl0)
GD32F30x User Manual Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value.
Page 56: Address Register 0 (Fmc_Addr0)
GD32F30x User Manual register. This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared. OBER Option bytes erase command bit This bit is set or clear by software.
Page 57: Option Byte Status Register (Fmc_Obstat)
GD32F30x User Manual Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase/program command address bits These bits are configured by software. ADDR bits are the address of flash erase/program command . Option byte status register (FMC_OBSTAT) 2.4.7. Address offset: 0x1C Reset value: 0x0XXX XXXX This register has to be accessed by word(32-bit) Reserved DATA[15:6]...
Page 58: Unlock Key Register 1(Fmc_Key1)
GD32F30x User Manual Bits Fields Descriptions 31:0 WP[31:0] Store WP of option bytes block after system reset. Unlock key register 1(FMC_KEY1) 2.4.9. Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0...
Page 59: Control Register 1(Fmc_Ctl1)
GD32F30x User Manual The software can clear it by writing 1. Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value.
Page 60: Address Register 1 (Fmc_Addr1)
GD32F30x User Manual This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared. Reserved Must be kept at reset value Main flash mass erase for bank1 command bit This bit is set or cleared by software.
Page 61: Product Id Register (Fmc_Pid)
GD32F30x User Manual Resrved Reserved BPEN WSEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value BPEN FMC bit program enable register This bit set and reset by software. 0: No effect, write page must check if flash is “FF” 1: Write page donot check the flash is FF.
Page 62: Power Management Unit (Pmu)
GD32F30x User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32F30x series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 63: Backup Domain
GD32F30x User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP WKUPR BREG BKP PAD WKUPN NRST WKUPF SLEEPING Cortex-M4 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V...
Page 64: Vdd
GD32F30x User Manual wakeup event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the Real-time Clock(RTC).
Page 65: Figure 3-3. Waveform Of The Lvd Threshold
GD32F30x User Manual Figure 3-2. Waveform of the POR / PDR 600mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register(PMU_CS), indicates if V is higher or lower than the LVD threshold.
Page 66: Power Domain
GD32F30x User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply V is implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 67 GD32F30x User Manual power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL register. The LDOVS bits should be configured only when the PLL is off, and the programmed value is selected to drive 1.2V domain after the PLL opened.
Page 68: Table 3-1. Power Saving Mode Summary
GD32F30x User Manual Normal-driver / Normal-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL register, and not in low-power mode depending on the LDOLP bit reset in the PMU_CTL register. Normal-driver / Low-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL register.
Page 69 GD32F30x User Manual Mode Sleep Deep-sleep Standby mode) normal driver mode or low driver mode) SLEEPDEEP = 1 SLEEPDEEP = 1 Configuration SLEEPDEEP = 0 STBMOD = 1, WURST STBMOD = 0 Entry WFI or WFE WFI or WFE WFI or WFE Any interrupt for WFI Any interrupt from EXTI NRST pin...
Page 70: Pmu Registers
GD32F30x User Manual 3.4. PMU registers PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit) LDEN[1:0] Reserved HDEN LDOVS[1:0] Reserved LDNP...
Page 71 GD32F30x User Manual 01: LDO output voltage low mode 10: LDO output voltage mid mode 11: LDO output voltage high mode 13:12 Reserved Must be kept at reset value. LDNP Low-driver mode when use normal power LDO 0: normal driver when use normal power LDO 1: Low-driver mode enabled when LDEN is 11 and use normal power LDO LDLP Low-driver mode when use low power LDO.
Page 72: Control And Status Register (Pmu_Cs)
GD32F30x User Manual 1: Enter the Standby mode when the Cortex ® -M4 enters SLEEPDEEP mode LDOLP LDO Low Power Mode 0: The LDO operates normally during the Deep-sleep mode 1: The LDO is in low power mode during the Deep-sleep mode Control and status register (PMU_CS) 3.4.2.
Page 73 GD32F30x User Manual 0: Disable WKUP pin function 1: Enable WKUP pin function If WUPEN is set before entering the Standby mode, a rising edge on the WKUP pin wakes up the system from the Standby mode. As the WKUP pin is active high, the WKUP pin is internally configured to input pull down mode.
Page 74: Backup Registers (Bkp)
GD32F30x User Manual Backup registers (BKP) 4.1. Introduction The Backup registers are located in the Backup domain that remains powered -on by V even if V power is shut down, they are f orty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action f rom Standby mode or system reset do not af f ect these registers.
Page 75 GD32F30x User Manual and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection conf iguration should be set before enable TAMPER pin.
Page 76: Bkp Registers
GD32F30x User Manual 4.4. BKP registers Backup data register x (BKP_DATAx) (x= 0..41) 4.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) DATA [15:0] Bits Fields Descriptions 15:0 DATA[15:0]...
Page 77: Tamper Pin Control Register (Bkp_Tpctl)
GD32F30x User Manual This bit is reset only by a Backup domain reset. ASOEN RTC alarm or second signal output enable 0: Disable RTC alarm or second output 1: Enable RTC alarm or second output When enable, the TAMPER pin will output the RTC output. This bit is reset only by a Backup domain reset.
Page 78 GD32F30x User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved TPIE Bits Fields Descriptions 15:10 Reserved Must be kept at reset value. Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred This bit is reset by writing 1 to the TIR bit or the TPIE bit being 0.
Page 79: Reset And Clock Unit (Rcu)
GD32F30x User Manual Reset and clock unit (RCU) High- and extra-density eset and clock control unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. GD32F30x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 80: Clock Control Unit (Cctl)
GD32F30x User Manual A system reset resets the processor core and peripheral IP components except for the SW- DP controller and the backup domain. A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset).
Page 81: Figure 5-2. Clock Tree
GD32F30x User Manual Figure 5-2. Clock tree CK_IRC48M CK_CTC 48 MHz 48 MHz IRC48M CK48MSEL CK_USBD USBD Prescaler (to USBD) 1,1.5,2,2.5 SCS[1:0] 3,3.5,4 CK_I2S CK_IRC8M I2S enable (to I2S1,2) 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M …,63 120 MHz max Prescaler 120 MHz max (to EXMC)
Page 82: Characteristics
GD32F30x User Manual The RTC is clocked by LXTAL clock or IRC40K clock or HXTAL clock divided by 128 (defined which select by RTCSRC bit in backup domain control register (RCU_BDCTL). After the RTC select HXTAL clock divided by 128, the clock disappeared when the 1.2V core domain power of f.
Page 83: Figure 5-4. Hxtal Clock Source In Bypass Mode
GD32F30x User Manual PLL input clock. Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the control register RCU_CTL. During bypass mode, the signal is connected to OSCIN, and OSCOUT remains in the suspended state, as shown in Figure 5-4.
Page 84 GD32F30x User Manual between 48MHz with 500ppm accuracy. A hardware automatically dynamic trim performed in CTC unit adjust the IRC48M to the needed frequency. Phase locked loop (PLL) There is one internal Phase Locked Loop, the PLL. The PLL can be switched on or of f by using the PLLEN bit in the RCU_CTL register. The PLLSTB f lag in the RCU_CTL register will indicate if the PLL clock is stable.
Page 85: Table 5-1. Clock Output 0 Source Select
GD32F30x User Manual register 0, RCU_CFG0. When the SCS value is changed, the CK_SYS will continue to operate using the original clock source until the target clock source is stable. When a clock source is directly or indirectly (by PLL) used as the CK_SYS, it is not possible to stop it. HXTAL clock monitor (CKM) The HXTAL clock monitor f unction is enabled by the HXTAL clock monitor enable bit, CKMEN, in the control register (RCU_CTL).
Page 86: Register Definition
GD32F30x User Manual 5.3. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLLSTB Reserved CKMEN...
Page 87: Clock Configuration Register 0 (Rcu_Cfg0)
GD32F30x User Manual HXTALBPS High speed crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0. 0: Disable the HXTAL Bypass mode 1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock.
Page 88 GD32F30x User Manual USBDPS ADCPSC[ PLLMF[5] Reserved PLLMF[4] CKOUT0SEL[2:0] USBDPSC[1:0] PLLMF[3:0] PREDV0 PLLSEL C[2] ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions USBDPSC[2] Bit 2 of USBDPSC see bits 23:22 of RCU_CFG0 PLLMF[5] Bit 5 of PLLMF see bits 21:18 of RCU_CFG0 Reserved Must be kept at reset value.
Page 89 GD32F30x User Manual 000001: CK_SYS = CK_PLL x 3 000010: CK_SYS = CK_PLL x 4 000011: CK_SYS = CK_PLL x 5 000100: CK_SYS = CK_PLL x 6 000101: CK_SYS = CK_PLL x 7 000110: CK_SYS = CK_PLL x 8 000111: CK_SYS = CK_PLL x 9 001000: CK_SYS = CK_PLL x 10 001001: CK_SYS = CK_PLL x 11 001010: CK_SYS = CK_PLL x 12...
Page 90 GD32F30x User Manual 0: (IRC8M / 2) clock selected as source clock of PLL 1: HXTAL or IRC48M(PLLPRESEL of RCU_CFG1 register) selected as source clock of PLL 15:14 ADCPSC[1:0] ADC clock prescaler selection These bits, bit 28 of RCU_CFG0 and bit 29 of RCU_CFG1 are written by software to define the ADC prescaler factor.Set and cleared by software.
Page 91: Clock Interrupt Register (Rcu_Int)
GD32F30x User Manual 1110: (CK_SYS / 256) selected 1111: (CK_SYS / 512) selected SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock. 00: Select CK_IRC8M as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_PLL as the CK_SYS source 11: Reserved SCS[1:0]...
Page 92 GD32F30x User Manual PLLSTBIC PLL stabilization interrupt clear Write 1 by software to reset the PLLSTBIF flag. 0: Not reset PLLSTBIF flag 1: Reset PLLSTBIF flag HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by software to reset the HXTALSTBIF flag. 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC...
Page 93 GD32F30x User Manual 0: Disable the IRC40K stabilization interrupt 1: Enable the IRC40K stabilization interrupt CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck. Reset when setting the CKMIC bit by software. 0: Clock operating normally 1: HXTAL clock stuck Reserved Must be kept at reset value.
Page 94: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F30x User Manual APB2 reset register (RCU_APB2RST) 5.3.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). TIMER10 TIMER9 TIMER8 Reserved Reserved ADC2RS USART0 TIMER7R TIMER0R ADC1RS ADC0RS SPI0RST PGRST PFRST PERST PDRST PCRST PBRST...
Page 95 GD32F30x User Manual 1: Reset the TIMER7 SPI0RST SPI0 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI0 TIMER0RST Timer 0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 ADC1RST ADC1 reset...
Page 96: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F30x User Manual 0: No reset 1: Reset the GPIO port B PARST GPIO port A reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port A Reserved Must be kept at reset value. AFRST Alternate function I/O reset This bit is set and reset by software.
Page 97 GD32F30x User Manual 1: Reset backup interface Reserved Must be kept at reset value. CAN0RST CAN0 reset This bit is set and reset by software. 0: No reset 1: Reset the CAN0 Reserved Must be kept at reset value. USBDRST USBD reset This bit is set and reset by software.
Page 98 GD32F30x User Manual 0: No reset 1: Reset the SPI2 SPI1RST SPI1 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI1 13:12 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT 10:9...
Page 99: Ahb Enable Register (Rcu_Ahben)
GD32F30x User Manual 0: No reset 1: Reset the TIMER3 TIMER2RST TIMER2 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER2 TIMER1RST TIMER1 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER1 AHB enable register (RCU_AHBEN) 5.3.6.
Page 100: Apb2 Enable Register (Rcu_Apb2En)
GD32F30x User Manual 1: Enabled CRC clock Reserved Must be kept at reset value. FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software to enable/disable FMC clock during Sleep mode. 0: Disabled FMC clock during Sleep mode 1: Enabled FMC clock during Sleep mode Reserved Must be kept at reset value.
Page 101 GD32F30x User Manual This bit is set and reset by software. 0: Disabled TIMER10 clock 1: Enabled TIMER10 clock TIMER9EN TIMER9 clock enable This bit is set and reset by software. 0: Disabled TIMER9 clock 1: Enabled TIMER9 clock TIMER8EN TIMER8 clock enable This bit is set and reset by software.
Page 102: Apb1 Enable Register (Rcu_Apb1En)
GD32F30x User Manual 1: Enabled ADC0 clock PGEN GPIO port G clock enable This bit is set and reset by software. 0: Disabled GPIO port G clock 1: Enabled GPIO port G clock PFEN GPIO port F clock enable This bit is set and reset by software. 0: Disabled GPIO po rt F clock 1: Enabled GPIO p ort F clock PEEN...
Page 103 GD32F30x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). UART4E UART3E USART2 USART1 Reserved DACEN PMUEN BKPIEN Reserved CAN0EN Reserved USBDEN I2C1EN I2C0EN Reserved WWDGT TIMER13 TIMER12 TIMER11 TIMER6E TIMER5E TIMER4E TIMER3E TIMER2E TIMER1E SPI2EN SPI1EN Reserved Reserved Bits...
Page 104 GD32F30x User Manual This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software.
Page 105: Backup Domain Control Register (Rcu_Bdctl)
GD32F30x User Manual TIMER12EN TIMER12 clock enable This bit is set and reset by software. 0: Disabled TIMER12 clock 1: Enabled TIMER12 clock TIMER11EN TIMER11 clock enable This bit is set and reset by software. 0: Disabled TIMER11 clock 1: Enabled TIMER11 clock TIMER6EN TIMER6 clock enable This bit is set and reset by software.
Page 106 GD32F30x User Manual register (RCU_BDCTL) are only reset af ter a backup domain reset. These bits can be modified only when the BKPWEN bit in the power control register (PMU_CTL) is set. Reserved BKPRST LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LXTALDRI[1:0] LXTALEN Bits...
Page 107: Reset Source/Clock Register (Rcu_Rstsck)
GD32F30x User Manual 1: Enable the LXTAL Bypass mode LXTALSTB Low speed crystal oscillator stabilization flag Set by hardware to indicate if the LXTAL output clock is stable and ready for use. 0: LXTAL is not stable 1: LXTAL is stable LXTALEN LXTAL enable Set and reset by software.
Page 108: Clock Configuration Register 1 (Rcu_Cfg1)
GD32F30x User Manual 1: free Watchdog timer reset generated SWRSTF Software reset flag Set by hardware when a software reset generated. Reset by writing 1 to the RSTFC bit. 0: No software reset generated 1: Software reset generated PORRSTF Power reset flag Set by hardware when a power reset generated.
Page 109: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F30x User Manual Reserved Bits Fields Descriptions Reserved Must be kept at reset value. PLLPRESEL PLL clock source preselection 0: HXTAL selected as PLL source clock 1: CK_IRC48M selected as PLL source clock ADCPSC[3] Bit 3 of ADCPSC see bits 15:14 of RCU_CFG0 and bit 28 of RCU_CFG0 28:0 Reserved Must be kept at reset value.
Page 110: Additional Clock Control Register (Rcu_Addctl)
GD32F30x User Manual Additional clock control register (RCU_ADDCTL) 5.3.13. Address offset: 0xC0 Reset value: 0x8000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC48MS IRC48ME IRC48MCALIB[7:0] Reserved CK48MS Reserved Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register These bits are load automatically at power on.
Page 111: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32F30x User Manual IRC48MS Reserved Reserved TBIC IRC48MS IRC48MS Reserved Reserved Reserved TBIE TBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. IRC48MSTBIC Internal 48 MHz RC oscillator stabilization interrupt clear Write 1 by software to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag 1: Reset IRC48MSTBIF flag 21:15...
Page 112: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F30x User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. CTCRST CTC reset This bit is set and reset by software. 0: No reset 1: Reset CTC 26:0 Reserved Must be kept at reset value. APB1 additional enable register (RCU_ADDAPB1EN) 5.3.16.
Page 113: Connectivity Line Devices: Reset And Clock Control Unit (Rcu)
GD32F30x User Manual Connectivity line devices: reset and clock control unit (RCU) 5.4. Reset control unit (RCTL) Overview 5.4.1. GD32F30x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 114: Clock Control Unit (Cctl)
GD32F30x User Manual source (external or internal reset). Figure 5-5. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us Sys tem Res et FWDGT_RSTn pulse generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have...
Page 115: Figure 5-5. Clock Tree
GD32F30x User Manual Figure 5-6. Clock tree CK_IRC48M CK_CTC 48 MHz 48 MHz IRC48M CK48MSEL CK_USBFS USB OTG Prescaler (to USBFS) 1,1.5,2,2.5 SCS[1:0] 3,3.5,4 CK_IRC8M 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M …,63 120 MHz max Prescaler 120 MHz max (to EXMC) EXMC enable ÷...
Page 116: Characteristics
GD32F30x User Manual prescaler is not 1). The USBFS is clocked by the clock of CK48M. The CK48M is selected from the clock of CK_PLL or the clock of IRC48M by CK48MSEL bit in RCU_ADDCTL register. The CTC is clocked by the clock of IRC48M. The IRC48M can be automatically trimmed by CTC unit.
Page 117: Figure 5-6. Hxtal Clock Source
GD32F30x User Manual Figure 5-7. HXTAL clock source The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL. The HXTALSTB f lag in control register RCU_CTL indicates if the high- speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released f or use until this HXTALSTB bit is set by the hardware.
Page 118 GD32F30x User Manual f requency is still less accurate than HXTAL. The application requirements, environment and cost will determine which oscillator type is selected. If the HXTAL or PLL is the system clock source, to minimize the time required for the system to recover from the Deep-sleep Mode, the hardware forces the IRC8M clock to be the system clock when the system initially wakes-up.
Page 119 GD32F30x User Manual circuit. The LXTAL oscillator can be switched on or off using the LXTALEN bit in the backup domain control register (RCU_BDCTL). The LXTALSTB f lag in the backup domain control register (RCU_BDCTL) will indicate if the LXTAL clock is stable. An interrupt can be generated if the related interrupt enable bit, LXTALSTBIE, in the interrupt register RCU_INT is set when the LXTAL becomes stable.
Page 120: Table 5-3. Clock Output 0 Source Select
GD32F30x User Manual Clock output capability The clock output capability is ranging from 4 MHz to 120 MHz. There are several clock signals can be selected via the CK_OUT0 clock source selection bits, CKOUT0SEL, in the clock conf iguration register 0 (RCU_CFG0). The corresponding GPIO pin should be configured in the properly alternate function I/O (AFIO) mode to output the selected clock signal..
Page 121: Register Definition
GD32F30x User Manual 5.6. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.6.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB Reserved...
Page 122 GD32F30x User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL is switched off 1: PLL is switched on 23:20...
Page 123: Clock Configuration Register 0 (Rcu_Cfg0)
GD32F30x User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M internal 8MHz RC oscillator stabilization flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable Set and reset by software.
Page 124 GD32F30x User Manual 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 23:22 USBFSPSC[1:0] USBFS clock prescaler selection Set and reset by software to control the USBFS clock prescaler value. The USBFS clock must be 48MHz.
Page 125 GD32F30x User Manual 011010: (PLL source clock x 27) 011011: (PLL source clock x 28) 011100: (PLL source clock x 29) 011101: (PLL source clock x 30) 011110: (PLL source clock x 31) 011111: (PLL source clock x 32) 100000: (PLL source clock x 33) 100001: (PLL source clock x 34) …...
Page 126: Clock Interrupt Register (Rcu_Int)
GD32F30x User Manual 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0] APB1 prescaler selection Set and reset by software to control the APB1 clock division ratio. Caution: The CK_APB1 output frequency must not exceed 60 MHz. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected...
Page 127 GD32F30x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIC STBIC STBIC STBIC STBIC STBIC STBIC STBIC PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIF STBIE...
Page 128 GD32F30x User Manual IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by software to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag Reserved Must be kept at reset value. PLL2STBIE PLL2 stabilization interrupt enable Set and reset by software to enable/disable the PLL2 stabilization interrupt. 0: Disable the PLL2 stabilization interrupt 1: Enable the PLL2 stabilization interrupt PLL1STBIE...
Page 129 GD32F30x User Manual Set by hardware when the PLL2 is stable and the PLL2STBIE bit is set. Reset when setting the PLL2STBIC bit by software. 0: No PLL2 stabilization interrupt generated 1: PLL2 stabilization interrupt generated PLL1STBIF PLL1 stabilization interrupt flag Set by hardware when the PLL1 is stable and the PLL1STBIE bit is set.
Page 130: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F30x User Manual APB2 reset register (RCU_APB2RST) 5.6.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). TIMER10 TIMER9 TIMER8 Reserved Reserved USART0 TIMER7R TIMER0R ADC1RS ADC0RS Reserved SPI0RST PGRST PFRST PERST PDRST PCRST PBRST...
Page 131 GD32F30x User Manual 1: Reset the SPI0 TIMER0RST Timer 0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 ADC1RST ADC1 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC1 ADC0RST ADC0 reset...
Page 132: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F30x User Manual 0: No reset 1: Reset the GPIO port A Reserved Must be kept at reset value. AFRST Alternate function I/O reset This bit is set and reset by software. 0: No reset 1: Reset Alternate Function I/O APB1 reset register (RCU_APB1RST) 5.6.5.
Page 133 GD32F30x User Manual 1: Reset the CAN1 CAN0RST CAN0 reset This bit is set and reset by software. 0: No reset 1: Reset the CAN0 24:23 Reserved Must be kept at reset value. I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C1 I2C0RST...
Page 134 GD32F30x User Manual 1: Reset the SPI1 13:12 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT 10:9 Reserved Must be kept at reset value. TIMER13RST TIMER13 reset This bit is set and reset by software.
Page 135: Ahb Enable Register (Rcu_Ahben)
GD32F30x User Manual 1: Reset the TIMER2 TIMER1RST TIMER1 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER1 AHB enable register (RCU_AHBEN) 5.6.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). ENETRXE Reserved ENETTX...
Page 136: Apb2 Enable Register (Rcu_Apb2En)
GD32F30x User Manual 11:9 Reserved Must be kept at reset value. EXMCEN EXMC clock enable This bit is set and reset by software. 0: Disabled EXMC clock 1: Enabled EXMC clock Reserved Must be kept at reset value. CRCEN CRC clock enable This bit is set and reset by software.
Page 137 GD32F30x User Manual TIMER10 TIMER9E TIMER8E Reserved Reserved USART0 TIMER7E TIMER0E Reserved SPI0EN ADC1EN ADC0EN PGEN PFEN PEEN PDEN PCEN PBEN PAEN Reserved AFEN Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. TIMER10EN TIMER10 clock enable This bit is set and reset by software. 0: Disabled TIMER10 clock 1: Enabled TIMER10 clock TIMER9EN...
Page 138 GD32F30x User Manual ADC1EN ADC1 clock enable This bit is set and reset by software. 0: Disabled ADC1 clock 1: Enabled ADC1 clock ADC0EN ADC0 clock enable This bit is set and reset by software. 0: Disabled ADC0 clock 1: Enabled ADC0 clock PGEN GPIO port G clock enable This bit is set and reset by software.
Page 139: Apb1 Enable Register (Rcu_Apb1En)
GD32F30x User Manual 0: Disabled Alternate Function IO clock 1: Enabled Alternate Function IO clock APB1 enable register (RCU_APB1EN) 5.6.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). UART4E UART3E USART2 USART1 Reserved DACEN...
Page 140 GD32F30x User Manual 24:23 Reserved Must be kept at reset value. I2C1EN I2C1 clock enable This bit is set and reset by software. 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN...
Page 141 GD32F30x User Manual 1: Enabled WWDGT clock 10:9 Reserved Must be kept at reset value. TIMER13EN TIMER13 clock enable This bit is set and reset by software. 0: Disabled TIMER13 clock 1: Enabled TIMER13 clock TIMER12EN TIMER12 clock enable This bit is set and reset by software. 0: Disabled TIMER12 clock 1: Enabled TIMER12 clock TIMER11EN...
Page 142: Backup Domain Control Register (Rcu_Bdctl)
GD32F30x User Manual Backup domain control register (RCU_BDCTL) 5.6.9. Address offset: 0x20 Reset value: 0x0000 0018, reset by backup domain reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the backup domain control register (RCU_BDCTL) are only reset after a backup domain reset.
Page 143: Reset Source/Clock Register (Rcu_Rstsck)
GD32F30x User Manual 10: Medium high driving capability 11: Higher driving capability (reset value) Note: The LXTALDRI is not in bypass mode. LXTALBPS LXTAL bypass mode enable Set and reset by software. 0: Disable the LXTAL bypass mode 1: Enable the LXTAL bypass mode LXTALSTB Low speed crystal oscillator stabilization flag Set by hardware to indicate if the LXTAL output clock is stable and ready for use.
Page 144 GD32F30x User Manual 0: No window watchdog reset generated 1: Window watchdog reset generated FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No free watchdog timer reset generated 1: free Watchdog timer reset generated SWRSTF Software reset flag...
Page 145: Ahb Reset Register (Rcu_Ahbrst)
GD32F30x User Manual AHB reset register (RCU_AHBRST) 5.6.11. Address offset: 0x28 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved ENETRS USBFSR Reserved Reserved Reserved Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ENETRST ENET reset This bit is set and reset by software.
Page 146 GD32F30x User Manual PLL2MF[4] Bit 5 of PLL2MF see bits 15:12 of RCU_CFG1 PLLPRESEL PLL clock source preselection 0: HXTAL selected as PLL source clock 1: CK_IRC48M selected as PLL source clock ADCPSC[3] Bit 4 of ADCPSC see bits 15:14 of RCU_CFG0 and bit 28 of RCU_CFG0 28:19 Reserved Must be kept at reset value.
Page 147 GD32F30x User Manual 10101: (PLL2 source clock x 23) 10110: (PLL2 source clock x 24) 10111: (PLL2 source clock x 25) 11000 :(PLL2 source clock x 26) 11001: (PLL2 source clock x 27) 11010: (PLL2 source clock x 28) 11011: (PLL2 source clock x 29) 11100: (PLL2 source clock x 30) 11101: (PLL2 source clock x 31) 11110: (PLL2 source clock x 32)
Page 148: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F30x User Manual 1111: PREDV2 input source clock divided by 16 PREDV0[3:0] PREDV0 division factor This bit is set and reset by software. These bits can be written when PLL is disable. Note: The bit 0 of PREDV0 is same as bit 17 of RCU_CFG0, so modifying Bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1.
Page 149: Additional Clock Control Register (Rcu_Addctl)
GD32F30x User Manual not recommended to use it) 010: The core voltage is (default value-0.2)V in Deep-sleep mode(customers are not recommended to use it) 011: The core voltage is (default value-0.3)V in Deep-sleep mode(customers are not recommended to use it) 1xx: Reserved Additional clock control register (RCU_ADDCTL) 5.6.14.
Page 150: Additional Clock Interrupt Register (Rcu_Addint)
GD32F30x User Manual Additional clock interrupt register (RCU_ADDINT) 5.6.15. Address offset: 0xCC Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC48MS Reserved Reserved TBIC IRC48MS IRC48MS Reserved Reserved Reserved TBIE TBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value.
Page 151: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F30x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved Reserved Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. CTCRST CTC reset This bit is set and reset by software. 0: No reset 1: Reset CTC 26:0 Reserved...
Page 152: Clock Trim Controller (Ctc)
GD32F30x User Manual Clock trim controller (CTC) 6.1. Overview The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the f requency of the IRC48M based on an external accurate ref erence signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 153: Ref Sync Pulse Generator
GD32F30x User Manual Figure 6-1. CTC overview PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 6.3.1.
Page 154: Frequency Evaluation And Automatically Trim Process
GD32F30x User Manual zero, and then up- counting to 128 x CKLIM (def ined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 155: Software Program Guide
GD32F30x User Manual If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed. ◼ CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 156 GD32F30x User Manual The typical step size is 0.12%. Where the F is the f requency of correct clock (IRC48M), clock the F is the f requency of reference sync pulse.
Page 157: Register Definition
GD32F30x User Manual 6.4. Register definition CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 158: Control Register 1 (Ctc_Ctl1)
GD32F30x User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim warning (CKWARNIF) interrupt enable...
Page 159: Status Register (Ctc_Stat)
GD32F30x User Manual 01: LXTAL clock selected 10: Reserved 11: Reserved Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8 100: Reference signal divided by 16...
Page 160 GD32F30x User Manual REFCAP bits. REFDIR CTC trim counter direction when reference sync pulse When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value.
Page 161: Interrupt Clear Register (Ctc_Intc)
GD32F30x User Manual CTC_INTC register. 0: No Error occur 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 162 GD32F30x User Manual This bit is written by software and read as 0. Write 1 to clear ERRIF, TRIMERR, REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register.
Page 163: Interrupt / Event Controller (Exti)
GD32F30x User Manual Interrupt / event controller (EXTI) Overview 7.1. ® Cortex -M4 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC f acilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. More details about ®...
Page 164: Table 7-1. Nvic Exception Types In Cortex ® -M4
GD32F30x User Manual ® Table 7-1. NVIC exception types in Cortex Vector Exception type Priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable...
Page 165 GD32F30x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector Address Number Number Interrupt Description Interrupt Description DMA0 channel3 global DMA0 channel3 global IRQ 14 0x0000_0078 interrupt interrupt DMA0 channel4 global DMA0 channel4 global IRQ 15 0x0000_007C interrupt interrupt DMA0 channel5 global DMA0 channel5 global IRQ 16 0x0000_0080...
Page 166 GD32F30x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector Address Number Number Interrupt Description Interrupt Description USBD wakeup from EXTI USBFS wakeup from EXTI IRQ 42 0x0000_00E8 interrupt interrupt TIMER7 break interrupt and TIMER7 break interrupt and IRQ 43 0x0000_00EC TIMER11 global interrupt TIMER11 global interrupt...
Page 167: External Interrupt And Event (Exti) Block Diagram
GD32F30x User Manual interrupts(IRQ24、IRQ25、IRQ26、IRQ43、IRQ44、IRQ45)are available only in the XD devices. 2. At non-connectivity devices, USB and CAN (IRQ19, IRQ 20) f unction cannot be used at the same time External interrupt and event (EXTI) block diagram 7.4. Figure 7-1. Block diagram of EXTI Polarity Software Control...
Page 168: Table 7-3. Exti Source
GD32F30x User Manual NVIC to be put into a very low-power sleep mode leaving the WIC to identify and prioritize interrupts and event. EXTI can be used to wake up processor and the whole system when some expected event occurs, such as a special GPIO pin toggling or RTC alarm. Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals.
Page 169 GD32F30x User Manual EXTI Line Source Number PA13 / PB13 / PC13 / PD13 / PE13 / PF13 / PG13 PA14 / PB14 / PC14 / PD14 / PE14 / PF14 / PG14 PA15 / PB15 / PC15 / PD15 / PE15 / PF15 / PG15 RTC Alarm USB Wakeup Ethernet Wakeup...
Page 170: Exti Register
GD32F30x User Manual EXTI Register 7.6. EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7 INTEN6...
Page 171: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F30x User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5 RTEN4 RTEN3...
Page 172: Pending Register (Exti_Pd)
GD32F30x User Manual Reserved SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19: 0 SWIEVx Interrupt / Event software trigger x (x = 0…19) 0: Deactivate the EXTIx software interrupt / event request 1: Activate the EXTIx software interrupt / event request Pending register (EXTI_PD)
Page 173: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32F30x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 8.1. There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions.
Page 174: Gpio Pin Configuration
GD32F30x User Manual Table 8-1. GPIO configuration table Configuration mode CTL[1:0] SPDy: MD[1:0] OCTL don’t care Analog don’t care Input floating Input x 00 Input pull-down Input pull-up x 00: Reserved Push-pull 0 or 1 General purpose x 01: Speed up to 10MHz Output (GPIO) Open-drain 0 or 1...
Page 175: External Interrupt/Event Lines
GD32F30x User Manual PA13: JTMS / SWDIO in PU mode. PB4: NJTRST in PU mode. PB3: JTDO in Floating mode. The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen.
Page 176: Output Configuration
GD32F30x User Manual Figure 8-2. Input configuration Output configuration 8.3.5. When GPIO pin is configured as output: ◼ The schmitt trigger input is enabled. ◼ The weak pull-up and pull-down resistors are disabled. ◼ The output buffer is enabled. ◼ Open Drain Mode, the pad outputs low level when setting “0”...
Page 177: Analog Configuration
GD32F30x User Manual Analog configuration 8.3.6. When GPIO pin is used as analog configuration: ◼ The weak pull-up and pull-down resistors are disabled. ◼ The output buffer is disabled. ◼ The schmitt trigger input is disabled. ◼ The port input status register of this I/O port bit is “0”. Figure 8-4.
Page 178: Gpio Locking Function
GD32F30x User Manual Figure 8-5. Alternate function configuration Output driver Alternate Function Output Output Control protection I/O pin Alternate Function Input Schmitt trigger Input driver GPIO locking function 8.3.8. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL0, GPIOx_CTL1. It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK).
Page 179: Main Features
GD32F30x User Manual line source by setting the relevant EXTI source selection register (AFIO_EXTISSx) to trigger an interrupt or event. Main features 8.4.2. ◼ EXTI source selection. ◼ Each pin has up to four alternative functions for configuration. JTAG/SWD alternate function remapping 8.4.3.
Page 180: Adc Af Remapping
GD32F30x User Manual ADC AF remapping 8.4.4. Refer to AFIO Port Configuration Register 0 (AFIO_ PCF0). Table 8-4. ADC0/ADC1 external trigger rountine conversion AF remapping Register ADC0 ADC1 ADC0 external signal trigger ADC0_ETRGRER_REMA normal conversion is connected P = 0 to EXTI11 ADC0 external signal trigger ADC0_ETRGRER_REMA...
Page 181: Table 8-6. Timer4 Alternate Function Remapping
GD32F30x User Manual TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 8，9，10，12， function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER1_CH0/T PA15 PA15 IMER1_ETI TIMER1_CH1 TIMER1_CH2 PB10 TIMER1_CH3 PB11 TIMER2_CH0 TIMER2_CH1 TIMER2_CH2 TIMER2_CH3 TIMER3_CH0 PD12 TIMER3_CH1 PD13 TIMER3_CH2 PD14...
Page 182: Usart Af Remapping
GD32F30x User Manual USART AF remapping 8.4.6. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-7. USART alternate function remapping Register USART0 USART1 USART2 PA9(USART0_TX) USART0_REMAP = 0 PA10(USART0_RX) PB6(USART0_TX) USART0_REMAP = 1 PB7(USART0_RX) PA0(USART1_CTS) PA1(USART1_RTS) USART1_REMAP = 0 PA2(USART1_TX) PA3(USART1_RX) PA4(USART1_CK)
Page 183: Spi/I2S Af Remapping
GD32F30x User Manual Table 8-8. I2C0 alternate function remapping Register I2C0_SCL I2C0_SDA I2C0_REMAP = 0 I2C0_REMAP = 1 SPI/I2S AF remapping 8.4.8. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-9. SPI/I2S alternate function remapping Register SPI0 SPI2/I2S PA4(SPI0_NSS) PA5(SPI0_SCK) PA6(SPI0_MISO) SPI0_REMAP = 0...
Page 184: Ethernet Af Remapping
GD32F30x User Manual Register CAN0 CAN1 PB12(CAN1_RX) CAN1_REMAP = “0” PB13(CAN1_TX) PB5(CAN1_RX) CAN1_REMAP = “1” PB6(CAN1_TX) CAN0_RX and CAN0_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single CAN interface. This remapping is available only on 100-pin packages. Ethernet AF remapping 8.4.10.
Page 185: Table 8-13. Osc32 Pins Configuration
GD32F30x User Manual 2. Refer to the note on IO usage restrictions in Section 3.3.1. Table 8-13. OSC32 pins configuration Alternate function LXTAL= ON LXTAL= OFF PC14 OSC32_IN PC14 PC15 OSC32_OUT PC15 The HXTAL oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1. Table 8-14.
Page 186: Register Definition
GD32F30x User Manual Register definition 8.5. GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..G) 8.5.1.
Page 187 GD32F30x User Manual 21:20 MD5[1:0] Pin 5 mode bits These bits are set and cleared by software refer to MD0[1:0]description 19:18 CTL4[1:0] Pin 4 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD4[1:0] Pin 4 mode bits These bits are set and cleared by software refer to MD0[1:0]description 15:14...
Page 188: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32F30x User Manual 11: AFIO output with open -drain MD0[1:0] Pin 0 mode bits These bits are set and cleared by software 00: Input mode (reset state) 01: Output mode ,max speed 10MHz 10: Output mode ,max speed 2 MHz 11: Output mode ,max speed 50MHz Port control register 1 (GPIOx_CTL1, x=A..G) 8.5.2.
Page 189: Port Input Status Register (Gpiox_Istat, X=A
GD32F30x User Manual 19:18 CTL12[1:0] Pin 12 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD12[1:0] Pin 12 mode bits These bits are set and cleared by software refer to MD0[1:0]description 15:14 CTL11[1:0] Pin 11 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 13:12...
Page 190: Port Output Control Register (Gpiox_Octl, X=A
GD32F30x User Manual ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT 0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 ISTATy Pin input status(y=0..15)
Page 191: Port Bit Clear Register (Gpiox_Bc, X=A
GD32F30x User Manual BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Pin Clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy...
Page 192: Port Bit Speed Register (Gpiox_ Spd, X=A
GD32F30x User Manual LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Lock sequence key It can only be setted using the lock key writing sequence. And it is always readable. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset.
Page 193: Event Control Register (Afio_Ec)
GD32F30x User Manual Event control register (AFIO_EC) 8.5.9. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PORT[2:0] PIN[3:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Event output enable Set and cleared by software.
Page 194 GD32F30x User Manual ADC1_ ADC0_ TIMER4C SPI2_ ETRGRE ETRGRE Reserved Reserved SWJ_ CFG[2:0] Reserved Reserved Reserved REMAP IREMAP _REMAP _REMAP PD01_ TIMER3_ TIMER2_REMAP TIMER1_REMAP TIMER0_REMAP USART2_ USART1_ USART0_ I2C0_ SPI0_ CAN_REMAP [1:0] REMAP REMAP [1:0] [1:0] [1:0] REMAP[1:0] REMAP REMAP REMAP REMAP Bits...
Page 195 GD32F30x User Manual Reserved Must be kept at reset value. TIMER4CH3_ TIMER4 channel3 internal remapping IREMAP Set and cleared by software.This bit controls the TIMER4_CH3 internal mapping. When reset, TIMER4_CH3 is connected to PA3. When set the IRC40K internal clock is connected to TIMER4_CH3 input for calibration purpose. Note: This bit is available only in High -density value line devices.
Page 196 GD32F30x User Manual Full remap(TIMER1_CH0-TIMER1_ETI/PA15, TIMER1_CH1/PB3, TIMER1_CH2/PB10, TIMER1_CH3/PB11) TIMER0_REMAP TIMER0 remapping [1:0] These bits are set and cleared by software. 00: No remap (TIMER0_ETI/PA12, TIMER0_CH0/ PA8, TIMER0_CH1/PA9, TIMER0_CH2/PA10, TIMER0_CH3/PA11, TIMER0_BKIN/PB12, TIMER0_CH0_ON/PB13, TIMER0_CH1_ON/PB14, TIMER0_CH2_ON/PB15) 01: Partial remap (TIMER0_ETI/PA12, TIMER0_CH0/ PA8, TIMER0_CH1/PA9, TIMER0_CH2/PA10, TIMER0_CH3/PA11, TIMER0_BKIN/PA6,...
Page 197 GD32F30x User Manual 1: Remap (SPI0_NSS/PA15, SPI0_SCK /PB3, SPI0_MISO /PB4, SPI0_MOSI /PB5, SPI0_IO2 /PB6, SPI0_IO3 /PB7) Memory map and bit definitions for connectivity devices: PTP_ TIMER1 ENET TIMER4 SPI2_ CAN1_ ENET_ Reserved PPS_ ITI1_ Reserved SWJ_ CFG[2:0] _PHY Reserved CH3_ REMAP REMAP REMAP...
Page 198 GD32F30x User Manual reset is SWJ ON witho ut trace.This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS/JTCK pin 000: Full SWJ(JTAG-DP +SW-DP): Reset State 001: Full SWJ(JTAG-DP +SW-DP): but without NJTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect...
Page 199 GD32F30x User Manual 01: Not used 10: Partial remap (CAN0_RX/PB8, CAN0_TX/PB9) 11: Full remap (CAN0_RX/PD0, CAN0_TX/PD1) TIMER3_REMAP TIMER3 remapping This bit is set and cleared by software. 0: No remap (TIMER3_CH0/PB6, TIMER3_CH1/PB7, TIMER3_CH2/PB8, TIMER3_CH3/PB9) 1: Full remap (TIMER3_CH0/PD12, TIMER3_CH1/PD13, TIMER3_CH2/PD14, TIMER3_CH3/PD15) 11:10 TIMER2_REMAP...
Page 200: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32F30x User Manual [1:0] These bits are set and cleared by software. 00: No remap (USART2_TX/PB10, USART2_RX /PB11, USART2_CK/PB12, USART2_CTS/PB13, USART2_RTS/PB14) 01: Partial remap (USART2_TX/PC10, USART2_RX /PC11, USART2_CK/PC12, USART2_CTS/PB13, USART2_RTS/PB14) 10: Not used 11: Full remap (USART2_TX/PD8, USART2_RX /PD9, USART2_CK/PD1 0, USART2_CTS/PD11, USART2_RTS/PD12) USART1_REMAP USART1 remapping...
Page 201 GD32F30x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS [3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin 0011: PD3 pin 0100: PE3 pin 0101: PF3 pin 0110: PG3 pin Other configurations are reserved.
Page 202: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32F30x User Manual EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.12. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 203: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32F30x User Manual EXTI4_SS [3:0] EXTI 4 sources selection 0000: PA4 pin 0001: PB4 pin 0010: PC4 pin 0011: PD4 pin 0100: PE4 pin 0101: PF4 pin 0110: PG4 pin Other configurations are reserved. EXTI sources selection register 2 (AFIO_EXTISS2) 8.5.13.
Page 204: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32F30x User Manual Other configurations are reserved. EXTI9_SS [3:0] EXTI 9 sources selection 0000: PA9 pin 0001: PB9 pin 0010: PC9 pin 0011: PD9 pin 0100: PE9 pin 0101: PF9 pin 0110: PG9 pin Other configurations are reserved. EXTI8_SS [3:0] EXTI 8 sources selection 0000: PA8 pin 0001: PB8 pin...
Page 205: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32F30x User Manual 0101: PF15 pin 0110: PG15 pin Other configurations are reserved. 11:8 EXTI14_SS [3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin 0010: PC14 pin 0011: PD14 pin 0100: PE14 pin 0101: PF14 pin 0110: PG14 pin Other configurations are reserved.
Page 206 GD32F30x User Manual EXMC_N TIMER13 TIMER12 TIMER10 TIMER9_ TIMER8_ Reserved CTC_REMAP [1:0] Reserved _REMAP _REMAP _REMAP REMAP REMAP Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:11 CTC_REMAP [1:0] CTC remapping These bits are set and cleared by software, they control the mapping of the CTC_SYNC alternate function onto the GPIO ports .
Page 207: Io Compensation Control Register (Afio_Cpsctl)
GD32F30x User Manual and TIMER8_CH1 alternate function onto the GPIO ports 0: No remap (TIMER8_CH0 on PA2 and TIMER8_CH1 on PA3) 1: Remap (PF6) (TIMER8_CH0 on PE5 and TIMER8_CH1 on PE6) Reserved Must be kept at reset value. IO compensation control register (AFIO_CPSCTL) 8.5.16.
Page 208: Cyclic Redundancy Checks Management Unit (Crc)
GD32F30x User Manual Cyclic redundancy checks management unit (CRC) 9.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32 bit CRC code with fixed polynomial. 9.2.
Page 209: Function Overview
GD32F30x User Manual Figure 9-1. Block diagram of CRC calculation unit Data Input Input Data Register (32 bit) CRC Management Unit Fixed polynomial 0x4C11DB7 Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) 9.3. Function overview ◼...
Page 210: Register Definition
GD32F30x User Manual 9.4. Register definition CRC base address: 0x4002 3000 Data register (CRC_DATA) 9.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads.
Page 211: Control Register (Crc_Ctl)
GD32F30x User Manual These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 9.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 212: Direct Memory Access Controller (Dma)
GD32F30x User Manual Direct memory access controller (DMA) Overview 10.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention f rom the CPU, thereby f reeing up bandwidth f or other system f unctions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 213: Block Diagram
GD32F30x User Manual Block diagram 10.3. Figure 10-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 214: Table 10-1. Dma Transfer Operation
GD32F30x User Manual Table 10-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 215: Peripheral Handshake
GD32F30x User Manual Peripheral handshake 10.4.2. To ensure a well-organized and efficient data transfer, a handshake mechanism is introduced between the DMA and peripherals, including a request signal and a acknowledge signal: ◼ Request signal asserted by peripheral to DMA controller, indicating that the peripheral is ready to transmit or receive data ◼...
Page 216: Circular Mode
GD32F30x User Manual base address registers (DMA_CHxPADDR, DMA_CHxMADDR). In the increasing mode, the next address is equal to the current address plus 1 or 2 or 4, depending on the transfer data width. Circular mode 10.4.5. Circular mode is implemented to handle continue peripheral requests (for example, ADC scan mode).
Page 217: Dma Request Mapping
GD32F30x User Manual including full transfer f inish, half transfer finish, and transfer error. Each interrupt event has a dedicated flag bit in the DMA_INTF reg ister, a dedicated clear bit in the DMA_INTC register, and a dedicated enable bit in the DMA_CHxCTL register. The relationship is described in the following Table 10-2.
Page 218: Figure 10-4. Dma0 Request Mapping
GD32F30x User Manual Figure 10-4. DMA0 request mapping Hardware priority ADC0 TIMER1_CH2 high Channel 0 TIMER3_CH0 SPI0_RX USART2_TX TIMER0_CH0 Channel 1 TIMER1_UP TIMER2_CH2 SPI0_TX USART2_RX TIMER0_CH1 Channel 2 TIMER2_CH3 TIMER2_UP SPI1/I2S1_RX USART0_TX I2C1_TX TIMER0_CH3 Channel 3 TIMER0_TG TIMER0_CMT TIMER3_CH1 SPI1/I2S1_TX USART0_RX I2C1_RX TIMER0_UP...
Page 219: Figure 10-5. Dma1 Request Mapping
GD32F30x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● SPI/I2S SPI0_RX SPI0_TX SPI1/I2S1_RX SPI1/I2S1_TX ● USART USART2_TX USART2_RX USART0_TX USART0_RX USART1_RX USART1_TX ● ● ● I2C1_TX I2C1_RX I2C0_TX I2C0_RX Figure 10-5.
Page 220 GD32F30x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 ● ● ● ● SDIO SDIO...
Page 221: Register Definition
GD32F30x User Manual Register definition 10.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the f ollowing registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 10.5.1.
Page 222: Interrupt Flag Clear Register (Dma_Intc)
GD32F30x User Manual Interrupt flag clear register (DMA_INTC) 10.5.2. Address offset: 0x04 Reset value: 0x0000 0000 Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0...
Page 223 GD32F30x User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 224: Channel X Counter Register (Dma_Chxcnt)
GD32F30x User Manual Circular mode enable CMEN Software set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’.
Page 225: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F30x User Manual 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer.
Page 226 GD32F30x User Manual Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 227: Debug (Dbg)
GD32F30x User Manual Debug (DBG) Introduction 11.1. The GD32F30x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm® CoreSightTM module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm®...
Page 228: Jtag Daisy Chained Structure
GD32F30x User Manual PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware).
Page 229: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32F30x User Manual When SLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN 11.3.2.
Page 230: Dbg Registers
GD32F30x User Manual 11.4. DBG registers DEBUG base address: 0xE0042000U ID code register (DBG_ID) 11.4.1. Address: 0xE004 2000 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant Control register 0 (DBG_CTL0) 11.4.2.
Page 231 GD32F30x User Manual This bit is set and reset by software 0: no effect 1: hold the TIMER 9 counter for debug when core halted TIMER8_HOLD TIMER 8 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 8 counter for debug when core halted TIMER13_HOLD TIMER 13 hold bit...
Page 232 GD32F30x User Manual 1: hold the TIMER7 counter for debug when core halted I2C1_HOLD I2C1 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C1 SMBUS timeout for debug when core halted I2C0_HOLD I2C0 hold bit This bit is set and reset by software 0: no effect...
Page 233 GD32F30x User Manual TRACE_IOEN Trace pin allocation enable This bit is set and reset by software 0: Trace pin allocation disable 1: Trace pin allocation enable Reserved Must be kept at reset value STB_HOLD Standby mode hold register This bit is set and reset by software 0: no effect 1: At the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, a system reset generated when exit standby mode...
Page 234: Analog-To-Digital Converter (Adc)
GD32F30x User Manual Analog-to-digital converter (ADC) Overview 12.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals f rom 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment or the most significant bit alignment.
Page 235: Pins And Internal Signals
GD32F30x User Manual ◼ Module supply requirements: 2.6V to 3.6V, and typical power supply voltage is 3.3V. ◼ ≤V ≤V Channel input voltage range: V REFN REFP 12.3. Pins and internal signals Figure 12-1. ADC module block diagram shows the ADC block diagram. Table 12-1.
Page 236: Functional Overview
GD32F30x User Manual 12.4. Functional overview Figure 12-1. ADC module block diagram DMA request Trig select routine sequence Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO ADC_IN15 routine data registers SAR ADC Over sampler 6~12bit （16 bits） SENSE REFINT TOVS...
Page 237: Adc Clock
GD32F30x User Manual Set CLB=1. Wait until CLB=0. ADC clock 12.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller. ADC clock can be divided and configured by RCU controller. 12.4.3. ADC enable The ADCON bit on the ADC_CTL1 register is the enable switch of the ADC module.
Page 238: Figure 12-3. Continuous Operation Mode
GD32F30x User Manual Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset. Conf igure RSQ0 with the analog channel number. Conf igure ADC_SAMPTx register. Conf igure ETERC and ETSRC bits in the ADC_CTL1 register if in need . Set the SWRCST bit, or generate an external trigger for the routine sequence.
Page 239: Figure 12-4. Scan Operation Mode, Continuous Disable
GD32F30x User Manual Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in the routine sequence till the end of the sequence , once the corresponding software trigger or external trigger is active.
Page 240: Conversion Result Threshold Monitor Function
GD32F30x User Manual the next n channels configured in the ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set. Figure 12-6.
Page 241: Sample Time Configuration
GD32F30x User Manual Figure 12-7. 12-bit Data storage mode 6-bit resolution data alignment is different from 12-bit/10-bit/8-bit resolution data alignment, shown as Figure 12-8. 6-bit Data storage mode. Figure 12-8. 6-bit Data storage mode Routine channel data DAL=0 Routine channel data DAL=1 12.4.8.
Page 242: Dma Request
GD32F30x User Manual ETSRC[2:0] Trigger Source Trigger Type TIMER2_TRGO TIMER3_CH3 EXTI11/ TIMER7_TRGO Software trigger SWRCST Table 12-4. External trigger source for ADC2 ETSRC[2:0] Trigger Source Trigger Type TIMER2_CH0 TIMER1_CH2 TIMER0_CH2 Hardware rigger TIMER7_CH0 TIMER7_TRGO TIMER4_CH0 TIMER4_CH2 Software trigger SWRCST DMA request 12.4.10.
Page 243: Programmable Resolution (Dres)
GD32F30x User Manual for the channel. Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the internal temperature sensor output voltage(V ), and get the temperature temperature with the following equation:...
Page 244: Figure 12-11. 20-Bit To 16-Bit Result Truncation
GD32F30x User Manual Summation units can produce up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the data register.
Page 245: Adc Sync Mode
GD32F30x User Manual mpling OVSS= shift shift shift shift shift shift shift shift ratio data 0000 OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= 0001 0010 0011 0100 0101 0110 0111 1000 0x1FFE 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x001F 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF...
Page 246: Free Mode
GD32F30x User Manual Figure 12-11. ADC sync block diagram Routine Routine data registers （16 bits） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO Routine Routine data registers （16 bits） channels ADC_IN15 SENSE REFINT Syncl mode control ADC0 EXTI11 (master) Routine trigger mux Free mode 12.5.1.
Page 247: Routine Follow-Up Fast Mode
GD32F30x User Manual 2. Two channels sampled by two ADCs at the same time should be configured with the same sampling time. Figure 12-12. Routine parallel mode on 10 channels Routine follow-up fast mode 12.5.3. The routine f ollow-up fast mode is applicable to sample the same channel of two ADCs. The source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register).
Page 248: Adc Interrupts
GD32F30x User Manual Continuous mode can’t be used in this mode, because it continuously converts the routine channel. The behavior of follow-up slow mode shows in the Figure 12-14. Routine follow- up slow mode. After an EOC interrupt is generated by ADC0 (if EOCIE bit is set), we can use a 32-bit DMA, which transfers to SRAM the ADC_RDATA register containing the ADC1 converted data in the [31: 16] bits field and the ADC0 converted data in the [15: 0] bits field.
Page 249: Adc Registers
GD32F30x User Manual 12.7. ADC registers ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 3C00 Status register (ADC_STAT) 12.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved STRC...
Page 250: Control Register 0 (Adc_Ctl0)
GD32F30x User Manual Control register 0 (ADC_CTL0) 12.7.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RWDEN Reserved SYNCM[3:0] DISNUM[2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value.
Page 251: Control Register 1 (Adc_Ctl1)
GD32F30x User Manual 1: A single channel has analog watchdog function Scan mode 0: Scan operation mode disable 1: Scan operation mode enable Reserved Must be kept at reset value. WDEIE Interrupt enable for WDE 0: Interrupt disable 1: Interrupt enable EOCIE Interrupt enable for EOC 0: Interrupt disable...
Page 252 GD32F30x User Manual This register has to be accessed by word(32-bit) Reserved TSVREN SWRCST Reserved ETERC ETSRC[2:0] Reserved Reserved Reserved. Reserved RSTCLB ADCON Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 16 and 17 enable of ADC0. 0: Channel 16 and 17 of ADC0 disable 1: Channel 16 and 17 of ADC0 enable SWRCST...
Page 253: Sample Time Register 0 (Adc_Sampt0)
GD32F30x User Manual 16:12 Reserved Must be kept at reset value Data alignment 0: LSB alignment 1: MSB alignment 10:9 Reserved Must be kept at reset value. DMA request enable. 0: DMA request disable 1: DMA request enable Reserved Must be kept at reset value. RSTCLB Reset calibration This bit is set by software and cleared by hardware after the calibration registers...
Page 254: Sample Time Register 1 (Adc_Sampt1)
GD32F30x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:21 SPT17[2:0] refer to SPT10[2:0] description 20:18 SPT16[2:0] refer to SPT10[2:0] description 17:15 SPT15[2:0] refer to SPT10[2:0] description 14:12 SPT14[2:0] refer to SPT10[2:0] description 11:9 SPT13[2:0] refer to SPT10[2:0] description SPT12[2:0] refer to SPT10[2:0] description...
Page 255: Watchdog High Threshold Register (Adc_Wdht)
GD32F30x User Manual 20:18 SPT6[2:0] refer to SPT0[2:0] description 17:15 SPT5[2:0] refer to SPT0[2:0] description 14:12 SPT4[2:0] refer to SPT0[2:0] description 11:9 SPT3[2:0] refer to SPT0[2:0] description SPT2[2:0] refer to SPT0[2:0] description SPT1[2:0] refer to SPT0[2:0] description SPT0[2:0] Channel sample time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles...
Page 256: Routine Sequence Register 0 (Adc_Rsq0)
GD32F30x User Manual Reserved Reserved WDLT[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDLT[11:0] Low threshold for analog watchdog These bits define the low threshold for the analog watchdog. Routine sequence register 0 (ADC_RSQ0) 12.7.8. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 257: Routine Sequence Register 2 (Adc_Rsq2)
GD32F30x User Manual Reserved RSQ11[4:0] RSQ10[4:0] RSQ9[4:1] RSQ9[0] RSQ8[4:0] RSQ7[4:0] RSQ6[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ11[4:0] refer to RSQ0[4:0] description 24:20 RSQ10[4:0] refer to RSQ0[4:0] description 19:15 RSQ9[4:0] refer to RSQ0[4:0] description 14:10 RSQ8[4:0] refer to RSQ0[4:0] description...
Page 258: Routine Data Register (Adc_Rdata)
GD32F30x User Manual conversion in the routine sequence. Routine data register (ADC_RDATA) 12.7.11. Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) ADC1RDTR[15:0] RDATA[15:0] Bits Fields Descriptions 31:16 ADC1RDTR[15:0] ADC1 routine channel data In sync mode, these bits contain the routine data of ADC1. These bits are only used in ADC0.
Page 259 GD32F30x User Manual 11:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio(OVSR[2:0]).
Page 260 GD32F30x User Manual ensures that no conversion is in progress).
Page 261: Digital-To-Analog Converter (Dac)
GD32F30x User Manual Digital-to-analog converter (DAC) Introduction 13.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 262: Function Description
GD32F30x User Manual Figure 13-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRGO TIMER7_TRGO TIMER6_TRGO TIMER4_TRGO TIMER1_TRGO TIMER3_TRGO EXTI9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Note: The TIMER7_TRGO trigger is replaced by TIMER2_TRGO in connectivity line devices. Table 13-1.
Page 263: Dac Data Configuration
GD32F30x User Manual The output buffer, which is turned on by default, can be turned off by setting the DBOFFx bits in the DAC_CTL register. DAC data configuration 13.3.3. The 12-bit DAC holding data (DACx_DH) can be configured by writing any one of these registers (DACx_R12DH, DACx_L12DH or DACx_R8DH).
Page 264: Dac Output Calculate
GD32F30x User Manual and Triangle wave mode. The noise wave mode can be selected by the DWMx bits in the DAC_CTL register. The amplitude of the noise can be configured by the DAC noise wave bit width (DWBWx) bits in the DAC_CTL register. LFSR noise wave mode: there is a Linear Feedback Shift Register (LFSR) in the DAC control logic, it controls the LFSR noise signal which is added to the DACx_DH value.
Page 265: Dma Function
GD32F30x User Manual DMA function 13.3.8. When the external trigger is enabled, the DMA request is enabled by setting the DDMAENx bits of the DAC_CTL register. When an external hardware trigger (not a software trigger) occurs ,A DMA request will be generated by DAC. DAC concurrent conversion 13.3.9.
Page 266: Dac Registers
GD32F30x User Manual DAC registers 13.4. DAC base address: 0x4000 7400 Control register (DAC_CTL) 13.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DDMAEN1 DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 Reserved DDMAEN0 DWBW0[3:0] DWM0[1:0] DTSEL0[2:0]...
Page 267 GD32F30x User Manual 00: wave disabled 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1. 000: TIMER5 TRGO 001: TIMER2 TRGO (connectivity line devices); TIMER7 TRGO (other type devices) 010: TIMER6 TRGO 011: TIMER4 TRGO...
Page 268: Software Trigger Register (Dac_Swt)
GD32F30x User Manual 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DAC0 noise wave mode These bits specify the mode selection of the noise wave signal of DAC0 when...
Page 269: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32F30x User Manual Reserved SWTR1 SWTR0 Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled DAC0 12-bit right-aligned data holding register (DAC0_R12DH) 13.4.3.
Page 270: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32F30x User Manual DAC0_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value DAC0 8-bit right-aligned data holding register (DAC0_R8DH) 13.4.5.
Page 271: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32F30x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC1_DH[11:0] DAC1 12-bit right-aligned data These bits specify the data that is to be converted by DAC1. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) 13.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 272: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32F30x User Manual These bits specify the MSB bits of the data that is to be converted by DAC1. DAC concurrent mode 12-bit right-aligned data holding register 13.4.9. (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved...
Page 273: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32F30x User Manual 31:20 DAC1_DH[11:0] DAC1 12-bit left-aligned data These bits specify the data that is to be converted by DAC1. 19:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value.
Page 274: Dac1 Data Output Register (Dac1_Do)
GD32F30x User Manual Reserved DAC0_DO [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC0_DO [11:0] DAC0 data output These bits, which are read only, reflect the data that is being converted by DAC0. DAC1 data output register (DAC1_DO) 13.4.13.
Page 275: Watchdog Timer (Wdgt)
GD32F30x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system f ailures due to software malfunctions. There are two watchdog timer peripherals in the chip: f ree watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 276: Figure 14-1. Free Watchdog Block Diagram
GD32F30x User Manual Figure 14-1. Free watchdog block diagram The f ree watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at anytime.
Page 277 GD32F30x User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: When after the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 278: Register Definition
GD32F30x User Manual Register definition 14.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 279 GD32F30x User Manual 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 280 GD32F30x User Manual Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update. During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid. This bit is reset by hardware after the update operation of FWDGT_RLD register.
Page 281: Window Watchdog Timer (Wwdgt)
GD32F30x User Manual 14.2. Window watchdog timer (WWDGT) Overview 14.2.1. The window watchdog timer (WWDGT) is used to detect system f ailures due to software malf unctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 282: Figure 14-3. Window Watchdog Timing Diagram
GD32F30x User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the conf igured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set).
Page 283: Table 14-2. Min/Max Timeout Value At 60 Mhz
GD32F30x User Manual Table 14-2. Min/max timeout value at 60 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 68.2 μs 1 / 1 4.3ms 136.4 μs 1 / 2 8.6 ms 272.8μs 1 / 4 17.2 ms 545.6 μs 1 / 8...
Page 284: Register Definition
GD32F30x User Manual Register definition 14.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 285 GD32F30x User Manual PSC[1:0] Prescaler. The time base of the watchdog timer counter. 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4 11: (PCLK1 / 4096) / 8 WIN[6:0] The Window value. A reset occurs if the watchdog counter (CNT bits in WWDGT_CTL) is written when the value of the watchdog counter is greater than the Window value.
Page 286: Real-Time Clock(Rtc)
GD32F30x User Manual Real-time Clock(RTC) Overview 15.1. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register. That means the RTC settings and time are kept when the device resets or wakes up from Standby mode.
Page 287: Rtc Reset
GD32F30x User Manual the RTC will generate an alarm interrupt when the system time equals to the alarm time (stored in the RTC_ALRMH/L register). Figure 15-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK...
Page 288: Rtc Flag Assertion
GD32F30x User Manual bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete. The value of the LWOFF bit in the RTC_CTL register sets to ‘1’, if the write operation finished.
Page 289 GD32F30x User Manual RTC second and overflow waveform example (RTC_PSC= 3) Figure 15-3.
Page 290: Rtc Register
GD32F30x User Manual RTC Register 15.4. RTC base address: 0x4000 2800 RTC interrupt enable register(RTC_INTEN) 15.4.1. Address offset : 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions Must be kept at reset...
Page 291: Rtc Prescaler High Register (Rtc_Psch)
GD32F30x User Manual Must be kept at reset value. 31:6 Reserved LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode. 1: Enter configuration mode.
Page 292: Rtc Prescaler Low Register(Rtc_Pscl)
GD32F30x User Manual RTC prescaler value high PSC[19:16] RTC prescaler low register(RTC_PSCL) 15.4.4. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits Fields Descriptions Must be kept at reset value. 31:16 Reserved RTC prescaler value low...
Page 293: Rtc Counter High Register(Rtc_Cnth)
GD32F30x User Manual Reserved DIV[15:0] Bits Fields Descriptions Must be kept at reset value. 31:16 Reserved 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated. RTC counter high register(RTC_CNTH) 15.4.7.
Page 294: Rtc Alarm High Register(Rtc_Alrmh)
GD32F30x User Manual RTC counter value low 15:0 CNT[15:0] RTC alarm high register(RTC_ALRMH) 15.4.9. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. RTC alarm value high 15:0 ALRM[31:16]...
Page 295: Timer(Timerx)
GD32F30x User Manual Timer(TIMERx) Table 16-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1~4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, Count mode UP ONLY UP ONLY UP ONLY...
Page 296: Advanced Timer (Timerx, X=0, 7)
GD32F30x User Manual 16.1. Advanced timer (TIMERx, x=0, 7) Overview 16.1.1. The advanced timer module (Timer0&Timer7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 297: Block Diagram
GD32F30x User Manual Block diagram 16.1.3. Figure 16-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 16-1. Advanced timer block diagram...
Page 298: Function Overview
GD32F30x User Manual Function overview 16.1.4. Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is f rom module RCU.
Page 299: Figure 16-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F30x User Manual 0x1, 0x2 or 0x3. ◼ SMC1== 1’b1 (external clock mode 1). External input ETI is selected as timer clock source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 300: Figure 16-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F30x User Manual times of overflow events. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode. Whenever, if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update event.
Page 301: Figure 16-5. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F30x User Manual Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 302 GD32F30x User Manual counter behavior in different clock frequencies when TIMERx_CAR=0x99. Figure 16-6. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF)
Page 303: Figure 16-7. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F30x User Manual Figure 16-7. Timing chart of down counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF)
Page 304 GD32F30x User Manual behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 16-8. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured...
Page 305: Figure 16-9. Repetition Timechart For Center-Aligned Counter
GD32F30x User Manual generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overf low.
Page 306: Figure 16-11. Repetition Timechart For Down-Counter
GD32F30x User Manual Figure 16-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 307: Figure 16-12. Channel Input Capture Principle
GD32F30x User Manual Figure 16-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 308 GD32F30x User Manual Result: when you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by sof tware directly.
Page 309: Figure 16-13. Output-Compare Under Three Modes
GD32F30x User Manual Figure 16-13. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 310 GD32F30x User Manual Figure 16-14. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-15. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 311 GD32F30x User Manual CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 312: Table 16-2. Complementary Outputs Controlled By Parameters
GD32F30x User Manual Table 16-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP...
Page 313: Figure 16-16. Complementary Output With Dead-Time Insertion
GD32F30x User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 314: Figure 16-17. Output Behavior In Response To A Break(The Break High Active)
GD32F30x User Manual HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 315: Figure 16-18. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32F30x User Manual decoder mode. The quadrature decoder can be regarded as an external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-period value. Therefore, TIMERx_CAR register must be configured before the counter starts to count.
Page 316: Figure 16-20. Hall Sensor Is Used To Bldc Motor
GD32F30x User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; the timers can support this function. Figure 16-20. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in (Advanced/General L0 TIMER) should accept three HALL sensor signals.
Page 317: Figure 16-21. Hall Sensor Timing Between Two Timers
GD32F30x User Manual Figure 16-21. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC[2:0] in the TIMERx_SMCFG register.
Page 318: Figure 16-22. Restart Mode
GD32F30x User Manual Table 16-4. Examples of slave mode Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0] LIST SMC[2:0] If you choose the CI0FE0 or For the ITIx no f ilter and 000: ITI0 CI1FE1, configure the CHxP prescaler can be used.
Page 319: Figure 16-23. Pause Mode
GD32F30x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection Figure 16-23. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF TRGS[2:0]=3’b11 Exam3 Event mode ETP = 0 no polarity ETPSC = 1, divided by 2. The counter will change. ETFC = 0 , no f ilter start count ETIF...
Page 320: Figure 16-25. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32F30x User Manual stopped and its value held. In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value.
Page 321 GD32F30x User Manual Figure 16-26. Timer0 master/slave mode timer example TIMER0 TIMER 4 TRGS Master ITI0 TRG O Pre scaler Counter mode control TIMER 1 Master TRG O ITI1 Pre scaler Counter mode control TIMER 2 Master ITI2 TRG O Pre scaler Counter mode...
Page 322: Figure 16-27. Triggering Timer0 With Enable Signal Of Timer2
GD32F30x User Manual divided internal clock after trigger by timer2 enable output. When Timer0 receives the trigger signal its CEN bit is set and the counter counts until we disable timer0. Both counter clock frequencies are divided by 3 by the prescaler compared to TIMER_CK (f CNT_CLK = f TIMER_CK /3).
Page 323: Figure 16-28. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F30x User Manual Figure 16-28. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event.
Page 324: Timerx Registers(X=0, 7)
GD32F30x User Manual TIMERx registers(x=0, 7) 16.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS...
Page 325 GD32F30x User Manual Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable. The counter continues after update event. 1: Single pulse mode enable. The counter counts until the next update event occurs.
Page 326 GD32F30x User Manual Bits Fields Descriptions Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit ISO2 Idle state of channel 2 output Refer to ISO0 bit ISO1N Idle state of channel 1 complementary output...
Page 327 GD32F30x User Manual 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in chann el0, a TRGO trigger signal is output.
Page 328 GD32F30x User Manual SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 329 GD32F30x User Manual 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 330 GD32F30x User Manual 101: Pause mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low. 110: Event mode. A rising edge of the trigger input enables the counter. 111: External clock mode 0. The counter counts on the rising edges of the selected trigger.
Page 331 GD32F30x User Manual BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled CH1IE...
Page 332 GD32F30x User Manual CH2OF Channel 2 over capture flag Refer to CH0OF description CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 333 GD32F30x User Manual 1: Channel 0 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit)
Page 334 GD32F30x User Manual Refer to CH0G description Channel 1’s capture or compare event generation CH1G Refer to CH0G description Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware.
Page 335 GD32F30x User Manual Refer to CH0COMFEN description CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1...
Page 336 GD32F30x User Manual When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled. 0: Channel 0 output co mpare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00.
Page 337 GD32F30x User Manual The filtering capability configuration is as follows: CH0CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
Page 338 GD32F30x User Manual Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection.
Page 339 GD32F30x User Manual than TIMERx_CH2CV, and high otherwise. When counting down, O2CPRE is high when the counter is larger than TIMERx_CH2CV, and low otherwise. If configured in PWM mode, the O2CPRE level changes only when the o utput compare mode is adjusted from “Timing” mode to “PWM” mode or the comparison result changes.
Page 340 GD32F30x User Manual CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the si gnal.
Page 341 GD32F30x User Manual Reserved CH3P CH3EN CH2NP CH2NEN CH2P CH2EN CH1NP CH1NEN CH1P CH1EN CH0NP CH0NEN CH0P CH0EN Bits Fields Descriptions 15:14 Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP...
Page 342 GD32F30x User Manual 0: Channel 0 complementary output disabled 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the o utput signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 343 GD32F30x User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) PSC[15:0] Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 344 GD32F30x User Manual Bits Fields Descriptions 15:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
Page 345 GD32F30x User Manual shadow register updates every update event. Channel 2 capture/compare value register (TIMERx_CH2CV) Address offset: 0x3C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH2VAL[15:0] Bits Fields Descriptions 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 346 GD32F30x User Manual POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input (asynchronous).
Page 347 GD32F30x User Manual 10 or 11. Idle mode off-state configure When POEN bit is reset, this bit specifies the output state for the channels which has been configured in output mode. 0: When POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled.
Page 348 GD32F30x User Manual Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 15:14 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value.
Page 349 GD32F30x User Manual Bits Fields Descriptions 15:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect OUTSEL...
Page 350: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32F30x User Manual 16.2. General level0 timer (TIMERx, x=1, 2, 3, 4) Overview 16.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 351 GD32F30x User Manual conf iguration of the general level0 timer. Figure 16-29. General Level 0 timer block diagram...
Page 352: Function Overview
GD32F30x User Manual Function overview 16.2.4. Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when the SMC [2:0] == 3’b000.
Page 353: Figure 16-31. Timing Chart Of Psc Value Change From 0 To 2
GD32F30x User Manual ◼ SMC1== 1’b1(external clock mode 1). External input pin source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 354: Figure 16-32. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F30x User Manual value will be initialized to 0 and generates an update event. If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled. When an update event occurs, all the shadow registers (counter autoreload register, prescaler register) are updated.
Page 355: Figure 16-33. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F30x User Manual Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 356: Figure 16-35. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F30x User Manual Figure 16-34. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Hardware set Software clear Update interrupt flag (UPIF) Figure 16-35.
Page 357: Figure 16-36. Timing Chart Of Center-Aligned Counting Mode
GD32F30x User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting direction and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 358 GD32F30x User Manual Figure 16-36. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Input capture and output compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 359: Figure 16-37. Channel Input Capture Principle
GD32F30x User Manual Figure 16-37. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on CH0P Filter TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 360 GD32F30x User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 361: Figure 16-38. Output-Compare Under Three Modes
GD32F30x User Manual Figure 16-38. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 362 GD32F30x User Manual Figure 16-39. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-40. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 363: Table 16-5. Examples Of Slave Mode
GD32F30x User Manual CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 364: Figure 16-41. Restart Mode
GD32F30x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b00 Exam1 Restart mode For ITI0, no polarity selector For the ITI0, no filter and The counter can be can be used. ITI0 is the prescaler can be used. clear and restart when a selection.
Page 365: Figure 16-43. Event Mode
GD32F30x User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b11 Exam3 Event mode ETP = 0 no polarity change. ETPSC = 1, divided by 2. The counter will start to ETFC = 0 , no filter count when a rising ETIF trigger input.
Page 366 GD32F30x User Manual set to 1, the TIMERx counter stops.
Page 367: Timerx Registers(X=1, 2, 3, 4)
GD32F30x User Manual TIMERx registers(x=1, 2, 3, 4) 16.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE...
Page 368 GD32F30x User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode.
Page 369 GD32F30x User Manual Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 15:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 370 GD32F30x User Manual This register has to be accessed by word (32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 371 GD32F30x User Manual EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 372 GD32F30x User Manual direction depends on CI0FE0 level. 011: Quadrature decoder mode 2. The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other. 100: Restart mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input.
Page 373 GD32F30x User Manual 0: disabled 1: enabled Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value. CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled...
Page 374 GD32F30x User Manual Refer to CH0OF description CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software.
Page 375 GD32F30x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TRGG Reserved CH3G CH2G CH1G CH0G Bits Fields Descriptions 15:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 376 GD32F30x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0]...
Page 377 GD32F30x User Manual equals to the output compare register TIMERx_CH0CV. 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0.
Page 378 GD32F30x User Manual 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability.
Page 379 GD32F30x User Manual Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions...
Page 380 GD32F30x User Manual comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT. 001: Set the channel output. O2CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH2CV. 010: Clear the channel output. O2CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH2CV.
Page 381 GD32F30x User Manual Note: When CH2MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions 15:12 CH3CAPFLT[3:0] Channel 3 input capture filter control Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description...
Page 382 GD32F30x User Manual 11: The input capture occurs on every 8 channel input edges CH2MS[1:0] Channel 2 mode selection Same as output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CH3P CH3EN...
Page 383 GD32F30x User Manual [CH0P==0]: CIxFE0’s rising edge is the active signal for capture or trigger operation in slave mode. And CIxFE0 will not be inverted. [CH0P==1]: CIxFE0’s falling edge is the active signal for capture or trigger operation in slave mode. And CIxFE0 will be inverted. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 384 GD32F30x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non -zero value (such as 0xFFFF) which is larger than user expected value.
Page 385 GD32F30x User Manual Bits Fields Descriptions 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 386 GD32F30x User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved DMATC[4:0] Reserved...
Page 387 GD32F30x User Manual Configuration register (TIMERx_CFG ) Address offset: 0xFC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CHVSEL Reserved Bits Fields Descriptions 15:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 388: General Level1 Timer (Timerx, X=8, 11)
GD32F30x User Manual 16.3. General level1 timer (TIMERx, x=8, 11) Overview 16.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 389: Block Diagram
GD32F30x User Manual Block diagram 16.3.3. Figure 16-44. General level1 timer block diagram provides details on the internal conf iguration of the general level1 timer. Figure 16-44. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1...
Page 390: Function Overview
GD32F30x User Manual Function overview 16.3.4. Clock source configuration The general level1 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when SMC [2:0] == 3’b000.
Page 391: Figure 16-46. Timing Chart Of Psc Value Change From 0 To 2
GD32F30x User Manual 0x1, 0x2 or 0x3. Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale f actor can be configured f rom 1 to 65536 through the prescaler register (TIMERx_PSC). The new written prescaler value will not take effect until the next update event.
Page 392: Figure 16-47. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F30x User Manual Figure 16-47. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-48.
Page 393: Figure 16-49. Channel Input Capture Principle
GD32F30x User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ◼...
Page 394 GD32F30x User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 395: Figure 16-50. Output-Compare Under Three Modes
GD32F30x User Manual About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN. The timechart below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 16-50. Output-compare under three modes CNT_CLK ….
Page 396: Figure 16-51. Eapwm Timechart
GD32F30x User Manual mode0 (CHxCOMCTL==3’b110). And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM mode0 (CHxCOMCTL==3’b110). Figure 16-51. EAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Figure 16-52. CAPWM timechart CHxVAL PWM MODE0 Cx OUT...
Page 397: Table 16-6．Examples Of Slave Mode
GD32F30x User Manual x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. These include, keeping the original level by setting the CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, s et to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
Page 398: Figure 16-53. Restart Mode
GD32F30x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 16-53. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Exam2 Pause mode CH0P==0, Filter is bypass in this TRGS[2:0]=3’b101 no inverted. Capture will be example. The counter can be CI0FE0 sensitive to the rising edge...
Page 399: Figure 16-55. Event Mode
GD32F30x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 16-55. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 400 GD32F30x User Manual Figure 16-56. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 Timers interconnection Advanced timer (TIMERx, x=0, Ref er to Timer debug mode ® When the Cortex -M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 401: Timerx Registers(X=8, 11)
GD32F30x User Manual TIMERx registers(x=8, 11) 16.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE Reserved UPDIS...
Page 402 GD32F30x User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values . These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 403 GD32F30x User Manual 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high.
Page 404 GD32F30x User Manual 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CH1OF CH0OF Reserved TRGIF Reserved CH1IF...
Page 405 GD32F30x User Manual mode, this flag is set when a compare event occurs. If Channel0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV. 0: No Channel 0interrupt occurred 1: Channel 0 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software.
Page 406 GD32F30x User Manual bit is set, the counter is cleared. The prescaler counter is cleared at the same time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH1COM CH1COM...
Page 407 GD32F30x User Manual 000: Timing mode. The O0CPRE signal keeps stable, independent of the comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT. 001: Set the channel output. O0CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output.
Page 408 GD32F30x User Manual 00: Channel 0 is programmed as output mode 01: Channel 0 is programmed as input mode, IS0 is connected to CI0FE0 10: Channel 0 is programmed as input mode, IS0 is connected to CI1FE0 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 409 GD32F30x User Manual is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection...
Page 410 GD32F30x User Manual When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0. [CH0NP==0, CH0P==0]: CIxFE0’s rising edge is the active signal for capture or trigger operation in slave mode.
Page 411 GD32F30x User Manual The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CARL[15:0]...
Page 412 GD32F30x User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH1VAL[15:0] Bits Fields Descriptions 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 413: General Level2 Timer (Timerx, X=9, 10, 12, 13)
GD32F30x User Manual 16.4. General level2 timer (TIMERx, x=9, 10, 12, 13) Overview 16.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 414 GD32F30x User Manual conf iguration of the general level2 timer. Figure 16-57. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update...
Page 415: Function Overview
GD32F30x User Manual Function overview 16.4.4. Clock source configuration The general level2 TIMER can only being clocked by the CK_TIMER. ◼ Internal timer clock CK_TIMER which is from module RCU The general level2 TIMER has only one clock source which is the internal CK_TIMER, used to drive the counter prescaler.
Page 416: Figure 16-59. Timing Chart Of Psc Value Change From 0 To 2
GD32F30x User Manual Figure 16-59. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is def ined in the TIMERx_CAR register, in a count-up direction.
Page 417: Figure 16-60. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F30x User Manual Figure 16-60. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-61.
Page 418: Figure 16-62. Channel Input Capture Principle
GD32F30x User Manual Input capture and output compare channels The general level2 timer has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ◼...
Page 419 GD32F30x User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode ( CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 420: Figure 16-63. Output-Compare Under Three Modes
GD32F30x User Manual The timechart below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 16-63. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 421 GD32F30x User Manual Timers interconnection Advanced timer (TIMERx, x=0, Ref er to Timer debug mode ® When the Cortex -M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 422: Timerx Registers(X=9, 10, 12, 13)
GD32F30x User Manual TIMERx registers(x=9, 10, 12, 13) 16.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE...
Page 423 GD32F30x User Manual This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values . These events generate update event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event.
Page 424 GD32F30x User Manual 011: When a capture or compare pulse event occurs in chann el0, a TRGO trigger signal is output. 100: When a compare event occurs, a TRGO trigger signal is output. The compare source is from O0CPRE. 101: Reserved 110: Reserved 111: Reserved Reserved...
Page 425 GD32F30x User Manual CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved...
Page 426 GD32F30x User Manual bit is set, the counter is cleared. The prescaler counter is cleared at the same time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH0COM CH0COM...
Page 427 GD32F30x User Manual 11 and CH0MS bit-filed is 00(COMPARE MODE). CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled. 0: Channel 0 output compare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1)
Page 428 GD32F30x User Manual 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 429 GD32F30x User Manual When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10. Must be kept at reset value.
Page 430 GD32F30x User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) PSC[15:0] Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 431 GD32F30x User Manual Bits Fields Descriptions 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 432: Basic Timer (Timerx, X=5, 6)
GD32F30x User Manual 16.5. Basic timer (TIMERx, x=5, 6) Overview 16.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 433: Figure 16-65. Timing Chart Of Internal Clock Divided By 1
GD32F30x User Manual Figure 16-65. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale f actor can be configured f rom 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 434: Figure 16-67. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F30x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is def ined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up f rom 0 again. The update event is generated at each counter overflow.
Page 435: Figure 16-68. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F30x User Manual Figure 16-68. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 436 GD32F30x User Manual TIMERx registers(x=5, 6) 16.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ARSE Reserved UPDIS Bits...
Page 437 GD32F30x User Manual 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized. Counter enable 0: Counter disable 1: Counter enable The CEN bit must be set by software when timer works in external clock, pause mode and encoder mode.
Page 438 GD32F30x User Manual Reserved UPDEN Reserved UPIE Bits Fields Descriptions 15:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10...
Page 439 GD32F30x User Manual Bits Fields Descriptions 15:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared. The prescaler counter is cleared at the same time.
Page 440 GD32F30x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non -zero value (such as 0xFFFF) which is larger than user expected value...
Page 441 GD32F30x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 17.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a f lexible serial data exchange interface. Data f rames can be transferred in f ull duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK1 or PCLK2) to produce a dedicated baud rate clock for the USART transmitter and receiver.
Page 442: Table 17-1. Description Of Usart Important Pins
GD32F30x User Manual – Block mode (T=1) – Direct and inverse convention ◼ Multiprocessor communication – Enter into mute mode if address match does not occur. – Wake up from mute mode by idle frame or address match detection. ◼ Various status flags: –...
Page 443: Figure 17-1. Usart Module Block Diagram
GD32F30x User Manual Figure 17-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address Transmitter Transimit clock...
Page 444 GD32F30x User Manual STB[1:0] stop bit length (bit) usage description normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 445: Figure 17-3. Usart Transmit Procedure
GD32F30x User Manual USART_DATA register and it is set by hardware after the data is put into the transmit shift register. If a data is written to the USART_DATA register while a transmission is ongoing, it will be firstly stored in the transmit buffer, and transferred to the transmit shift register after the current transmission is done.
Page 446: Figure 17-4. Receiving A Frame Bit By Oversampling Method
GD32F30x User Manual Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. Set the baud rate in USART_BAUD. Set the REN bit in USART_CTL0. After being enabled, the receiver receives a bit stream after a valid start pulse has been detected.
Page 447: Figure 17-5. Configuration Step When Using Dma For Usart Transmission
GD32F30x User Manual If a noise error (NERR), parity error (PERR), frame error (FERR) or overrun error (ORERR) is generated during a receiving process, then NERR, PERR, FERR or ORERR will be set at same time with RBNE. If DMA is disabled, the software needs to check whether the RBNE interrupt is caused by noise error, parity error, framing error or overflow error when the RBNE interrupt occurs.
Page 448: Figure 17-6. Configuration Steps When Using Dma For Usart Reception
GD32F30x User Manual occurs if the TCIE bit in USART_CTL0 is set. When DMA is used for USART reception, DMA transfers data from the receive data buffer of the USART to the internal SRAM. The configuration steps are shown in Figure 17-6.
Page 449: Figure 17-7. Hardware Flow Control Between Two Usarts
GD32F30x User Manual Figure 17-7. Hardware flow control between two USARTs RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame.
Page 450 GD32F30x User Manual big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, software can put an USART module into a mute mode by setting the RWU bit in USART_CTL0 register.
Page 451: Figure 17-9. Break Frame Occurs During Idle State
GD32F30x User Manual asserted FERR status. Figure 17-9. Break frame occurs during idle state frame0 frame1 frame2 RX pin 1 frame time FERR USART_DATA data0 data1 00000000 data2 LBDF As shown in Figure 17-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame.
Page 452: Figure 17-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32F30x User Manual Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 17.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 453: Figure 17-14. Irda Data Modulation
GD32F30x User Manual width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block.
Page 454: Figure 17-15. Iso7816-3 Frame Format
GD32F30x User Manual bit may be configured for a receiver. Figure 17-15. ISO7816-3 frame format Character (T=0) mode Comparing to the timing in normal operation, the transmission time from transmit shift register to the TX pin is delayed by half baud clock, and the TC flag assertion time is delayed by a guard time that is configured by the GUAT[7:0] bits in USART_GP.
Page 455 GD32F30x User Manual When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. This timeout period is expressed in baud time units. The RTF bit in USART_STAT1 will be asserted, if no answer is received from the card before the expiration of this period.
Page 456: Figure 17-16. Usart Interrupt Mapping Diagram
GD32F30x User Manual Table 17-3. USART interrupt requests Enable Interrupt event Event flag Control register Control bit Transmit data buffer empty USART_CTL0 TBEIE CTS toggled flag CTSF USART_CTL2 CTSIE Transmission complete USART_CTL0 TCIE Received buff not empty RBNE USART_CTL0 RBNEIE Overrun error ORERR Idle frame...
Page 457 GD32F30x User Manual 17.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register 0 (USART_STAT0) 17.4.1. Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 458 GD32F30x User Manual 1: Transmit data buffer is empty. Transmission complete. This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
Page 459 GD32F30x User Manual registers one by one. 0: The USART does not detect a framing error. 1: The USART has detected a framing error. PERR Parity error flag This bit is set when the parity bit of a receive frame does not match the expected parity value.
Page 460 GD32F30x User Manual INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value. 15:4 INTDIV[11:0] Integer part of baud -rate divider. FRADIV[3:0] Fraction part of baud -rate divider. Control register 0 (USART_CTL0) 17.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 461 GD32F30x User Manual If this bit is set, an interrupt occurs when the PERR bit in USART_STAT0 is set. 0: Parity error interrupt is disabled . 1: Parity error interrupt is enabled . TBEIE Transmitter buffer empty interrupt enable. If this bit is set, an interrupt occurs when the TBE bit in USART_STAT0 is set. 0: Transmitter buffer empty interrupt is disabled .
Page 462 GD32F30x User Manual 1: Transmit a break frame. Control register 1 (USART_CTL1) 17.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved LMEN STB[1:0] CKEN CLEN Reserved. LBDIE LBLEN Reserved ADDR[3:0] Bits Fields Descriptions...
Page 463 GD32F30x User Manual This bit specifies the length of the CK signal in synchronous mode. 0: There are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame 1: There are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame This bit is reserved for UART3/4.
Page 464 GD32F30x User Manual This bit enables the CTS hardware flow control function. 0: CTS hardware flow control disabled. 1: CTS hardware flow control enabled . This bit is reserved for UART3/4. RTSEN RTS enable This bit enables the RTS hardware flow control function. 0: RTS hardware flow control disabled.
Page 465 GD32F30x User Manual When DMA request for reception is enabled (DENR=1), if this bit is set, an interrupt occurs when any one of the FERR, ORERR and NERR bits in USART_STAT0 is set. 0: Error interrupt disabled . 1: Error interrupt enabled . Guard time and prescaler register (USART_GP) 17.4.7.
Page 466 GD32F30x User Manual Control register 3 (USART_CTL3) 17.4.8. Address offset: 0x80 Reset value: 0x0000 0000 This register is not available for UART3/4. This register has to be accessed by word (32-bit). Reserved Reserved MSBF DINV TINV RINV Reserved EBIE RTIE SCRTNUM[2:0] RTEN Bits...
Page 467 GD32F30x User Manual RTIE Interrupt enable bit of receive timeout event. If this bit is set, an interrupt occurs when the RTF bit in USART_STAT1 is set. 0: Receive timeout interrupt is enabled. 1: Receive timeout interrupt is disabled. SCRTNUM[2:0] Smartcard auto-retry number.
Page 468 GD32F30x User Manual USART_STAT1 is written to 0, the Block length counter is reset. 23:0 RT[23:0] Receiver timeout threshold. These bits are used to specify receiver timeout value in terms of number of baud clocks. If Smartcard mode is not enabled, the RTF bit of USART_STAT1 is set if no new start bit is detected longer than RT bits time after the last received character.
Page 469 GD32F30x User Manual Receiver timeout flag. This bit is set when the RX pin is in idle state for longer than RT bits time. An interrupt occurs if the RTIE bit in USART_CTL3 is set. Software can clear this bit by writing 0 to it. 0: Receiver timeout event does not occur.
Page 470: Figure 18-1. I2C Module Block Diagram
GD32F30x User Manual Inter-integrated circuit interface (I2C) Overview 18.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard-mode, fast-mode and fast- mode-plus as well as CRC calculation and checking, SMBus (system management bus) and PMBus (power management bus).
Page 471: Table 18-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32F30x User Manual Figure 18-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register Control Registers Timing and SMBA Control Logic Status Flags DMA/ Interrupts Table 18-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 472: Figure 18-2. Data Validation
GD32F30x User Manual devices connected to the bus must have an open-drain or open-collect to perform the wired- AND function. Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in the standard-mode, up to 400 Kbit/s in the fast-mode and up to 1Mbit/s in the fast-mode-plus if the FMPEN bit in I2C_FMPCFG is set.
Page 473: Figure 18-4. Clock Synchronization
GD32F30x User Manual This is done by clock synchronization and bus arbitration. In a single master sy stem, clock synchronization and bus arbitration are unnecessary. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line causes the masters concerned to start counting their LOW period and, once a master clock has gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see Figure 18-4.
Page 474: Figure 18-6. I2C Communication Flow With 7-Bit Address
GD32F30x User Manual I2C communication flow 18.3.6. Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can be operated as either a transmitter or receiver, depending on the function of the device. An I2C slave will continue to detect addresses after a START signal on I2C bus and compare the detected address with its slave address which is programmed by software.
Page 475 GD32F30x User Manual ◼ Master Receiver. ◼ Slave Transmitter. ◼ Slave Receiver. I2C block supports all of the four I2C modes. After system reset, it works in slave mode. After sending a START signal on I2C bus, it changes into master mode. The I2C changes back to slave mode after sending a STOP signal on I2C bus.
Page 476: Figure 18-9. Programming Model For Slave Transmitting Mode (10-Bit Address Mode)
GD32F30x User Manual Figure 18-9. Programming model for slave transmitting mode (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 477: Figure 18-11. Programming Model For Master Transmitting Mode (10-Bit Address Mode)
GD32F30x User Manual As soon as the first byte is received, RBNE is set by hardware. Software can now read the first byte from I2C_DATA and RBNE is cleared as well. Any time RBNE is set, software can read a byte from I2C_DATA. After the last byte is received, RBNE is set.
Page 478 GD32F30x User Manual I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address which has been sent is header of a 10-bit address, the hardware sets ADD10SEND bit after sending the header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA.
Page 479 GD32F30x User Manual Figure 18-11. Programming model for master transmitting mode (10-bit address mode) I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends ACK Set ADD10SEND...
Page 480: Figure 18-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32F30x User Manual register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address which has been sent is header of a 10-bit address, the hardware sets ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA.
Page 481 GD32F30x User Manual address mode) Hardware I2C Line State Software Flow Action 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address Slave sends Acknowledge...
Page 482: Figure 18-13. Programming Model For Master Receiving Mode Using Solution B
GD32F30x User Manual ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1.
Page 483 GD32F30x User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 484 GD32F30x User Manual register is filled with the next data to be transmitted. When the RBNE and BTC bits are set in receiving mode, the receiver stretches the SCL line low until the data in the transfer buffer is read out. When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register.
Page 485 GD32F30x User Manual SMBus support 18.3.11. The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two- wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with power source for ON/OFF instructions.It is derived from I2C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data).
Page 486: Table18-2. Event Status Flags
GD32F30x User Manual the address and read/write bit. The polynomial used is x8+x2+x+1 (the CRC-8-ATM HEC algorithm, initialized to zero). SMBus alert The SMBus has an extra optional shared interrupt signal called SMBALERT# which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data.
Page 487 GD32F30x User Manual Error Name Description AERR No acknowledge received CRC value doesn’t match PECERR SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert...
Page 488 GD32F30x User Manual Register definition 18.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PECTRA SRESET Reserved SALT...
Page 489 GD32F30x User Manual byte 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte ACKEN ACK enable This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent...
Page 490 GD32F30x User Manual 1: SMBus mode I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit) Reserved Reserved DMALST DMAON...
Page 491 GD32F30x User Manual Reserved Must be kept at reset value. I2CCLK[6:0] I2C peripheral clock frequency I2CCLK[6:0]should be the frequency of input APB1 clock in MHz which is at least 0d – 1d: Not allowed 2d – 60d: 2 MHz~60MHz 61d – 127d: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 492 GD32F30x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual -Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled...
Page 493 GD32F30x User Manual LOSTAR ADD10S ADDSEN SMBALT SMBTO Reserved PECERR OUERR AERR BERR RBNE Reserved STPDET SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode)
Page 494 GD32F30x User Manual 0: No bus error 1: A bus error detected I2C_DATA is empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail).
Page 495 GD32F30x User Manual 0: In slave mode, no address is received or the received address does not match witih its own address. In master mode, no address is sent or address has been sent but not received the ACK from slave. 1: In slave mode, address is received and matches witih its own address.
Page 496 GD32F30x User Manual This bit is cleared by hardware after a STOP or a START signal or I2CEN=0. 0: No general call address (0x00) received 1: General call address (0x00) received Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver.
Page 497 GD32F30x User Manual 13:12 Reserved Must be kept the reset value 11:0 CLKC[11:0] I2C clock control in master mode In standard speed mode: T =CLKC* T high PCLK1 In fast speed mode or fast mode plus, if DTCY=0: =CLKC* T =2*CLKC*T high PCLK1...
Page 498 GD32F30x User Manual Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. FMPEN Fast mode plus enable The I2C device supports up to 1MHz when this bit is set. 0: Fast mode plus disabled 1: Fast mode plus enabled...
Page 499 GD32F30x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 19.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 500: Figure 19-1. Block Diagram Of Spi
GD32F30x User Manual SPI function overview 19.3. SPI block diagram 19.3.1. Figure 19-1. Block diagram of SPI SYSCLK MOSI TXBuffer MISO RX Buffer SPI signal description 19.3.2. Normal configuration (Not Quad-SPI Mode) Table 19-1. SPI signal description Pin Name Direction Description Master: SPI Clock Output I / O...
Page 501: Figure 19-2. Spi Timing Diagram In Normal Mode
GD32F30x User Manual application. Slave in Hardware NSS Mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0). Quad-SPI mode can only work at master mode.
Page 502: Figure 19-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32F30x User Manual Figure 19-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample MOSI D1[4] D0[4] D0[0] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D1[7] D0[7] D0[3] D1[3] In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits.
Page 503: Table 19-4. Nss Function In Master Mode
GD32F30x User Manual software NSS mode) goes low, the SPI automatically enters to slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). NSS stays high after SPI is enabled and goes low when transmission or reception process begins.
Page 504 GD32F30x User Manual Mode Description Register Configuration Data Pin Usage BDEN = 0 BDOEN: Don’t care MSTMOD = 1 Master Reception with RO = 1 MOSI: Not used unidirectional connection BDEN = 0 MISO: Reception BDOEN: Don’t care MSTMOD = 1 Master Transmission with RO = 0 MOSI: Transmission...
Page 505: Figure 19-4. A Typical Full-Duplex Connection
GD32F30x User Manual Figure 19-4. A typical Full-duplex connection Slave Master MISO MISO MOSI MOSI Figure 19-5. A typical simplex connection (Master: Receive, Slave: Transmit) Figure 19-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Figure 19-7. A typical bidirectional connection MISO MISO MOSI...
Page 506 GD32F30x User Manual SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 507: Figure 19-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32F30x User Manual frame, while in full-duplex master mode (MFD), hardware only receives the next data frame when the transmit buffer is not empty. SPI operation sequence in different modes (Not Quad -SPI, TI mode or NSSP mode) In full-duplex mode, either MFD or SFD, application should monitor the RBNE and TBE flags and follow the sequences described above.
Page 508: Figure 19-9. Timing Diagram Of Ti Master Mode With Continuous Transfer
GD32F30x User Manual Figure 19-9. Timing diagram of TI master mode with continuous transfer sample MOSI D[7] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] D[6] D[5] D[4] D[3] D[2] D[1] D[0] D[1] D[0] MISO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]...
Page 509: Figure 19-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32F30x User Manual mode, and frame format should follow the normal SPI protocol, and set the data capture edge to first clock transition. In summary: NSSP = 1; MSTMOD = 1; CKPH = 0; When active, a pluse duration of least 1 SCK clock priod is inserted between succ essive data frames depending on internal data transmit buffer status, multiple SCK clock cycle interval is possible if the transfer buffer stays empty.
Page 510: Figure 19-12. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32F30x User Manual Figure 19-12. Timing diagram of quad write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[0] D0[4] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 511: Figure 19-13. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32F30x User Manual Figure 19-13. Timing diagram of quad read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7]...
Page 512 GD32F30x User Manual Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that, TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared. DMA function 19.3.6.
Page 513: Table 19-6. Spi Interrupt Requests
GD32F30x User Manual This bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register. ◼ SPI Transmitting On-Going flag (TRANS) TRANS is a status flag to indicate whether the transfer is on-going or not.
Page 514: Figure 19-14. Block Diagram Of I2S
GD32F30x User Manual Interrupt Flag Description Clear Method Enable bit CRCERR CRC error Write 0 to CRCERR bit FERR TI Mode Format Error Write 0 to FERR bit I2S function overview 19.4. I2S block diagram 19.4.1. Figure 19-14. Block diagram of I2S SYSCLK I2S_MCK SPI_SCK /...
Page 515: Figure 19-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F30x User Manual I2S audio standards 19.4.3. The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time-multiplexed on two channels (the left channel and the right channel).
Page 516: Figure 19-17. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32F30x User Manual Figure 19-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 19-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) When the packet type is 32-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 517: Figure 19-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F30x User Manual Figure 19-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 19-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete a frame.
Page 518: Figure 19-26. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F30x User Manual Figure 19-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 19-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) 24-bit data 8-bit 0 Figure 19-29.
Page 519: Figure 19-31. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F30x User Manual Figure 19-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 520: Figure 19-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F30x User Manual synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register. The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard. The timing diagrams for each configuration of the short frame synchronization mode are shown below.
Page 521: Figure19-40. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32F30x User Manual Figure19-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 19-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 19-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 16-bit data...
Page 522: Figure 19-46. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F30x User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure 19-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 19-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 24-bit data 8-bit 0 Figure 19-48.
Page 523: Figure 19-51. Block Diagram Of I2S Clock Generator
GD32F30x User Manual (DTLEN=00, CHLEN=1, CKPL=1) I2S clock 19.4.4. Figure 19-51. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 19-51. Block diagram of I2S clock generator. The I2S interf ace clocks are configured by the DIV bits, the OF bit, the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register.
Page 524: Figure 19-52. I2S Initialization Sequence
GD32F30x User Manual Table 19-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) Operation 19.4.5.
Page 525 GD32F30x User Manual Figure 19-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 526 GD32F30x User Manual and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmit buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 527: Figure 19-53. I2S Master Reception Disabling Sequence
GD32F30x User Manual Figure 19-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTDSEL !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 528 GD32F30x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The difference between them is described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 529: Table 19-10. I2S Interrupt
GD32F30x User Manual In the slave transmit mode, when the valid SCK signal starts transmitting, if the transmit buffer is empty, TXURERR will be set. ◼ Reception Overrun Error Flag (RXORERR) This condition occurs when the receive buffer is full and a newly incoming data has been completely received.
Page 530 GD32F30x User Manual Register definition 19.5. SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 19.5.1. Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word (32-bit) This register has no meaning in I2S mode.
Page 531 GD32F30x User Manual In full-duplex or transmit-only mode, set this bit after the last data is written to SPI_DATA register. In receive only mode, set this bit after the sec ond last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer.
Page 532 GD32F30x User Manual CKPH Clock phase selection 0: Capture the first data at the first clock transition 1: Capture the first data at the second clock transition Control register 1 (SPI_CTL1) 19.5.2. Address offset: 0x04 Reset value: 0x0000 This register has to be accessed by word (32-bit) Reserved Reserved TBEIE...
Page 533 GD32F30x User Manual If the NSS pin is configured as input, the NSS pin should be pulled high in master mode, and this bit has no effect. DMATEN Transmit buffer DMA enable 0: Transmit buffer DMA is disabled 1: Transmit buffer DMA is enabled. When the TBE bit in SPI_STAT is set, it will generate a DMA request at corresponding DMA channel.
Page 534 GD32F30x User Manual 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register. CONFERR SPI configuration error bit 0: No configuration fault occurs 1: Configuration fault occurred.
Page 535 GD32F30x User Manual Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardware has two buffers, including transmit buffer and receive buffer. Write data to SPI_DATA will save the data to transmit buffer and read data from SPI_DATA will get the data from receive buffer.
Page 536 GD32F30x User Manual Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC register When the CRCERRN bit of SPI_CTL0 is set, the hardware computes the CRC value of the received bytes and saves them in RCR register.
Page 537 GD32F30x User Manual value in TCRC [7:0]. When the Data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC [15:0]. The hardware computes the CRC value after each transmitted bit, when the TRANS is set, a read to this register could return an intermediate value.
Page 538 GD32F30x User Manual This bit has a meaning only when PCM standard is used. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. Reserved Must be kept at reset value. I2SSTD[1:0] I2S standard selection 00: I2S Phillips standard 01: MSB justified standard...
Page 539 GD32F30x User Manual Reserved MCKOEN DIV[7:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: I2S_MCK output is disabled 1: I2S_MCK output is enabled This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode.
Page 540 GD32F30x User Manual 0: SPI is in quad wire write mode 1: SPI is in quad wire read mode This bit should be only be configured when SPI is not busy (TRANS bit cleared) This bit is only available in SPI0. Quad-SPI mode enable QMOD 0: SPI is in single wire mode...
Page 541 GD32F30x User Manual Note: SDIO supports only one SD, SD I/O, MMC4.2 card or CE-ATA device at any one time and a stack of MMC 4.1 or previous. 20.3. SDIO bus topology Af ter a power-on reset, the host must initialize the card by a special message-based bus protocol.
Page 542: Figure 20-1. Sdio "No Response" And "No Data" Operations
GD32F30x User Manual blocks. Figure 20-1. SDIO “no response” and “no data” operations Note that the Multiple Block operation mode is faster than Single Block operation. A multiple block transmission is terminated when a stop command follows on the CMD line. Data transfer can be configured by the host to use single or multiple data lines.
Page 543: Figure 20-5. Sdio Sequential Write Operation
GD32F30x User Manual sequential write operation are the stream read and write operation. Figure 20-4. SDIO sequential read operation SDIO_CMD Command Response Command Response Host to Device Device to Host Host to Device Device to Host SDIO_DAT DATA STREAM Device to Host Data Read operation Data stop operation Figure 20-5.
Page 544: Figure 20-6. Sdio Block Diagram
GD32F30x User Manual Figure 20-6. SDIO block diagram SDIO controller SDIO adapter AHB interface control unit SDIO_CLK interrupt DMA r equest comm and SDIO_CMD unit registers AHB bus data unit SDIO_DAT[7:0] FIFO HCLK SDIOCLK SDIO adapter 20.4.1. The SDIO adapter contains control unit, command unit and data unit, and generates signals to cards.
Page 545: Table 20-1. Sdio I/O Definitions
GD32F30x User Manual to the 8-bit mode the card disconnects the internal pull-ups of lines DAT1, DAT2 and DAT4- DAT7. Table 20-1. SDIO I/O definitions Pin function Direction Description SDIO_CLK SD/SD I/O /MMC clock SDIO_CMD Command input/output SDIO_DAT[7:0] Data input/output for data lines DAT[7:0] The SDIO adapter is an interface to SD, SD I/O, MMC and CE-ATA.
Page 546 GD32F30x User Manual → 1.CSM enabled and WAITDEND enabled CS_Pend → 2.CSM enabled and WAITDEND disabled CS_Send → 3.CSM disabled CS_Idle Note: The state machine remains in the Idle state for at least eight SDIO_CLK periods to meet the N and N timing constraints.
Page 547 GD32F30x User Manual SDIO_DAT[7:0] signals when 8-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b10), use SDIO_DAT[3:0] signals when 4-bits data width (BUSMODE bits in SDIO_CLKCTL register is 0b01), or SDIO_DAT[0] signal when 1-bit data width (BUSMODE bits in SDIO_CLKCTL register is 0b00).
Page 548 GD32F30x User Manual → 3.Data timeout reached DS_Idle → 4.Receives a start bit before timeout DS_Receive Note: The command timeout programmed in the data timer register (SDIO_DATATO). DS_Receive Receive data from the card and write it to the data FIFO. →...
Page 549 GD32F30x User Manual with 1 (SDIO card host waits for a short response); CSMEN with ‘1’ (enable to send a command). Other fields are their reset value. When the CMDRECV flag is set, program the SDIO data control register (SDIO_DATACTL): DATAEN with 1 (enable to send data);...
Page 550 GD32F30x User Manual CID register: The Card Identification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual Read/Write (RW) card shall have a unique identification number. The host can use CMD2 and CMD10 to get the content of this register.
Page 551: Figure 20-7. Command Token Format
GD32F30x User Manual ◼ Broadcast commands with response (bcr) response from all cards simultaneously ◼ Addressed (point-to-point) commands (ac) no data transfer on DAT ◼ Addressed (point-to-point) data transfer commands (adtc) data transfer on DAT Command format All commands have a fixed code length of 48 bits, as show in Figure 20-7.
Page 552: Table 20-3. Card Command Classes (Cccs)
GD32F30x User Manual For CE-ATA device, the device shall support the MMC commands required to achieve the transfer state during device initialization. Other interface configuration settings, such as bus width, may require additional MMC commands also be supported. See the MMC reference. CE-ATA makes use of the following MMC commands: CMD0 - GO_IDLE_STATE, CMD12 - STOP_TRANSMISSION, CMD39 - FAST_IO, CMD60 - RW_MULTIPLE_REGISTER, CMD61 - RW_MULTIPLE_BLOCK.
Page 553 GD32F30x User Manual CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC.CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card.
Page 554: Table 20-4. Basic Commands (Class 0)
GD32F30x User Manual Table 20-4. Basic commands (class 0) Response type argument Abbreviation Description index format CMD0 [31:0] stuff bits GO_IDLE_STATE Resets all cards to idle state Asks the card, in idle state, to [31:0] SEND_OP_CON send its Operating Conditions CMD1 without busy Register...
Page 555: Table 20-5. Block-Oriented Read Commands (Class 2)
GD32F30x User Manual For MMC only. The card sends CMD8 adtc [31:0] stuff bits SEND_EXT_CSD its EXT_CSD register as a block of data. Addressed card sends its card - [31:16] RCA CMD9 SEND_CSD specific data (CSD) on the CMD [15:0] stuff bits line.
Page 556: Table 20-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32F30x User Manual cases, if block length is set larger than 512Bytes, the card sets the BLOCK_LEN_ERROR bit. In the case of a Standard Capacity SD and MMC, this command reads a block of the size selected [31:0] data READ_SINGLE_B CMD17 adtc SET_BLOCKLEN command.
Page 557: Table 20-8. Erase Commands (Class 5)
GD32F30x User Manual Response type argument Abbreviation Description index format Defines the number of blocks which are going to be transferred [31:16] set to 0 in the immediately succeeding SET_BLOCK_ CMD23 [15:0] number multiple block read or write COUNT of blocks command.
Page 558: Table 20-9. Block Oriented Write Protection Commands (Class 6)
GD32F30x User Manual index format [31:0] data ERASE_WR_BLK Sets the address of the first write CMD32 address _START block to be erased.(SD) Sets the address of the last write [31:0] data ERASE_WR_BLK CMD33 block of the continuous range to address _END be erased.(SD) Sets the address of the first erase...
Page 559: Table 20-10. Lock Card (Class 7)
GD32F30x User Manual Note: 1. High Capacity SD Memory Card does not support these three commands. Table 20-10. Lock card (class 7) Response type argument Abbreviation Description index format See description in Table 20-5. [31:0] block CMD16 SET_BLOCK_LEN Block-Oriented read length commands (class Used to set/reset the password...
Page 560: Table 20-12. I/O Mode Commands (Class 9)
GD32F30x User Manual Response type argument Abbreviation Description index format data block from the card for general purpose/application specific command. The host sets RD/WR=1 for reading data from the card and sets to 0 for writing data to the card. [31] WR [23:18] Address R1(read)/...
Page 561: Table 20-13. Switch Function Commands (Class 10)
GD32F30x User Manual Response type argument Abbreviation Description index format [27] RAW Flag 128K of register space in any [26] Stuff Bits function, including the [25:9] Register common I/O area (CIA). This Address command reads or writes 1 [8] Stuff Bits byte using only...
Page 562: Figure 20-8. Response Token Format
GD32F30x User Manual [7:4] function group 2 for command system [3:0] function group 1 for access mode Responses 20.5.3. All responses are sent on the CMD line. The response transmission always starts with the left bit of the bit string corresponding to the response code word. The code length depends on the response type.
Page 563: Table 20-14. Response R1
GD32F30x User Manual terminated by the end bit (always 1). R1 (normal response command) Code length is 48 bits. The bits 45:40 indicate the index of the command to be responded to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits.
Page 564: Table 20-16. Response R3
GD32F30x User Manual Table 20-16. Response R3 Bit position [45:40] [39:8] [7:1] Width ‘0’ ‘0’ ‘111111’ ‘1111111’ ‘1’ Value transmission description start bit reserved reserved end bit register R4 (Fast I/O) For MMC only. Code length 48 is bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its contents.
Page 565: Table 20-20. Response R5 For Sd I/O
GD32F30x User Manual [31:16] [15:0] Not defined. start transmission description CMD40 winning card or of May be used for IRQ CRC7 the host data For SD I/O only. The SDIO card's response to CMD52 and CMD53 is R5. If the communication between the card and host is in the 1-bit or 4-bit SD mode, the response shall be in a 48-bit response (R5).
Page 566: Figure 20-9. 1-Bit Data Bus Width
GD32F30x User Manual bit mode is optional. Although using 1-bit mode, DAT3 also need to notify card current working mode is SDIO or SPI, when card reset and initialize. 1-bit data packet format After card reset and initialize, only DAT0 pin is used to transfer data. And other pin can be used freely.
Page 567: Table 20-23. Card Status
GD32F30x User Manual Two status fields of the card 20.5.5. The SD Memory supports two status fields and others just support the first one: Card Status: Error and state information of a executed command, indicated in the response SD Status: Extended status field of 512 bits that supports special features of the SD Memory Card and future Application-Specific features.
Page 568 GD32F30x User Manual ’0’= no error BLOCK_LEN_ERROR The transferred block length is ’1’= error not allowed for this card, or the number of transferred bytes does not match the block length. ’0’= no error ERASE_SEQ_ERROR An error in the sequence of ’1’= error erase commands occurred.
Page 569 GD32F30x User Manual bits was made. ’0’= not protected WP_ERASE_SKIP Set when only partial address ’1’= protected space was erased due to existing write protected blocks or the temporary or permanent write protected card erased. ’0’= enabled CARD_ECC_DISABLE command been ’1’= disabled executed without using the internal ECC.
Page 570: Table 20-24. Sd Status
GD32F30x User Manual [1:0] Reserved for manufacturer test mode. Note: 18, 17, 7 bits are only for MMC. 14, 3 bits are only for SD memory. SD status register The SD Status contains status bits that are related to the SD Memory Card proprietary features and may be used for future application-specific usage.
Page 571 GD32F30x User Manual Bits Identifier Type Value Description Clear Condition [431: AU_SIZE Size of AU (See below) 428] [427: reserved 424] [423: ERASE_SIZE Number of AUs to (See below) 408] be erased at a time [407: ERASE_TIMEOUT Timeout value for (See below) 402] erasing...
Page 572: Table 20-25. Performance Move Field
GD32F30x User Manual 05h–FFh: Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm and the value can be set by 1 [MB/sec] step. If the card does not move useing RUs, Pm should be considered as infinity. Setting to FFh means infinity. The minimum value of Pm is defined in Table 20-25.
Page 573: Table 20-28. Erase Size Field
GD32F30x User Manual Size ERASE_SIZE This 16-bit field indicates N . When N of AUs are erased, the timeout value is ERASE ERASE specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine proper number of AUs to be erased in one operation so that the host can indicate progress of erase operation.
Page 574 GD32F30x User Manual 1 [sec] 2 [sec] 3 [sec] 20.6. Programming sequence Card identification 20.6.1. The host will be in card identification mode after reset and while it is looking for new cards on the bus. While in card identification mode the host resets all the cards, validates operation voltage range, identifies cards and asks them to publish Relative Card Address (RCA).
Page 575 GD32F30x User Manual If the card cannot operate on the supplied voltage, it returns no response and stays in idle state. It is mandatory to issue CMD8 prior to ACMD41 to initialize SDHC Card. Receipt of CMD8 makes the cards realize that the host supports the Physical Layer Version 2.00 and the card can enable new functions.
Page 576 GD32F30x User Manual and the SDIO_CMDAGMT register with appropriate parameters. Using these two registers, the host forms the command and sends it to the command bus. The host reflects the errors in the command response through the error bits of the SDIO_STAT register. When a response is received the host sets the CMDRECV (CRC check passed) or CCRCERR (CRC check error) bit in the SDIO_STAT register.
Page 577 GD32F30x User Manual 1. Write the data size in bytes in the SDIO_DATALEN register. 2. Write the block size in bytes (BLKSZ) in the SDIO_DATACTL register; the host sends data in blocks of size BLKSZ. 3. Program SDIO_CMDAGMT register with the data address to which data should be written. 4.
Page 578 GD32F30x User Manual 1. Write the data size in bytes in the SDIO_DATALEN register. 2. Write the block size in bytes (BLKSZ) in the SDIO_DATACTL register. The host expects data from the card in blocks of size BLKSZ each. 3. Program the SDIO_CMDAGMT register with the data address of the beginning of a data read.
Page 579 GD32F30x User Manual WRITE_BL_LEN: Max write data block length. NSAC: Data read access-time 2 in CLK cycles. TAAC: Data read access-time 1. R2W_FACTOR: Write speed factor. All the parameters are defined in CSD register. If the host attempts to use a higher frequency, the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command.
Page 580 GD32F30x User Manual the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command. As the host sends CMD12, the card will respond with the RXORE bit set and return to Transfer state Erase 20.6.6.
Page 581 GD32F30x User Manual BUS_WIDTH byte is 0x00. If the host tries to write an invalid value, the BUS_WIDTH byte is not changed and the SWITCH_ERROR bit is set. This register is write only. For SD memory, using SET_BUS_WIDTH command (ACMD6) to change the bus width. The default bus width after power up or GO_IDLE_STATE command (CMD0) is 1 bit.
Page 582: Table 20-31. Lock Card Data Structure
GD32F30x User Manual Similar to the existing CSD register write commands, the lock/unlock command is available in "transfer state" only. This means that it does not include an address argument and the card shall be selected before using it. The card lock/unlock command has the structure and bus transaction type of a regular single block write command.
Page 583 GD32F30x User Manual password length internally by subtracting the old password length from PWDS_LEN field. ⚫ In the case that the sent old password is not correct (not equal in size and content), then the LOCK_UNLOCK_FAILED error bit will be set in the status register and the old password does not change.
Page 584: Figure 20-12. Read Wait Control By Stopping Sdio_Clk
GD32F30x User Manual 20.7. Specific operations SD I/O specific operations 20.7.1. The SD I/O only card and SD I/O combo card support these specific operations: Read Wait operation Suspend/resume operation Interrupts The SD I/O supports these operations only if the SDIO_DATACTL[11] bit is set, except for read suspend that does not need specific hardware implementation.
Page 585: Figure 20-13. Read Wait Operation Using Sdio_Dat[2]
GD32F30x User Manual Figure 20-13. Read wait operation using SDIO_DAT[2] We can start the Read Wait interval before the data block is received: when the data unit is enabled (SDIO_DATACTL[0] bit set), the SD I/O specific operation is enabled (SDIO_DATACTL[11] bit set), Read Wait starts (SDIO_DATACTL[10] = 0 and SDIO_DATACTL[8] = 1) and data direction is from card to SD I/O (SDIO_DATACTL[1] = 1), the DSM directly moves from Idle to Read Wait.
Page 586: Figure 20-15. Read Interrupt Cycle Timing
GD32F30x User Manual completed, the resume is issued to function, causing the data transfer to resume (DF=1). Figure 20-14. Function2 read cycle inserted during function1 multiple read cycle When the host sends data to the card, the host can suspend the write operation. The SDIO_CMDCTL[11] bit is set and indicates to the CSM that the current command is a suspend command.
Page 587: Figure 20-16. Write Interrupt Cycle Timing
GD32F30x User Manual Figure 20-16. Write interrupt cycle timing When transferring multiple blocks of data in the 4-bit SD mode, a special definition of the interrupt period is required. In order to allow the highest speed of communication, the interrupt period is limited to a 2-clock interrupt period.
Page 588: Figure 20-19. The Operation For Command Completion Disable Signal
GD32F30x User Manual Command completion signal CE-ATA def ines a command completion signal that the device uses to notify the host upon normal ATA command completion or when ATA command termination has occurred due to an error condition the device has encountered. If the ‘enable CMD completion’...
Page 589 GD32F30x User Manual 20.8. SDIO registers SDIO base address: 0x4001 8000 Power control register (SDIO_PWRCTL) 20.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value PWRCTL[1:0] SDIO power control bits.
Page 590 GD32F30x User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division between the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL 30:15 Reserved Must be kept at reset value HWCLKEN Hardware Clock Control enable bit If this bit is set, hardware controls the SDIO_CLK on/off depending on the system...
Page 591 GD32F30x User Manual Command argument register (SDIO_CMDAGMT) 20.8.3. Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits...
Page 592 GD32F30x User Manual NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used when CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
Page 593: Table 20-32. Sdio_Respx Register At Different Response Type
GD32F30x User Manual Command index response register (SDIO_RSPCMDIDX) 20.8.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RSPCMDIDX[5:0] Last response command index Read-only bits field.
Page 594 GD32F30x User Manual Register Short response Long response SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 Data timeout register (SDIO_DATATO) 20.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits...
Page 595 GD32F30x User Manual starts, the data counter loads this register and starts decrement. If block data transfer selected, the content of this register must be a multiple of the block Note: size (ref er to SDIO_DATACTL). The data timer register and the data length register must be updated before being written to the data control register when need a data transfer.
Page 596 GD32F30x User Manual 0101: block size = 2 = 32 bytes 0110: block size = 2 = 64 bytes 0111: block size = 2 = 128 bytes 1000: block size = 2 = 256 bytes 1001: block size = 2 = 512 bytes 1010: block size = 2 = 1024 bytes...
Page 597 GD32F30x User Manual Bits Fields Descriptions 31:25 Reserved Must be kept at reset value 24:0 DATACNT[24:0] Data count value Read-only bits field. When these bits are read, the number of remaining data bytes to be transferred is returned. Status register (SDIO_STAT) 20.8.11.
Page 598 GD32F30x User Manual Transmit FIFO is full Receive FIFO is half full: at least 8 words can be read in the FIFO Transmit FIFO is half empty: at least 8 words can be written into the FIFO RXRUN Data reception in progress TXRUN Data transmission in progress CMDRUN...
Page 599 GD32F30x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag. 21:11 Reserved Must be kept at reset value...
Page 600 GD32F30x User Manual ATAENDI SDIOINTI RXDTVA TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE CMDRUN DTBLKE CMDSEN CMDREC DTTMOU CMDTMO DTCRCE CCRCER RFHIE TFHIE RXRUNIE TXRUNIE STBITEIE DTENDIE RXOREIE TXUREIE NDIE UTIE RRIE Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDIE CE-ATA command completion signal received interrupt enable Write 1 to this bit to enable the interrupt.
Page 601 GD32F30x User Manual Write 1 to this bit to enable the interrupt. STBITEIE Start bit error interrupt enable Write 1 to this bit to enable the interrupt. DTENDIE Data end interrupt enable Write 1 to this bit to enable the interrupt. CMDSENDIE Command sent interrupt enable Write 1 to this bit to enable the interrupt.
Page 602 GD32F30x User Manual These bits define the remaining number words to be written or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is word-aligned or SDIO_DATALEN[24:2]+1 if SDIO_DATALEN is not word -aligned) when DATAEN is set, and start count decrement when a word write to or read from the FIFO.
Page 603 GD32F30x User Manual External memory controller (EXMC) 21.1. Overview The external memory controller EXMC, is used as a translator for MCU to access a variety of external memory. By configuring the related registers, it can automatically convert AMBA memory access protocol into a specific memory access protocol, such as SRAM, ROM, NOR Flash, NAND Flash and PC Card.
Page 604: Figure 21-1. The Exmc Block Diagram
GD32F30x User Manual Figure 21-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NAND-Flash/PC Card NOR-Flash/PSRAM Controller Controller NOR/PSRAM Shared PSRAM PC Card NAND NOR/PSRAM Pins /NAND Pins Pins Pins Pins Shared Pin Basic regulation of EXMC access...
Page 605: Figure 21-2. Exmc Memory Banks
GD32F30x User Manual External device address mapping 21.3.3. Figure 21-2. EXMC memory banks Address Banks Supported memory type 0x6000 0000 NOR/PSRAM 0x6FFF FFFF 0x7000 0000 0x7FFF FFFF NAND 0x8000 0000 0x8FFF FFFF 0x9000 0000 PC Card 0x9FFF FFFF EXMC access space is divided into multiple banks. Each bank is 256 Mbytes. The f irst bank (Bank0) is f urther divided into f our regions, and each region is 64 Mbytes.
Page 606 GD32F30x User Manual Figure 21-3. Four regions of bank0 address mapping HADDR[27:26] Address Regions Supported memory type 0x60000000 NOR/PSRAM Region0 0x63FF FFFF 0x64000000 Region1 NOR/PSRAM 0x67FF FFFF 0x68000000 Region2 NOR/PSRAM 0x6BFF FFFF 0x6C000000 NOR/PSRAM Region3 0x6FFF FFFF HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency.
Page 607: Figure 21-4. Nand/Pc Card Address Mapping
GD32F30x User Manual Figure 21-4. NAND/PC Card address mapping EXMC Memory Memory Space Address Bank 0x7000_0000 Common Memory Space 0x73FF_FFFF Bank1 0x7800_0000 Attribute Memory Space 0x7BFF_FFFF 0x8000_0000 Common Memory Space 0x83FF_FFFF Bank2 0x8800_0000 Attribute Memory Space 0x8BFF_FFFF 0x9000_0000 Common Memory Space 0x93FF_FFFF 0x9800_0000...
Page 608: Table 21-1. Nor Flash Interface Signals Description
GD32F30x User Manual HADDR [17:16] bits are used to select one of the three areas. – When HADDR [17:16] = 00, the data area is selected. – When HADDR [17:16] = 01, the command area is selected. – When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as f ollows.
Page 609: Table 21-2. Psram Non-Muxed Signal Description
GD32F30x User Manual EXMC Pin Direction Mode Functional description (muxed) Async/Sync Input/output Data bus (non-muxed) Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal EXMC_NL(NADV) Output Async/Sync Address valid Table 21-2.
Page 610: Table 21-4. Nor / Psram Controller Timing Parameters
GD32F30x User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Use of byte lanes Async EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync Sync Async...
Page 611: Table 21-5. Exmc_Timing Models
GD32F30x User Manual Parameter Function Access mode Unit DSET Data setup time Async HCLK AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 21-5. EXMC_timing models Timing Extend Write timing Read timing Mode description model mode parameter parameter DSET...
Page 612: Figure 21-6. Mode 1 Read Access
GD32F30x User Manual Figure 21-6. Mode 1 read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK) Figure 21-7.
Page 613: Figure 21-8. Mode A Read Access
GD32F30x User Manual Bit Position Bit Name Reference Setting Value NREN No effect Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 0x0000 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT...
Page 614: Figure 21-9. Mode A Write Access
GD32F30x User Manual Figure 21-9. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The different between mode A and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode A write timing configuration is independent of its read configuration.
Page 615: Figure 21-10. Mode 2/B Read Access
GD32F30x User Manual Bit Position Bit Name Reference Setting Value Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30 Reserved...
Page 616: Figure 21-11. Mode 2 Write Access
GD32F30x User Manual Figure 21-11. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET+1 HCLK) (DSET HCLK) Figure 21-12. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 617: Figure 21-13. Mode C Read Access
GD32F30x User Manual Bit Position Bit Name Reference Setting Value NREN Depends on memory NRTP 0x2，NOR Flash NRMUX NRBKEN EXMC_SNTCFGx(Read and write in mode 2,read in mode B) 31-30 Reserved 0x0000 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to...
Page 618: Figure 21-14. Mode C Write Access
GD32F30x User Manual Figure 21-14. Mode C write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The different between mode C and mode 1 write timing is that read/write timing is specified by the same set of timing conf iguration, while mode C write timing conf iguration is independent of its read configuration.
Page 619: Figure 21-15. Mode D Read Access
GD32F30x User Manual Bit Position Bit Name Reference Setting Value Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28...
Page 620: Figure 21-16. Mode D Write Access
GD32F30x User Manual Figure 21-16. Mode D write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WAHLD+1 HCLK) (WDSET HCLK) Table 21-10.
Page 621: Figure 21-17. Multiplex Mode Read Access
GD32F30x User Manual Bit Position Bit Name Reference Setting Value AHLD Depends on memory and user ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode D:0x3 27-20 Reserved 0x00 Time between EXMC_NE[x] rising edge to 19-16 WBUSLAT EXMC_NE[x] falling edge Depends on memory and user (WDSET+1HCLK 15-8...
Page 622: Table 21-11. Multiplex Mode Related Registers Configuration
GD32F30x User Manual Table 21-11. Multiplex mode related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31-20 Reserved 0x000 SYNCWR 18-16 ASYNCWTEN Depends on memory EXMODEN NRWTEN Depends on memory NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 623: Figure 21-19. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32F30x User Manual maxT ≥ T (21-2) WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE ≥(maxT )+4HCLK (21-3) DATA_SETUP WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE Otherwise ≥ 4HCLK (21-4) DATA_SETUP Figure 21-19. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1...
Page 624 GD32F30x User Manual in the EXMC_SNTCFGx register. 1. Data latency and NOR Flash latency Data latency is the number of EXMC_CLK cycles to wait bef ore sampling the data. The relationship between data latency and NOR Flash specification’s latency parameter is as f ollows: For NOR Flash’s specification excluding the EXMC_NADV cycle, their relationship should be: NOR Flash latency=DLAT+2...
Page 625: Figure 21-21. Read Timing Of Synchronous Multiplexed Burst Mode
GD32F30x User Manual a burst transmission whose length is 1. If the needed data of AHB is 32-bit, EXMC will make the transmission divided into two 16-bit transmissions, that is, EXMC perf orms a burst transmission whose length is 2. For other configurations please ref ers to Table 21-3.
Page 626: Figure 21-22. Write Timing Of Synchronous Multiplexed Burst Mode
GD32F30x User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx NRTP Depends on memory，0x1/0x2 NRMUX 0x1, Depends on memory and users NRBKEN EXMC_SNTCFGx(Read) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above：0x1,EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge...
Page 627: Table 21-14. 8-Bit Or 16-Bit Nand Interface Signal
GD32F30x User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx AYSNCWAIT EXMODEN NRWTEN Depends on memory WREN NRWTCFG 0x0(Here must be zero) WRAPEN NTWTPOL Depends on memory SBRSTEN No effect Reserved NREN Depends on memory NRTP NRMUX 0x1, Depends on users NRBKEN EXMC_SNTCFGx(Write) 31-30...
Page 628: Table 21-15. 16-Bit Pc Card Interface Signal
GD32F30x User Manual EXMC Pin Direction Functional description EXMC_NOE(NR Output Output enable EXMC_NWE Output Write enable EXMC_NWAIT/ Input NAND Flash ready/busy input signal to the EXMC, x=1, 2 EXMC_INT[x] Table 21-15. 16-bit PC Card interface signal EXMC Pin Direction Functional description EXMC_A[10:0] Output Address bus of PC Card...
Page 629: Figure 21-23. Access Timing Of Common Memory Space Of Pc Card Controller
GD32F30x User Manual devices. Each bank has a corresponding register to manage and control the external memory, such as EXMC_NPCTLx, EXMC_NPINTENx, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 and EXMC_NECCx. Among these registers, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 registers contain four timing parameters individually which are conf igured according to user specification and features of the external memory. Table 21-17.
Page 630: Figure 21-24. Access To None "Nce Don't Care" Nand Flash
GD32F30x User Manual When EXMC sends command or address to NAND Flash, it needs to use the command latch signal (A [16]) or address latch signal (EXMC_A [17]), namely , the CPU needs to perform write operation in particular address. Example: NAND Flash read operation steps: Conf igure EXMC_NPCTLx and EXMC_NPCTCFGx register.
Page 631 GD32F30x User Manual Write ADD0 into NAND Flash bank common space address area. Write ADD1 into NAND Flash bank common space address area. Write ADD2 into NAND Flash bank common space address area. Write ADD3 into NAND Flash bank common space address area. Write CMD1 into NAND Flash bank attribute space command area.
Page 632 GD32F30x User Manual Attribute space: EXMC_NCE3_x (x = 0, 1) is the chip enable signal, it indicates whether 8- or 16-bit access operation is being performed. EXMC_NWE and EXMC_NOE dictates whether the on-going operation is a write or read operation, and EXMC_NREG is low during attribute space access.
Page 633 GD32F30x User Manual 21.4. Registers definition NOR/PSRAM controller registers 21.4.1. SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DB for region0, and 0x0000 30D2 for region1, region2, and region3. This register has to be accessed by word (32-bit) SYNC CPS[2:0]...
Page 634 GD32F30x User Manual 0: Disable NWAI signal 1: Enable NWAIT signal WREN Write enable 0: Disabled write in the bank by the EXMC, otherwise an AHB error is reported 1: Enabled write in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state...
Page 635 GD32F30x User Manual Address offset: 0x04 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0FFF FFFF This register has to be accessed by word(32-bit) Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0] DSET[7:0] AHLD[3:0] ASET[3:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 636 GD32F30x User Manual 0x00: Reserved 0x01: Data setup time = 2 * HCLK period …… 0xFF: Data setup time = 256 * HCLK period AHLD[3:0] Address hold time This field is used to set the time of address hold phase, which only used in mode D and multiplexed mode.
Page 637 GD32F30x User Manual 11: Mode D access 27:20 Reserved Must be kept at reset value. 19:16 WBUSLAT[3:0] Bus latency Bus latency added at the end of each write transaction to match with the minimum time between consecutive transactions. 0x0: Bus latency = 1 * HCLK period 0x1: Bus latency = 2 * HCLK period ……...
Page 638 GD32F30x User Manual ATR[2:0] CTR[3:0] Reserved ECCEN NDW[1:0] NDTP NDBKEN NDWTEN Reserved Bits Fields Description 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0]...
Page 639 GD32F30x User Manual 1: Enable wait function Reserved Must be kept at reset value. NAND Flash/PC Card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0042 (for bank1 and bank2), 0x0000 0043 (for bank3) This register has to be accessed by word (32-bit) In addition to interrupt controlling bits, this register also contains a FIFO empty status bit, design specifically f or ECC purpose.
Page 640 GD32F30x User Manual 0: Not detect interrupt high -level 1: Detect interrupt high -level INTRS Interrupt rising edge status 0: Not detect interrupt rising edge 1: Detect interrupt rising edge NAND Flash/PC Card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFCFC FCFC This register has to be accessed by word(32-bit)
Page 641 GD32F30x User Manual 0x01: COMWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: COMWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: Reserved COMSET[7:0] Common memory setup time Define the time to build address before sending command 0x00: COMSET = 1 * HCLK ……...
Page 642 GD32F30x User Manual 0xFF: Reserved 15:8 ATTWAIT[7:0] Attribute memory wait time Define the minimum time to maintain command 0x00: Reserved 0x01: ATTWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: ATTWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: ATTWAIT = Reserved ATTSET[7:0] Attribute memory setup time Define the time to build address before sending command...
Page 643 GD32F30x User Manual 0xFF: IOHLD = 255 * HCLK 15:8 IOWAIT[7:0] IO space wait time Define the minimum time to maintain command 0x00: Reserved 0x01: IOWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFF: IOWAIT = 256 * HCLK (+NWAIT active cycles) IOSET[7:0] IO space setup time Define the time to build address before sending command...
Page 644 GD32F30x User Manual Controller area network (CAN) 22.1. Overview CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A and B.
Page 645: Figure 22-1. Can Module Block Diagram
GD32F30x User Manual 22.3. Function overview Figure 22-1. CAN module block diagram shows the CAN block diagram. Figure 22-1. CAN module block diagram Transmit Receive CAN0 CAN0 Tx/Rx mailbox[0..2] FIFO[0..1] Transmit Receive CAN1 CAN1 Tx/Rx mailbox[0..2] FIFO[0..1] Working mode 22.3.1. The CAN interface has three working modes: ◼...
Page 646 GD32F30x User Manual Initial working mode When the conf iguration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set.
Page 647: Figure 22-2. Transmission Register
GD32F30x User Manual FIFOs, the RX pin is disconnected f rom the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave. Loopback communication mode is useful for self-test. Loopback and silent communication mode Loopback and silent communication mode means the RX and TX pins are disconnected from the CAN network while the transmitted messages are transferred into the Rx FIFOs.
Page 648: Figure 22-3. State Of Transmit Mailbox
GD32F30x User Manual Transmit mailbox state A transmit mailbox can be used when it is free (empty state). If the mailbox is filled with data, set TEN bit in CAN_TMIx register to prepare for starting the transmission (pending state). If more than one mailbox is in the pending state, they need scheduling the transmission (scheduled state).
Page 649: Figure 22-4. Reception Register
GD32F30x User Manual done immediately. In the transmit state, the abort of transmission does not take effect immediately until the transmission is finished. In case that the transmission is successful, the MTFNERR and MTF in CAN_TSTAT are set and state changes to be empty. In case that the transmission is failed, the state changes to be scheduled and then the abort of transmission can be done immediately.
Page 650 GD32F30x User Manual Rx FIFO Rx FIFO has three mailboxes. The reception f rames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of f rames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
Page 651: Figure 22-5. 32-Bit Filter
GD32F30x User Manual Figure 22-5. 32-bit filter Figure 22-6. 16-bit filter. 16-bit: SFID [10:0], FT, FF and EFID[17:15] bits. As is shown in Figure 22-6. 16-bit filter Mask mode For the Identif ier of a data f rame to be filtered, the mask mode is used to specify which bits must be the same as the preset Identif ier and which bits need not be judged.
Page 652: Table 22-1. 32-Bit Filter Number
GD32F30x User Manual Filter number Filter consists of some f ilter bank. According to the mode and the scale of each of the f ilter banks, filter has different effects. For example, there are two f ilter banks. Bank0 is configured as 32-bit mask mode. Bank1 is Table 22-1.
Page 653: Table 22-2. Filtering Index
GD32F30x User Manual Table 22-2. Filtering index Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank nunber bank nunber F0DATA0-32bits-ID F2DATA0[15:0]-16bits-ID F2DATA0[31:16]-16bits- F0DATA1-32bits-Mask Mask F1DATA0-32bits-ID F2DATA1[15:0]-16bits-ID F2DATA1[31:16]-16bits- F1DATA1-32bits-ID Mask F3DATA0[15:0]-16bits-ID F4DATA0-32bits-ID F3DATA0[31:16]-16bits- F4DATA1-32bits-Mask Mask F3DATA1[15:0]-16bits-ID F5DATA0-32bits-ID F3DATA1[31:16]-16bits- F5DATA1-32bits-ID Mask F7DATA0[15:0]-16bits-ID F6DATA0[15:0]-16bits-ID F7DATA0[31:16]-16bits- F6DATA0[31:16]-16bits- ID...
Page 654 GD32F30x User Manual Time-triggered communication 22.3.6. The time-triggered CAN protocol is a higher layer protocol on top of the CAN data link layer. Time-triggered communication means that activities are triggered by the elapsing of time segments. In a time-triggered communication system, all time points of message transmission are pre-defined.
Page 655: Figure 22-11. The Bit Time
GD32F30x User Manual delay segment and Phase buf fer segment 1 in the CAN standard. Its duration is programmable f rom 1 to 16 time quanta but it may be automatically lengthened to compensate f or positive phase drifts due to different f requency of the various nodes of the network.
Page 656 GD32F30x User Manual Error flags 22.3.8. The state of CAN bus can be ref lected by Transmit Error Counter (TECNT) and Receive Error Counter (RECNT) of CAN_ERR register. The value can be increased or decreased by the hardware according to the error, and the software can judge the stability of the CAN network by these values.
Page 657: Table 22-3. Can Event / Interrupt Flags
GD32F30x User Manual Receive FIFO0 interrupt The Rx FIFO0 interrupt can be generated by the following conditions: ◼ Rx FIFO0 not empty: RFL0 bits in the CAN_RFIFO0 register are not ‘00’ and RFNEIE0 in CAN_INTEN register is set. ◼ Rx FIFO0 full: RFF0 bit in the CAN_RFIFO0 register is set and RFFIE0 in CAN_INTEN register is set.
Page 658 GD32F30x User Manual nterrupt event nterrupt / Event flag Enable control bit Warning error (WERR) WERRIE Passive error (PERR) PERRIE Error interrupt ERRIE flag (ERRIF) Bus-Off error (BOERR) BOIE Error number (1<= ERRN[2:0] <= 6) ERRNIE EWMC interrupt Status change interrupt flag of waking up from sleep working mode (WUIF) Status change interrupt flag of entering sleep SLPWIE...
Page 659 GD32F30x User Manual 22.4. CAN registers CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 Control register (CAN_CTL) 22.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit) Reserved SLPWMO SWRST Reserved ABOR RFOD IWMOD Bits...
Page 660 GD32F30x User Manual detected, and SLPWMOD bit in CAN_CTL register will be cleared automatically. 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission 1: Disable automatic retransmission RFOD Rx FIFO overwrite disable...
Page 661 GD32F30x User Manual LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
Page 662 GD32F30x User Manual Initial working state This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed.
Page 663 GD32F30x User Manual 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
Page 664 GD32F30x User Manual hardware when next transmit starts. MAL1 Mailbox 1 arbitration lost This bit is set when the arbitration lost occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when next transmit starts.
Page 665 GD32F30x User Manual Receive message FIFO0 register (CAN_RFIFO0) 22.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RFD0 Rx FIFO0 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO0.
Page 666 GD32F30x User Manual Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w1 rc_w1 Bits Fields Descriptions Must be kept at reset value. 31:6 Reserved Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. RFD1 This bit is reset by hardware when the dequeuing is done.
Page 667 GD32F30x User Manual 1: Sleep working interrupt enabled Wakeup interrupt enable 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled ERRIE Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled 14:12 Reserved Must be kept at reset value. ERRNIE Error number interrupt enable 0: Error number interrupt disabled 1: Error number interrupt enabled...
Page 668 GD32F30x User Manual 0: Rx FIFO0 not empty interrupt disabled 1: Rx FIFO0 not empty interrupt enabled TMEIE Transmit mailbox empty interrupt enable 0: Transmit mailbox empty interrupt disabled 1: Transmit mailbox empty interrupt enabled Error register (CAN_ERR) 22.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) RECNT[7:0]...
Page 669 GD32F30x User Manual hardware. WERR Warning error Whenever the TECNT or RECNT is greater than or equal to 96, the bit will be set by hardware. Bit timing register (CAN_BT) 22.4.8. Address offset: 0x1C Reset value: 0x0123 0000 This register has to be accessed by word(32-bit) SCMOD LCMOD Reserved SJW[1:0]...
Page 670 GD32F30x User Manual Transmit mailbox identifier register (CAN_TMIx) (x = 0…2) 22.4.9. Address offset: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (bit0=0) This register has to be accessed by word(32-bit) SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:1 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16...
Page 671 GD32F30x User Manual TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value. TSEN Time stamp enable 0: Time stamp disabled 1: Time stamp enabled. The TS[15:0] will be transmitted in the DB6 and DB7 in This bit is available when the TTC bit in CAN_CTL is set.
Page 672 GD32F30x User Manual Transmit mailbox data1 register (CAN_TMDATA1x) (x = 0...2) 22.4.12. Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6...
Page 673 GD32F30x User Manual EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame 1: Extended format frame Frame type 0: Data frame 1: Remote frame Reserved Must be kept at reset value. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x = 0,1) 22.4.14.
Page 674 GD32F30x User Manual DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0,1) 22.4.16. Address offset: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0]...
Page 675 GD32F30x User Manual Reserved The f ilter control register with GD32F30x CL: Reserved Reserved HBC1F[5:0] Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 HBC1F[5:0] Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 filter. Bank0 ~ Bank HBC1F-1 is used for CAN0.
Page 676 GD32F30x User Manual 0: Filter x with mask mode 1: Filter x with list mode Filter scale configuration register (CAN_FSCFG) (Just for CAN0) 22.4.19. Address offset: 0x20C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set.
Page 677 GD32F30x User Manual 1: Filter x associated with FIFO1 Filter working register (CAN_FW) (Just for CAN0) 22.4.21. Address offset: 0x21C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved FW27 FW26 FW25 FW24 FW23 FW22 FW21 FW20 FW19 FW18...
Page 678 GD32F30x User Manual...
Page 679 GD32F30x User Manual Ethernet (ENET) Overview 23.1. This section applies only to GD32F307xx connectivity line devices. This chapter describes the Ethernet peripheral module. There is a media access controller (MAC) designed in Ethernet module to support 10/100Mbps interf ace speed. For more ef f icient data transfer between Ethernet and memory, a DMA controller is designed in this module.
Page 680: Figure 23-1. Enet Module Block Diagram
GD32F30x User Manual ◼ Support Ethernet f rame time stamping f or both transmit and receive operation, which describes in IEEE 1588-2008, and 64 bit time stamps are given in each frame’s status. ◼ Two independent FIFO for transmitting and receiving. ◼...
Page 681: Figure 23-2. Mac/Tagged Mac Frame Format
GD32F30x User Manual ◼ TxDMA controller, used to read descriptors and data from memory and writes status to memory. ◼ TxMTL, used to control, management and store the transmit data. TxFIFO is implemented in this module and used to cache transmitting data from memory for MAC transmission.
Page 682: Table 23-1. Ethernet Signals (Mii Default)
GD32F30x User Manual The Ethernet f rame’s 32-bit CRC calculation value generating polynomial is fixed 0x04C11DB7 and this polynomial is used in all 32-bit CRC calculation places in Ethernet module, as follows: G(x) = x + x + 1 Ethernet signal description 23.2.3.
Page 683: Table 23-3. Ethernet Signals (Rmii Default)
GD32F30x User Manual Signals Pin mode MII_RXD1 PD10 Floating input (reset state) MII_RXD2 PD11 Floating input (reset state) MII_RXD3 PD12 Floating input (reset state) PPS_OUT AF output push-pull MII_TXD3 AF output push-pull MII_RX_ER PB10 Floating input (reset state) MII_TX_EN PB11 AF output push-pull MII_TXD0 PB12...
Page 684: Figure 23-3. Station Management Interface Signals
GD32F30x User Manual Function overview 23.3. Interface configuration 23.3.1. The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet PHY connected through the MII/RMII interface. MII or RMII mode is selected by software and carry on the PHY management through the SMI interface. SMI: Station management interface SMI is designed to access and configure PHY’s configuration.
Page 685: Table 23-5. Clock Range
GD32F30x User Manual Read operation Applications need to operate the ENET_MAC_PHY_CTL register as follows: Set the PHY device address and PHY register address and set PW to 0, so that can select read mode. Set PB bit to start reception. In the process of transaction PB is always high until the transf er is complete.
Page 686: Figure 23-4. Media Independent Interface Signals
GD32F30x User Manual MII: Media independent interface Figure 23-4. Media independent interface signals - MII_TX_CLK: clock signal for transmitting data. For the data transmission speed of 10Mbit/s, the clock is 2.5MHz, for the data transmission speed of 100Mbit/s, the clock is 25MHz. - MII_RX_CLK: Clock signal for receiving data.
Page 687: Table 23-6. Rx Interface Signal Encoding
GD32F30x User Manual transmission is completed. It must be inactive prior to the first clock cycle that follows the final 4-bit. MII_RX_DV signals should be effective before the SFD field appearing to ensure that receive the correct frame. - MII_RX_ER: Receive error signal. In order to indicate that MAC detected an error in the receiving process, the MII_RX_ER signal must remain effective for one or more clock cycles (MII_RX_CLK).
Page 688: Figure 23-5. Reduced Media-Independent Interface Signals
GD32F30x User Manual Figure 23-5. Reduced media-independent interface signals TX_EN TXD[1:0] CRS_DV MAC Controller RXD[1:0] REF_CLK RMII clock sources To ensure the synchronization of the clock source, the same clock source is selected for the MAC and external PHY which is called REF_CLK. The REF_CLK input clock can be connected to the external 50MHz crystal or microcontroller CK_OUT0 pin.
Page 689 GD32F30x User Manual LAN and the two devices are both configured for Full-duplex mode. MAC module can achieve the f ollows f unctions: 1) The data packaging (transmission and reception), that includes detecting / decoding f rame and delimitating f rame boundary; handling source address and destination address;...
Page 690 GD32F30x User Manual If the byte length of one transmission MAC frame’s data field is less than 46 (for Tagged MAC f rame is less than 42), application can configure the MAC f or automatically adding a load of content of ‘0’ bit to make the byte length of frame’s data field in accordance with the relevant domain of definition of IEEE802.3 specification.
Page 691 GD32F30x User Manual be pended unless the counter reach the gap time. But if the second transmit frame presents af ter the gap time counter has reached the conf igured gap time, this f rame will send immediately. For Half -duplex mode, the gap time counter f ollows the Truncated Binary Exponential Backoff algorithm.
Page 692 GD32F30x User Manual In this f ilter mode, MAC uses a HASH mechanism. MAC uses a 64-bit hash list to f ilter the received unicast frame. This filter mode obeys the followings two filtering steps: 1) The MAC calculates the CRC value of the received frame’s destination address. 2) Using the high 6 bits of the calculated CRC value as the index to retrieve the hash list.
Page 693: Table 23-7. Destination Address Filtering Table
GD32F30x User Manual register, this address f ilter reverse f unction can be enabled. DAIFLT bit is used f or unicast and multicast frames’ DA filtering result, SAIFLT bit is used for unicast and multicast frames SA f iltering result. The f ollowing Table 23-7.
Page 694 GD32F30x User Manual Frame SAIFLT SAFLT SA filter operation type Pass all frames Pass status on perfect/group filter match but do not Unicast drop frames that fail Fail status on perfect/group filter match but do not drop frame Pass on perfect/group filter match and drop frames that fail Unicast Fail on perfect/group filter match and drop frames that...
Page 695 GD32F30x User Manual number will be cut off. When RxFIFO works at Cut-Through mode, it starts popping out data from RxFIFO when the number of FIFO is greater than threshold value (RTHC bits in ENET_DMA_CTL register). Af ter all data of a f rame pop out, receive status word is sent to DMA for writing back to descriptor.
Page 696 GD32F30x User Manual pressure f eature. Both of the two conditions are triggered to enable back pressure f unction which is implemented by sending a special pattern (called jam pattern) 0x5555 5555 once to notif y conflict to all other sites. The f irst condition is triggered by application setting the FLCB/BKPA bit in ENET_MAC_FCTL register.
Page 697 GD32F30x User Manual In Full-duplex mode, the MAC can detect the pause control f rames, and perf orm it by suspending a certain time which is indicated in pause time f ield of detected pause control f rame and then to transmit data. This f unction can set by RFCEN bit in ENET_MAC_FCTL register.
Page 698 GD32F30x User Manual The checksum of fload module processes the IPv4 or IPv6 header (including extension headers) and marks the type of frame (TCP, UDP or ICMP). But when the f ollowing f rame cases are detected, the checksum offload f unction will be bypassed and these frames will not be processed by the checksum offload module: Incomplete IPv4 or IPv6 frames.
Page 699 GD32F30x User Manual errors: ◼ Any mismatch between the IPv4 calculation result by checksum offload module and the value in received frame’s checksum field. ◼ Any inconsistent between the data type of Ethernet type field and IP header version f ield. ◼...
Page 700 GD32F30x User Manual second data address or the next descriptor address which is determined by the configured descriptor table type: Ring or Chain. Buffer space only contains frame data which are located in host’s physical memory space. One buffer can store only one f rame data but one frame data can be stored in more than one buffer which means one buffer can only store a part of a f rame.
Page 701: Figure 23-6. Descriptor Ring And Chain Structure
GD32F30x User Manual Figure 23-6. Descriptor ring and chain structure Chain structure Ring structure If descriptor end Buffer 1 Buffer 1 Descriptor 0 Descriptor 0 Buffer 2 Buffer 1 Buffer 1 Descriptor 1 Descriptor 1 Buffer 2 Buffer 1 Descriptor 2 Buffer 2 Descriptor 2 Buffer 1...
Page 702 GD32F30x User Manual bit and LSG bit in Transmit Descriptor0 are both reset, it knows the current buffer is pointing to a part of current frame. When the DMA controller reads a descriptor with LSG bit in Transmit Descriptor0 is set, it knows the current buffers is pointing to the last part of the current frame. Normally one f rame is stored only in one buffer (because buffer size is large enough for a normal f rame), so FSG bit and LSG bit are set in the same descriptor.
Page 703 GD32F30x User Manual Program the Tx and Rx descriptor table start address by writing the ENET_DMA_TDTADDR register and the ENET_DMA_RDTADDR register. Conf igure filter option by writing related registers. According to the auto-negotiation result with external PHY, set the SPD bit and DPM bit f or selecting the communication mode (Half-duplex/Full-duplex) and the communication speed (10Mbit/s or 100Mbit/s).
Page 704 GD32F30x User Manual Initialize the f rame data into the buffer space and configure the descriptor (Transmit Descriptor0-3) with DAV bit of Transmit Descriptor0 sets to 1. Enable TxDMA controller by setting STE bit in ENET_DMA_CTL register. The TxDMA controller starts continue polling and performing transmit descriptor. When the DAV bit in Transmit Descriptor0 that TxDMA controller read is cleared, or any error condition occurs, the controller will enter suspend state and at the same time both the transmit buffer unavailable bit in ENET_DMA_STAT and normal interrupt summary bit...
Page 705 GD32F30x User Manual TxDMA controller continues polling descriptor and frame data until the EOF is transf erred. If a f rame is described with more than one descriptor, the intermediate descriptors are all closed by TxDMA controller after fetched. The TxDMA controller enters the state of waiting for the transmission status and time stamp of the previous frame (if timestamp enabled).
Page 706: Figure 23-7. Transmit Descriptor In Normal Mode
GD32F30x User Manual Transmit DMA descriptor with IEEE 1588 timestamp format When TTSEN bit is set, the timestamp function is enabled. The TxDMA controller writes transmit timestamp status TTMSS and timestamp back to desc riptor af ter the f rame transmission complete.
Page 707 GD32F30x User Manual frame have been set. 0: The descriptor is available for CPU not for DMA 1: The descriptor is available for DMA not for CPU INTC Interrupt on completion bit Only when the LSG bit is set, this bit is valid. 0: TS bit in ENET_DMA_STAT is not set when frame transmission complete.
Page 708 GD32F30x User Manual This bit is used only in ring mode and has higher priority than TCHM 0: The current descriptor is not the last descriptor in the table 1: The descriptor table reached its final descriptor. The DMA descriptor pointer returns to the start address of the table.
Page 709 GD32F30x User Manual 0: No jabber timeout occurred 1: Jabber timeout of MAC transmitter has occurred . FRMF Frame flushed bit This bit is set to flush the Tx frame by software IPPE IP payload error bit The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP, UDP or ICMP packet bytes received from the application and issues an error status i n case of a mismatch 0: No IP payload error occurred...
Page 710 GD32F30x User Manual collisions that has occurred. Excessive deferral bit Only when the DFC bit in the ENET_MAC_CFG register is set, this bit is valid 0: No excessive deferral occurred 1: The transmission has ended because of excessive deferral time is over 3036 bytes Underflow error bit This bit shows that the TxDMA comes across an empty TxFIFO while transmitting...
Page 711 GD32F30x User Manual TB1AP/TTSL[31:16] TB1AP/TTSL[15:0] Bits Fields Descriptions 31:0 TB1AP/TTSL[31:0] Transmit buffer 1 address pointer/Transmit frame timestamp low 32-bit value bits Before transmitting frame, application must configure these bits for transmit buffer 1 address (TB1AP). When the transmitting frame is complete, these bits can be changed to the timestamp low 32-bit value (TTSL) for transmitting frame if DFM=0.
Page 712: Figure 23-8. Transmit Descriptor In Enhanced Mode
GD32F30x User Manual ~ Transmit Descriptor7. The descriptions of Transmit Descriptor0 ~ Transmit Descriptor3 are the same with normal mode descriptor; Transmit Descriptor4 ~ Transmit Descriptor7 are given below: Note: When a f rame is described by more than one descriptor, only the control bits of the first descriptor are accept by DMA controller (except INTC).
Page 713 GD32F30x User Manual TTSH[15:0] Bits Fields Descriptions 31:0 TTSH[31:0] Transmit frame timestamp high 32-bit value bits When TTSEN =1 and LSG=1, these bits are updated by TxDMA for recording timestamp high 32-bit value of the current transmitting frame. Reception process of DMA When a f rame is presented on the interface, the MAC starts to receive it.
Page 714 GD32F30x User Manual Reception management of DMA The receiving process of the RxDMA controller is described detailed as below: 1. Applications initialize the receive descriptors with the DAV bit in the Receive Descriptor0 is set. 2. Setting the SRE bit in ENET_DMA_CTL register to make RxDMA controller entering running state.
Page 715 GD32F30x User Manual Once exiting suspend mode, the RxDMA controller fetches the next descriptor and the f ollowing operation goes to Step 2. Receive descriptor fetching regulation Descriptor fetching occurs if any one or more of the following conditions are met: ◼...
Page 716: Figure 23-9. Receive Descriptor In Normal Mode
GD32F30x User Manual Figure 23-9. Receive descriptor in normal mode ◼ Receive Descriptor0: Receive descriptor word 0 DAFF FRML[13:0] ERRS DERR SAFF LERR OERR VTAG FDES LDES IPHERR FRMT RWDT RERR DBERR CERR PCERR Bits Fields Descriptions Descriptor available bit This bit shows whether the DMA controller can use this descriptor.
Page 717 GD32F30x User Manual DERR: Descriptor error OERR: Overflow error LCO: Late collision RWDT: Watchdog timeout RERR: Receive error CERR: CRC error IPHERR = 0, FRMT = 1 and PCERR = 1: payload checksum error IPHERR = 1, FRMT = 1 and PCERR = 0: header checksum error IPHERR = 1, FRMT = 1 and PCERR = 1: both header and payload checksum errors This bit is logical ORed by the following bits when DFM is equal to 1:...
Page 718 GD32F30x User Manual 1: Received frame is a tag frame FDES First descriptor bit This bit shows whether current descriptor contains the SOF of the received frame. 0: The current descriptor does not store the SOF of the received frame 1: The current descriptor buffer saves the SOF of the received frame LDES Last descriptor bit...
Page 719: Table 23-9. Error Status Decoding In Receive Descriptor0, Only Used For Normal Descriptor (Dfm=0)
GD32F30x User Manual DBERR Dribble bit error bit This bit indicates whether a nibble is present in the received data frame. Only when in MII interface mode, this bit is valid . 0: No dribble bit error occurred 1: Dribble bit error occurred CERR CRC error bit This bit shows whether FCS field in received frame is mismatch with the calculation...
Page 720 GD32F30x User Manual 2) Calculated header checksum mismatch the header checksum field 3) Expected IP header bytes is not received enough IPv4 or IPv6 frame, both header and payload checksum detected errors ◼ Receive Descriptor1: Receive descriptor word 1 DINTC Reserved RB2S[12:0] RERM...
Page 721 GD32F30x User Manual next descriptor (RCHM=1) ◼ Receive Descriptor2: Receive descriptor word 2 RB1AP/RTSL[31:16] RB1AP/RTSL[15:0] Bits Fields Descriptions 31:0 RB1AP/RTSL[31:0] Receive buffer 1 address pointer / Receive frame timestamp low 32-bit These bits are designed for two different functions: buffer address pointer (RB1AP) or timestamp low 32-bit value (RTSL).
Page 722: Figure 23-10. Receive Descriptor In Enhanced Mode
GD32F30x User Manual When this address is used for next descriptor address, the word alignment is needed. The other conditions have no limitation for these bits. RTSH: When timestamp function is enabled and LDES is set, these bits will be changed to timestamp high 32-bit value by RxDMA controller if received frame passed the filter and satisfied the snapshoot condition.
Page 723 GD32F30x User Manual PTPOEF PTP on Ethernet frame bit 0: Received PTP frame is a IP-UDP frame if PTPMT is not zero 1: Received PTP frame is a IEEE802.3 Ethernet frame 11:8 PTPMT[3:0] PTP message type bits PTP message type is decoded to following number: 0x0: Not PTP frame received 0x1: SYNC 0x2: FOLLOW_UP...
Page 724 GD32F30x User Manual IPPLDT[2:0] IP frame payload type bits These bits are valid only when IPFCO=1, IPHERR=0 and LDES=1. 0x0: Unsupported payload type or IP payload bypassed 0x1: payload type is UDP 0x2: payload type is TCP 0x3: payload type is ICMP 0x4~0x7: Reserved ◼...
Page 725 GD32F30x User Manual counters designed f or gathering statistics data. These MAC counters are called statistics counters (MSC). In Section ‘Register Description’, there is a detailed description of the f unction of these registers. When the transmit frame does not appear the situations, such as frame underflow, no carrier, carrier lost, excessive deferral, late collision，excessive collision and jabber timeout, it can be called “good frame”.
Page 726 GD32F30x User Manual Magic packet detection Another wakeup method is detecting Magic Packet f rame (see ‘Magic Packet Technology’, Advanced Micro Devices). A Magic Packet frame is a special frame with formed packet solely intended for wakeup purposes. This packet can be received, analyzed and recognized by the Ethernet block and used to trigger a wakeup event.
Page 727: Figure 23-11. Wakeup Frame Filter Register
GD32F30x User Manual Wait the current sending frame completes and then reset the TxDMA block by clearing STE bit in ENET_DMA_CTL register. Clear the TEN and REN bit in ENET_MAC_CFG register to disable the MAC’s transmit and receive f unction. Check the RS bit in ENET_DMA_STAT register, waiting receive DMA read out all the f rames in the receive FIFO and then close RxDMA.
Page 728 GD32F30x User Manual wakeup f rame or not by f ilter n (n=0, 1, 2, 3). Bit 31 must be set to 0. Bit 30 to bit 0 are valid byte mask. If bit m(m means byte number) is set, the filter n offset + m of the receiving frame is calculated by the CRC unit, conversely, filter n offset + m is ignored.
Page 729: Figure 23-12. System Time Update Using The Fine Correction Method
GD32F30x User Manual System time calibration PTP input reference clock is used to update 64-bit PTP system time. The PTP system time is used as the source to record transmission/reception f rame’s timestamp. The system time initialization and calibration support two methods: coarse method and f ine method. The purpose of calibration is to correct the frequency offset.
Page 730 GD32F30x User Manual ENET_PTP_TSADDEND register is 2 / 1.7 = 0x9696 9697. If the ref erence clock drift higher, f or example, up to 76MHz, the value should to be set in the ENET_PTP_TSADDEND register is 2 / 1.9 = 0x86BC A1AF. Initially, the slave clock frequency is set to Clock Addend Value (0) in the addend register.
Page 731 GD32F30x User Manual Setting TMSEN bit in the ENET_PTP_TSCTL register to enable timestamp function Conf igure the subsecond increment register according to the PTP clock frequency precision If application hopes to use fine correction method, configure the timestamp addend register and set TMSARU bit in the ENET_PTP_TSCTL register to 1. If application hopes to use coarse correction method, please jump directly to step 7 and step 4-6 can be ignored.
Page 732 GD32F30x User Manual another word, only the f rame matched the PTP conf iguration is marked a PTP f rame, and timestamp will be recorded in descriptor. To be marked as a PTP f rame, the received frame PTP version should be coincide with PFSV bit and then the corresponding frame type enable bit(bit 13 to bit 11 in register ENET_PTP_TSCTL) is set.
Page 733 GD32F30x User Manual Conf igure GPIO module to make selected PADs to alternate function. ◼ Wait the resetting complete Polling the ENET_DMA_BCTL register until the SWR bit is reset. (SWR bit is set by def ault after power-on reset or system reset). ◼...
Page 734: Figure 23-13. Mac Interrupt Scheme
GD32F30x User Manual Ethernet interrupts 23.3.8. There are two interrupt vectors in Ethernet module. The f irst interrupt vector is made up of normal operation interrupts and the second vector is made up of WUM events f or wakeup which is mapped to the EXTI line 19. All of the MAC and DMA controller interrupt are co nnected to the f irst interrupt vector.
Page 735: Figure 23-14. Ethernet Interrupt Scheme
GD32F30x User Manual bit is cleared. If both normal and abnormal interrupts are cleared, the DMA interrupt will be cleared. Below block diagram illustrates the Ethernet module interrupt connection: Figure 23-14. Ethernet interrupt scheme TBUIE NISE Normal Interrupt ERIE Ethernet MSCI Interrupt WUMI...
Page 736 GD32F30x User Manual Register definition 23.4. ENET base address: 0x4002 8000 MAC configuration register (ENET_MAC_CFG) 23.4.1. Address offset: 0x0000 Reset value: 0x0000 8000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register configures the operation mode of the MAC. It also configures the MAC receiver and MAC transmitter operating mode.
Page 737 GD32F30x User Manual 0x0: 96 bit times 0x1: 88 bit times 0x2: 80 bit times 0x3: 72 bit times 0x4: 64 bit times 0x5: 56 bit times(For Half-duplex, must be reserved) 0x6: 48 bit times(For Half-duplex, must be reserved) 0x7: 40 bit times(For Half-duplex, must be reserved) Carrier sense disable bit 0: The carrier sense error is generated by MAC transmitter, and the transmission will be aborted.
Page 738 GD32F30x User Manual 0: The MAC forwards all received frames without modify it 1: The MAC strips the Pad/FCS field on received frames BOL[1:0] Back-off limit bits When in Full-duplex mode, these bits can be ignored. When a collision occurred, the MAC needs to retry sending current frame after delay some time.
Page 739 GD32F30x User Manual Reserved HPFLT SAFLT SAIFLT PCFRM[1:0] BFRMD DAIFLT Bits Fields Descriptions Frames all received bit This bit controls the receive filter function. 0: Only the frame passed the filter can be forwarded to application. 1: All received frame are forwarded to application. But filter result will also be updated to receive descriptor status.
Page 740 GD32F30x User Manual 1: All received broadcast frames is filtered by address filters . Multicast filter disable bit 0: Multicast filter is enabled. The filtering mode of multicast frame is determined by HMF bit. 1: Multicast filter is disabled. All received multicast frames are passed. The first bit in the destination address field of multicast frames is '1', but not all bits in the destination are ‘1’.
Page 741 GD32F30x User Manual MAC hash list low register (ENET_MAC_HLL) 23.4.4. Address offset: 0x000C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HLL[31:16] HLL[15:0] Bits Fields Descriptions 31:0 HLL[31:0] Hash list low bits These bits take the low 32-bit value of hash list MAC PHY control register (ENET_MAC_PHY_CTL) 23.4.5.
Page 742 GD32F30x User Manual 0x3: HCLK/26 (HCLK range: 35-60 MHz) other: Reserved PHY write bit This bit indicates the PHY operation mode 0: Sending read operation to PHY 1: Sending write operation to PHY PHY busy bit This bit indicates the running state of operation on PHY. Application sets this bit to 1 and should wait it cleared by hardware.
Page 743 GD32F30x User Manual FLCB/BK Reserved DZQP Reserved PLTS[1:0] UPFDT RFCEN TFCEN Bits Fields Descriptions 31:16 PTM[15:0] Pause time bits These bits configured the pause time filed value in transmit pause control frame. 15:8 Reserved Must be kept at reset value. DZQP Disable Zero-quanta pause bit 0: Enable automatic zero -quanta generation function for pause control frame.
Page 744 GD32F30x User Manual FLCB/BKPA Flow control busy/back pressure activate bit This bit only valid when TFCEN is set. This bit can send a pause frame in Full-duplex mode or activate the back pressure function in Half-duplex mode by application. For Full-duplex mode, application must make sure this bit is 0 before writing ENET_MAC_FCTL register.
Page 745: Figure 23-15. Wakeup Frame Filter Register
GD32F30x User Manual When comparison bits not all zeros, VLAN tag comparison use bit VLTI[11:0] (if VLTC=1) or VLTI[15:0] (if VLTC=0) for checking . MAC remote wakeup frame filter register (ENET_MAC_RWFF) 23.4.9. Address offset: 0x0028 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). The MAC remote wakeup frame filter register is actually a pointer to eight (with same address of fset) such wakeup f rame f ilter registers.
Page 746 GD32F30x User Manual This bit can reset the inner pointer of ENET_MAC_RWFF register by application set it to 1. Hardware clears it when resetting completes. 0: No effect 1: Reset the ENET_MAC_RWFF register inner pointer 30:10 Reserved Must be kept at reset value. Global unicast bit 0: Not all of received unicast frame is considered to be a wakeup frame 1: Any received unicast frame passed address filtering is considered to be a...
Page 747 GD32F30x User Manual Reserved RXFS[1:0] Reserved RXFRS[1:0] RXFW Reserved RXAFS[1:0] MRNI Bits Fields Descriptions 31:26 Reserved Must be kept at reset value TXFF TxFIFO Full flag 0: TxFIFO not full 1: TxFIFO is full TXFNE TxFIFO not empty flag 0: TxFIFO is empty 1: TxFIFO is not empty Reserved Must be kept at reset value...
Page 748 GD32F30x User Manual 0x2: The flow-control high threshold is lower than RxFIFO number of value 0x3: The RxFIFO is full Reserved Must be kept at reset value RXFRS[1:0] RxFIFO read operation status 0x0: RxFIFO read controller is in idle state 0x1: RxFIFO read controller is in reading state 0x2: RxFIFO read controller is reading frame status(including time-stamp) 0x3: RxFIFO read controller is flushing frame...
Page 749 GD32F30x User Manual Reserved Must be kept at reset value. MSCT MSC transmit status bit 0: All the bits in register ENET_MSC_TINTF are cleared 1: An interrupt is generated in the ENET_MSC_TINTF register MSCR MSC receive status bit 0: All the bits in register ENET_MSC_RINTF are cleared 1: An interrupt is generated in the ENET_MSC_RINTF register MSC status bit This bit is logic ORed from MSCT and MSCR bit.
Page 750 GD32F30x User Manual 1: Mask the interrupt generation due to the WUM bit in ENET_MAC_INTF register Reserved Must be kept at reset value. MAC address 0 high register (ENET_MAC_ADDR0H) 23.4.14. Address offset: 0x0040 Reset value: 0x8000 FFFF This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved ADDR0H[15:0] Bits...
Page 751 GD32F30x User Manual pause frame transmitting during transmit flow control. MAC address 1 high register (ENET_MAC_ADDR1H) 23.4.16. Address offset: 0x0048 Reset value: 0x0000 FFFF This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). MB[5:0] Reserved ADDR1H[15:0] Bits Fields Descriptions Address filter enable bit 0: MAC address1 is ignored by address filter for filtering 1: MAC address1 is used by address filter for perfect filtering...
Page 752 GD32F30x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). ADDR1L[31:16] ADDR1L[15:0] Bits Fields Descriptions 31:0 ADDR1L[31:0] MAC address1 low 32-bit This field contains the low 32-bit of the 6-byte MAC address1 MAC address 2 high register (ENET_MAC_ADDR2H) 23.4.18.
Page 753 GD32F30x User Manual MB[0]: ENET_MAC_ADDR2L [7:0] 23:16 Reserved Must be kept at reset value. 15:0 ADDR2H[15:0] MAC address2 high 16-bit This field contains the high 16-bit (bit 47 to 32) of the 6-byte MAC address2 MAC address 2 low register (ENET_MAC_ADDR2L) 23.4.19.
Page 754 GD32F30x User Manual 1: Comparing MAC address3 with the source address field of the received frame 29:24 MB[5:0] Mask byte bits If these bits is set, the destination address / source address corresponding byte of the received frame is not compared with MAC address3. Each bit controls one byte mask as follows: MB[5]: ENET_MAC_ADDR3H [15:8] MB[4]: ENET_MAC_ADDR3H [7:0]...
Page 755 GD32F30x User Manual Reserved RFD[2:0] Reserved RFA[2:0] Bits Fields Descriptions 31:7 Reserved Must be kept at reset value RFD[2:0] Threshold of deactive flow control This field configures the threshold of the deactive flow control. The value should always be less than the Threshold of active flow control value configured in bits[2:0]. When the value of the unprocessed data in RxFIFO is less than this value configured, the flow control function will deactive.
Page 756 GD32F30x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. AFHPM Almost full or half preset mode 0: Preset all MSC counters to almost-half (0x7FFF FFF0) value 1: Preset all MSC counters to almost-full (0xFFFF FFF0) value Note: This bit is valid only when PMC is set Preset MSC counter 0: No effect...
Page 757 GD32F30x User Manual 31:18 Reserved Must be kept at reset value. RGUF Received good unicast frames bit 0: Good unicast frame received counter is less than half of the maximum value 1: Good unicast frame received counter reaches half of the maximum value 16:7 Reserved Must be kept at reset value.
Page 758 GD32F30x User Manual maximum value 1: Good frame after a single collision transmitted counter reaches half of the maximum value 13:0 Reserved Must be kept at reset value. MSC receive interrupt mask register (ENET_MSC_RINTMSK) 23.4.26. Address offset: 0x010C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 759 GD32F30x User Manual Reserved TGFIM Reserved TGFMSCI TGFSCIM Reserved Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. TGFIM Transmitted good frames interrupt mask bit 0: Unmask the interrupt when the TGF bit is set 1:Mask the interrupt when the TGF bit is set 20:16 Reserved Must be kept at reset value.
Page 760 GD32F30x User Manual These bits count the number of a transmitted good frames after only a single collision MSC transmitted good frames after more than a single collision counter 23.4.29. register (ENET_MSC_MSCCNT) Address offset: 0x0150 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register counts the number of successfully transmitted f rames af ter more than one single collision in Half-duplex mode.
Page 761 GD32F30x User Manual received frames with error counter register 23.4.31. (ENET_MSC_RFCECNT) Address offset: 0x0194 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register counts the number of frames received with CRC error. RFCER[31:16] RFCER[15:0] Bits Fields...
Page 762 GD32F30x User Manual received good unicast frames counter register 23.4.33. (ENET_MSC_RGUFCNT) Address offset: 0x01C4 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register counts the number of good unicast frames received. RGUF[31:16] RGUF[15:0] Bits Fields Descriptions...
Page 763 GD32F30x User Manual 0x2: Type of end-to-end transparent clock 0x3: Type of peer-to-peer transparent clock MNMSEN Received master node message snapshot enable This bit is valid only when CKNT=0x0 or 0x1. 0: Snapshot is only taken for slave node message 1: Snapshot is only take for master node message ETMSEN Received event type message snapshot enable...
Page 764: Table 23-10. Supported Time Stamp Snapshot With Ptp Register Configuration
GD32F30x User Manual Note: After the timestamp trigger interrupt happened the TMSITEN bit is cleared . TMSSTU Timestamp system time update bit Both the TMSSTU and TMSSTI bits must be read as 0 before application set this 0: Not update the system time 1: Update the system time with the value in the ENET_PTP_TSUH and ENET_PTP_TSUL registers.
Page 765 GD32F30x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register conf igures the 8-bit value f or the incrementing subsecond register. In coarse mode, this value is added to the system time every HCLK clock cycle. In fine mode, this value is added to the system time when the accumulator reaches overflow.
Page 766 GD32F30x User Manual STMSS[15:0] Bits Fields Descriptions System time sign bit 0: Time value is positive 1: Time value is negative 30:0 STMSS[30:0] System time subseconds bits These bits show the current subsecond of the system time with 0.46 ns accuracy . PTP time stamp update high register (ENET_PTP_TSUH) 23.4.38.
Page 767 GD32F30x User Manual TMSUSS[15:0] Bits Fields Descriptions TMSUPNS Timestamp update positive or negative sign bit When TMSSTI is set, this bit must be 0. 0: Timestamp update value is added to system time 1: Timestamp update value is subtracted from system time 30:0 TMSUSS[30:0] Timestamp update subsecond bits...
Page 768 GD32F30x User Manual ETSH[15:0] Bits Fields Descriptions 31:0 ETSH[31:0] Expected time high bits These bits store the expected target second time. PTP expected time low register (ENET_PTP_ETL) 23.4.42. Address offset: 0x0720 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). ETSL[31:16] ETSL[15:0] Bits...
Page 769 GD32F30x User Manual Note: Reading ENET_PTP_TSF register will clear this bit. TSSCO Timestamp second counter overflow bit 0: Timestamp second counter has not overflowed 1: Timestamp second counter is greater than 0xFFFF FFFF PTP PPS control register (ENET_PTP_PPSCTL) 23.4.44. Address offset: 0x072C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 770 GD32F30x User Manual 31:27 Reserved Must be kept at reset value. Mixed burst 0: AHB master interface only transfer fixed burst length with 16 and below 1: AHB master interface will transfer burst length greater than 16 with INCR Note: MB and FB should be and must be only one of bit is set. Address-aligned bit 0: Disable address-aligned 1: Enabled address-aligned.
Page 771 GD32F30x User Manual 0x2: RxDMA: TxDMA = 3:1 0x3: RxDMA: TxDMA = 4:1 Note: This bit is valid only when the arbitration mode is Round -robin (DAB=0) 13:8 PGBL[5:0] Programmable burst length bits These bits indicate the maximum number of beats to be transferred in one DMA transaction.
Page 772 GD32F30x User Manual This register is used by the application to make the TxDMA controller poll the transmit descriptor table. The TxDMA controller can go into suspend state because of an underflow error in a transmitted frame or the descriptor unavailable (DAV=0). Application can write any value into this register for attempting to re-f etch the current descriptor.
Page 773 GD32F30x User Manual DMA receive descriptor table address register (ENET_DMA_RDTADDR) 23.4.48. Address offset: 0x100C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register points to the start of the receive descriptor table. The descriptor table is located in the physical memory space and must be word -aligned.
Page 774 GD32F30x User Manual DMA status register (ENET_DMA_STAT) 23.4.50. Address offset: 0x1014 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register contains all the status bits that the DMA controller recorded. Writing 1 to meaningful bits in this register clears them but writing 0 has no ef f ect.
Page 775 GD32F30x User Manual 1: Error occurs while TxDMA transfer data 0: Error occurs while RxDMA transfer data EB[1]: 1: Error occurs while read transfer 0: Error occurs while write transfer EB[2]: 1: Error occurs while access descriptor 0: Error occurs while access data buffer 22:20 TP[2:0] Transmit process state bit...
Page 776 GD32F30x User Manual TJT: Timeout of transmit jabber RO: Overflow of receive FIFO TU: Underflow transmit RBU: Receive buffer RPS: Unavailable of receive process stopped RWT: Timeout of receive watchdog ET: Interrupt of early transmit FBE: Error of fatal bus error Note: Each time when this bit is set, application must cleared its source bit by writing 1 to that bit.
Page 777 GD32F30x User Manual entered suspend state Receive overflow status bit 0: Receive overflow error has not occurred during frame reception 1: The RxFIFO encountered an overflow error during frame reception. If a part of frame data has transferred to the memory, the overflow status OERR bit in Receive Descriptor0 is also set Transmit jabber timeout status bit 0: Transmit jabber timeout has not occurred during frame transmission...
Page 778 GD32F30x User Manual 0: All error frames will be dropped when FERF=0 1: The received frame with only payload error but no other errors will not be dropped. RSFD Receive Store-and-Forward bit 0: The RxFIFO operates in Cut-Through mode. The forwarding threshold depends on the RTHC bits 1: The RxFIFO operates in Store-and-Forward mode.
Page 779 GD32F30x User Manual current frame is being transmitted. After complete transmitting, the next descriptor address will become current descriptor address for the address pointer. If the TxDMA controller is in suspend state, reset this bit make the controller entering stop state. 1: The TxDMA controller will enter running state.
Page 780 GD32F30x User Manual descriptor Start/stop receive enable bit 0: The RxDMA controller will enter stop state after transfer complete if current received frame is transmitting to memory by RxDMA. After transfer complete, the next descriptor address in the receive table will become the current descriptor address when restart the RxDMA controller.
Page 781 GD32F30x User Manual 0: Disable abnormal interrupt 1: Enable abnormal interrupt This bit enables the following bits: TPS: Halt of transmit process TJT: Timeout of transmit jabber RO: Overflow of receive FIFO TU: Underflow transmit RBU: Receive buffer RPS: Unavailable of receive process stopped RWT: Timeout of receive watchdog ET: Interrupt of early transmit FBE: Error of fatal bus error...
Page 782 GD32F30x User Manual 1: Enable overflow interrupt TJTIE Transmit jabber timeout interrupt enable bit 0: Disable transmit jabber timeout interrupt 1: Enable transmit jabber timeout interrupt TBUIE Transmit buffer unavailable interrupt enable bit 0: Disable transmit buffer unavailable interrupt 1: Enable transmit buffer unavailable interrupt TPSIE Transmit process stopped interrupt enable bit 0: Disable transmission stopped interrupt...
Page 783 GD32F30x User Manual These bits indicate the number of frames missed by the RxDMA controller because of the unavailable receive buffer. Each time the RxDMA controller flushes one frame, this counter will plus 1. DMA receive state watchdog counter register (ENET_DMA_RSWDC) 23.4.54.
Page 784 GD32F30x User Manual Bits Fields Descriptions 31:0 TDAP[31:0] Transmit descriptor address pointer bits These bits are automatically updated by TxDMA controller during operation. current receive descriptor address register 23.4.56. (ENET_DMA_CRDADDR) Address offset: 0x104C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register points to the start descriptor address of the current receive descriptor read by the RxDMA controller.
Page 785 GD32F30x User Manual DMA current receive buffer address register (ENET_DMA_CRBADDR) 23.4.58. Address offset: 0x1054 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). This register points to the current receive buffer address being read by the RxDMA controller. RBAP[31:16] RBAP[15:0] Bits...
Page 786: Figure 24-1. Usbd Block Diagram
GD32F30x User Manual Universal Serial Bus full-speed device interface (USBD) The USBD is only available on GD32F303 series. 24.1. Overview The Universal Serial Bus f ull-speed device interf ace (USBD) module provides a device solution for implementing a USB 2.0 f ull-speed compliant peripheral. It contains a f ull-speed internal USB PHY and no more external PHY chip is needed.
Page 787: Table 24-1. Usbd Signal Description
GD32F30x User Manual 24.4. Signal description Table 24-1. USBD signal description I/O port Type Description VBUS Input Bus power port Input/Output Differential D- Input/Output Differential D+ Note: As soon as the USBD is enabled, these pins are connected to the USBD internal transceiver automatically.
Page 788 GD32F30x User Manual 24.6. Function overview USB endpoints 24.6.1. USBD supports 8 USB endpoints that can be individually configured. Each endpoint supports: Single/Double buffer (endpoint 0 can’t use double buffer). ◼ ◼ One endpoint buffer descriptor. Programmable buffer starting address and buffer length. ◼...
Page 789: Figure 24-2. An Example With Buffer Descriptor Table Usage (Usbd_Baddr = 0)
GD32F30x User Manual Figure 24-2. an example with buffer descriptor table usage (USBD_BADDR = 0) offset 0x1FF IN endpoint 1 double buffer 0 IN endpoint 1 double buffer 1 Endpoint 0 reception buffer Endpoint 0 transmission buffer COUNT1_TX1 ADDR1_TX1 COUNT1_TX0 Endpoint 1 buffer descriptor (double buffer) ADDR1_TX0 COUNT0_RX...
Page 790: Table 24-2. Double-Buffering Buffer Flag Definition
GD32F30x User Manual Table 24-2. Double-buffering buffer flag definition Buffer flag Tx endpoint Rx endpoint TX_DTG (USBD_EPxCS bit 6) RX_DTG (USBD_EPxCS bit 14) SW_BUF RX_DTG (USBD_EPxCS bit 14) TX_DTG (USBD_EPxCS bit 6) The DTG bit and the SW_BUF bit are responsible f or the f low control. When a transfer completes, the USB peripheral toggle the DTG bit;...
Page 791 GD32F30x User Manual Af ter the transaction process is completed, an endpoint-specific interrupt is generated. In the interrupt routine, the application can process it accordingly. Transaction f ormatting is performed by the hardware, including CRC generation and checking. Once the endpoint is enabled, endpoint control and status register, buf fer address and COUNT f iled should not be modified by the application software.
Page 792 GD32F30x User Manual greater than actually allocated length, the excess data are not copied. This is a buffer overrun situation. A STALL handshake is sent, and this transaction fails. If an addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the ACK, according to the endpoint status and no data is written to the endpoint data buffers.
Page 793 GD32F30x User Manual the data transmission or reception of data in another buffer. The DTOG bit indicates which buf fer that the USB peripheral is currently using. The application software initializes the DTOG according to the first buffer to be used. At the end of each transaction, the RX_ST or TX_ST bit is set, depending on the enabled direction regardless of CRC errors or buffer-overrun conditions (if errors occur, the ERRIF bit will be set).
Page 794 GD32F30x User Manual ◼ A device in the non-configured state should draw a maximum of 100mA from the USB bus. ◼ A conf igured device can draw only up to what is specified in the Max Power field of the conf iguration descriptor.
Page 795 GD32F30x User Manual 2. Clear USBD_INTF register to remove any spurious pending interrupt. 3. Program USBD_BADDR register to set endpoint buffer base address. 4. Set USBD_CTL register to enable interrupts. 5. Wait f or the reset interrupt (RSTIF). 6. In the reset interrupt, initialize default control endpoint 0 to start enumeration process and program USBD_BADDR to set the device address to 0 and enable USB module function.
Page 796 GD32F30x User Manual 3. Wait f or successful transfer interrupt (STIF). 4. In the interrupt handler, application can get the transaction type by reading the STEUP bit in USBD_EPxCS register. Then application will read the data payload from the endpoint data buffer with the start address defined in USBD_EPxRBAR register. Last application will interpret the data and process the corresponding transaction.
Page 797 GD32F30x User Manual Registers definition 24.7. USBD base address: 0x4000 5C00 USBD control register (USBD_CTL) 24.7.1. Address offset: 0x40 Reset value: 0x0003 This register can be accessed by half-word (16-bit) or word (32-bit) L1RSRE STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE ESOFIE L1REQIE Reserved RSREQ...
Page 798 GD32F30x User Manual 1: Interrupt generated when SOFIF bit in USBD_INTF register is set. Expected start of frame interrupt enable ESOFIE 0: Expected start of frame interrupt disabled 1: Interrupt generated when ESOFIF bit in USBD_INTF register is set. LPM L1 state request interrupt enable L1REQIE 0: LPM L1 state request interrupt disabled 1: Interrupt generated when L1REQ bit in USBD_INTF register is set.
Page 799 GD32F30x User Manual 1: A reset generated. USBD interrupt flag register (USBD_INTF) 24.7.2. Address offset: 0x44 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) STIF PMOUIF ERRIF WKUPIF SPSIF RSTIF SOFIF ESOFIF L1REQ Reserved EPNUM[3:0] rc_w0 rc_w0...
Page 800 GD32F30x User Manual Reserved Must be kept at reset value Direction of transaction Set by the hardware to indicate the direction of the transaction 0: IN type 1: OUT type Endpoint Number EPNUM[3:0] Set by the hardware to identify the endpoint which the transaction is directed to USBD status register (USBD_STAT) 24.7.3.
Page 801 GD32F30x User Manual Bits Fields Descriptions 15:8 Reserved Must be kept at reset value USB device enable Set by software to enable the USB device USBEN 0: The USB device disabled. No transactions handled. 1: The USB device enabled. USBD device address After bus reset, the address is reset to USBDAR[6:0] 0x00.
Page 802: Table 24-4. Reception Status Encoding
GD32F30x User Manual Set by hardware when a successful OUT/SETUP transaction complete Cleared by software by writing 0 RX_DTG Reception data PID toggle This bit represent the toggle data bit (0=DATA0,1=DATA1)for non -isochronous endpoint Used to implement the flow control for double-buffered endpoint Used to swap buffer for isochronous endpoint 13:12 RX_STA[1:0]...
Page 803: Table 24-5. Endpoint Type Encoding
GD32F30x User Manual Table 24-5. Endpoint type encoding EP_CTL[1:0] Meaning BULK: bulk endpoint CONTROL: control endpoint ISO: isochronous endpoint INTERRUPT: interrupt endpoint Table 24-6. Endpoint kind meaning EP_KCTL[1:0] EP_KCTL Meaning BULK DBL_BUF CONTROL STATUS_OUT Table 24-7. Transmission status encoding TX_STA[1:0] Meaning DISABLED: ignore all transmission requests of this endpoint STALL: STALL handshake status...
Page 804 GD32F30x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved EPTXCNT[9:0] Bits Fields Descriptions 15:10 Reserved Must be kept at reset value EPTXCNT[9:0] Endpoint transmission byte count The number of bytes to be transmitted at next IN token USBD endpoint reception...
Page 805 GD32F30x User Manual Bits Fields Descriptions BLKSIZ Block size 0: block size is 2 bytes 1: block size is 32 bytes 14:10 BLKNUM[4:0] Block number The number of blocks allocated to the packet buffer EPRCNT[9:0] Endpoint reception byte count The number of bytes to be received at next OUT/SETUP token USBD LPM control and status register (USBD_LPMCS) 24.7.11.
Page 806 GD32F30x User Manual Universal serial bus full-speed interface (USBFS) The USBFS is available on GD32F305 and GD32F307 series. 25.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution f or portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol).
Page 807: Figure 25-1. Usbfs Block Diagram
GD32F30x User Manual 25.3. Block diagram Figure 25-1. USBFS block diagram interrupts AHB Slave Device bus Host Port control Control Data FIFO Transcation UTMI USB FS PHY Scheduler Control VBUS USB Clock USB Clock Domain 48MHz 25.4. Signal description Table 25-1. USBFS signal description I/O port Type Description...
Page 808: Figure 25-2. Connection With Host Or Device Mode
GD32F30x User Manual Figure 25-2. Connection with host or device mode 5V Power Supply GPIO (needed in host mode) VBUS VBUS When USBFS works in host mode (FHM bit is set and FDM bit is cleared), the VBUS is 5V power, and detecting pin which is using for voltage detection is defined in USB protocol.
Page 809: Figure 25-3. Connection With Otg Mode
GD32F30x User Manual Figure 25-3. Connection with OTG mode 5V Power GPIO Supply VBUS VBUS USB host function 25.5.2. USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state.
Page 810 GD32F30x User Manual PRST bit is used f or USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset. This bit only takes effect when port is at connected or enabled state.
Page 811 GD32F30x User Manual USB transaction request or a channel operation request. Application needs to write packet into data FIFO via AHB register interface if it wants to start an OUT transaction on USB bus. USBFS hardware will automatically generate a transaction request entry in request queue after the application wrote a whole packet.
Page 812 GD32F30x User Manual a resume signal on USB bus. When USBFS detects the resume signal, the WKUPIF flag in USBFS_GINTF register will be set and the USBFS wake up interrupt will be triggered. In suspend mode, USBFS is also able to remotely wake up the USB bus. Software may set RWKUP bit in USBFS_DCTL register to send a remote wake-up signal, and if remote wake- up is supported in USB host, the host will begin to send resume signal on USB bus.
Page 813 GD32F30x User Manual Micro-B plug for device) is inserted. By utilizing the Host Negotiation Protocol (HNP), an On- The-Go B-Device, which is the default device, may make a request to be a host. The process f or changing the role to be a host is described in this section. This protocol eliminates the necessity of switching the cable connection for the roles change of the connected devices.
Page 814: Figure 25-5. Host Mode Fifo Space In Sram
GD32F30x User Manual Figure 25-5. HOST mode FIFO space in SRAM USBFS provides a special register area f or the internal data FIFO reading and writing. Figure 25-6. Host mode FIFO access register map describes the register memory area that the data FIFO can access.
Page 815: Figure 25-7. Device Mode Fifo Space In Sram
GD32F30x User Manual Figure 25-7. Device mode FIFO space in SRAM Start: 0x00 Rx FIFO RXFD IEPTX0RSAR[15:0] Tx FIFO0 IEPTX0FD IEPTX1RSAR[15:0] IEPTX1FD Tx FIFO1 IEPTX3RSAR[15:0] IEPTX3FD Tx FIFO3 End: 0x13F USBFS provides a special register area for the internal data FIFO reading and writing. Figure 25-8.
Page 816 GD32F30x User Manual Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the TxFIFO’s empty threshold, etc. GINTEN bit should be kept cleared at this time. 2. Program USBFS_GUSBCS register according to application’s demand, such as the operation mode (host, device or OTG) and some parameters of OTG and USB protocols.
Page 817 GD32F30x User Manual Sof tware can disable the channel by setting both CEN and CDIS bits at the same time. USBFS will generate a channel disable request entry in request queue af ter the register setting operation. When the request entry reaches the top of request queue, it will be processed by USBFS immediately: For OUT channels, the specified channel will be disabled immediately.
Page 818 GD32F30x User Manual 4. When the request entry reaches the top of the request queue, USBFS begins to process this request entry. If bus time for the transaction indicated by the request entry is enough, USBFS starts the OUT transaction on USB bus. 5.
Page 819 GD32F30x User Manual enable bits. 3. Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register. PCNT is the number of packets in a transfer and TLEN is the total byte number of all the transmitted or received packets in a transfer. For IN endpoint：If PCNT=1, the single packet’s size is equal to TLEN. If PCNT>1, the f ormer PCNT-1 packets are considered as max-packet-length packets whose size are def ined by MPL f ield in USBFS_DIEPxCTL register, and the last packet’s size is calculated based on PCNT, TLEN and MPL.
Page 820: Table 25-2. Usbfs Global Interrupt
GD32F30x User Manual FIFO successfully and sends ACK handshake on USB bus), PCNT in USBFS_DOEPxLEN register is decreased by 1 and the ACK flag is triggered, otherwise, the status flags report the transaction result. 4. After all the data packets in a transfer are successfully received on USB bus, USBFS pushes a TF status entry into the Rx FIFO on top of the last packet data.
Page 821 GD32F30x User Manual Interrupt Flag Description Operation Mode OTGIF OTG interrupt flag Host or device mode MFIF Mode fault interrupt flag Host or device mode Wake-up interrupt can be triggered when USBFS is in suspend state, even if when the USBFS’s clocks are stopped.
Page 822 GD32F30x User Manual 25.7. Register definition USBFS base address: 0x5000 0000 Global control and status registers 25.7.1. Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 823 GD32F30x User Manual protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes. 15:12 Reserved Must be kept at reset value...
Page 824 GD32F30x User Manual Note: Only accessible in device mode. SRPS SRP success This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP fails 1: SRP succeeds Note: Only accessible in device mode. Global OTG interrupt flag register (USBFS_GOTGINTF) Address offset: 0x0004 Reset value: 0x0000 0000...
Page 825 GD32F30x User Manual Set by the core when a HNP ends. Read the HNPS in USBFS_GOTGCS register to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP.
Page 826 GD32F30x User Manual empty Host mode: 0: NPTXFEIF will be triggered when the non-periodic transmit FIFO is half empty 1: NPTXFEIF will be triggered when the non-periodic transmit FIFO is completely empty 6：1 Reserved Must be kept at reset value GINTEN Global interrupt enable 0: Global interrupt is not enabled .
Page 827 GD32F30x User Manual pin. 0: Normal mode 1: Host mode The application must wait at least 25 ms for the change taking effect after setting the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value 13:10 UTT[3:0] USB turnaround time...
Page 828 GD32F30x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non -periodic Tx FIFO is flushed 00001: Only periodic Tx FIFO is flushed 1XXXX: Both periodic and non-periodic Tx FIFOs are flushed Other: Non data FIFO is flushed...
Page 829 GD32F30x User Manual Set by the application to reset AHB clock domain circuit. Hardware automatically clears this bit after the reset process completes. After setting this bit, application should wait until this bit is cleared before any other operation on USBFS. Note: Accessible in both device and host modes.
Page 830 GD32F30x User Manual Reserved Must be kept at reset value PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the periodic transmit FIFO is either half or completely empty. The threshold is determined by the periodic Tx FIFO emp ty level bit (PTXFTH) in the USBFS_GAHBCS regis ter.
Page 831 GD32F30x User Manual IEPIF IN endpoint interrupt flag Set by USBFS when one of the IN endpoints in device mode has raised an interrupt. Software should first read USBFS_DAEPINT register to get the device number, and then read the corresponding USBFS_DIEPxINTF register to get the flags of the endpoint that cause the interrupt.
Page 832 GD32F30x User Manual Note: Only accessible in device mode. NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the non-periodic transmit FIFO is either half or completely empty. The threshold is determined by the non-periodic Tx FIFO empty level bit (TXFTH) in the USBFS_GAHBCS register.
Page 833 GD32F30x User Manual This register has to be accessed by word (32-bit) Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable wakeup interrupt 1: Enable wakeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes.
Page 834 GD32F30x User Manual HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value PXNCIE Periodic transfer not complete Interrupt enable 0: Disable periodic transfer not complete interrupt 1: Enable periodic transfer not complete interrupt Note: Only accessible in host mode.
Page 835 GD32F30x User Manual RSTIE USB reset interrupt enable 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode. SPIE USB suspend interrupt enable 0: Disable USB suspend interrupt 1: Enable USB suspend interrupt Note: Only accessible in device mode. ESPIE Early suspend interrupt enable 0: Disable early suspend interrupt...
Page 836 GD32F30x User Manual 1: Enable mode fault interrupt Note: Accessible in both device and host modes. Reserved Must be kept at reset value Global receive status read/receive status read and pop registers (USBFS_GRSTATR/USBFS_GRSTATP) Address offset for Read: 0x001C Address offset for Pop: 0x0020 Reset value: 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO.
Page 837 GD32F30x User Manual 10: DATA1 Others: Reserved 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to which the current received packet belongs. Device mode: Bits Fields Descriptions 31:21 Reserved Must be kept at reset value 20:17 RPCKST[3:0]...
Page 838 GD32F30x User Manual Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit words.
Page 839 GD32F30x User Manual Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit words. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx RAM start address The start address for non -periodic transmit FIFO RAM is in term of 32-bit words. Device Mode: Bits Fields...
Page 840 GD32F30x User Manual Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token – 01: Zero-length OUT packet – 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 NPTXRQS[7:0] Non-periodic Tx request queue space The remaining space of the non-periodic transmit request queue.
Page 841 GD32F30x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value VBUSIG ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and always consider V voltage as valid both in host mode and in device mode, then free the V pin for other usage.
Page 842 GD32F30x User Manual Bits Fields Descriptions Core ID Software can write or read this field and uses this field as a unique ID for its 31:0 application Host periodic transmit FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word 32-bit) r/rw r/rw...
Page 843 GD32F30x User Manual r/rw r/rw Bits Fields Descriptions 31:16 IEPTXFD[15:0] IN endpoint Tx FIFO depth In terms of 32-bit words. 1≤HPTXFD≤1024 15:0 IEPTXRSAR[15:0] IN endpoint FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32-bit words. Host control and status registers 25.7.2.
Page 844 GD32F30x User Manual 31:2 Reserved Must be kept at reset value CLKSEL Clock select for usbclock. 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the f rame interval for the current enumerating speed when USBFS controller is enumerating.
Page 845 GD32F30x User Manual Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks . 15:0 FRNUM[15:0] Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF.
Page 846 GD32F30x User Manual Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 PTXREQS[7:0] Periodic Tx request queue space The remaining space of the periodic transmit request queue. 0: Request queue is Full 1: 1 entry 2 entries...
Page 847 GD32F30x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN) Address offset: 0x0418 Reset value: 0x0000 0000 This register can be used by sof tware to enable or disable a channel’s interrupt.
Page 848 GD32F30x User Manual This register has to be accessed by word (32-bit) rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value 18:17 Port speed Report the enumerated speed of the device attached to this port. 01: Full speed 10: Low speed Others: Reserved...
Page 849 GD32F30x User Manual stops sending SOF tokens. This bit can only be cleared by the following operations: – PRST bit in this register is set by application – PREM bit in this register is set – A remote wakeup signal is detected –...
Page 850 GD32F30x User Manual EPTYPE[1:0] Bits Fields Descriptions Channel enable Set by the application and cleared by USBFS. 0: Channel disabled 1: Channel enabled Software should following the operation guide to disable or enable a channel. CDIS Channel disable Software can set this bit to disable the channel from processing transactions . Software should follow the operation guide to disable or enable a channel.
Page 851 GD32F30x User Manual The transfer direction of the endpoint that this channel wants to communicate with. 0: OUT 1: IN 14:11 EPNUM Endpoint number The number of the endpoint that this channel wants to communicate with. 10:0 Maximum packet length The target endpoint’s maximum packet length.
Page 852 GD32F30x User Manual maximum packet length. USBER USB Bus Error The USB error flag is set when the following conditions occurs during receiving a packet: – A received packet has a wrong CRC field – A stuff error detected on USB bus –...
Page 853 GD32F30x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value DTERIE Data toggle error interrupt enable 0: Disable data toggle error interrupt 1: Enable data toggle error interrupt REQOVRIE Request queue overrun interrupt enable 0: Disable request queue overrun interrupt 1: Enable request queue overrun interrupt BBERIE Babble error interrupt enable...
Page 854 GD32F30x User Manual 1: Enable transfer finished interrupt Host channel-x transfer length register (USBFS_HCHxLEN) (x = 0..7, where x = channel number) Address offset: 0x0510 + (channel_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 855 GD32F30x User Manual to be transmitted in an OUT transfer. Software should program this field before the channel is enabled. When software successfully writes a packet into the channel’s data TxFIFO, this field is decreased by the byte size of the packet. For IN transfer each time software or DMA reads out a pack et from the RxFIFO, this field is decreased by the byte size of the packet.
Page 856 GD32F30x User Manual Reserved Must be kept at reset value NZLSOH Non-zero-length status OUT handshake When a USB device receives a non -zero-length data packet during status OUT stage, this field controls that either USBFS should receive this packet or reject this packet with a STALL handshake.
Page 857 GD32F30x User Manual USBFS_GINTF register triggered after a while. Software should clear the GONAK flag before writing this bit again. CGINAK Clear global IN NAK Software sets this bit to clear GINS bit in this register. SGINAK Set global IN NAK Software sets this bit to set GINS bit in this register.
Page 858 GD32F30x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value 21:8 FNRSOF[13:0] The frame number of the received SOF. USBFS always update this field after receiving a SOF token Reserved Must be kept at reset value ES[1:0] Enumerated speed This field reports the enumerated device speed.
Page 859 GD32F30x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value IEPNEEN IN endpoint NAK effective interrupt enable bit 0: Disable IN endpoint NAK effective interrupt 1: Enable IN endpoint NAK effective interrupt Reserved Must be kept at reset value EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 0: Disable endpoint Tx FIFO underrun interrupt...
Page 860 GD32F30x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value BTBSTPEN Back-to-back SETUP packets (Only for control OUT endpoint) interrupt enable bit 0: Disable back-to-back SETUP packets interrupt 1: Enable back-to-back SETUP packets interrupt Reserved Must be kept at reset value EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable bit 0: Disable endpoint Rx FIFO overrun interrupt...
Page 861 GD32F30x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value 19:16 OEPITB[3:0] Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value...
Page 862 GD32F30x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value 19:16 OEPIE[3:0] Out endpoint interrupt enable 0: Disable OUT endpoint-n interrupt 1: Enable OUT endpoint-n interrupt Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value...
Page 863 GD32F30x User Manual Device VBUS pulsing time register (USBFS_DVBUSPT) Address offset: 0x082C Reset value: 0x0000 05B8 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DVBUSPT[11:0] Device V pulsing time This field defines the pulsing time for V The true pulsing time is...
Page 864 GD32F30x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register. Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 0: Disable FIFO empty interrupt 1: Enable FIFO empty interrupt...
Page 865 GD32F30x User Manual 29:28 Reserved Must be kept at reset value SNAK Set NAK Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register. 25:22 TXFNUM[3:0] Tx FIFO number Defines the Tx FIFO number of IN endpoint 0.
Page 866 GD32F30x User Manual Device IN endpoint-x control register (USBFS_DIEPxCTL) (x = 1..3, where x = endpoint_number) Address offset: 0x0900 + (endpoint_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS.
Page 867 GD32F30x User Manual Software sets this bit to clear NAKS bit in this register. 25:22 TXFNUM[3:0] Tx FIFO number Defines the Tx FIFO number of this IN endpoint. STALL STALL handshake Software can set this bit to make USBFS sends STALL handshake when receiving IN token.
Page 868 GD32F30x User Manual 1: Data packet’s PID is DATA1 EPACT Endpoint active This bit controls whether this endpoint is active. If an endpoint is not active, it ignores all tokens and doesn’t make any response. 14:11 Reserved Must be kept at reset value 10:0 MPL[10:0] This field defines the maximum packet length in bytes.
Page 869 GD32F30x User Manual STALL STALL handshake Set this bit to make USBFS send STALL handshake during an OUT transaction. USBFS will clear this bit after a SETUP token is received on OUT endpoint 0. This bit has a higher priority than NAKS bit in this register, i.e. if both STALL and NAKS bits are set, the STALL bit takes effect.
Page 870 GD32F30x User Manual This register has to be accessed by word (32-bit) rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint.
Page 871 GD32F30x User Manual transaction. This bit has a higher priority than NAKS bit in this register and GINAK in USBFS_DCTL register. If both STALL and NAKS bits are set, the STALL bit takes effect. For control OUT endpoint: Only USBFS can clear this bit when a SETUP token is received on the corresponding OUT endpoint.
Page 872 GD32F30x User Manual ignores all tokens and doesn’t make any response. 14:11 Reserved Must be kept at reset value 10:0 MPL[10:0] This field defines the maximum packet length in bytes. Device IN endpoint-x interrupt flag register (USBFS_DIEPxINTF) (x = 0..3, where x = endpoint_number) Address offset: 0x0908 + (endpoint_number ×...
Page 873 GD32F30x User Manual incoming CITO Control IN Timeout interrupt This flag is triggered if the device waiting for a handshake is timeout in a control IN transaction. Reserved Must be kept at reset value EPDIS Endpoint disabled This flag is triggered when an endpoint is disabled by the software’s request. Transfer finished This flag is triggered when all the IN transactions assigned to this endpoint have been finished.
Page 874 GD32F30x User Manual This flag is triggered if the OUT endpoint’s Rx FIFO has no enough space for a packet data when an OUT token is incoming. USBFS will drop the incoming OUT data packet and sends a NAK handshake in this case. STPF SETUP phase finished (Only for control OUT endpoint) This flag is triggered when a setup phase finished, i.e.
Page 875 GD32F30x User Manual The total data byte number of a transfer. This field is the total data bytes of all the data packets desired to be transmitted in an IN transfer. Program this field before the endpoint is enabled. When software successfully writes a packet into the endpoint’s Tx FIFO, this field is decreased by the byte size of the packet.
Page 876 GD32F30x User Manual on bus. 18:7 Reserved Must be kept at reset value TLEN[6:0] Transfer length The total data byte number of a transfer. This field is the total data bytes of all the data packets desired to receive in an OUT transfer.
Page 877 GD32F30x User Manual transmission. 18:0 TLEN[18:0] Transfer length The total data byte number of a transfer. This field is the total data bytes of all the data packets desired to be transmitted in an IN transfer. Program this field before the endpoint is enabled. When software successfully writes a packet into the endpoint’s Tx FIFO, this field is decreased by the byte size of the packet.
Page 878 GD32F30x User Manual 10: 2 packets 11: 3 packets 28:19 PCNT[9:0] Packet count The number of data packets desired to receive in a transfer . Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet reception on bus.
Page 879 GD32F30x User Manual n: n words available Power and clock control register (USBFS_PWRCLKCTL) 25.7.4. Address offset: 0x0E00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:2 Reserved Must be kept at reset value SHCLK Stop HCLK Stop the HCLK to save power.
Page 880: Table 26-1. Revision History
GD32F30x User Manual Revision history Table 26-1. Revision history Revision No. Description Date Initial Release Feb.10, 2017 Revise ADC/DAC/DMA/RCU/USART Oct. 17, 2017 Adapt To New Document Specification Dec.14, 2018 Add Operation process of ADC Temperature Sensor, Jun.10, 2019 refer to Temperature sensor, and internal reference voltage VREFINT In PMU chapter 3.3, update block diagram of PMU, refers to Figure 3-1.
Page 881 GD32F30x User Manual the description of bits[9:8], refers to Channel control register 0 (TIMERx_CHCTL0) and Channel control register 1 (TIMERx_CHCTL1), TIMERx(x = 8.11) registers modified, refers to Channel control register 0 (TIMERx_CHCTL0), TIMERx(x = 0~4,7,8,11) registers, modify the description of bits[2:0], refers to Slave mode configuration register (TIMERx_SMCFG) In PMU chapter 3.3.2 VDDA domain, when the value of VDDA and VDD is different, VDDA should be no more...
Page 882 GD32F30x User Manual Delete bit field of TRACE_MODE Modify context from ADC to ADCs in the system diagram Modify flash range of GD32F30X_HD from 128KB to 512KB Add product of GD32F303xB, modify density range of GD32F30X_HD from 128KB to 512KB Consistency update of Clock trim controller (CTC) chapter Modify description of SPI AF remap...
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