GigaDevice Semiconductor GD32F3x0 User Manual

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GigaDevice Semiconductor Inc.

GD32F3x0

Arm

Cortex

-M4 32-bit MCU

User Manual

Revision 2.6

(Jun. 2022)

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Page 1 GigaDevice Semiconductor Inc. GD32F3x0 ® ® Cortex -M4 32-bit MCU User Manual Revision 2.6 (Jun. 2022)
Page 2: Table Of Contents
GD32F3x0 User Manual Table of Contents Table of Contents ......................2 List of Figures ......................15 List of Table ........................21 1. System and memory architecture ................ 23 ® ® -M4 processor ..................23 1.1. Cortex System architecture ....................... 24 1.2.
Page 3 GD32F3x0 User Manual 2.3.9. Option byte description ......................47 2.3.10. Page erase/Program protection .................... 48 2.3.11. Security protection ........................ 49 2.4. Register definition......................50 2.4.1. Wait state register (FMC_WS) ....................50 2.4.2. Unlock key register (FMC_KEY) ................... 50 2.4.3. Option byte unlock key register (FMC_OBKEY) ..............51 2.4.4.
Page 4 GD32F3x0 User Manual 4.3.7. APB2 enable register (RCU_APB2EN) ................91 4.3.8. APB1 enable register (RCU_APB1EN) ................92 4.3.9. Backup domain control register (RCU_BDCTL) ..............94 4.3.10. Reset source /clock register (RCU_RSTSCK) ..............96 4.3.11. AHB reset register (RCU_AHBRST)..................97 4.3.12.
Page 5 GD32F3x0 User Manual 6.6.6. Pending register (EXTI_PD) ....................123 7. General-purpose and alternate-function I/Os (GPIO) ........125 7.1. Overview ........................125 Characteristics ......................125 7.2. Function overview......................125 7.3. 7.3.1. GPIO pin configuration ....................... 126 7.3.2. Alternate functions (AF) ...................... 127 7.3.3.
Page 6 GD32F3x0 User Manual 9. Direct memory access controller (DMA) ............149 9.1. Overview ........................149 9.2. Characteristics ......................149 Block diagram ......................150 9.3. Function overview......................150 9.4. 9.4.1. DMA operation ........................150 9.4.2. Peripheral handshake ......................152 9.4.3. Arbitration ..........................152 9.4.4.
Page 7 GD32F3x0 User Manual 11.4.1. Foreground calibration function ..................172 11.4.2. Dual clock domain architecture ................... 173 11.4.3. ADCON enable ........................173 11.4.4. Routine sequence ....................... 173 11.4.5. Operation modes ........................ 173 11.4.6. Conversion result threshold monitor function ..............176 11.4.7.
Page 8 GD32F3x0 User Manual 12.4.2. Software trigger register (DAC_SWT) ................199 12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH) ..........200 12.4.4. DAC 12-bit left-aligned data holding register(DAC_L12DH) ..........200 12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH) ..........201 12.4.6. DAC data output register (DAC_DO) .................. 201 12.4.7.
Page 9 GD32F3x0 User Manual 15.3.8. RTC shift function ....................... 227 15.3.9. RTC reference clock detection ................... 228 15.3.10. RTC smooth digital calibration .................... 229 15.3.11. Time-stamp function ......................231 15.3.12. Tamper detection ........................ 231 15.3.13. Calibration clock output ...................... 232 15.3.14. Alarm output ........................232 15.3.15.
Page 10 GD32F3x0 User Manual 16.3.3. Block diagram ........................348 16.3.4. Function overview ....................... 349 16.3.5. Register definition ....................... 356 16.4. General level3 timer (TIMERx, x=14) ..............366 16.4.1. Overview ..........................366 16.4.2. Characteristics ........................366 16.4.3. Block diagram ........................367 16.4.4.
Page 11 GD32F3x0 User Manual 18.3.12. Smartcard (ISO7816-3) mode .................... 459 18.3.13. ModBus communication ..................... 461 18.3.14. Receive FIFO ........................462 18.3.15. Wakeup from deep-sleep mode ..................462 18.3.16. USART interrupts ........................ 463 Register definition ....................465 18.4. 18.4.1. Control register 0 (USART_CTL0) ..................465 18.4.2.
Page 12 GD32F3x0 User Manual 19.4.7. Transfer status register 1 (I2C_STAT1) ................508 19.4.8. Clock configure register (I2C_CKCFG) ................509 19.4.9. Rise time register (I2C_RT) ....................510 19.4.10. Fast-mode-plus configure register(I2C_FMPCFG)............. 510 Serial peripheral interface/Inter-IC sound (SPI/I2S) ........512 20.1. Overview ........................512 20.2.
Page 13 GD32F3x0 User Manual 21.3. Function overview ....................554 21.3.1. CEC bus pin ........................554 21.3.2. Message description ......................555 21.3.3. Bit timing description ......................556 21.3.4. Arbitration ..........................557 21.3.5. SFT option bit description ....................558 21.3.6. Error definition........................558 21.3.7.
Page 14 GD32F3x0 User Manual Universal serial bus full-speed interface (USBFS) ......... 589 23.1. Overview ........................589 23.2. Characteristics ......................589 Block diagram ......................590 23.3. Signal description ....................590 23.4. Function overview ....................590 23.5. 23.5.1. USBFS clocks and working modes..................590 23.5.2.
Page 15: List Of Figures
® -M4 processor..............24 Figure 1-1. The structure of the Cortex Figure 1-2. Series system architecture of GD32F3x0 series ............25 Figure 2-1. Process of page erase operation .................. 43 Figure 2-2. Process of the mass erase operation ................44 Figure 2-3.
Page 16 GD32F3x0 User Manual Figure 13-1. CMP block diagram of GD32F3x0 series ..............204 Figure 13-2. CMP hysteresis ......................205 Figure 14-1. Free watchdog timer block diagram................. 211 Figure 14-2. Window watchdog timer block diagram ..............217 Figure 14-3. Window watchdog timer timing diagram ..............218 Figure 15-1.
Page 17 GD32F3x0 User Manual Figure 16-39. EAPWM timechart ....................... 318 Figure 16-40. CAPWM timechart ....................... 318 Figure 16-41. Restart mode ........................ 320 Figure 16-42. Pause mode ........................320 Figure 16-43. Event mode ........................320 Figure 16-44. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 ....... 322 Figure 16-45.
Page 18 GD32F3x0 User Manual Figure 16-83. Timing chart of up counting mode, PSC=0/2 ............437 Figure 16-84. Timing chart of up counting mode, change TIMERx_CAR on the go ... 437 Figure 17-1. IFRP output timechart 1 ....................444 Figure 17-2. IFRP output timechart 2 ....................445 Figure 17-3.
Page 19 GD32F3x0 User Manual Figure 20-8. Timing diagram of TI master mode with discontinuous transfer ..... 520 Figure 20-9. Timing diagram of TI master mode with continuous transfer ......520 Figure 20-10. Timing diagram of TI slave mode ................521 Figure 20-11. Timing diagram of NSS pulse with continuous transmit ........522 Figure 20-12.
Page 20 GD32F3x0 User Manual CHLEN=0, CKPL=0) ........................534 Figure20-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ........................535 Figure 20-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ........................535 Figure 20-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ........................
Page 21: List Of Table
GD32F3x0 User Manual List of Table Table 1-1. Memory map of GD32F3x0 series ................... 26 Table 1-2. Flash module organization ....................29 Table 1-3. Boot modes .......................... 30 Table 2-1. Base address and size for flash memory ..............41 Table 2-2. Option byte ..........................47 Table 2-3.
Page 22 GD32F3x0 User Manual Table 18-3. USART interrupt requests ..................... 463 Table 19-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) ........................... 484 Table 19-2. Event status flags......................499 Table 19-3. Error flags ......................... 499 Table 20-1. SPI signal description ....................513 Table 20-2.
Page 23: System And Memory Architecture
GD32F3x0 User Manual System and memory architecture ® The GD32F3x0 series are 32-bit general-purpose microcontrollers based on the Arm ® ® Cortex -M4 processor. The Cortex -M4 processor includes three AHB buses known as ® I-Code, D-Code and System buses. All memory accesses of the Cortex...
Page 24: System Architecture
1.2. System architecture The system architecture of GD32F3x0 series is shown in the Figure 1-2. Series system architecture of GD32F3x0 series (For system architecture of the specific device, please refer to the datasheet of the corresponding device). The AHB matrix based on AMBA 3.0 AHB-LITE is a multi-layer AHB, which enables parallel access paths between multiple masters and slaves in the system.
Page 25: Memory Map
GD32F3x0 User Manual Figure 1-2. Series system architecture of GD32F3x0 series 1.2V TPIU GPIO Ports AHB2: Fma x = 108MHz POR/PDR A, B, C, D, F ARM Cortex-M4 Processor SRAM SRAM : 108MHz Controller IBus Flash : 108MHz Touch Flash...
Page 26: Table 1-1. Memory Map Of Gd32F3X0 Series
Table 1-1. Memory map of GD32F3x0 series shows the memory map of GD32F3x0 series, including Code, SRAM, peripheral, and other pre-defined regions (For the memory map of the specific device, please refer to the data sheet of the corresponding device). Each peripheral of either type is allocated 1KB of space. This allows simplifying the address decoding for each peripheral.
Page 27 GD32F3x0 User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 3000 - 0x4001 33FF SPI0/I2S0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF 0x4001 0800 - 0x4001 23FF Reserved 0x4001 0400 - 0x4001 07FF...
Page 28: Bit-Banding
1.3.2. On-chip SRAM memory The GD32F3x0 series contain up to 16KB of on-chip SRAM which starts at the address 0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) access. In order to increase memory robustness, parity check is supported. The user can enable the parity check function using the bit SRAM_PARITY_CHECK in the user option byte (refer to Chapter 2.3.9...
Page 29: On-Chip Flash Memory
1.4. Boot configuration The GD32F3x0 series provide three kinds of boot sources which can be selected using the bit BOOT1_n in the user option byte (refer to Chapter 2.3.9 Option byte description) and the BOOT0 pin.
Page 30: I / O Compensation Cell
GD32F3x0 User Manual Table 1-3. Boot modes Boot mode selection pins Selected boot source Boot1 Boot0 Main Flash Memory System Memory On-chip SRAM 1. The Boot1 value is the opposite of the BOOT1_n value. ® ® After power-on sequence or a system reset, the Arm...
Page 31: System Configuration Registers (Syscfg)
GD32F3x0 User Manual 1.6. System configuration registers (SYSCFG) SYSCFG base address: 0x4001 0000 1.6.1. System configuration register 0 (SYSCFG_CFG0) Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the BOOT1_n option bit after reset).
Page 32: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32F3x0 User Manual USART0_TX_DMA_ USART0_TX DMA request remapping enable 0: Not remap (USART0_TX DMA requests are mapped on DMA channel 1) 1: Remap (USART0_TX DMA requests are mapped on DMA channel 3) ADC_DMA_RMP ADC DMA request remapping enable 0: Not remap (ADC DMA requests are mapped on DMA channel 0)
Page 33: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32F3x0 User Manual X010: PC2 pin X011: PD2 pin X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI1_SS[3:0] EXTI 1 sources selection X000: PA1 pin X001: PB1 pin X010: PC1 pin X011: Reserved X100: Reserved X101: PF1 pin X110: Reserved...
Page 34: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32F3x0 User Manual X001: PB7 pin X010: PC7 pin X011: Reserved X100: Reserved X101: PF7 pin X110: Reserved X111: Reserved 11:8 EXTI6_SS[3:0] EXTI 6 sources selection X000: PA6 pin X001: PB6 pin X010: PC6 pin X011: Reserved X100: Reserved X101: PF6 pin...
Page 35 GD32F3x0 User Manual Reserved EXTI11_SS [3:0] EXTI10_SS [3:0] EXTI9_SS [3:0] EXTI8_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI11_SS[3:0] EXTI 11 sources selection X000: PA11 pin X001: PB11 pin X010: PC11 pin X011: Reserved...
Page 36: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32F3x0 User Manual X101: Reserved X110: Reserved X111: Reserved 1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0]...
Page 37: System Configuration Register 2 (Syscfg_Cfg2)
GD32F3x0 User Manual X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI12_SS[3:0] EXTI 12 sources selection X000: PA12 pin X001: PB12 pin X010: PC12 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved 1.6.6. System configuration register 2 (SYSCFG_CFG2)
Page 38: I / O Compensation Control Register (Syscfg_Cpsctl)
GD32F3x0 User Manual LVDEN and LVDT[2:0] in the PMU_CTL register are read only. SRAM_PARITY_ SRAM parity check error lock ERROR_LOCK This bit is set by software and cleared by a system reset. 0: The SRAM parity check error is disconnected from the break input of TIMER0 /...
Page 39: Device Electronic Signature
GD32F3x0 User Manual 1.7. Device electronic signature The device electronic signature contains memory density information and the 96-bit unique device ID. It is stored in the information block of the Flash memory. The 96-bit unique device ID is unique for any device. It can be used as serial numbers, or part of security keys, etc.
Page 40 GD32F3x0 User Manual 31:0 UNIQUE_ID[31:0] Unique device ID Base address: 0x1FFF F7B0 The value is factory programmed and can never be altered by user. This register has to be accessed by word (32-bit). UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32]...
Page 41: Flash Memory Controller (Fmc)
GD32F3x0 User Manual Flash memory controller (FMC) 2.1. Overview The Flash Memory Controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time within 64K bytes while CPU executes instruction. It also provides page erase, mass erase, and word / half-word / bit program for operations for flash memory.
Page 42: Read Operations
GD32F3x0 User Manual The Information Block stores the bootloader - this block cannot be programmed or Note: erased by user. 2.3.2. Read operations The flash can be addressed directly as a common memory space. Any instruction fetch and the data access from the flash are through the IBUS or DBUS from the CPU.
Page 43: Mass Erase
GD32F3x0 User Manual moment, if the ENDIE bit in the FMC_CTL register is set, an interrupt will be triggered by FMC. It is notable that a correct target page address must be confirmed, otherwise the software may run out of control if the incorrect target erase page is being used for fetching codes or accessing data.
Page 44: Figure 2-2. Process Of The Mass Erase Operation
GD32F3x0 User Manual Send the mass erase command to the FMC by setting the START bit in FMC_CTL register. Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_STAT register. Read and verify the flash memory by using a DBUS access if necessary.
Page 45: Main Flash Programming
GD32F3x0 User Manual 2.3.6. Main flash programming The FMC provides a 32-bit word / 16-bit half word / bit programming function which is used to modify the main flash memory contents. The following steps show the word programming operation register access sequence.
Page 46: Option Byte Erase
GD32F3x0 User Manual Figure 2-3. Process of the word programming operation Start Is the LK bit 0 Unlock the FMC_CTL Is the BUSY bit 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit 0 Finish 2.3.7.
Page 47: Option Byte Programming
GD32F3x0 User Manual 2.3.8. Option byte programming The FMC provides a 16-bit half word programming function which is used for modifying the option byte block contents. The following steps show the programming operation sequence. Unlock the FMC_CTL register if necessary.
Page 48: Page Erase/Program Protection
GD32F3x0 User Manual Address Name Description kept if unnecessary 1: Enable VDDA monitor, specific function refer to PMU section [4]: BOOT1_n 0: BOOT1 bit is 1 1: BOOT1 bit is 0 [3]: Reserved [2]: nRST_STDBY 0: Generate a reset when system try to enter in standby...
Page 49: Security Protection
GD32F3x0 User Manual Table 2-3. OB_WP bit for pages protected OB_WP bit pages protected OB_WP[0] page 0 ~ page 3 OB_WP[1] page 4 ~ page 7 OB_WP[2] page 8 ~ page 11 OB_WP[14] page 56 ~ page 59 OB_WP[15] page 60 ~ page 127 2.3.11.
Page 50: Register Definition
GD32F3x0 User Manual 2.4. Register definition Base address: 0x4002 2000 2.4.1. Wait state register (FMC_WS) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value...
Page 51: Option Byte Unlock Key Register (Fmc_Obkey)
GD32F3x0 User Manual 2.4.3. Option byte unlock key register (FMC_OBKEY) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_CTL option byte operation unlock registers These bits are only be written by software Write OBKEY [31:0] with key to unlock option byte command in FMC_CTL register.
Page 52: Control Register (Fmc_Ctl)
GD32F3x0 User Manual BPEN = 1, no program error will be generated). The software can clear it by writing Reserved Must be kept at reset value BUSY The flash busy bit When the operation is in progress, this bit is set to 1. When the operation is end or an error generated, this bit is clear to 0.
Page 53: Address Register (Fmc_Addr)
GD32F3x0 User Manual FMC_CTL lock bit This bit is cleared by hardware when right sequent written to FMC_KEY register. This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared.
Page 54: Option Byte Status Register (Fmc_Obstat)
GD32F3x0 User Manual Bits Fields Descriptions 31:0 ADDR[31:0] Flash command address bits These bits are set by software. ADDR bits are the address of flash erase command 2.4.7. Option byte status register (FMC_OBSTAT) Address offset: 0x1C Reset value: 0xXXXX XX0X This register has to be accessed by word (32-bit).
Page 55: Wait State Enable Register (Fmc_Wsen)
GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 OB_WP[15:0] Store OB_WP[15:0] of option byte block after system reset 0: Protection active 1: Unprotected 2.4.9. Wait state enable register (FMC_WSEN) Address offset: 0xFC Reset value: 0x0000 0000...
Page 56 GD32F3x0 User Manual PID[31:16] PID[15:0] Bits Fields Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by software. These bits are unchanged constantly after power on. These bits are one time programmed when the chip product.
Page 57: Power Management Unit (Pmu)
The power consumption is regarded as one of the most important issues for the devices of GD32F3x0 series. The Power management unit (PMU), provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 58: Backup Domain
GD32F3x0 User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD PB15 WKUPN NRST WKUPF SLEEPING Cortex-M4 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain...
Page 59: Dd Dda Power Domain
GD32F3x0 User Manual lines to achieve the RTC timer wakeup event. After entering the power saving mode for a certain amount of time, the RTC alarm will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the...
Page 60: Figure 3-3. Waveform Of The Lvd Threshold
GD32F3x0 User Manual Figure 3-2. Waveform of the POR / PDR 600mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register (PMU_CTL). The LVD...
Page 61: Power Domain
IRC8M or HXTAL selected as system clock. The high-driver mode exit automatically when exiting from Deep-sleep mode. 3.3.4. Power saving modes After a system reset or a power reset, the GD32F3x0 MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing...
Page 62 GD32F3x0 User Manual down the system clocks (HCLK, PCLK1, PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL register. The LDOVS bits should be configured only when the PLLs is off, and the programmed value is selected to drive 1.2V domain after the PLL opened.
Page 63: Table 3-1. Power Saving Mode Summary
GD32F3x0 User Manual LDEN to 00 in the PMU_CTL register, and not in low-power mode depending on the LDOLP bit reset in the PMU_CTL register. Normal-driver/Low-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL register. The low-power mode enters depending on the LDOLP bit set in the PMU_CTL register.
Page 64 GD32F3x0 User Manual Mode Sleep Deep-sleep Standby normal driver mode or mode) low driver mode SLEEPDEEP = 1 SLEEPDEEP = 1 Configuration SLEEPDEEP = 0 STBMOD = 0 STBMOD = 1, WURST=1 Entry WFI or WFE WFI or WFE WFI or WFE...
Page 65: Register Definition
GD32F3x0 User Manual 3.4. Register definition PMU base address: 0x4000 7000 3.4.1. Control register (PMU_CTL) Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register can be accessed by half-word (16-bit) or word (32-bit). Reserved...
Page 66 GD32F3x0 User Manual 00: Reserved (LDO output voltage low mode) 01: LDO output voltage low mode 10: LDO output voltage mid mode 11: LDO output voltage high mode 13:12 Reserved Must be kept at reset value. LDNP Low-driver mode when use normal power LDO 0: normal driver when use normal power LDO 1: Low-driver mode enabled when LDEN is 0b’11 and use normal power LDO...
Page 67: Control And Status Register (Pmu_Cs)
GD32F3x0 User Manual STBMOD Standby Mode ® 0: Enter the Deep-sleep mode when the Cortex -M4 enters SLEEPDEEP mode ® 1: Enter the Standby mode when the Cortex -M4 enters SLEEPDEEP mode LDOLP LDO Low Power Mode 0: The LDO operates normally during the Deep-sleep mode 1: The LDO is in low power mode during the Deep-sleep mode Note: Some peripherals may work with the IRC8M clock in the Deep-sleep mode.
Page 68 GD32F3x0 User Manual 1: LDO voltage select ready WUPEN6 WKUP Pin6 (PB15) Enable 0: Disable WKUP pin6 function 1: Enable WKUP pin6 function If WUPEN6 is set before entering the Standby mode, a rising edge on the WKUP pin6 wakes up the system from the Standby mode. As the WKUP pin6 is active high, the WKUP pin6 is internally configured to input pull down mode.
Page 69 GD32F3x0 User Manual threshold) 1: Low Voltage event occurred (V is equal to or lower than the specified LVD threshold) Note: The LVD function is stopped in Standby mode. STBF Standby Flag 0: The device has not entered the Standby mode...
Page 70: Reset And Clock Unit (Rcu)
The power reset which active signal is low will be de-asserted when the internal LDO voltage regulator is ready to provide 1.2V power for GD32F3x0 series. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
Page 71: Clock Control Unit (Cctl)
GD32F3x0 User Manual source (external or internal reset). Figure 4-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the Backup domain control register or Backup domain power on reset (V...
Page 72: Figure 4-2. Clock Tree
The ADC are clocked by the clock of APB2 divided by 2, 4, 6, 8 or by the clock of AHB divided by 3, 5, 7, 9 or IRC28M or IRC28M/2 clock for GD32F3x0 series selected by ADCSEL bit in configuration register 2 (RCU_CFG2). The USART0 is clocked by IRC8M clock or LXTAL clock or system clock or APB2 clock, which selected by USART0SEL bits in configuration register 2 (RCU_CFG2).
Page 73: Characteristics
GD32F3x0 User Manual CK_PLL or the clock of IRC48M by CK48MSEL bit in RCU_ADDCTL register. The FWDGT is clocked by IRC40K clock, which is forced on when FWDGT started. If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1.
Page 74: Figure 4-4. Hxtal Clock Source In Bypass Mode
GD32F3x0 User Manual Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the Control Register RCU_CTL. During bypass mode, the signal is connected to OSCIN, and OSCOUT remains in the suspended state, as shown in Figure 4-4. HXTAL clock source in bypass mode.
Page 75 GD32F3x0 User Manual as ADC clock. The IRC28M RC oscillator can be switched on or off using the IRC28MEN bit in the control register 1 (RCU_CTL1). The IRC28MSTB flag in the control register 1 (RCU_CTL1) is used to indicate if the internal 28M RC oscillator is stable. An interrupt can be generated if the related interrupt enable bit, IRC28MSTBIE, in the interrupt register, RCU_INT, is set when the IRC28M becomes stable.
Page 76: Table 4-1. Clock Source Select
GD32F3x0 User Manual System Clock (CK_SYS) Selection After the system reset, the default CK_SYS source will be IRC8M and can be switched to HXTAL or PLL by changing the system clock switch bits, SCS, in the Configuration register 0, RCU_CFG0. When the SCS value is changed, the CK_SYS will continue to operate using the original clock source until the target clock source is stable.
Page 77: Table 4-2. Core Domain Voltage Selected In Deep-Sleep Mode
GD32F3x0 User Manual capable of open IRC8M clock or close IRC8M clock, which used to the HDMI CEC or USART0 to wake up the Deep-sleep mode. Voltage control The core domain voltage in deep-sleep mode can be controlled by DSLPVS[1:0] bit in the deep-sleep mode voltage register (RCU_DSV).
Page 78: Register Definition
GD32F3x0 User Manual 4.3. Register definition RCU base address: 0x4002 1000 4.3.1. Control register0 (RCU_CTL0) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved PLLSTB PLLEN Reserved...
Page 79: Configuration Register 0 (Rcu_Cfg0)
GD32F3x0 User Manual 0: Disable the HXTAL Bypass mode 1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the inputclock. HXTALSTB External crystal oscillator (HXTAL) clock stabilization flag Set by hardware to indicate if the HXTAL oscillator is stable and ready for use.
Page 80 GD32F3x0 User Manual ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions PLLDV The CK_PLL divide by 1 or 2 for CK_OUT 0: CK_PLL divide by 2 for CK_OUT 1: CK_PLL divide by 1 for CK_OUT 30:28 CKOUTDIV[2:0] The CK_OUT divider which the CK_OUT frequency can be reduced see bits 26:24 of RCU_CFG0 for CK_OUT.
Page 81 GD32F3x0 User Manual 21:18 PLLMF[3:0] PLL multiply factor These bits and bit 27 of RCU_CFG0 and bit 31 of RCU_CFG1 are written by software to define the PLL multiplication factor. 000000: (PLL source clock x 2) 000001: (PLL source clock x 3)
Page 82 GD32F3x0 User Manual Set and cleared by software to divide or not which is selected to PLL. 0: HXTAL or CK_IRC48M clock selected 1: (HXTAL or CK_IRC48M) / 2 clock selected PLLSEL PLL Clock Source Selection Set and reset by software to control the PLL clock source.
Page 83: Interrupt Register (Rcu_Int)
GD32F3x0 User Manual 1101: (CK_SYS / 128) selected 1110: (CK_SYS / 256) selected 1111: (CK_SYS / 512) selected SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock. 00: Select CK_IRC8M as the CK_SYS source...
Page 84 GD32F3x0 User Manual Reserved Must be kept at reset value IRC28MSTBIC IRC28M stabilization Interrupt Clear Write 1 by software to reset the IRC28MSTBIF flag. 0: Not reset IRC28MSTBIF flag 1: Reset IRC28MSTBIF flag PLLSTBIC PLL stabilization Interrupt Clear Write 1 by software to reset the PLLSTBIF flag.
Page 85 GD32F3x0 User Manual IRC8MSTBIE IRC8M Stabilization Interrupt Enable Set and reset by software to enable/disable the IRC8M stabilization interrupt 0: Disable the IRC8M stabilization interrupt 1: Enable the IRC8M stabilization interrupt LXTALSTBIE LXTAL Stabilization Interrupt Enable LXTAL stabilization interrupt enable/disable control...
Page 86: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F3x0 User Manual 1: IRC8M stabilization interrupt generated LXTALSTBIF LXTAL stabilization interrupt flag Set by hardware when the External 32.768 kHz crystal oscillator clock is stable and the LXTALSTBIE bit is set. Reset by software when setting the LXTALSTBIC bit.
Page 87: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F3x0 User Manual 0: No reset 1: Reset the TIMER14 USART0RST USART0 Reset This bit is set and reset by software. 0: No reset 1: Reset the USART0 Reserved Must be kept at reset value SPI0RST SPI0 Reset This bit is set and reset by software.
Page 88 GD32F3x0 User Manual Bits Fields Descriptions Reserved Must be kept at reset value CECRST HDMI CEC reset This bit is set and reset by software. 0: No reset 1: Reset hdmi cec unit DACRST DAC reset This bit is set and reset by software.
Page 89: Ahb Enable Register (Rcu_Ahben)
GD32F3x0 User Manual 1: Reset window watchdog timer 10:9 Reserved Must be kept at reset value TIMER13RST TIMER13 timer reset This bit is set and reset by software. 0: No reset 1: Reset TIMER13 TIMER Reserved Must be kept at reset value...
Page 90 GD32F3x0 User Manual 0: Disabled TSI clock 1: Enabled TSI clock Reserved Must be kept at reset value PFEN GPIO port F clock enable This bit is set and reset by software. 0: Disabled GPIO port F clock 1: Enabled GPIO port F clock...
Page 91: Apb2 Enable Register (Rcu_Apb2En)
GD32F3x0 User Manual mode. 0: Disabled FMC clock during Sleep mode 1: Enabled FMC clock during Sleep mode Reserved Must be kept at reset value SRAMSPEN SRAM interface clock enable This bit is set and reset by software to enable/disable SRAM interface clock during Sleep mode.
Page 92: Apb1 Enable Register (Rcu_Apb1En)
GD32F3x0 User Manual TIMER14EN TIMER14 timer clock enable This bit is set and reset by software. 0: Disabled TIMER14 timer clock 1: Enabled TIMER14 timer clock Reserved Must be kept at reset value USART0EN USART0 clock enable This bit is set and reset by software.
Page 93 GD32F3x0 User Manual WWDGT TIMER13 TIMER5E TIMER2E TIMER1E Reserved SPI1EN Reserved Reserved Reserved Reserved Bits Fields Descriptions Reserved Must be kept at reset value CECEN HDMI CEC interface clock enable This bit is set and reset by software. 0: Disabled HDMI CEC interface clock...
Page 94: Backup Domain Control Register (Rcu_Bdctl)
GD32F3x0 User Manual 13:12 Reserved Must be kept at reset value WWDGTEN Window watchdog timer clock enable This bit is set and reset by software. 0: Disabled Window watchdog timer clock 1: Enabled Window watchdog timer clock 10:9 Reserved Must be kept at reset value...
Page 95 GD32F3x0 User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by software.
Page 96: Reset Source /Clock Register (Rcu_Rstsck)
GD32F3x0 User Manual 4.3.10. Reset source /clock register (RCU_RSTSCK) Address offset: 0x24 Reset value: 0x0C00 0000, reset flags reset by power Reset only, other reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGT...
Page 97: Ahb Reset Register (Rcu_Ahbrst)
GD32F3x0 User Manual 1: Power reset generated EPRSTF External PIN reset flag Set by hardware when an External PIN generated. Reset by writing 1 to the RSTFC bit. 0: No External PIN reset generated 1: External PIN reset generated OBLRSTF Option byte loader reset flag Set by hardware when an option byte loader generated.
Page 98 GD32F3x0 User Manual USBFSR Reserved Reserved Bits Fields Descriptions 31:25 Reserved Must be kept at reset value TSIRST TSI unit reset This bit is set and reset by software. 0: No reset TSI unit 1: Reset TSI unit Reserved Must be kept at reset value...
Page 99: Configuration Register 1 (Rcu_Cfg1)
GD32F3x0 User Manual 11:0 Reserved Must be kept at reset value 4.3.12. Configuration register 1 (RCU_CFG1) Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PLLPRES PLLMF[5] Reserved Reserved PREDV[3:0] Bits Fields...
Page 100: Configuration Register 2 (Rcu_Cfg2)
GD32F3x0 User Manual 1110: Input to PLL divided by 15 1111: Input to PLL divided by 16 4.3.13. Configuration register 2 (RCU_CFG2) Address offset: 0x30 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) ADCPS...
Page 101: Control Register 1 (Rcu_Ctl1)
GD32F3x0 User Manual This bit is set and reset by software. 00: CK_USART0 select CK_APB2 01: CK_USART0 select CK_SYS 10: CK_USART0 select CK_LXTAL 11: CK_USART0 select CK_IRC8M 4.3.14. Control register 1 (RCU_CTL1) Address offset: 0x34 Reset value: 0x0000 XX80 where X is undefined.
Page 102: Additional Clock Interrupt Register (Rcu_Addint)
GD32F3x0 User Manual Reset value: 0x8000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) IRC48M IRC48ME IRC48MCALIB[7:0] Reserved CK48M Reserved Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register These bits are load automatically at power on.
Page 103: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F3x0 User Manual IRC48M IRC48M Reserved Reserved Reserved STBIE STBIF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization Interrupt Clear Write 1 by software to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag...
Page 104: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32F3x0 User Manual CTCEN CTC clock enable This bit is set and reset by software. 0: Disabled CTC clock 1: Enabled CTC clock 26:0 Reserved Must be kept at reset value 4.3.18. APB1 additional reset register (RCU_ADDAPB1RST) Address offset: 0xFC...
Page 105: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F3x0 User Manual These bits are written only by software and read as 0. Only after write 0x1A2B3C4D to the RCU_VKEY, the RCU_DSV register can be written. 4.3.20. Deep-sleep mode voltage register (RCU_DSV) Offset: 0x134 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
Page 106: Clock Trim Controller (Ctc)
GD32F3x0 User Manual Clock trim controller (CTC) 5.1. Overview The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. If using IRC48M clock to USBFS, the IRC48M must be 48 MHz with 500ppm. The internal oscillator without such a high degree of accuracy needs to be trimmed.
Page 107: Ref Sync Pulse Generator
GD32F3x0 User Manual Figure 5-1. CTC overview PCLK1 APB1 BUS Register REFSEL REFPSC SWREFPU 1'b0 Prescaler CTC_SYNC (/1,/2,/4, ,/128 LXTAL 1'b0 REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM 5.3.1. REF sync pulse generator Firstly, the reference signal source can select GPIO, LXTAL clock output by setting REFSEL bits in CTC_CTL1 register.
Page 108: Frequency Evaluation And Automatically Trim Process
GD32F3x0 User Manual down-count to zero, and then up- counting to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 109: Software Program Guide
GD32F3x0 User Manual is not changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register add 1 when down-counting or sub 1 when up-counting.
Page 110: Register Definition
GD32F3x0 User Manual 5.4. Register definition CTC base address: 0x4000 C800 5.4.1. Control register 0 (CTC_CTL0) Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit). Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved...
Page 111: Control Register 1 (Ctc_Ctl1)
GD32F3x0 User Manual 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable...
Page 112: Status Register (Ctc_Stat)
GD32F3x0 User Manual 10: Reserved, equals 0 selected 11: Reserved, equals 0 selected. Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2...
Page 113 GD32F3x0 User Manual REFDIR CTC trim counter direction when reference sync pulse When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value.
Page 114: Interrupt Clear Register (Ctc_Intc)
GD32F3x0 User Manual 0 : No Error occur 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 115 GD32F3x0 User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect.
Page 116: Interrupt/Event Controller (Exti)
Each edge detector in the EXTI can be configured and masked independently. 6.2. Characteristics  Cortex-M4 system exception  Up to 68 maskable peripheral interrupts for GD32F3x0 series  4 bits interrupt priority configuration - 16 priority levels  Efficient interrupt processing  Support exception pre-emption and tail-chaining ...
Page 117: Table 6-2. Interrupt Vector Table
GD32F3x0 User Manual 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable 0x0000_0014 fault Undefined instruction or illegal UsageFault Programmable 0x0000_0018 state 0x0000_001C...
Page 118 GD32F3x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number TIMER5 and DAC global interrupt 0x0000_0084 IRQ 17 IRQ 18 Reserved 0x0000_0088 IRQ 19 TIMER13 global interrupt 0x0000_008C IRQ 20 TIMER14 global interrupt 0x0000_0090 IRQ 21 TIMER15 global interrupt...
Page 119: External Interrupt And Event (Exti) Block Diagram
GD32F3x0 User Manual 6.4. External interrupt and event (EXTI) block diagram Figure 6-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~27 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 6.5. External interrupt and Event function overview The EXTI contains up to 24 independent edge detectors and generates interrupts request or event to the processer.
Page 120: Table 6-3. Exti Source
GD32F3x0 User Manual Table 6-3. EXTI source EXTI Line Source Number PA0 / PB0 / PC0 / PF0 PA1 / PB1 / PC1 / PF1 PA2 / PB2 / PC2 / PD2 PA3 / PB3 / PC3 PA4 / PB4 / PC4 / PF4...
Page 121: Register Definition
GD32F3x0 User Manual 6.6. Register definition EXTI base address: 0x4001 0400 6.6.1. Interrupt enable register (EXTI_INTEN) Address offset: 0x00 Reset value: 0x0F94 0000 This register has to be accessed by word (32-bit) Reserved INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16...
Page 122: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F3x0 User Manual 1: Event from Linex is enabled 6.6.3. Rising edge trigger enable register (EXTI_RTEN) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved RTEN22 RTEN21 Reserved RTEN19 RTEN18 RTEN17 RTEN16...
Page 123: Software Interrupt Event Register (Exti_Swiev)
GD32F3x0 User Manual 22: 21 FTENx Falling edge trigger enable (x=21,22) 0: Falling edge of Linex is invalid 1: Falling edge of Linex is valid as an interrupt/event request Reserved Must be kept at reset value 19: 0 FTENx Falling edge trigger enable (x=0,19)
Page 124 GD32F3x0 User Manual PD15 PD14 PD13 PD12 PD11 PD10 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31: 23 Reserved Must be kept at reset value 22: 21 Interrupt pending status (x=21,22) 0: EXTI Linex is not triggered 1: EXTI Linex is triggered.
Page 125: General-Purpose And Alternate-Function I/Os (Gpio)
GD32F3x0 User Manual General-purpose and alternate-function I/Os (GPIO) 7.1. Overview There are up to 55 general purpose I/O pins, (GPIO), named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4 ~ PF7 for the device to implement logic input/output functions.
Page 126: Gpio Pin Configuration
GD32F3x0 User Manual Table 7-1. GPIO configuration table PAD TYPE CTLn PUDn Floating GPIO Pull-up INPUT Pull-down Floating Push-pull Pull-up GPIO Pull-down OUTPUT Floating Open-drain Pull-up Pull-down Floating AFIO Pull-up INPUT Pull-down Floating Push-pull Pull-up AFIO Pull-down OUTPUT Floating Open-drain...
Page 127: Alternate Functions (Af)
GD32F3x0 User Manual mode after reset: PA14: SWCLK in AF pull-down mode PA13: SWDIO in AF pull-up mode The GPIO pins can be configured as inputs or outputs. And all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen. When the GPIO pins are configured as input pins, the data on the external pads can be captured at every AHB clock cycle to the port input status register (GPIOx_ISTAT).
Page 128: Output Configuration
GD32F3x0 User Manual Figure 7-2. Basic structure of Input configuration 7.3.5. Output configuration When GPIO pin is configured as output:  The schmitt trigger input is activated.  The weak pull-up and pull-down resistors could be chosen.  The output buffer is enabled: Open-Drain mode: The pad outputs “0”...
Page 129: Alternate Function (Af) Configuration
GD32F3x0 User Manual  The schmitt trigger input is de-activated.  Read access to the port input status register gets the value “0”. Figure 7-4. Basic structure of Analog configuration shows the analog configuration of the GPIO pin. Figure 7-4. Basic structure of Analog configuration 7.3.7.
Page 130: Gpio Locking Function
GD32F3x0 User Manual 7.3.8. GPIO locking function The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPDy(y=0,1), GPIOx_PUD, GPIOx_AFSELy(y=0,1). It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK). When the LOCK sequence has been applied on a port bit, it is no longer able to modify the value of the port bit until the next reset.
Page 131: Register Definition
GD32F3x0 User Manual 7.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOF base address: 0x4800 1400 7.4.1. Port control register (GPIOx_CTL, x=A..D,F) Address offset: 0x00 Reset value: 0x2800 0000 for port A;...
Page 132: Port Output Mode Register (Gpiox_Omode, X=A
GD32F3x0 User Manual Refer to CTL0[1:0] description 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description...
Page 133 GD32F3x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value OM15 Pin 15 output mode bit These bits are set and cleared by software.
Page 134: Port Output Speed Register 0 (Gpiox_Ospd0, X=A
GD32F3x0 User Manual Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 3 output mode bit These bits are set and cleared by software.
Page 135 GD32F3x0 User Manual Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 25:24 OSPD12[1:0] Pin 12 output max speed bits These bits are set and cleared by software.
Page 136: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32F3x0 User Manual OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits These bits are set and cleared by software. x0: Output max speed 2M (reset value)
Page 137: Port Input Status Register (Gpiox_Istat, X=A
GD32F3x0 User Manual Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 17:16 PUD8[1:0] Pin 8 pull-up or pull-down bits These bits are set and cleared by software.
Page 138: Port Output Control Register (Gpiox_Octl, X=A
GD32F3x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3 ISTAT2 ISTAT1 ISTAT0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value...
Page 139: Port Configuration Lock Register (Gpiox_Lock, X=A,B)
GD32F3x0 User Manual BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit...
Page 140: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A,B,C)
GD32F3x0 User Manual 7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C) Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) SEL7[3:0] SEL6[3:0] SEL5[3:0] SEL4[3:0] SEL3[3:0] SEL2[3:0] SEL1[3:0] SEL0[3:0] Bits Fields Descriptions 31:28...
Page 141: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A,B,C)
GD32F3x0 User Manual 0011: AF3 selected 0100: AF4 selected (Port A,B only) 0101: AF5 selected (Port A,B only) 0110: AF6 selected (Port A,B only) 0111: AF7 selected (Port A,B only) 1000 ~ 1111: Reserved 7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C)
Page 142: Bit Clear Register (Gpiox_Bc, X=A
GD32F3x0 User Manual These bits are set and cleared by software. Refer to SEL8[3:0] description SEL8[3:0] Pin 8 alternate function selected These bits are set and cleared by software. 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected...
Page 143: Port Output Speed Register 1 (Gpiox_Ospd1, X=A
GD32F3x0 User Manual Reserved TG15 TG14 TG13 TG12 TG11 TG10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 Port Toggle bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Toggle the corresponding OCTLy bit 7.4.13.
Page 144: Cyclic Redundancy Checks Management Unit (Crc)
GD32F3x0 User Manual Cyclic redundancy checks management unit (CRC) 8.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial.
Page 145: Function Overview
GD32F3x0 User Manual 8.3. Function overview  CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If do not clear the CRC_DATA register by software setting CRC_CTL register, the new input raw data will calculate based on the result of previous value of CRC_DATA.
Page 146: Register Definition
GD32F3x0 User Manual 8.4. Register definition CRC base address: 0x4002 3000 8.4.1. Data register (CRC_DATA) Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit) DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software write and read.
Page 147: Control Register (Crc_Ctl)
GD32F3x0 User Manual These bits are unrelated with CRC calculation. This byte can be used for any goals by any other peripheral. The CRC_CTL register will generate no effect to the byte. 8.4.3. Control register (CRC_CTL) Address offset: 0x08 Reset value: 0x0000 0000...
Page 148: Polynomial Register (Crc_Poly)
GD32F3x0 User Manual Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit) IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value.
Page 149: Direct Memory Access Controller (Dma)
GD32F3x0 User Manual Direct memory access controller (DMA) 9.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 150: Block Diagram
GD32F3x0 User Manual 9.3. Block diagram Figure 9-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management...
Page 151: Table 9-1. Dma Transfer Operation
GD32F3x0 User Manual Table 9-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8...
Page 152: Peripheral Handshake
GD32F3x0 User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 153: Address Generation
GD32F3x0 User Manual  For channels with equal software priority level, priority is given to the channel with lower channel number. 9.4.4. Address generation Two kinds of address generation algorithm are implemented independently for memory and peripheral, including the fixed mode and the increased mode. The PNAGA and MNAGA bit in the DMA_CHxCTL register are used to configure the next address generation algorithm of peripheral and memory.
Page 154: Interrupt
GD32F3x0 User Manual 4. Confi gure the PRIO bits in the DMA_CHxCTL register to set the channel software priority. 5. Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register. 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register.
Page 155: Dma Request Mapping
GD32F3x0 User Manual 9.4.9. DMA request mapping Several requests from peripherals may be mapped to one DMA channel. They are logically ORed before entering the DMA. For details, see the following Figure 9-4. DMA request mapping. The request of each peripheral can be independently enabled or disabled by programming the registers of the corresponding peripheral.
Page 156: Figure 9-4. Dma Request Mapping
GD32F3x0 User Manual Figure 9-4. DMA request mapping Hardware priority ADC(1) TIMER1_CH2 high TIMER16_CH0(1) Channel 0 TIMER16_UP(1) ADC(2) SPI/I2S0_RX USART0_TX(1) I2C0_TX TIMER0_CH0 Channel 1 TIMER1_UP TIMER2_CH2 TIMER16_CH0(2) TIMER16_UP(2) SPI/I2S0_TX USART0_RX(1) T2C0_RX TIMER0_CH1 TIMER1_CH1 TIMER2_CH3 Channel 2 TIMER2_UP TIMER5_UP TIMER15_CH0(1) TIMER15_UP(1)
Page 157: Table 9-3. Dma Requests For Each Channel
GD32F3x0 User Manual Table 9-3. DMA requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● ● ● ADC(1) ADC(2) ● ● ● SPI/I2S SPI/I2S0_RX SPI/I2S0_TX SPI1_RX SPI1_TX...
Page 158: Register Definition
GD32F3x0 User Manual 9.5. Register definition DMA base address: 0x4002 0000 9.5.1. Interrupt flag register (DMA_INTF) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved ERRIF6 HTFIF6 FTFIF6 GIF6 ERRIF5 HTFIF5 FTFIF5 GIF5...
Page 159: Channel X Control Register (Dma_Chxctl)
GD32F3x0 User Manual This register has to be accessed by word(32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIFC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0...
Page 160 GD32F3x0 User Manual Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium...
Page 161: Channel X Counter Register (Dma_Chxcnt)
GD32F3x0 User Manual Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt...
Page 162: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F3x0 User Manual is read-only, and decreases after each DMA transfer. If the register is zero, no transaction can be issued whether the channel is enabled or not. Once the transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode.
Page 163 GD32F3x0 User Manual These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address.
Page 164: Debug (Dbg)
GD32F3x0 User Manual Debug (DBG) 10.1. Overview The GD32F3x0 series provide a large variety of debug, trace and test features. They are ® implemented with a standard configuration of the Arm Arm CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm Cortex®-M4.
Page 165: Debug Hold Function Overview
GD32F3x0 User Manual 10.3. Debug hold function overview 10.3.1. Debug support for power saving mode When STB_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in standby mode.
Page 166: Register Definition
GD32F3x0 User Manual 10.4. Register definition DBG base address: 0xE004 2000 10.4.1. ID code register (DBG_ID) Address: 0xE004 2000 Read only This register has to be accessed by word(32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by software.
Page 167 GD32F3x0 User Manual 0: no effect 1: hold the TIMER5 counter for debugging when the core is halted. 18:17 Reserved Must be kept at reset value. I2C1_HOLD I2C1 hold bit This bit is set and reset by software. 0: no effect 1: hold the I2C1 SMBUS timeout for debugging when the core is halted.
Page 168: Control Register 1 (Dbg_Ctl1)
GD32F3x0 User Manual DSLP_HOLD Deep-sleep mode hold bit This bit is set and reset by software. 0: no effect 1: In the Deep-sleep mode, the clock of AHB bus and system clock are provided by CK_IRC8M. SLP_HOLD Sleep mode hold bit This bit is set and reset by software.
Page 169 GD32F3x0 User Manual 1: hold the RTC counter for debugging when the core is halted. Reserved Must be kept at reset value.
Page 170: Analog To Digital Converter (Adc)
GD32F3x0 User Manual Analog to digital converter (ADC) 11.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels, 2 internal channels and the battery voltage (V ) channel.
Page 171: Pins And Internal Signals
GD32F3x0 User Manual – Oversampling ratio adjustable from 2x to 256x. – Programmable data shift up to 8-bits. ≤V ≤V  Channel input range: V 11.3. Pins and internal signals Figure 11-1. ADC module block diagram shows the ADC block diagram.
Page 172: Function Overview
GD32F3x0 User Manual 11.4. Function overview Figure 11-1. ADC module block diagram Trig select DMA request Routine channels Interrupt Interrupt Channel Mangement generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Routine data registers ADC_IN15 Over SAR ADC 6~12-bit （16 bits）...
Page 173: Dual Clock Domain Architecture
GD32F3x0 User Manual 11.4.2. Dual clock domain architecture The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock, which can be asynchronous and independent from the APB clock. Application can reduce PLCK frequency for low power operation while still keeping optimum ADC performance.
Page 174: Figure 11-3. Continuous Operation Mode
GD32F3x0 User Manual Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset. Configure RSQ0 with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if it is needed.
Page 175: Figure 11-4. Scan Operation Mode, Continuous Disable
GD32F3x0 User Manual Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in routine sequence till the end of sequence, once the corresponding software trigger or external trigger is active.
Page 176: Conversion Result Threshold Monitor Function
GD32F3x0 User Manual the ADC_CTL0 register. When the corresponding software trigger or external trigger is active, samples converts next channels configured ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set.
Page 177: Sample Time Configuration
GD32F3x0 User Manual of 8-bit resolution Figure 11-10. Data storage mode of 6-bit resolution Figure 11-7. Data storage mode of 12-bit resolution Routine sequence data D11 D10 DAL=0 Routine sequence data D11 D10 DAL=1 Figure 11-8. Data storage mode of 10-bit resolution Figure 11-9.
Page 178: External Trigger Configuration
GD32F3x0 User Manual 11.4.9. External trigger configuration The conversion of routine sequence can be triggered by rising edge of external trigger inputs. The external trigger source of routine sequence is controlled by the ETSRC [2:0] bits in the ADC_CTL1 register.
Page 179: Adc Interrupts
GD32F3x0 User Manual Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the temperature data(V ) in the ADC data register, and get the...
Page 180: On-Chip Hardware Oversampling
GD32F3x0 User Manual 11.4.14. On-chip hardware oversampling The on-chip hardware oversampling circuit unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted, and D...
Page 181: Table 11-5. Maximum Output Results For N And M Combimations (Grayed Values Indicates Truncation)
GD32F3x0 User Manual Figure 11-12. Numerical example with 5-bits shift and rounding Table 11-5. Maximum output results for N and M combimations (grayed values indicates truncation) gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 182 GD32F3x0 User Manual The oversampling configuration can only be changed when ADCON is reset. Make sure configuring the oversampling before setting ADCON to 1.
Page 183: Register Definition
GD32F3x0 User Manual 11.5. Register definition ADC base address: 0x4001 2400 11.5.1. Status register (ADC_STAT) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved STRC Reserved rc_w0 rc_w0 rc_w0 Bits Fields...
Page 184 GD32F3x0 User Manual This register has to be accessed by word(32-bit). Reserved DRES [1:0] RWDEN Reserved DISNUM [2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL [4:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:24 DRES [1:0]...
Page 185: Control Register 1 (Adc_Ctl1)
GD32F3x0 User Manual EOCIE Interrupt enable for EOC 0: Interrupt disable 1: Interrupt enable WDCHSEL [4:0] Analog watchdog channel select 00000: ADC channel0 00001: ADC channel1 00010: ADC channel2 …… 01111: ADC channel15 10000: ADC channel16 10001: ADC channel17 10010: ADC channel18 Other values are reserved.
Page 186 GD32F3x0 User Manual Reserved Must be kept at reset value. ETERC External trigger enable for routine sequence 0: External trigger for routine sequence disable 1: External trigger for routine sequence enable 19:17 ETSRC [2:0] External trigger select for routine sequence...
Page 187: Sampling Time Register 0 (Adc_Sampt0)
GD32F3x0 User Manual 1: ADC enable 11.5.4. Sampling time register 0 (ADC_SAMPT0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SPT18[2:0] SPT17[2:0] SPT16[2:0] SPT15[2:1] SPT15[0] SPT14[2:0] SPT13[2:0] SPT12[2:0] SPT11[2:0] SPT10[2:0] Bits...
Page 188: Watchdog High Threshold Register (Adc_Wdht)
GD32F3x0 User Manual This register has to be accessed by word (32-bit). Reserved SPT9[2:0] SPT8[2:0] SPT7[2:0] SPT6[2:0] SPT5[2:1] SPT5[0] SPT4[2:0] SPT3[2:0] SPT2[2:0] SPT1[2:0] SPT0[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:27 SPT9[2:0] refer to SPT0[2:0] description...
Page 189: Watchdog Low Threshold Register (Adc_Wdlt)
GD32F3x0 User Manual Reserved WDHT [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDHT [11:0] High threshold for analog watchdog These bits define the high threshold for the analog watchdog. 11.5.7. Watchdog low threshold register (ADC_WDLT)
Page 190: Routine Sequence Register1(Adc_Rsq1)
GD32F3x0 User Manual The total number of conversion in routine sequence equals to RL [3:0] +1. 19:15 RSQ15[4:0] refer to RSQ0[4:0] description 14:10 RSQ14[4:0] refer to RSQ0[4:0] description RSQ13[4:0] refer to RSQ0[4:0] description RSQ12[4:0] refer to RSQ0[4:0] description 11.5.9. Routine sequence register1(ADC_RSQ1)
Page 191: Routine Data Register (Adc_Rdata)
GD32F3x0 User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ5[4:0] refer to RSQ0[4:0] description 24:20 RSQ4[4:0] refer to RSQ0[4:0] description 19:15 RSQ3[4:0] refer to RSQ0[4:0] description 14:10 RSQ2[4:0] refer to RSQ0[4:0] description RSQ1[4:0] refer to RSQ0[4:0] description RSQ0[4:0] The channel number (0..18) are written to these bits to select a channel as the nth...
Page 192 GD32F3x0 User Manual Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio (OVSR [2:0]).
Page 193 GD32F3x0 User Manual 1: Oversampling enabled Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress).
Page 194: Digital-To-Analog Converter (Dac)
GD32F3x0 User Manual Digital-to-analog converter (DAC) 12.1. Overview The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 195: Function Overview
GD32F3x0 User Manual Table 12-1. DAC I/O description Name Description Signal type Analog power supply Power Ground for analog power supply Power DAC_OUT DAC analog output Analog output The GPIO pin (PA4) should be configured to analog mode before enable the DAC module.
Page 196: Dac Workflow
GD32F3x0 User Manual DTSEL[2:0] Trigger Source Trigger Type 3b’110 EXTI9 3b’111 SWTRIG Software trigger The TIMERx_TRGO signals are generated from the timers, while the software trigger can be generated by setting the SWTR bit in the DAC_SWT register. 12.3.5. DAC workflow...
Page 197: Dac Output Calculate
GD32F3x0 User Manual minimum value of the triangle signal is 0, while the maximum value of the triangle signal is (2<<DWBW) -1. Figure 12-3. DAC triangle noise wave 12.3.7. DAC output calculate The output voltages on the DAC pin are determined by the following equation:...
Page 198: Registers Definition
GD32F3x0 User Manual 12.4. Registers definition DAC base address: 0x4000 7400 12.4.1. Control register (DAC_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DDUDRIE DDMAEN DWBW[3:0] DWM[1:0] DTSEL[2:0] DTEN DBOFF...
Page 199: Software Trigger Register (Dac_Swt)
GD32F3x0 User Manual These bits specify the mode selection of the noise wave signal of DAC when external trigger of DAC is enabled (DTEN=1). 00: Wave disabled 01: LFSR noise mode 1x: Triangle noise mode DTSEL[2:0] DAC trigger selection These bits are only used if bit DTEN = 1 and select the external event used to trigger DAC.
Page 200: Dac 12-Bit Right-Aligned Data Holding Register(Dac_R12Dh)
GD32F3x0 User Manual 31:1 Reserved Must be kept at reset value. SWTR DAC software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled 12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 201: Dac 8-Bit Right-Aligned Data Holding Register (Dac_R8Dh)
GD32F3x0 User Manual 12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DAC_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 202 GD32F3x0 User Manual Reserved Reserved DDUDR Reserved rc_w1 Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. DDUDR DAC DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred...
Page 203: Comparator (Cmp)
GD32F3x0 User Manual Comparator (CMP) 13.1. Overview The general purpose comparators, CMP0 and CMP1, can work either standalone (all terminal are available on I/Os) or together with the timers. 13.2. Characteristic  Rail-to-rail comparators.  Configurable hysteresis.  Configurable speed and consumption.
Page 204: Cmp Clock And Reset
GD32F3x0 User Manual Figure 13-1. CMP block diagram of GD32F3x0 series Note: V is 1.2V. REFINT 13.3.1. CMP clock and reset The CMP clock is synchronous with the PCLK. The CMP share common reset and clock enable bits with SYSCFG.
Page 205: Cmp Operating Mode
GD32F3x0 User Manual whitchmake the CMP exit from power saving modes. 13.3.3. CMP operating mode For a given application, there is a trade-off between the CMP power consumption versus propagation delay, which is adjusted by configuring bits CMPxM [1:0] in CMP_CS register.
Page 206: Cmp Registers
GD32F3x0 User Manual 13.4. CMP registers CMP base address：0x4001 001C 13.4.1. Control/status register (CMP_CS) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1LK CMP1O CMP1HST[1:0] CMP1PL CMP1OSEL[2:0] WNDEN CMP1MSEL[2:0] CMP1M Reserved CMP1EN...
Page 207 GD32F3x0 User Manual 010: TIMER0 channel0 input capture 011: TIMER0 OCPRE_CLR input 100: TIMER1 channel3 input capture 101: TIMER1 OCPRE_CLR input 110: TIMER2 channel0 input capture 111: TIMER2 OCPRE_CLR input WNDEN Window mode enable This bit is used to disconnect the CMP1_IP input of CMP1 from PA3 and connect it to CMP0’s CMP0_IP input.
Page 208 GD32F3x0 User Manual 1: Non-inverting input above inverting input and the output is high 13:12 CMP0HST[1:0] CMP0 hysteresis These bits are used to control the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis CMP0PL Polarity of CMP0 output This bit is used to select the polarity of CMP0 output.
Page 209 GD32F3x0 User Manual This bit is used to closes a switch between CMP0 non-inverting input on PA1 and PA4 (DAC) I/O. 0: Switch open 1: Switch closed CMP0EN CMP0 enable 0: CMP0 disabled 1: CMP0 enabled...
Page 210: Watchdog Timer (Wdgt)
GD32F3x0 User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 211 GD32F3x0 User Manual Figure 14-1. Free watchdog timer block diagram The free watchdog is enabled by writing the value 0xCCCC in the control register (FWDGT_CTL), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated.
Page 212: Table 14-1. Min/Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32F3x0 User Manual Table 14-1. Min/max FWDGT timeout period at 40 kHz (IRC40K) PSC[2:0] Min timeout (ms) Max timeout (ms) Prescaler divider bits RL[11:0]=0x000 RL[11:0]=0xFFF 1 / 4 0.025 409.525 1 / 8 0.025 819.025 1 / 16 0.025 1638.025 1 / 32 0.025...
Page 213: Register Definition
GD32F3x0 User Manual 14.1.4. Register definition FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 214 GD32F3x0 User Manual register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 215 GD32F3x0 User Manual Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter window value update When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 216 GD32F3x0 User Manual These bits are write protected. Write 5555h in the FWDGT_CTL register before writing these bits. If several window values are used by the application, it is mandatory to wait until WUD bit is reset before changing the window value. However, after updating the...
Page 217: Window Watchdog Timer (Wwdgt)
GD32F3x0 User Manual 14.2. Window watchdog timer (WWDGT) 14.2.1. Overview The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of downcounter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared).
Page 218: Figure 14-3. Window Watchdog Timer Timing Diagram
GD32F3x0 User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. Whenever window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set).
Page 219: Table 14-2. Min-Max Timeout Value At 54 Mhz
GD32F3x0 User Manual Table 14-2. Min-max timeout value at 54 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 75 μs 1 / 1 4.85 ms 151 μs 1 / 2 9.71 ms 303 μs 1 / 4 19.41 ms...
Page 220: Register Definition
GD32F3x0 User Manual 14.2.4. Register definition WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 221 GD32F3x0 User Manual reaches 0x40. It can be cleared by a hardware reset or software reset by setting the WWDGTRST bit of the RCU module. A write of 0 has no effect. PSC[1:0] Prescaler. The time base of the watchdog counter...
Page 222: Real-Time Clock (Rtc)
GD32F3x0 User Manual Real-time clock (RTC) 15.1. Overview The RTC provides a time which includes hour / minute / second / sub-second and a calendar including year / month / day / week day. The time and calendar are expressed in BCD code except sub-second.
Page 223: Function Overview
GD32F3x0 User Manual 15.3. Function overview 15.3.1. Block diagram Figure 15-1. Block diagram of RTC ALARM 0 Alarm-0 Flag Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_spre (Default 1 Hz) IRC40K 15-bit 7-bit ck_apre Digital (Default 256 Hz)
Page 224: Shadow Registers Introduction
GD32F3x0 User Manual In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. Asynchronous prescaler is mainly used for reducing power consumption.
Page 225: Rtc Initialization And Configuration
GD32F3x0 User Manual 15.3.5. RTC initialization and configuration RTC register write protection BKPWEN bit in the PMU_CTL register is cleared in default, so writing to RTC registers needs setting BKPWEN bit ahead of time. After power-on reset, most of RTC registers are write protected. Unlocking this protection is the first step before writing to them.
Page 226: Calendar Reading
GD32F3x0 User Manual when next second comes. Alarm function operation process To avoid unexpected alarm assertion and metastable state, alarm function has an operation flow: Disable Alarm (by resetting ALRMxEN in RTC_CTL). Set the Alarm registers needed (RTC_ALRMxTD / RTC_ALRMxSS).
Page 227: Resetting The Rtc
GD32F3x0 User Manual Especially that software must clear RSYNF bit and wait it asserted before reading calendar register after wakeup from power saving mode. Reading calendar registers under BPSHAD = 1 When BPSHAD = 1, RSYNF is cleared and maintains as 0 by hardware so reading calendar registers does not care about RSYNF bit.
Page 228: Rtc Reference Clock Detection
GD32F3x0 User Manual has an offset (in a fraction of a second) with the remote clock, RTC unit provides a function named shift function to remove this offset and thus make second precision higher. RTC_SS register indicates the fraction of a second in binary format and is down counting when RTC is running.
Page 229: Rtc Smooth Digital Calibration
GD32F3x0 User Manual When reference detection function is running while the external reference clock is removed (no reference clock edge found in 3 ck_apre window), the calendar updating still can be performed by LXTAL clock only. If the reference clock is recovered later, detection function will use 7 ck_apre window to identify the reference clock and use 3 ck_apre window to adjust the 1Hz clock (ck_spre) edge.
Page 230 GD32F3x0 User Manual When the FACTOR_A is less than 3, the FACTOR_S value should be set to a value less than the nominal value. Assuming that RTC clock frequency is nominal 32.768 KHz, the corresponding FACTOR_S should be set as following rule: FACTOR_A = 2: 2 less than nominal FACTOR_S (8189 with 32.768 KHz).
Page 231: Time-Stamp Function
GD32F3x0 User Manual 15.3.11. Time-stamp function Time-stamp function is performed on RTC_TS pin and is enabled by control bit TSEN. When a time-stamp event occurs on RTC_TS pin, the calendar value will be saved in time-stamp registers (RTC_DTS / RTC_TTS / RTC_SSTS) and the time-stamp flag (TSF) is set to 1 by hardware.
Page 232: Calibration Clock Output
GD32F3x0 User Manual Edge detection mode on tamper input detection When FLT bit is set to 0x0, the tamper detection is set to edge detection mode and TPxEG bit determines the rising edge or falling edge is the detecting edge. When tamper detection is under edge detection mode, the internal pull-up resistors on the tamper detection input pin are deactivated.
Page 233: Rtc Power Saving Mode Management
GD32F3x0 User Manual The OPOL bit in RTC_CTL can configure the polarity of the alarm output which means that the RTC_ALARM output is the opposite of the corresponding flag bit or not. 15.3.15. RTC power saving mode management Table 15-1. RTC power saving mode management...
Page 234: Register Definition
GD32F3x0 User Manual 15.4. Register definition RTC base address: 0x4000 2800 15.4.1. Time register (RTC_TIME) Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state.
Page 235: Control Register (Rtc_Ctl)
GD32F3x0 User Manual Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[2:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 YRT[3:0] Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0] Days of the week...
Page 236 GD32F3x0 User Manual 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output 0x2: Reserved 0x3: Reserved OPOL Output polarity This bit is used to invert output RTC_ALARM...
Page 237: Status Register (Rtc_Stat)
GD32F3x0 User Manual ALRM0EN Alarm-0 function enable 0: Disable alarm function 1: Enable alarm function Reserved Must be kept at reset value. Clock System 0: 24-hour format 1: 12-hour format Note: Can only be written in initialization state BPSHAD Shadow registers bypass control...
Page 238 GD32F3x0 User Manual initialization mode and set to 0 by hardware when smooth calibration configuration is taken into account. Reserved Must be kept at reset value. TP1F RTC_TAMP1 detected flag Set to 1 by hardware when tamper detection is found on tamper1 input pin.
Page 239: Prescaler Register (Rtc_Psc)
GD32F3x0 User Manual Set by hardware if the year field of calendar date register is not the default value 0. 0: Calendar has not been initialized 1: Calendar has been initialized SOPF Shift function operation pending flag 0: No shift operation is pending...
Page 240 GD32F3x0 User Manual This register has to be accessed by word (32-bit). MSKD DOWS DAYT[1:0] DAYU[3:0] MSKH HRT[1:0] HRU[3:0] MSKM MNT[2:0] MNU[3:0] MSKS SCT[2:0] SCU[3:0] Bits Fields Descriptions MSKD Alarm date mask bit 0: Not mask date / day field...
Page 241: Write Protection Key Register (Rtc_Wpk)
GD32F3x0 User Manual 15.4.7. Write protection key register (RTC_WPK) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved WPK[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. WPK[7:0] Key for write protection 15.4.8.
Page 242: Time Of Time Stamp Register (Rtc_Tts)
GD32F3x0 User Manual Reserved Reserved SFS[14:0] Bits Fields Descriptions One second add 0: Not add 1 second 1: Add 1 second to the clock/calendar. This bit is jointly used with SFS field to add a fraction of a second to the clock.
Page 243: Date Of Time Stamp Register (Rtc_Dts)
GD32F3x0 User Manual 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code Reserved Must be kept at reset value. 14:12 MNT[2:0] Minute tens in BCD code 11:8 MNU[3:0] Minute units in BCD code Reserved Must be kept at reset value.
Page 244: High Resolution Frequency Compensation Register (Rtc_Hrfc)
GD32F3x0 User Manual Backup domain reset: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1. Reset TSF bit will also clear this register. This register has to be accessed by word (32-bit)
Page 245: Tamper Register (Rtc_Tamp)
GD32F3x0 User Manual Note: When CWND8 = 1, CMSK[1:0] are stuck at “00”. CWND16 Frequency compensation window 16 second selected 0: No effect 1: Calibration window is 16 second Note: When CWND16 = 1, CMSK[0] are stuck at “0”. 12:9 Reserved Must be kept at reset value.
Page 246 GD32F3x0 User Manual When PC13 is used to output alarm: 0: PC13 is in open-drain output type 1: PC13 is in push-pull output type When all RTC alternate functions are disabled and PC13MDE = 1: 0: PC13 output 0 1: PC13 output 1...
Page 247: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32F3x0 User Manual TP1EG Tamper 1 event trigger edge If tamper detection is in edge mode (FLT = 0): 0: Rising edge triggers a tamper detection event 1: Falling edge triggers a tamper detection event If tamper detection is in level mode(FLT ≠ 0):...
Page 248: Backup Registers (Rtc_Bkpx) (X = 0
GD32F3x0 User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:24 MSKSSC[3:0] Mask control bit of SSC 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched.
Page 249 GD32F3x0 User Manual in power saving mode because they can powered-on by V . Tamper detection flag TPxF assertion will reset these registers. Also when the FMC readout protection disables will reset these registers.
Page 250: Timer (Timerx)
GD32F3x0 User Manual Timer (TIMERx) Table 16-1. Timers (TIMERx) are devided into six sorts TIMER TIMER0 TIMER1/2 TIMER13 TIMER14 TIMER15/16 TIMER5 TYPE Advanced General-L0 General-L2 General-L3 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit(TIMER1) Counter 16-bit 16-bit 16-bit...
Page 251: Advanced Timer (Timerx ,X=0)
GD32F3x0 User Manual 16.1. Advanced timer (TIMERx ,x=0) 16.1.1. Overview The advanced timer module (TIMER0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The advanced timer has a 16-bit counter that can be used as an unsigned counter.
Page 252: Block Diagram
GD32F3x0 User Manual 16.1.3. Block diagram Figure 16-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 16-1. Advanced timer block diagram...
Page 253: Function Overview
GD32F3x0 User Manual 16.1.4. Function overview Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is from module RCU.
Page 254: Figure 16-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F3x0 User Manual ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0, 0x1, 0x2 or 0x3.  SMC1== 1’b1 (external clock mode 1). External input ETI is selected as timer clock source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of...
Page 255: Figure 16-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F3x0 User Manual will be generated. In addition, the update events will be generated after (TIMERx_CREP+1) times of overflow events. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode. Whenever, if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update event.
Page 256: Figure 16-5. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F3x0 User Manual Timing chart of up counting mode, change TIMERx_CAR on the go Figure 16-5. TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG...
Page 257: Figure 16-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F3x0 User Manual Timing chart of down counting mode, PSC=0/2 Figure 16-6. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Hardware set Software clear Update interrupt flag (UPIF) Timing chart of down counting mode, change TIMERx_CAR on the go Figure 16-7.
Page 258 GD32F3x0 User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting direction and generates an underflow event when the counter counts to 1 in the down-counting direction.
Page 259: Figure 16-8. Timing Chart Of Center-Aligned Counting Mode
GD32F3x0 User Manual Timing chart of center-aligned counting mode Figure 16-8. TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear...
Page 260: Figure 16-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32F3x0 User Manual effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overflow.
Page 261: Figure 16-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32F3x0 User Manual Repetition counter timing chart of down counting mode Figure 16-11. TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 262: Figure 16-12. Channel Input Capture Principle
GD32F3x0 User Manual Channel principle Figure 16-12. input capture Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal...
Page 263 GD32F3x0 User Manual Result: when you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN.
Page 264: Figure 16-13. Output-Compare Under Three Modes
GD32F3x0 User Manual Figure 16-13. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the...
Page 265: Figure 16-14. Eapwm Timechart
GD32F3x0 User Manual Figure 16-14. EAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Figure 16-15. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF...
Page 266: Table 16-2. Complementary Outputs Controlled By Parameters
GD32F3x0 User Manual 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 267 GD32F3x0 User Manual Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O output disable. CHxNP CHx_ON output enable CHx_ON = LOW CHx_O=OxCPRE⊕ CHxP CHx_ON output CHx_O output enable disable. CHx_O=OxCPRE⊕ CHx_ON=(!OxCPRE)⊕ CHxP CHxNP CHx_O output enable CHx_ON output enable...
Page 268: Figure 16-16. Complementary Output With Dead-Time Insertion
GD32F3x0 User Manual The dead time delay is greater than or equal to the CHx_ON duty cycle, then the CHx_ON signal is always the inactive value. Figure 16-16. Complementary output with dead-time insertion CHxVAL CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime > pulse width...
Page 269: Figure 16-17. Output Behavior In Response To A Break(The Break High Active)
GD32F3x0 User Manual Figure 16-17. Output behavior in response to a break(The break high active) BRKIN OxCPRE = ISOx CHx_O CHxEN: 1 CHxNEN: 1 CHxP : 0 CHxNP : 0 ISOx = ~ISOxN = ISOxN CHx_ON = ISOx CHx_O CHxEN: 1 CHxNEN: 0...
Page 270: Figure 16-18. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32F3x0 User Manual CI0FE0= Down Note: "-" means "no counting"; "X" means impossible. ”0” means “low level”, ”1” means “high level”. Figure 16-18. Counter behavior with CI0FE0 polarity non-inverted in mode 2 CI0FE0 CI1FE1 TIMERx_CAR 24 25 23 22 CNT_REG Figure 16-19.
Page 271 GD32F3x0 User Manual And TIMER_out need have functions of complementary and Dead-time, so only advanced timer can be chosen. Else, based on the timers’ internal connection relationship, pair’s timers can be selected. For example: TIMER_in (TIMER1) -> TIMER_out (TIMER0 ITI1) And so on.
Page 272: Figure 16-21. Hall Sensor Timing Between Two Timers
GD32F3x0 User Manual Figure 16-21. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management...
Page 273: Figure 16-22. Restart Mode
GD32F3x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection mode) 101: CI0FE0 configure the ETP for Filter by ETFC and 110: CI1FE1 polarity selection and Prescaler by ETPSC. 111: ETIFP inversion. Restart mode TRGS[2:0]=3’b0 The counter can...
Page 274: Figure 16-24. Event Mode
GD32F3x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection trigger input. Figure 16-24. Event mode TIMER_CK ETIFP CNT_REG TRGIF Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0.
Page 275: Figure 16-26. Timer0 Master/Slave Mode Timer Example
GD32F3x0 User Manual Figure 16-25. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG OxCPRE Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt.
Page 276: Figure 16-27. Triggering Timer0 With Enable Signal Of Timer1
GD32F3x0 User Manual  TIMER1 as prescaler for TIMER0 We configure TIMER1 as a prescaler for TIMER0. Refer to Figure 16-26. TIMER0 Master/Slave mode timer example for connections. Do as follow: 1. Configure TIMER1 in master mode and select its Update Event (UPE) as trigger output (MMC=010 in the TIMER1_CTL1 register).
Page 277: Figure 16-28. Triggering Timer0 And Timer1 With Timer1'S Ci0 Input
GD32F3x0 User Manual triggered by its CI0 input rises edge. To ensure 2 timers start synchronously, TIMER1 must be configured in Master/Slave mode. Do as follow: 1. Configure TIMER1 slave mode to get the input trigger from CI0 (TRGS=100 in the TIMER1_SMCFG register).
Page 278 GD32F3x0 User Manual next 3 accesses to TIMERx_DMATB. In a word, one-time DMA internal interrupt event assert, DMATC+1 times request will be send by TIMERx. If one more time DMA request event coming, TIMERx will repeat the process as above.
Page 279: Register Definition
GD32F3x0 User Manual 16.1.5. Register definition TIMER0 base address: 0x4001 2C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions...
Page 280 GD32F3x0 User Manual Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable. The counter continues after update event. 1: Single pulse mode enable. The counter counts until the next update event occurs.
Page 281 GD32F3x0 User Manual Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N...
Page 282 GD32F3x0 User Manual CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 283 GD32F3x0 User Manual SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 284 GD32F3x0 User Manual 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 285 GD32F3x0 User Manual edge, while the direction depends on each other. 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low.
Page 286 GD32F3x0 User Manual 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled...
Page 287 GD32F3x0 User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value.
Page 288 GD32F3x0 User Manual Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
Page 289 GD32F3x0 User Manual 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 290 GD32F3x0 User Manual CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description...
Page 291 GD32F3x0 User Manual 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise.
Page 292 GD32F3x0 User Manual Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description...
Page 293 GD32F3x0 User Manual CH0MS[1:0] Channel 0 mode selection Same as Output compare mode Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM...
Page 294 GD32F3x0 User Manual 1: Channel 2 output compare clear enable CH2COMCTL[2:0] Channel 2 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 295 GD32F3x0 User Manual 0: Channel 2 output quickly compare disable. 1: Channel 2 output quickly compare enable. CH2MS[1:0] Channel 2 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH2EN bit in TIMERx_CHCTL2 register is reset).).
Page 296 GD32F3x0 User Manual 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge...
Page 297 GD32F3x0 User Manual Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable Refer to CH0NEN description CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable...
Page 298 GD32F3x0 User Manual 11 or 10. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0.
Page 299 GD32F3x0 User Manual value of this bit-filed will be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 300 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 301 GD32F3x0 User Manual This register has to be accessed by word (32-bit). Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 302 GD32F3x0 User Manual Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event.
Page 303 GD32F3x0 User Manual 1: When POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits in TIMERx_CHCTL2 register. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11.
Page 304 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1).
Page 305 GD32F3x0 User Manual Configuration register (TIMERx_CFG) Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CHVSEL OUTSEL Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 306: General Level0 Timer (Timerx, X=1, 2)
GD32F3x0 User Manual 16.2. General level0 timer (TIMERx, x=1, 2) 16.2.1. Overview The general level0 timer module (TIMER1, 2) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 307: Block Diagram
GD32F3x0 User Manual 16.2.3. Block diagram Figure 16-29. General Level 0 timer block diagram provides details on the internal configuration of the general level0 timer. Figure 16-29. General Level 0 timer block diagram...
Page 308: Function Overview
GD32F3x0 User Manual 16.2.4. Function overview Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU.
Page 309: Figure 16-31. Timing Chart Of Psc Value Change From 0 To 2
GD32F3x0 User Manual 0x1, 0x2 or 0x3.  SMC1== 1’b1(external clock mode 1). External input pin source (ETI) The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 310: Figure 16-32. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F3x0 User Manual When the update event is set by the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update event. If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled.
Page 311: Figure 16-33. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F3x0 User Manual Timing chart of up counting mode Figure 16-33. , change TIMERx_CAR on the go. TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1...
Page 312: Figure 16-35. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F3x0 User Manual Timing chart of down counting mode Figure 16-34. , PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Hardware set Software clear...
Page 313: Figure 16-36. Center-Aligned Counter Timechart
GD32F3x0 User Manual Counter center-aligned counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The TIMER module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting mode and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 314 GD32F3x0 User Manual Figure 16-36. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Input capture and output compare channels The general level0 TIMER has four independent channels which can be used as capture inputs or compare match outputs.
Page 315: Figure 16-37. Channels Input Capture Principle
GD32F3x0 User Manual Channels principle Figure 16-37. input capture Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal...
Page 316 GD32F3x0 User Manual and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 317: Figure 16-38. Output-Compare Under Three Modes
GD32F3x0 User Manual Figure 16-38. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the...
Page 318 GD32F3x0 User Manual Figure 16-39. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-40. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down...
Page 319: Table 16-5. Examples Of Slave Mode
GD32F3x0 User Manual 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 320: Figure 16-41. Restart Mode
GD32F3x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection clear and restart when ITI0 is the used. a rising trigger input. selection. Figure 16-41. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF TI0S=0.(Non-xor) TRGS[2:0]=3’b Pause mode...
Page 321: Figure 16-44. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32F3x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 322: Table 16-6. Timerx(X=1,2) Interconnection
GD32F3x0 User Manual Figure 16-44. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG OxCPRE Timers interconnection Refer to Advanced timer (TIMERx, x=0) Table 16-6. TIMERx(x=1,2) interconnection Slave TIMER ITI0(TRGS = 000) ITI1(TRGS = 001)
Page 323: Register Definition
GD32F3x0 User Manual 16.2.5. Register definition TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE...
Page 324 GD32F3x0 User Manual After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode.
Page 325 GD32F3x0 User Manual Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 326 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 327 GD32F3x0 User Manual EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 328 GD32F3x0 User Manual 001: Quadrature decoder mode 0. The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level. 010: Quadrature decoder mode 1. The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level. 011: Quadrature decoder mode 2. The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other.
Page 329 GD32F3x0 User Manual CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value.
Page 330 GD32F3x0 User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag...
Page 331 GD32F3x0 User Manual 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG)
Page 332 GD32F3x0 User Manual 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
Page 333 GD32F3x0 User Manual Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. CH0COMCEN Channel 0 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O0CPRE signal will be cleared.
Page 334 GD32F3x0 User Manual result of the comparison. 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection.
Page 335 GD32F3x0 User Manual 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
Page 336 GD32F3x0 User Manual Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH3EN bit in TIMERx_CHCTL2 register is reset).
Page 337 GD32F3x0 User Manual updates at each update event will be enabled. 0: Channel 2 output compare shadow disable 1: Channel 2 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1)
Page 338 GD32F3x0 User Manual CH2CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear.
Page 339 GD32F3x0 User Manual Refer to CH0NP description Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP Channel 2 complementary output polarity...
Page 340 GD32F3x0 User Manual trigger operation in slave mode. And CIxFE0 will not be inverted. [CH0NP==0, CH0P==1]: CIxFE0’s falling edge is the active signal for capture or trigger operation in slave mode. And CIxFE0 will be inverted. [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode.
Page 341 GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 342 GD32F3x0 User Manual expected value. Counter auto reload register (TIMERx_CAR) (x=2) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 343 GD32F3x0 User Manual Channel 0 capture/compare value register (TIMERx_CH0CV) (x=2) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0...
Page 344 GD32F3x0 User Manual Channel 1 capture/compare value register (TIMERx_CH1CV) (x=2) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0...
Page 345 GD32F3x0 User Manual Channel 2 capture/compare value register (TIMERx_CH2CV) (x=2) Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0...
Page 346 GD32F3x0 User Manual This register has to be accessed by word (32-bit). Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 347 GD32F3x0 User Manual DMA transfer buffer register (TIMERx_DMATB) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed.
Page 348: General Level2 Timer (Timerx, X=13)
GD32F3x0 User Manual 16.3. General level2 timer (TIMERx, x=13) 16.3.1. Overview The general level2 timer module (TIMER 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 349: Figure 16-46. Timing Chart Of Internal Clock Divided By 1
GD32F3x0 User Manual 16.3.4. Function overview Clock source configuration The general level2 TIMER can only being clocked by the CK_TIMER.  Internal timer clock CK_TIMER which is from module RCU. The general level2 TIMER has only one clock source which is the internal CK_TIMER, used to drive the counter prescaler.
Page 350: Figure 16-47. Timing Chart Of Psc Value Change From 0 To 2
GD32F3x0 User Manual Timing chart of PSC value change from 0 to 2 Figure 16-47. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 351: Figure 16-48. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F3x0 User Manual Timing chart of up counting mode, PSC=0/2 Figure 16-48. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 16-49.
Page 352: Figure 16-50. Channel Input Capture Principle
GD32F3x0 User Manual Input capture and output compare channels The general level2 timer has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage.
Page 353 GD32F3x0 User Manual CHxCAPFLT. Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS! =0x0) and TIMERx_CHxCV cannot be written any more.
Page 354: Figure 16-51. Output-Compare Under Three Modes
GD32F3x0 User Manual Figure 16-51. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the...
Page 355 GD32F3x0 User Manual Figure 16-52. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 356 GD32F3x0 User Manual 16.3.5. Register definition TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions...
Page 357 GD32F3x0 User Manual event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 358 GD32F3x0 User Manual Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 359 GD32F3x0 User Manual channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 360 GD32F3x0 User Manual 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise. 111: PWM mode1. When counting up, O0CPRE is low when the counter is smaller than TIMERx_CH0CV, and high otherwise.
Page 361 GD32F3x0 User Manual Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level.
Page 362 GD32F3x0 User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 0 active high...
Page 363 GD32F3x0 User Manual This register has to be accessed by word (32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter.
Page 364 GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value.
Page 365 GD32F3x0 User Manual 31:2 Reserved Must be kept at reset value. CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER13_CH0) 01: Channel 0 input is connected to the RTCCLK 10: Channel 0 input is connected to HXTAL/32 clock...
Page 366 GD32F3x0 User Manual 16.4. General level3 timer (TIMERx, x=14) 16.4.1. Overview The general level3 timer module (TIMER14) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 367: Figure 16-53. General Level3 Timer Block Diagram
GD32F3x0 User Manual 16.4.3. Block diagram Figure 16-53. General level3 timer block diagram provides details of the internal configuration of the general level3 timer. Figure 16-53. General level3 timer block diagram...
Page 368: Figure 16-54. Timing Chart Of Internal Clock Divided By 1
GD32F3x0 User Manual 16.4.4. Function overview Clock source configuration The general level3 timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).  SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is from module RCU.
Page 369: Figure 16-55. Timing Chart Of Psc Value Change From 0 To 2
GD32F3x0 User Manual ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0, 0x1, 0x2 or 0x3. Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 370: Figure 16-56. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F3x0 User Manual Figure 16-56. Timing chart of up counting mode, PSC=0/2 show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Timing chart of up counting mode, PSC=0/2 Figure 16-56. TIMER_CK PSC = 0 PSC_CLK...
Page 371: Figure 16-57. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F3x0 User Manual Timing chart of up counting mode Figure 16-57. , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1...
Page 372: Figure 16-58. Repetition Counter Timing Chart Of Up Counting Mode
GD32F3x0 User Manual Repetition counter timing chart of up counting mode Figure 16-58. TIMER_CK PSC_CLK 98 99 0 97 98 99 0 98 99 98 99 0 CNT_REG 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF...
Page 373: Figure 16-59. Channel Input Capture Principle
GD32F3x0 User Manual Channel input capture principle Figure 16-59. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal...
Page 374 GD32F3x0 User Manual Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register...
Page 375: Figure 16-60. Output-Compare Under Three Modes
GD32F3x0 User Manual Figure 16-60. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 376 GD32F3x0 User Manual Figure 16-61. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 377: Table 16-7. Complementary Outputs Controlled By Parameters
GD32F3x0 User Manual Table 16-7. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable:...
Page 378: Figure 16-62. Complementary Output With Dead-Time Insertion
GD32F3x0 User Manual TIMERx_CCHP. The dead time delay insertion ensures that no two complementary signals drive the active state at the same time. When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled because under PWM0 mode. At point A in the Figure 16-62.
Page 379: Figure 16-63. Output Behavior In Response To A Break(The Break High Active)
GD32F3x0 User Manual CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0. If IOS is 0 then the timer releases the enable output else the enable output remains high. The complementary outputs are first put in reset state, and then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead-time.
Page 380: Figure 16-64. Restart Mode
GD32F3x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection 3'b110 (event 100: CI0F_ED mode) 101: CI0FE0 110: CI1FE1 111: Reserved Restart mode TRGS[2:0]=3’b0 The counter can For ITI0, no polarity For the ITI0, no filter and be clear and ITI0 is the selector can be used.
Page 381: Figure 16-67. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32F3x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection trigger input. Figure 16-66. Event mode TIMER_CK CI0FE0 CNT_REG TRGIF Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0.
Page 382: Table 16-9. Timerx(X=14) Interconnection
GD32F3x0 User Manual Figure 16-67. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG O0CPRE Timers interconnection Refer to Advanced timer (TIMERx, x=0) Table 16-9. TIMERx(x=14) interconnection Slave TIMER ITI0(TRGS = 000) ITI1(TRGS = 001)
Page 383 GD32F3x0 User Manual 16.4.5. Register definition TIMER14 base address: 0x4001 4000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions...
Page 384 GD32F3x0 User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update...
Page 385 GD32F3x0 User Manual The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value. MMC[2:0] Master mode control These bits control the selection of TRGO signal, which is sent in master mode to slave timers for synchronization function.
Page 386 GD32F3x0 User Manual After these bits have been written, they are updated based when commutation event coming. When a channel does not have a complementary output, this bit has no effect. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 387 GD32F3x0 User Manual 010: Reserved 011: Reserved 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low.
Page 388 GD32F3x0 User Manual UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value.
Page 389 GD32F3x0 User Manual CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software.
Page 390 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved BRKG TRGG CMTG Reserved CH1G CH0G Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 391 GD32F3x0 User Manual 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event Update event generation This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
Page 392 GD32F3x0 User Manual through TRGS bits in TIMERx_SMCFG register. Reserved Must be kept at reset value. CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 393 GD32F3x0 User Manual 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 394 GD32F3x0 User Manual 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge...
Page 395 GD32F3x0 User Manual 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 396 GD32F3x0 User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 397 GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value.
Page 398 GD32F3x0 User Manual 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 399 GD32F3x0 User Manual POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event.. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input.
Page 400 GD32F3x0 User Manual disabled. 1: When POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits in TIMERx_CHCTL2 register. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11.
Page 401 GD32F3x0 User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001.
Page 402 GD32F3x0 User Manual Reserved CHVSEL OUTSEL Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the...
Page 403 GD32F3x0 User Manual 16.5. General level4 timer (TIMERx, x=15,16) 16.5.1. Overview The general level4 timer module (TIMER15, TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level4 timer has a 16-bit counter that can be used as an unsigned counter.
Page 404: Figure 16-68. General Level4 Timer Block Diagram
GD32F3x0 User Manual 16.5.3. Block diagram Figure 16-68. General level4 timer block diagram provides details of the internal configuration of the general level4 timer. Figure 16-68. General level4 timer block diagram...
Page 405: Figure 16-69. Timing Chart Of Internal Clock Divided By 1
GD32F3x0 User Manual 16.5.4. Function overview Clock source configuration The general level4 TIMER can only being clocked by the CK_TIMER.  Internal timer clock CK_TIMER which is from module RCU The general level4 TIMER has only one clock source which is the internal CK_TIMER, used to drive the counter prescaler.
Page 406: Figure 16-70. Timing Chart Of Psc Value Change From 0 To 2
GD32F3x0 User Manual Timing chart of PSC value change from 0 to 2 Figure 16-70. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 407: Figure 16-71. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F3x0 User Manual Figure 16-71. Timing chart of up counting mode, PSC=0/2 show some examples of the counter behavior for different clock prescaler factor when TIMERx_CAR=0x99. Timing chart of up counting mode, PSC=0/2 Figure 16-71. TIMER_CK PSC = 0 PSC_CLK...
Page 408: Figure 16-72. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F3x0 User Manual Timing chart of up counting mode Figure 16-72. , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1...
Page 409: Figure 16-73. Repetition Counter Timing Chart Of Up Counting Mode
GD32F3x0 User Manual Repetition counter timing chart of up counting mode Figure 16-73. TIMER_CK PSC_CLK 98 99 0 97 98 99 0 98 99 98 99 0 CNT_REG 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF...
Page 410: Figure 16-74. Channel Input Capture Principle
GD32F3x0 User Manual Channel input capture principle Figure 16-74. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal...
Page 411 GD32F3x0 User Manual TIMERx_DMAINTEN. Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly.  Channel output compare function In channel output compare function, the TIMERx can generate timed pulses with programmable position, polarity, duration and frequency.
Page 412: Figure 16-75. Output-Compare Under Three Modes
GD32F3x0 User Manual Figure 16-75. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the...
Page 413 GD32F3x0 User Manual Figure 16-76. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 414: Table 16-10. Complementary Outputs Controlled By Parameters
GD32F3x0 User Manual Table 16-10. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable:...
Page 415: Figure 16-77. Complementary Output With Dead-Time Insertion
GD32F3x0 User Manual is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for channel 1. The detail about the delay time, refer to the register TIMERx_CCHP. The dead time delay insertion ensures that no two complementary signals drive the active state at the same time.
Page 416: Figure 16-78. Output Behavior In Response To A Break (The Break High Active)
GD32F3x0 User Manual the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0. If IOS is 0 then the timer releases the enable output else the enable output remains high.
Page 417: Figure 16-79. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F3x0 User Manual counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0 register. After a...
Page 418 GD32F3x0 User Manual 16.5.5. Register definition TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE...
Page 419 GD32F3x0 User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update...
Page 420 GD32F3x0 User Manual Reserved Must be kept at reset value. DMAS DMA request source selection 0: When capture or compare event occurs, the DMA request of channel x is sent 1: When update event occurs, the DMA request of channel x is sent.
Page 421 GD32F3x0 User Manual BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value. CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value. CH0IE Channel 0 capture/compare interrupt enable 0: disabled...
Page 422 GD32F3x0 User Manual 0: No active level break has been detected. 1: An active level has been detected. Reserved Must be kept at reset value. CMTIF Channel commutation interrupt flag This flag is set by hardware when channel’s commutation event occurs, and...
Page 423 GD32F3x0 User Manual Reserved Must be kept at reset value. CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 424 GD32F3x0 User Manual 31:7 Reserved Must be kept at reset value. CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 425 GD32F3x0 User Manual 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 426 GD32F3x0 User Manual is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 427 GD32F3x0 User Manual When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0. [CH0NP==0, CH0P==0]: CIxFE0’s rising edge is the active signal for capture or trigger operation in slave mode.
Page 428 GD32F3x0 User Manual Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 429 GD32F3x0 User Manual Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
Page 430 GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event..
Page 431 GD32F3x0 User Manual Idle mode off-state configure When POEN bit is reset, this bit specifies the output state for the channels which has been configured in output mode. 0: When POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled.
Page 432 GD32F3x0 User Manual Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001.
Page 433 GD32F3x0 User Manual Reserved Reserved CHVSEL OUTSEL Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the...
Page 434: Figure 16-80. Basic Timer Block Diagram
GD32F3x0 User Manual 16.6. Basic timer (TIMERx, x=5) 16.6.1. Overview The basic timer module (TIMER5) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 435: Figure 16-81. Timing Chart Of Internal Clock Divided By 1
GD32F3x0 User Manual counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Timing chart of internal clock divided by 1 Figure 16-81. CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE)
Page 436: Figure 16-82. Timing Chart Of Psc Value Change From 0 To 2
GD32F3x0 User Manual Timing chart of PSC value change from 0 to 2 Figure 16-82. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 437: Figure 16-83. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F3x0 User Manual Timing chart of up counting mode, PSC=0/2 Figure 16-83. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 16-84.
Page 438 GD32F3x0 User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 439 GD32F3x0 User Manual 16.6.5. Register definition TIMER5 base address: 0x4000 1000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 440 GD32F3x0 User Manual The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 441 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value.
Page 442 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared.
Page 443 GD32F3x0 User Manual PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 444: Figure 17-1. Ifrp Output Timechart 1
GD32F3x0 User Manual Infrared ray port (IFRP) 17.1. Overview Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control. There is no register in this module, which is controlled by TIMER15 and TIMER16. You can improve the module's output to high current capacity by set the GPIO pin to Fast Mode.
Page 445: Figure 17-2. Ifrp Output Timechart 2
GD32F3x0 User Manual Note: IFRP_OUT has one APB clock delay from TIMER16_CH0. Figure 17-2. IFRP output timechart 2 TIMER16_CH0 TIMER15_CH0 IFRP_OUT Note: Carrier (TIMER15_CH0)’s duty cycle can be changed, and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high.
Page 446 GD32F3x0 User Manual Universal synchronous / asynchronous receiver / transmitter (USART) 18.1. Overview The Universal Synchronous / Asynchronous Receiver / Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK1 or PCLK2) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 447 GD32F3x0 User Manual – Transmits parity bit. – Checks parity of received data byte.  LIN break generation and detection.  IrDA support.  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface. –...
Page 448: Figure 18-1. Usart Module Block Diagram
GD32F3x0 User Manual 18.3. Function overview The interface is externally connected to another device by the main pins listed in Table 18-1. Description of USART important pins. Table 18-1. Description of USART important pins Type Description Input Receive Data Output I/O Transmit Data.
Page 449: Figure 18-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32F3x0 User Manual Figure 18-2. USART character frame (8 bits data and 1 stop bit) In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 18-2. Configuration of stop bits...
Page 450 GD32F3x0 User Manual Get the value of USART_BUAD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, the nearest integer is 6, so FRADIV=6 (0x6). USART_BUAD=0x1E6. roundness of Note: If the FRADIV is 16 (overflow), the carry must be added to the integer part.
Page 451: Figure 18-3. Usart Transmit Procedure
GD32F3x0 User Manual Figure 18-3. USART transmit procedure It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. The TC bit can be cleared by writing 1 to TCC bit in USART_INTC register.
Page 452: Figure 18-4. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32F3x0 User Manual frame bit are 0, the frame bit is confirmed as a 0, else 1. If the three samples of any bit of a frame are not the same, whatever it is a start bit, data bit, parity bit or stop bit, a noisy error (NERR) status will be generated for the frame.
Page 453: Figure 18-5. Configuration Step When Using Dma For Usart Transmission
GD32F3x0 User Manual Figure 18-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address...
Page 454: Figure 18-6. Configuration Step When Using Dma For Usart Reception
GD32F3x0 User Manual Figure 18-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA...
Page 455: Figure 18-8. Hardware Flow Control
GD32F3x0 User Manual next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted. If the TBE bit in USART_STAT is ‘0’ and the nCTS signal is low, the transmitter transmits the data frame.
Page 456: Figure 18-9. Break Frame Occurs During Idle State
GD32F3x0 User Manual The idle frame wakes up method is selected by default. When an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode. When it is woken up by an idle frame, the IDLEF bit in USART_STAT will not be set.
Page 457: Figure 18-10. Break Frame Occurs During A Frame
GD32F3x0 User Manual Figure 18-10. As shown in Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame. Figure 18-10. Break frame occurs during a frame...
Page 458: Figure 18-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32F3x0 User Manual Figure 18-12. 8-bit format USART synchronous waveform (CLEN=1) Idle frame data (8bit) Idle CK pin (CPL=0, CPH=0) CK pin(CPL=1, CPH=0) CK pin (CPL=0, CPH=1) CK pin (CPL=1, CPH=1) Start Master data output bit0 bit1 bit2 bit3 bit4...
Page 459: Figure 18-14. Irda Data Modulation
GD32F3x0 User Manual the pulse width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times of PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block.
Page 460: Figure 18-15. Iso7816-3 Frame Format
GD32F3x0 User Manual Figure 18-15. ISO7816-3 frame format Character (T=0) mode Compared to the timing in normal operation, the transmission time from transmit shift register to the TX pin is delayed by half baud clock, and the TC flag assertion time is delayed by a guard time that is configured by the GUAT[7:0] bits in USART_GP.
Page 461 GD32F3x0 User Manual is signaled by the RBNE interrupt. If DMA is used to read from the smartcard in block mode, the DMA must be enabled only after the first character is received. In order to allow the automatic check of the maximum wait time between two consecutive...
Page 462: Figure 18-16. Usart Receive Fifo Structure
GD32F3x0 User Manual USART_CTL0 register must be set. The USART_RT register must be set to the value corresponding to a timeout of 2 characters time. After the last stop bit is received, when the receive line is idle for this duration, an interrupt will be generated, informing the software that the current block reception is completed.
Page 463: Table 18-3. Usart Interrupt Requests
GD32F3x0 User Manual DMA must be disabled before entering deep-sleep mode. Before entering deep-sleep mode, software must check that the USART is not performing a transfer, by checking the BSY flag in the USART_STAT register. The REA bit must be checked to ensure the USART is actually enabled.
Page 464: Figure 18-17. Usart Interrupt Mapping Diagram
GD32F3x0 User Manual Figure 18-17. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ORERR ERRIE LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 465 GD32F3x0 User Manual 18.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 18.4.1. Control register 0 (USART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE...
Page 466 GD32F3x0 User Manual 0: Oversampling by 16 1: Oversampling by 8 This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be written when the USART is enabled (UEN=1). AMIE ADDR match interrupt enable 0: ADDR match interrupt is disabled.
Page 467 GD32F3x0 User Manual USART_STAT. IDLEIE IDLE line detected interrupt enable 0: IDLE line detected interrupt disabled. 1: An interrupt will occur whenever the IDLEF bit is set in USART_STAT. Transmitter enable 0: Transmitter is disabled. 1: Transmitter is enabled. Receiver enable 0: Receiver is disabled.
Page 468 GD32F3x0 User Manual on matching. This bit field cannot be written when both reception (REN=1) and USART (UEN=1) are enabled. RTEN Receiver timeout enable 0: Receiver timeout function disabled 1: Receiver timeout function enabled This bit is reserved in USART1.
Page 469 GD32F3x0 User Manual CKEN CK pin enable 0: CK pin disabled 1: CK pin enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in USART1. Clock polarity 0: Steady low value on CK pin outside transmission window in synchronous mode.
Page 470 GD32F3x0 User Manual 18.4.3. Control register 2 (USART_CTL2) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP...
Page 471 GD32F3x0 User Manual Driver enable polarity mode 0: DE signal is active high. 1: DE signal is active low. This bit field cannot be written when the USART is enabled (UEN=1). Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin.
Page 472 GD32F3x0 User Manual 1: RTS hardware flow control enabled, data can be requested only when there is space in the receive buffer. This bit field cannot be written when the USART is enabled (UEN=1). DENT DMA enable for transmission 0: DMA mode is disabled for transmission.
Page 473 GD32F3x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). This register cannot be written when the USART is enabled (UEN=1). Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 474 GD32F3x0 User Manual 00000001: divides the source clock by 1. 00000010: divides the source clock by 2. In IrDA normal mode, 00000001: can be set this value only In smartcard mode, the prescaler value for dividing the system clock is stored in PSC[4:0] bits.
Page 475 GD32F3x0 User Manual In standard mode, the RTF flag is set if no new start bit is detected for more than the RT value after the last received character. In smartcard mode, the CWT and BWT are implemented by this value. In this case, the timeout measurement is started from the start bit of the last received character.
Page 476 GD32F3x0 User Manual Reserved Reserved CTSF LBDF RBNE IDLEF ORERR NERR FERR PERR Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknowledge flag. This bit, which is set/reset by hardware, reflects the receive enable state of the USART core logic.
Page 477 GD32F3x0 User Manual Set by software, by writing 1 to the SBKCMD bit in the USART_CMD register. Cleared by hardware during the stop bit of break transmission. ADDR match flag 0: ADDR does not match the received character 1: ADDR matches the received character, an interrupt is generated if AMIE=1 in the USART_CTL0 register.
Page 478 GD32F3x0 User Manual 0: LIN Break is not detected. 1: LIN Break is detected. An interrupt will occur if the LBDIE bit is set in USART_CTL1 Set by hardware when the LIN break is detected. Cleared by writing 1 to LBDC bit in USART_INTC register.
Page 479 GD32F3x0 User Manual Set by hardware when the word in the receive shift register is ready to be transferred into the USART_RDATA register while the RBNE bit is set. Cleared by writing 1 to OREC bit in USART_INTC register. NERR Noise error flag 0: No noise error is detected.
Page 480 GD32F3x0 User Manual This bit is reserved in USART1. 19:18 Reserved Must be kept at reset value. ADDR match clear Writing 1 to this bit clears the AMF bit in the USART_STAT register. 16:13 Reserved Must be kept at reset value.
Page 481 GD32F3x0 User Manual This register has to be accessed by word (32-bit). Reserved Reserved RDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. RDATA[8:0] Receive data value The received data character is contained in these bits. The value read in the MSB (bit 7 or bit 8 depending on the data length) will be the received parity bit, if receiving with the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
Page 482 GD32F3x0 User Manual This register has to be accessed by word (32-bit). Reserved RFFINT RFCNT[2:0] RFFIE RFEN Reserved ELNACK r_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. RFFINT Receive FIFO full interrupt flag 14:12 RFCNT[2:0] Receive FIFO counter number...
Page 483: Figure 19-1. I2C Module Block Diagram
GD32F3x0 User Manual Inter-integrated circuit interface (I2C) 19.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL.
Page 484: Table 19-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32F3x0 User Manual Figure 19-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register Control Registers Timing and SMBA Control Logic Status Flags DMA/ Interrupts Table 19-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips...
Page 485: Figure 19-2. Data Validation
GD32F3x0 User Manual if the FMPEN bit in I2C_FMPCFG is set. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V 19.3.2.
Page 486: Figure 19-4. Clock Synchronization
GD32F3x0 User Manual transition of this clock may not change the state of the SCL line. The SCL line is therefore held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time.
Page 487: Figure 19-6. I2C Communication Flow With 7-Bit Address
GD32F3x0 User Manual to the following command on I2C bus: transmitting or receiving the desired data. Additionally, if General Call is enabled by software, the I2C slave always responds to a General Call Address (0x00). The I2C block supports both 7-bit and 10-bit address modes.
Page 488 GD32F3x0 User Manual Programming model in slave transmitting mode As is shown in Figure 19-9. Programming model for slave transmitting (10-bit address mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing.
Page 489: Figure 19-9. Programming Model For Slave Transmitting (10-Bit Address Mode)
GD32F3x0 User Manual Figure 19-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge...
Page 490: Figure 19-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32F3x0 User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit.
Page 491 GD32F3x0 User Manual I2C_STAT1. Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 492: Figure 19-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32F3x0 User Manual Figure 19-11. Programming model for master transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND...
Page 493 GD32F3x0 User Manual bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1.
Page 494: Figure 19-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32F3x0 User Manual Figure 19-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header...
Page 495 GD32F3x0 User Manual I2C_STAT1. If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 496: Figure 19-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32F3x0 User Manual Figure 19-13. Programming model for master receiving mode using solution B (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master...
Page 497 GD32F3x0 User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 498 GD32F3x0 User Manual derived from I2C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols.
Page 499: Table 19-2. Event Status Flags
GD32F3x0 User Manual SMBus alert The SMBus has an extra optional shared interrupt signal called SMBALERT# which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data.
Page 500 GD32F3x0 User Manual Error Name Description SMBALT SMBus Alert...
Page 501 GD32F3x0 User Manual 19.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 19.4.1. Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved...
Page 502 GD32F3x0 User Manual 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte. ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0.
Page 503 GD32F3x0 User Manual 0: I2C is disabled 1: I2C is enabled 19.4.2. Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE ERRIE...
Page 504 GD32F3x0 User Manual I2CCLK[5:0] I2C peripheral clock frequency I2CCLK[5:0] should be the frequency of input APB1 clock in MHz which is at least 000000 - 000001: Not allowed 000010 - 110110: 2 MHz~54 MHz 110111 - 111111: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 505 GD32F3x0 User Manual Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled 19.4.5.
Page 506 GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode)
Page 507 GD32F3x0 User Manual I2C_DATA is empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail).
Page 508 GD32F3x0 User Manual sent but not received the ACK from slave. 1: In slave mode, address is received and matches witih its own address. In master mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA.
Page 509 GD32F3x0 User Manual 1: General call address (0x00) received Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver. It is cleared by hardware after a STOP or a START signal or I2CEN=0 or LOSTARB=1.
Page 510 GD32F3x0 User Manual In standard speed mode: T =CLKC*T high PCLK1 In fast speed mode or fast mode plus, if DTCY=0: =CLKC*T =2*CLKC*T high PCLK1 PCLK1 In fast speed mode or fast mode plus, if DTCY=1: =9*CLKC*T =16*CLKC*T high PCLK1...
Page 511 GD32F3x0 User Manual The I2C device supports up to 1MHz when this bit is set. 0: Fast mode plus disabled 1: Fast mode plus enabled...
Page 512 GD32F3x0 User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 20.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 513: Figure 20-1. Block Diagram Of Spi
GD32F3x0 User Manual 20.3. SPI function overview 20.3.1. SPI block diagram Figure 20-1. Block diagram of SPI SYSCLK MOSI TXBuffer MISO RX Buffer 20.3.2. SPI signal description Normal configuration (not Quad-SPI mode) Table 20-1. SPI signal description Pin name Direction...
Page 514: Figure 20-2. Spi Timing Diagram In Normal Mode
GD32F3x0 User Manual Pin name Direction Description application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI1).
Page 515: Figure 20-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32F3x0 User Manual Figure 20-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register.
Page 516: Table 20-4. Nss Function In Master Mode
GD32F3x0 User Manual software NSS mode) goes low, the SPI automatically enters slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). NSS goes low after SPI is enabled.
Page 517: Figure 20-4. A Typical Full-Duplex Connection
GD32F3x0 User Manual Mode Description Register configuration Data pin usage MSTMOD = 1 Master reception with RO = 1 MOSI: not used unidirectional connection BDEN = 0 MISO: reception BDOEN: Don’t care MSTMOD = 1 Master transmission with RO = 0...
Page 518: Figure 20-5. A Typical Simplex Connection (Master: Receive, Slave: Transmit)
GD32F3x0 User Manual Figure 20-5. A typical simplex connection (Master: receive, Slave: transmit) Figure 20-6. A typical simplex connection (Master: transmit only, Slave: receive) Figure 20-7. A typical bidirectional connection SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence...
Page 519 GD32F3x0 User Manual If TI mode is used, set TMOD bit in SPI_CTL1 register, otherwise, ignore this step. Configure MSTMOD, RO, BDEN and BDOEN depending on the operation modes described in SPI operating modes section. If Quad-SPI mode is used, set the QMOD bit in SPI_QCTL register. Ignore this step if Quad-SPI mode is not used.
Page 520: Figure 20-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32F3x0 User Manual full-duplex mode. In MRU or MRB mode, after SPI is enabled, the SPI continuously generates SCK until the SPI is disabled. So the application should ignore the TBE flag and read out reception buffer in time after the RBNE flag is set, otherwise a data overrun fault will occur.
Page 521: Figure 20-10. Timing Diagram Of Ti Slave Mode
GD32F3x0 User Manual Figure 20-10. Timing diagram of TI slave mode sample MOSI D[7] D[1] D[6] D[5] D[4] D[3] D[2] D[0] MISO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] In slave TI mode, after the last rising edge of SCK in transfer, the slave begins to transmit the LSB bit of the last data byte, and after a half-bit time, the master begins to sample the line.
Page 522: Figure 20-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32F3x0 User Manual Figure 20-11. Timing diagram of NSS pulse with continuous transmit MOSI MISO Don t Care Don t Care Don t Care 1 SCK Quad-SPI mode operation sequence The Quad-SPI mode is designed to control Quad-SPI Flash. In order to enter Quad-SPI mode, the software should first verify that the TBE bit is set and TRANS bit is cleared, then set QMOD bit in SPI_QCTL register.
Page 523: Figure 20-12. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32F3x0 User Manual Figure 20-12. Timing diagram of write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 524: Figure 20-13. Timing Diagram Of Read Operation In Quad-Spi Mode
GD32F3x0 User Manual Figure 20-13. Timing diagram of read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D1[6] D0[6] D0[2]...
Page 525 GD32F3x0 User Manual Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared.
Page 526 GD32F3x0 User Manual 20.3.8. SPI interrupts Status flags  Transmission buffer empty flag (TBE) This bit is set when the transmission buffer is empty, the software can write the next data to the transmission buffer by writing the SPI_DATA register.
Page 527: Figure 20-14. Block Diagram Of I2S
GD32F3x0 User Manual CRCERR is set when they are different. Table 20-6. SPI interrupt requests Interrupt Flag Description Clear method enable bit Transmission buffer empty Write SPI_DATA register. TBEIE RBNE Reception buffer not empty Read SPI_DATA register. RBNEIE Read or write SPI_STAT register,...
Page 528: Figure 20-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F3x0 User Manual 20.4.2. I2S signal description There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI.
Page 529: Figure 20-16. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32F3x0 User Manual Figure 20-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation...
Page 530: Figure 20-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F3x0 User Manual 24-bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits: D[23:8], and the second one should be a 16-bit data. The higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value. In reception mode, if a 24-bit data D[23:0] is received, the first data read from the SPI_DATA register is D[23:8], and the second one is a 16-bit data.
Page 531: Figure 20-25. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32F3x0 User Manual Figure 20-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 20-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left)
Page 532: Figure 20-31. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F3x0 User Manual than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below.
Page 533: Figure 20-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F3x0 User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 534: Figure 20-36. Pcm Standard Short Frame Synchronization Mode Timing Diagram
GD32F3x0 User Manual Figure 20-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure20-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1...
Page 535: Figure 20-45. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32F3x0 User Manual Figure20-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16 bits I2S_SD Figure 20-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1...
Page 536: Figure 20-49. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F3x0 User Manual Figure 20-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16-bit data 16-bit 0 I2S_SD Figure 20-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1)
Page 537: Figure 20-52. I2S Initialization Sequence
GD32F3x0 User Manual So, in order to get the desired audio sampling frequency, the clock generator needs to be configured according to the formulas listed in Table 20-8. Audio sampling frequency calculation formulas. Table 20-8. Audio sampling frequency calculation formulas...
Page 538 GD32F3x0 User Manual Figure 20-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity...
Page 539 GD32F3x0 User Manual (TBE is high) and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmission buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 540: Figure 20-53. I2S Master Reception Disabling Sequence
GD32F3x0 User Manual Figure 20-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTDSEL !=2b'10 ? Wait for the last RBNE...
Page 541 GD32F3x0 User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 542: Table 20-10. I2S Interrupt
GD32F3x0 User Manual Error conditions There are three error flags:  Transmission underrun error flag (TXURERR) This situation occurs when the transmission buffer is empty when the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the reception buffer is full and a newly incoming data has been completely received.
Page 543 GD32F3x0 User Manual 20.5. Register definition SPI0/I2S0 base address: 0x4001 3000 SPI1 base address: 0x4000 3800 20.5.1. Control register 0 (SPI_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 544 GD32F3x0 User Manual received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN NSS software mode selection 0: NSS hardware mode.
Page 545 GD32F3x0 User Manual CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle. 1: CLK pin is pulled high when SPI is idle. CKPH Clock phase selection 0: Capture the first data at the first clock transition.
Page 546 GD32F3x0 User Manual 1: Enable master NSS output DMATEN Transmit buffer DMA enable 0: Disable transmit buffer DMA 1: Enable transmit buffer DMA, when the TBE bit in SPI_STAT is set, it will be a DMA request on corresponding DMA channel.
Page 547 GD32F3x0 User Manual register followed by a read access to the SPI_STAT register. CONFERR SPI configuration error 0: No configuration fault occurs. 1: Configuration fault occurred. (In master mode, the NSS pin is pulled low in NSS hardware mode or SWNSS bit is low in NSS software mode.) This bit is set by hardware and cleared by a read or write operation on the SPI_STAT register followed by a write access to the SPI_CTL0 register.
Page 548 GD32F3x0 User Manual SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardware has two buffers, including transmission buffer and reception buffer. Write data to SPI_DATA will save the data to transmission buffer and read data from SPI_DATA will get the data from reception buffer.
Page 549 GD32F3x0 User Manual RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the received bytes and saves them in RCRC register. If the data frame format is...
Page 550 GD32F3x0 User Manual 20.5.8. I I2S control register (SPI_I2SCTL) Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved PCMSMO Reserved I2SSEL I2SEN I2SOPMOD[1:0] Reserved I2SSTD[1:0] CKPL DTLEN[1:0]...
Page 551 GD32F3x0 User Manual 10: LSB justified standard 11: PCM standard These bits should be configured when I2S mode is disabled. These bits are not used in SPI mode. CKPL Idle state clock polarity 0: The idle state of I2S_CK is low level.
Page 552 GD32F3x0 User Manual This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1 This bit should be configured when I2S mode is disabled.
Page 553 GD32F3x0 User Manual cleared). This bit is only available in SPI1.
Page 554 GD32F3x0 User Manual HDMI-CEC controller (HDMI-CEC) 21.1. Overview The products of the GD32F150xx series integrate the HDMI-CEC controller inside to support the CEC protocol. Consumer Electronics Control (CEC) belongs to a part of HDMI (High-Definition Multimedia Interface) standard. CEC as a kind of protocol, provides the advanced control functions of all kinds of audio-visual products in a user environment.
Page 555: Figure 21-1. Hdmi-Cec Controller Block Diagram
GD32F3x0 User Manual device is in the output state, in order to allow a wired-and connection, the CEC pin need to be configured in alternate function open drain mode, and an external 27kΩ resister is needed for pulling-up the CEC pin to a +3.3V supply voltage.
Page 556: Figure 21-2. Start Bit
GD32F3x0 User Manual Information bits ENDOM The information bits are data, opcodes or addresses, dependent on context. The control bits, ENDOM and ACK, are always present and always have the same usage. 21.3.3. Bit timing description All bits timing in the message are divided into two types: Start bit and Data bit.
Page 557: Figure 21-4. Signal Free Time
GD32F3x0 User Manual Time (ms) The bit start event. T5 as the earliest time that a device is allowed to return to a high 1.3ms impedance state(logical 0). T6 as the latest time that a device is allowed to return to a high 1.7ms...
Page 558: Figure 21-5. Error Bit Period
GD32F3x0 User Manual Precondition Signal Free Time (nominal data bit periods) ≥5 New Initiator wants to send a message ≥3 Previous attempt to send message unsuccessful This means that there is an opportunity for other devices to gain access to the CEC line during the periods mentioned above to send their own messages after the current device has finished sending its current message.
Page 559: Figure 21-6. Bit Period Long Error
GD32F3x0 User Manual Frame error CEC protocol defines that each frame of message need the acknowledgement to confirm the communication is successful. For broadcast(destination address=0xF), the ACK bit should be logic 1 and for singlecast(destination address<0xF), the ACK bit should be logic 0, otherwise the frame error occurs(TAERR/RAE flag asserted).
Page 560: Figure 21-7. Transmission Error Detection
GD32F3x0 User Manual Legend: Checking Window SBPE LBPE High Impedence Logic Low Impedence 1.5ms 2.4ms High Impedence Logic Low Impedence 0.6ms 2.4ms Nominal sample time 1.05 ms Table 21-2. Error Handling Timing Parameter Table Symbol RTOL Time(ms) Description The bit start event.
Page 561: Table 21-3. Terr Timing Parameter Table
GD32F3x0 User Manual TX arb-bit=0/1 Legend: Checking Window TX data=0 High Impedence Logic Low Impedence 1.5ms 2.4ms TX ack TX data=1 High Impedence Logic Low Impedence 0.6ms 2.4ms Nominal sample time 1.05 ms Table 21-3. TERR Timing Parameter Table Symbol...
Page 562 GD32F3x0 User Manual Interrupt event in HDMI-CEC Event flag Interrupt enable bit Transmit Byte buffer underrun TUIE Transmit error TERR TERRIE Transmit acknowledge error TAERR TAERRIE Byte Received BRIE Reception end REND RENDIE Receive Overrun ROIE Bit rising error BREIE...
Page 563 GD32F3x0 User Manual 21.4. Register definition HDMI-CEC base address: 0x4000 7800 21.4.1. Control register (CEC_CTL) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved ENDOM STAOM CECEN Bits Fields Descriptions 31:3 Reserved Must be kept at reset value ENDOM ENDOM bit value in the next frame in Transmit mode.
Page 564 GD32F3x0 User Manual 21.4.2. Configuration register (CEC_CFG) Address offset: 0x04 Reset value: 0x0000 0000 Note: This register can only be write when CECEN=0 LMEN OAD [14:0] Reserved SFTOPT BCNG BPLEG BREG BRES RTOL SFT[2:0] Bits Fields Descriptions LMEN Listen Mode Enable Bit This bit is set and cleared by software.
Page 565 GD32F3x0 User Manual 1: Generate an Error-bit on CEC line when detected BPLE in singlecast BREG Generate an Error-bit when detected BRE in singlecast This bit is set and cleared by software. 0: Not generate an Error-bit on CEC line when detected BRE in singlecast...
Page 566 GD32F3x0 User Manual Reserved TDATA[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TDATA[7:0] Transmit data register These bits are write only and contain the data byte to be transmit. 21.4.4. Receive data register (CEC_RDATA) Address offset: 0xC...
Page 567 GD32F3x0 User Manual The ACK bit is received 1 in singlecast and is received 0 in broadcast will assert the flag. TAERR will stop sending message and clear STAOM and ENDOM. TERR Transmit Error This bit is set by hardware and cleared by software writing 1.
Page 568 GD32F3x0 User Manual BPSE is asserted if a data-bit period is less than the minimal period. Bit Rising Error This bit is set by hardware and cleared by software writing 1. BRE is asserted if the rising edge in a period is occurs in unexpected time.
Page 569 GD32F3x0 User Manual This bit is set and cleared by software. 0: TU interrupt disable 1: TU interrupt enable TENDIE TEND Interrupt Enable. This bit is set and cleared by software. 0: TEND interrupt disable 1: TEND interrupt enable TBRIE TBR Interrupt Enable.
Page 570 GD32F3x0 User Manual BRIE BR Interrupt Enable. This bit is set and cleared by software. 0: BR interrupt disable 1: BR interrupt enable...
Page 571: Figure 22-1. Block Diagram Of Tsi Module
GD32F3x0 User Manual Touch sensing interface (TSI) 22.1. Overview Touch Sensing Interface (TSI) provides a convenient solution for touch keys, sliders and capacitive proximity sensing applications. The controller builds on charge transfer method. Placing a finger near fringing electric fields adds capacitance to the system and TSI is able to measure this capacitance change using charge transfer method.
Page 572: Figure 22-2. Block Diagram Of Sample Pin And Channel Pin
GD32F3x0 User Manual strain, etc. Detecting the change of a system is the key problem and goal in these technologies. The TSI module is designed to use charge transfer method which detects the capacitive change of an electrode when touched by or a finger close to it. In order to detect the capacitive change, TSI performs a charge transfer sequence including several charging, transfer steps.
Page 573: Table 22-1. Pin And Analog Switch State In A Charge-Transfer Sequence
GD32F3x0 User Manual diagram of Sample pin and Channel Pin, i.e. PIN0 is channel pin and PIN1 is sample pin. Table 22-1. Pin and analog switch state in a charge-transfer sequence Step Name ASW_0 ASW_1 Pin0 Pin1 Discharge Close Close...
Page 574: Figure 22-3. Voltage Of A Sample Pin During Charge-Transfer Sequence
GD32F3x0 User Manual 7. Buffer Time3 Buffer time with ASW_0 and ASW_1 open, PIN0 is configured to input floating. 8. Compare ASW_0, ASW_1 and PIN0 remain the configuration of Step7. At this step, the voltage of sample pin PIN1 is compared to a threshold called V .
Page 575: Figure 22-4. Fsm Flow Of A Charge-Transfer Sequence
GD32F3x0 User Manual Figure 22-4. FSM flow of a charge-transfer sequence IDLE(discharge) Started Buffer Time1 Extend Charge Charge enabled Spread spectrum disabled Extend Charge Buffer Time2 Vx > Vth ！(Vx > Vth) or the cycle number or the cycle number...
Page 576: Table 22-2. Duration Time Of Extend Charge State In Each Cycle
GD32F3x0 User Manual cycles, V (the voltage of sample pin) reaches V (the threshold voltage). There is also a max cycle number defined by MCN in TSI_CTL0 register. When the cycle number reaches MCN, FSM returns to IDLE state and stops after Compare State, whether reaches V or not.
Page 577: Table 22-3. Spread Spectrum Deviation Base On Hclk Period
GD32F3x0 User Manual Cycle Number Number of ECCLKs in Extend Charge state … … Table 22-3. Spread spectrum deviation base on HCLK period Spread spectrum deviation with different ECDIV value (ECDT=0x7F) HCLK Period ECDIV[2:0]=0x0 (Min) ECDIV[2:0]=0x1 ECDIV[2:0]=0x7(Max) 41.6ns (24MHz) 5333.3ns 10666.6ns...
Page 578: Table 22-4. Tsi Errors And Flags
GD32F3x0 User Manual 22.3.8. TSI operation flow The normal operation flow of TSI is listed below: System initialization, such as system clock configuration, TSI related GPIO configuration, etc. Program TSI_CTL0, TSI_CHCFG, TSI_INTEN, TSI_SAMPCFG and GEx bits of TSI_GCTL register according to demand.
Page 579 GD32F3x0 User Manual TSI Group TSI Pins GPPIN pins PIN1 PIN2 PIN3 PIN0 PB11 PIN1 PB12 TSI_GRP5 PIN2 PB13 PIN3 PB14...
Page 580 GD32F3x0 User Manual 22.4. Registers definition TSI base address: 0x4002 4000 22.4.1. Control register0 (TSI_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word (32-bit). CDT[3:0] CTDT[3:0] ECDT[6:0] ECEN ECDIV[0] CTCDIV[2:0] Reserved MCN[2:0] PINMOD EGSEL...
Page 581 GD32F3x0 User Manual 1111111: 128×t ECCLK ECEN Extend Charge State Enable. 0: Extend Charge disabled 1: Extend Charge enabled ECDIV[0] Extend Charge clock(ECCLK) division factor. ECCLK in TSI is divided from HCLK and ECDIV defines the division factor. 0x0: f...
Page 582 GD32F3x0 User Manual 111: Reserved PINMOD Pin mode This bit defines a TSI pin’s mode when charge-transfer sequence is IDLE. 0: TSI pin will output low when IDLE 1: TSI pin will keep input mode when IDLE EGSEL Edge selection This bit defines the edge type in hardware trigger mode.
Page 583 GD32F3x0 User Manual 0: MNERR interrupt is disabled 1: MNERR interrupt is enabled CTCFIE Charge-transfer complete flag Interrupt Enable 0: CTCF interrupt is disabled 1: CTCF interrupt is enabled 22.4.3. Interrupt flag clear register (TSI_INTC) Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by word(32-bit).
Page 584 GD32F3x0 User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value MNERR Max Cycle Number Error This bit is set by hardware after charge-transfer sequence stops because it reaches the max cycle number defined by MCN[2:0]. This bit is cleared by writing 1 to CMNERR bit in TSI_ICR register.
Page 585 GD32F3x0 User Manual Reserved G5P3 G5P2 G5P1 G5P0 G4P3 G4P2 G4P1 G4P0 G3P3 G3P2 G3P1 G3P0 G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1P1 G1P0 G0P3 G0P2 G0P1 G0P0 Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:0 GxPy Analog switch state.
Page 586 GD32F3x0 User Manual Reserved G5P3 G5P2 G5P1 G5P0 G4P3 G4P2 G4P1 G4P0 G3P3 G3P2 G3P1 G3P0 G2P3 G2P2 G2P1 G2P0 G1P3 G1P2 G1P1 G1P0 G0P3 G0P2 G0P1 G0P0 Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:0...
Page 587 GD32F3x0 User Manual 22.4.10. Group x cycle number registers(TSI_GxCYCN)(x= 0..5) Address offset: 0x30 + 0x04 *(x + 1) Reset value: 0x0000 0000 This register can be accessed by word (32-bit). Reserved Reserved CYCN[13:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value...
Page 588 GD32F3x0 User Manual 0x4: f ECCLK HCLK 0x5: f ECCLK HCLK 0x6: f ECCLK HCLK 0x7: f ECCLK HCLK Note:ECDIV[2:1] are located in TSI_CTL1 and ECDIV[0] is located in TSI_CTL0. 27:25 Reserved Must be kept at reset value CTCDIV[3] Charge Transfer clock(CTCLK) division factor.
Page 589 GD32F3x0 User Manual Universal serial bus full-speed interface (USBFS) 23.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol). USBFS contains a full-speed internal USB PHY and external PHY chip is not contained.
Page 590: Figure 23-1. Usbfs Block Diagram
GD32F3x0 User Manual 23.3. Block diagram Figure 23-1. USBFS block diagram USB interrupts AHB Slave Register Device bus Host Port control Control Data FIFO Transcation UTMI USB FS PHY Scheduler Control VBUS USB Clock 48MHz USB Clock Domain 23.4. Signal description Table 23-1.
Page 591: Figure 23-2. Connection With Host Or Device Mode
GD32F3x0 User Manual Figure 23-2. Connection with host or device mode USBFS 5V Power Supply (needed in GPIO host mode) VBUS VBUS When USBFS works in host mode (FHM bit is set and FDM bit is cleared), the VBUS is 5V power detecting pin used for voltage detection defined in USB protocol.
Page 592: Figure 23-3. Connection With Otg Mode
GD32F3x0 User Manual Figure 23-3. Connection with OTG mode USBFS 5V Power GPIO Supply VBUS VBUS 23.5.2. USB host function USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state.
Page 593 GD32F3x0 User Manual Connection, Reset and Speed identification As a USB host, USBFS will trigger a connection flag for application after a connection is detected and will trigger a disconnection flag after a disconnection event. PRST bit is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset.
Page 594 GD32F3x0 User Manual USB 2.0 protocol divides these transfers into 2 kinds: non-periodic transfer (control and bulk) and periodic transfer (interrupt and isochronous). Based on this, USBFS includes two request queues: periodic request queue and non-periodic request queue, to perform efficient transaction schedule.
Page 595 GD32F3x0 User Manual Suspend and Wake-up A USB device will enter into suspend state when the USB bus stays at IDLE state for 3ms. When USB device is in suspend state, most of its clock are closed to save power. The USB host is able to wake up the suspended device by generating a resume signal on USB bus.
Page 596 GD32F3x0 User Manual The Host Negotiation Protocol (HNP) allows the host function to be switched between two directly connected On-The-Go devices and eliminates the necessity of switching the cable connections for the change of control of communications between the devices. HNP will be initialized typically by the user or an application on the On-The-Go B-Device.
Page 597: Figure 23-5. Host Mode Fifo Space In Sram
GD32F3x0 User Manual transmission packet. All IN channels shares the Rx FIFO for packets reception. All the periodic OUT channels share the periodic Tx FIFO to packets transmission. All the non-periodic OUT channels share the non-Periodic Tx FIFO for transmit packets. The size and start offset of these data FIFOs should be configured using these registers: USBFS_GRFLEN, USBFS_HNPTFLEN and USBFS_HPTFLEN.
Page 598: Figure 23-7. Device Mode Fifo Space In Sram
GD32F3x0 User Manual Device mode In device mode, the data FIFO is divided into several parts: one Rx FIFO and 4 Tx FIFOs (one for each IN endpoint). All the OUT endpoints share the Rx FIFO for receiving packets. The size and start offset of these data FIFOs should be configured using USBFS_GRFLEN and USBFS_DIEPxTFLEN (x=0…3) registers.
Page 599 GD32F3x0 User Manual Figure 23-8. Device mode FIFO access register map 23.5.6. Operation guide This section describes the advised operation guide for USBFS. Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the TxFIFO’s empty threshold, etc.
Page 600 GD32F3x0 User Manual Channel initialization and enable sequence 1. Program USBFS_HCHxCTL registers with desired transfer type, direction, packet size, etc. Ensure that CEN and CDIS bits keep cleared during configuration. 2. Program USBFS_HCHxINTEN register. Set the desired interrupt enable bits.
Page 601 GD32F3x0 User Manual the received data packet into the Rx FIFO and triggers ACK flag. Otherwise, the status flag (NAK) reports the transaction result. 7. If the IN transaction described in step 5 is successful and PCNT is larger than 1 in step2, return to step 3 and continues to receive the remaining packets.
Page 602 GD32F3x0 User Manual 2. Program USBFS_GUSBCS register according to application’s demand, such as: the operation mode (host, device or OTG) and some parameters of OTG and USB protocols. 3. Program USBFS_GCCFG register according to application’s demand. 4. Program USBFS_GRFLEN, USBFS_HNPTFLEN_DIEP0TFLEN, USBFS_DIEPxTFLEN register to configure the data FIFOs according to application’s demand.
Page 603: Table 23-2. Usbfs Global Interrupt
GD32F3x0 User Manual 1. Initialize USBFS global registers. 2. Initialize and enable the IN endpoint. 3. Write packets into the endpoint’s Tx FIFO. Each time a data packet is written into the FIFO, USBFS decreases the TLEN field in USBFS_DIEPxLEN register by the written packet’s size.
Page 604 GD32F3x0 User Manual Interrupt Flag Description Operation Mode PTXFEIF Periodic Tx FIFO empty interrupt flag Host Mode HCIF Host channels interrupt flag Host Mode HPIF Host port interrupt flag Host Mode Periodic transfer Not Complete Interrupt ISOONCIF/PXNCI flag /Isochronous OUT transfer Not...
Page 605 GD32F3x0 User Manual 23.7. Register definition USBFS base address: 0x5000 0000 23.7.1. Global control and status registers Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit)
Page 606 GD32F3x0 User Manual Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes. 15:12...
Page 607 GD32F3x0 User Manual Note: Only accessible in device mode. SRPS SRP success This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP fails 1: SRP succeeds Note: Only accessible in device mode.
Page 608 GD32F3x0 User Manual Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP. Note: Accessible in both device and host modes.
Page 609 GD32F3x0 User Manual 1: NPTXFEIF will be triggered when the non-periodic transmit FIFO is completely empty 6：1 Reserved Must be kept at reset value GINTEN Global interrupt enable 0: Global interrupt is not enabled. 1: Global interrupt is enabled. Note: Accessible in both device and host modes.
Page 610 GD32F3x0 User Manual 28:14 Reserved Must be kept at reset value 13:10 UTT[3:0] USB turnaround time Turnaround time in PHY clocks. Note: Only accessible in device mode. HNPCEN HNP capability enable Controls whether the HNP capability is enabled 0: HNP capability is disabled 1: HNP capability is enabled Note: Accessible in both device and host modes.
Page 611 GD32F3x0 User Manual 31:11 Reserved Must be kept at reset value 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non-periodic Tx FIFO is flushed...
Page 612 GD32F3x0 User Manual Global interrupt flag register (USBFS_GINTF) Address offset: 0x0014 Reset value: 0x0400 0021 This register has to be accessed by word (32-bit) rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields...
Page 613 GD32F3x0 User Manual read USBFS_ HACHINT register to get the channel number, and then read the corresponding USBFS_HCHxINTF register to get the flags of the channel that cause the interrupt. This bit will be automatically cleared after the respective channel’s flags which cause channel interrupt are cleared.
Page 614 GD32F3x0 User Manual When USB bus time in a frame reaches the value defined by EOPFT [1:0] bits in USBFS_DCFG register, USBFS sets this flag. Note: Only accessible in device mode. ISOOPDIF Isochronous OUT packet dropped interrupt flag USBFS set this bit if it receives an isochronous OUT packet but cannot save it into Rx FIFO because the FIFO doesn’t have enough space.
Page 615 GD32F3x0 User Manual Start of frame Host Mode: USBFS sets this bit when it prepares to transmit a SOF or Keep-Alive on USB bus. Software can clear this bit by writing 1. Device Mode: USBFS sets this bit after it receives a SOF token. The application can read the Device Status register to get the current frame number.
Page 616 GD32F3x0 User Manual Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable wakeup interrupt 1: Enable wakeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes.
Page 617 GD32F3x0 User Manual Note: Only accessible in device mode. ISOINCIE Isochronous IN transfer not complete interrupt enable 0: Disable isochronous IN transfer not complete interrupt 1: Enable isochronous IN transfer not complete interrupt Note: Only accessible in device mode. OEPIE...
Page 618 GD32F3x0 User Manual Reserved Must be kept at reset value GONAKIE Global OUT NAK effective interrupt enable 0: Disable global OUT NAK interrupt 1: Enable global OUT NAK interrupt Note: Only accessible in device mode. GNPINAKIE Global non-periodic IN NAK effective interrupt enable...
Page 619 GD32F3x0 User Manual FIFO. The entries in Rx FIFO have different meanings in host and device modes. Software should only read this register after when Receive FIFO non-empty interrupt flag bit of the global interrupt flag register (RXFNEIF bit in USBFS_GINTF) is triggered.
Page 620 GD32F3x0 User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value 20:17 RPCKST[3:0] Received packet status 0001: Global OUT NAK (generates an interrupt) 0010: OUT data packet received 0011: OUT transfer completed (generates an interrupt) 0100: SETUP transaction completed (generates an interrupt)
Page 621 GD32F3x0 User Manual r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit words. 1≤RXFD≤1024 Host non-periodic transmit FIFO length register /Device IN endpoint 0 transmit FIFO length (USBFS_HNPTFLEN _DIEP0TFLEN)
Page 622 GD32F3x0 User Manual 31:16 IEP0TXFD[15:0] IN Endpoint 0 Tx FIFO depth In terms of 32-bit words. 16≤IEP0TXFD≤140 15:0 IEP0TXRSAR[15:0] IN Endpoint 0 TX RAM start address The start address for endpoint0 transmit FIFO RAM is in term of 32-bit words.
Page 623 GD32F3x0 User Manual 1: 1 entry 2: 2 entries … n: n entries (0≤n≤8) Others: Reserved 15:0 NPTXFS[15:0] Non-periodic Tx FIFO space The remaining space of the non-periodic transmit FIFO. In terms of 32-bit words. 0: Non-periodic Tx FIFO is full...
Page 624 GD32F3x0 User Manual SOFOEN SOF output enable 0: SOF pulse output disabled. 1: SOF pulse output enabled. VBUSBCEN The V B-device Comparer enable 0: V B-device comparer disabled 1: V B-device comparer enabled VBUSACEN The VBUS A-device Comparer enable 0: V...
Page 625 GD32F3x0 User Manual Host periodic transmit FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word 32-bit) r/rw r/rw Bits Fields Descriptions 31:16 HPTXFD[15:0] Host Periodic Tx FIFO depth In terms of 32-bit words.
Page 626 GD32F3x0 User Manual Bits Fields Descriptions 31:16 IEPTXFD[15:0] IN endpoint Tx FIFO depth In terms of 32-bit words. 1≤HPTXFD≤1024 15:0 IEPTXRSAR[15:0] IN endpoint FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32-bit words.
Page 627 GD32F3x0 User Manual controller is enumerating. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 FRI[15:0] Frame interval This value describes the frame time in terms of PHY clocks. Each time when port is enabled after a port reset operation, USBFS use a proper value according to the current speed, and software can write to this field to change the value.
Page 628 GD32F3x0 User Manual Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks. 15:0 FRNUM[15:0] Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF.
Page 629 GD32F3x0 User Manual … n: n entries (0≤n≤8) Others: Reserved 15:0 PTXFS[15:0] Periodic Tx FIFO space The remaining space of the periodic transmit FIFO. In terms of 32-bit words. 0: periodic Tx FIFO is full 1: 1 word 2: 2 words n: n words (0≤n≤PTXFD)
Page 630 GD32F3x0 User Manual channel whose corresponding bit in this register is set is able to cause the channel interrupt flag HCIF in USBFS_GINTF register. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:8 Reserved Must be kept at reset value...
Page 631 GD32F3x0 User Manual Bits Fields Descriptions 31:19 Reserved Must be kept at reset value 18:17 PS[1:0] Port speed Report the enumerated speed of the device attached to this port. 01: Full speed 10: Low speed Others: Reserved 16:13 Reserved Must be kept at reset value Port power This bit should be set before a port is used.
Page 632 GD32F3x0 User Manual 0: No resume driven 1: Resume driven Reserved Must be kept at reset value PEDC Port enable/disable change Set by the core when the status of the Port enable bit 2 in this register changes. Port Enable This bit is automatically set by USBFS after a USB reset signal finishes and cannot be set by software.
Page 633 GD32F3x0 User Manual Channel enable Set by the application and cleared by USBFS. 0: Channel disabled 1: Channel enabled Software should following the operation guide to disable or enable a channel. CDIS Channel disable Software can set this bit to disable the channel from processing transactions. Software should follow the operation guide to disable or enable a channel.
Page 634 GD32F3x0 User Manual Reset value: 0x0000 0000 This register contains the status and events of a channel, when software gets a channel interrupt, it should read this register for the respective channel to know the source of the interrupt. The flag bits in this register are all set by hardware and cleared by writing 1.
Page 635 GD32F3x0 User Manual STALL STALL A STALL response is received. Reserved Must be kept at reset value Channel halted This channel is disabled by a request, and it will not response to other requests during the request processing. Transfer finished All the transactions of this channel finish successfully, and no error occurs.
Page 636 GD32F3x0 User Manual REQOVRIE Request queue overrun interrupt enable 0: Disable request queue overrun interrupt 1: Enable request queue overrun interrupt BBERIE Babble error interrupt enable 0: Disable babble error interrupt 1: Enable babble error interrupt USBERIE USB bus error interrupt enable...
Page 637 GD32F3x0 User Manual Bits Fields Descriptions Reserved Must be kept at reset value 30:29 DPID[1:0] Data PID Software should write this field before the transfer starts. For OUT transfers, this field controls the Data PID of the first transmitted packet. For IN transfers, this field controls the expected Data PID of the first received packet, and DTERR will be triggered if the Data PID doesn’t match.
Page 638 GD32F3x0 User Manual commands or enumeration. Do not change this register after device initialization. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:13 Reserved Must be kept at reset value 12:11 EOPFT[1:0] End of periodic frame time This field defines the percentage time point in a frame that the end of periodic frame (EOPF) flag should be triggered.
Page 639 GD32F3x0 User Manual Device control register (USBFS_DCTL) Address offset: 0x0804 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:12 Reserved Must be kept at reset value POIF Power-on initialization finished Software should set this bit to notify USBFS that the registers are initialized after waking up from power down state.
Page 640 GD32F3x0 User Manual the OUT data packet are decided by Rx FIFO status, endpoint’s NAK and STALL bits. 1: USHBS always responses to OUT transaction with NAK handshake and doesn’t save the incoming OUT data packet. GINS Global IN NAK status 0: The response to IN transaction is decided by Tx FIFO status, endpoint’s NAK and...
Page 641 GD32F3x0 User Manual USBFS always update this field after receiving a SOF token Reserved Must be kept at reset value ES[1:0] Enumerated speed This field reports the enumerated device speed. Read this field after the ENUMF flag in USBFS_GINTF register is triggered.
Page 642 GD32F3x0 User Manual Reserved Must be kept at reset value EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 0: Disable endpoint Tx FIFO underrun interrupt 1: Enable endpoint Tx FIFO underrun interrupt CITOEN Control IN timeout interrupt enable bit 0: Disable control IN timeout interrupt...
Page 643 GD32F3x0 User Manual 0: Disable back-to-back SETUP packets interrupt 1: Enable back-to-back SETUP packets interrupt Reserved Must be kept at reset value EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable bit 0: Disable endpoint Rx FIFO overrun interrupt 1: Enable endpoint Rx FIFO overrun interrupt...
Page 644 GD32F3x0 User Manual 19:16 OEPITB[3:0] Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value IEPITB[3:0] Device all IN endpoint interrupt bits Each bit represents an IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3.
Page 645 GD32F3x0 User Manual Each bit represents an IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3. Device VBUS discharge time register (USBFS_DVBUSDT) Address offset: 0x0828 Reset value: 0x0000 17D7 This register has to be accessed by word (32-bit)
Page 646 GD32F3x0 User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DVBUSPT[11:0] Device V pulsing time This field defines the pulsing time for V The true pulsing time is 1024*DVBUSPT[11:0] BUS. , where T is the period time of USB clock.
Page 647 GD32F3x0 User Manual This register has to be accessed by word (32-bit) Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint.
Page 648 GD32F3x0 User Manual NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are cleared: 0: USBFS sends data or handshake packets according to the status of the endpoint’s Tx FIFO.
Page 649 GD32F3x0 User Manual Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should following the operation guide to disable or enable an endpoint.
Page 650 GD32F3x0 User Manual NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are are cleared: 0: USBFS sends data or handshake packets according to the status of the endpoint’s Tx FIFO.
Page 651 GD32F3x0 User Manual Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable This bit is fixed to 0 for OUT endpoint 0.
Page 652 GD32F3x0 User Manual this bit. Reserved Must be kept at reset value EPACT Endpoint active This field is fixed to ‘1’ for endpoint 0. 14:2 Reserved Must be kept at reset value MPL[1:0] Maximum packet length This is a read-only field, and its value comes from the MPL field of USBFS_DIEP0CTL...
Page 653 GD32F3x0 User Manual Software can set this bit to disable the endpoint. Software should follow the operation guide to disable or enable an endpoint. SODDFRM Set odd frame (For isochronous OUT endpoints) This bit has effect only if this is an isochronous OUT endpoint.
Page 654 GD32F3x0 User Manual GONS bit in USBFS_DCTL register are cleared: 0: USBFS sends handshake packets according to the status of the endpoint’s Rx FIFO. 1: USBFS always sends NAK handshake to the OUT token. This bit is read-only and software should use CNAK and SNAK in this register to control this bit.
Page 655 GD32F3x0 User Manual rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TXFE Transmit FIFO empty The Tx FIFO of this IN endpoint has reached the empty threshold value defined by TXFTH field in USBFS_GAHBCS register.
Page 656 GD32F3x0 User Manual rc_w1/rw rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:7 Reserved Must be kept at reset value BTBSTP Back-to-back SETUP packets (Only for control OUT endpoint) This flag is triggered when a control out endpoint has received more than 3 back-to-back setup packets.
Page 657 GD32F3x0 User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value 20:19 PCNT[1:0] Packet count The number of data packets desired to be transmitted in a transfer. Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet transmission.
Page 658 GD32F3x0 User Manual Bits Fields Descriptions Reserved Must be kept at reset value 30:29 STPCNT[1:0] SETUP packet count This field defines the maximum number of back-to-back SETUP packets this endpoint can accept. Program this field before setup transfers. Each time a back-to-back setup packet is received, USBFS decrease this field by one.
Page 659 GD32F3x0 User Manual Bits Fields Descriptions Reserved Must be kept at reset value 30:29 MCPF[1:0] Multi packet count per frame This field indicates the packet count that must be transmitted per frame for periodic IN endpoints on the USB. It is used to calculate the data PID for isochronous IN endpoints by the core.
Page 660 GD32F3x0 User Manual Bits Fields Descriptions Reserved Must be kept at reset value 30:29 RXDPID[1:0] Received data PID (For isochronous OUT endpoints) This field saves the PID of the latest received data packet on this endpoint. 00: DATA0 10: DATA1...
Page 661 GD32F3x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 IEPTFS[15:0] IN endpoint’s Tx FIFO space remaining IN endpoint’s Tx FIFO space remaining in 32-bit words: 0: FIFO is full 1: 1 word available …...
Page 662 GD32F3x0 User Manual 0: HCLK is not stopped 1: HCLK is stopped SUCLK Stop the USB clock Stop the USB clock to save power. 0: USB clock is not stopped 1: USB clock is stopped...
Page 663: Table 24-1. Revision History
PB9 pin is disabled, and the speed control of the pin is bypassed. Modified Table 1 1. Memory map of GD32F3x0 series: the SRAM address size range from 20K to 16K. Arm® Cortex®-M4 processor and Figure 1 1. The May.31, 2021...
Page 664 GD32F3x0 User Manual description of the temperature sensor. Register definition chapter: modified the description of EWIE bit in WWDGT_CFG register. Modified the description Power management unit (PMU) chapter. Add GD32F310 series products. Jan.06, 2022 Modified the description Inter-integrated circuit interface (I2C) chapter.
Page 665 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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