GigaDevice Semiconductor GD32A508 Series User Manual

Arm cortex-m33 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32A508xx

Arm

Cortex

-M33 32-bit MCU

User Manual

Revision 1.5

(Dec. 2024)

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Summary of Contents for GigaDevice Semiconductor GD32A508 Series

Page 1 GigaDevice Semiconductor Inc. GD32A508xx ® Cortex -M33 32-bit MCU ® User Manual Revision 1.5 (Dec. 2024)
Page 2: Table Of Contents
GD32A508xx User Manual Table of Contents Table of Contents ......................2 List of Figures ......................18 List of Tables ........................ 27 1. System and memory architecture ................ 31 ® ® 1.1. Cortex -M33 processor ..................31 1.2. System architecture ....................... 32 1.3.
Page 3 GD32A508xx User Manual 2.4.5. Control register (FMC_CTL) ....................55 2.4.6. Address register (FMC_ADDR) .................... 57 2.4.7. Option byte status register (FMC_OBSTAT) ................. 57 2.4.8. Erase/Program protection register (FMC_WP) ..............58 2.4.9. Product ID register (FMC_PID)..................... 58 3. Backup registers (BKP) ..................60 3.1.
Page 4 GD32A508xx User Manual 5.3.1. Control register (RCU_CTL) ....................90 5.3.2. Clock configuration register 0 (RCU_CFG0) ................ 92 5.3.3. Clock interrupt register (RCU_INT) ..................96 5.3.4. APB2 reset register (RCU_APB2RST) ................. 99 5.3.5. APB1 reset register (RCU_APB1RST) ................101 5.3.6. AHB enable register (RCU_AHBEN) .................. 104 5.3.7.
Page 5 GD32A508xx User Manual 7.5.1. Hardware trigger ......................... 143 7.5.2. Software trigger........................143 7.6. EXTI Register ........................ 145 7.6.1. Interrupt enable register (EXTI_INTEN) ................145 7.6.2. Event enable register (EXTI_EVEN) .................. 145 7.6.3. Rising edge trigger enable register (EXTI_RTEN) ............. 146 7.6.4.
Page 6 GD32A508xx User Manual 8.5.6. Port bit clear register (GPIOx_BC, x=A..G) ................ 165 8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G) ............ 165 8.5.8. Port bit speed register (GPIOx_ SPD, x=A..G) ..............166 8.5.9. Event control register (AFIO_EC) ..................167 8.5.10. AFIO port configuration register 0 (AFIO_PCF0) ............... 167 8.5.11.
Page 7 GD32A508xx User Manual 10.3.10. Mode 7 description ......................200 10.3.11. Mode 8 description ......................201 10.4. Software guideline ....................201 10.5. TMU register ......................203 10.5.1. Input data0 register (TMU_IDATA0) ................... 203 10.5.2. Input data1 register (TMU_IDATA1) ................... 203 10.5.3. Control register (TMU_CTL) ....................
Page 8 GD32A508xx User Manual 12.3. Debug hold function description ................223 12.3.1. Debug support for power saving mode ................223 12.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN ..........224 12.4. DBG registers ......................225 12.4.1. ID code register (DBG_ID) ....................225 12.4.2.
Page 9 GD32A508xx User Manual 13.7.9. Routine sequence register 1 (ADC_RSQ1) ................ 253 13.7.10. Routine sequence register 2 (ADC_RSQ2) ................ 253 13.7.11. Routine data register (ADC_RDATA) .................. 254 13.7.12. Oversample control register (ADC_OVSAMPCTL) ............254 13.7.13. Watchdog 1 channel selection register (ADC_WD1SR) ............. 256 13.7.14.
Page 10 GD32A508xx User Manual 15.1. Overview ........................279 15.2. Characteristics ......................279 15.3. Function overview ....................279 15.3.1. CMP clock ........................... 280 15.3.2. CMP I / O configuration ...................... 280 15.3.3. CMP register write protection ..................... 281 15.3.4. CMP output blanking......................282 15.4.
Page 11 GD32A508xx User Manual 17.4.9. RTC alarm high register (RTC_ALRMH) ................308 17.4.10. RTC alarm low register (RTC_ALRML) ................308 Timer (TIMERx) ....................309 18.1. Advanced timer (TIMERx, x=0, 7) ................310 18.1.1. Overview ..........................310 18.1.2. Characteristics ........................310 18.1.3. Block diagram ........................
Page 12 GD32A508xx User Manual 19.4.2. Slave_TIMERx(x=0..4) unit ....................472 19.4.3. DLL calibrate ........................503 19.4.4. Bunch mode ........................503 19.4.5. Synchronization input/output ....................508 19.4.6. External event ........................509 19.4.7. Fault input ..........................511 19.4.8. Trigger to ADC ........................513 19.4.9. Trigger to DAC ........................
Page 13 GD32A508xx User Manual 22.2. Characteristics ......................775 22.2.1. SPI characteristics ......................775 22.2.2. I2S characteristics ......................775 22.3. SPI function overview ....................776 22.3.1. SPI block diagram ....................... 776 22.3.2. SPI signal description ......................776 22.3.3. SPI clock timing and data format ..................777 22.3.4.
Page 14 GD32A508xx User Manual 23.3.7. Read/Write operation flow ....................821 23.3.8. SQPI controller mode timing ....................821 23.4. Register definition ....................823 23.4.1. SQPI Initial Register (SQPI_INIT)..................823 23.4.2. SQPI Read Command Register (SQPI_RCMD) ..............824 23.4.3. SQPI Write Command Register (SQPI_WCMD) ..............825 23.4.4.
Page 15 GD32A508xx User Manual 25.4.4. Receive message FIFO0 register (CAN_RFIFO0) ............. 890 25.4.5. Receive message FIFO1 register (CAN_RFIFO1) ............. 890 25.4.6. Interrupt enable register (CAN_INTEN) ................891 25.4.7. Error register (CAN_ERR) ....................893 25.4.8. Bit timing register (CAN_BT) ....................894 25.4.9. FD control register (CAN_FDCTL)..................
Page 16 GD32A508xx User Manual 26.4.4. MAC hash list low register (ENET_MAC_HLL) ..............970 26.4.5. MAC PHY control register (ENET_MAC_PHY_CTL) ............970 26.4.6. MAC PHY data register (ENET_MAC_PHY_DATA) ............971 26.4.7. MAC flow control register (ENET_MAC_FCTL) ..............971 26.4.8. MAC VLAN tag register (ENET_MAC_VLT) ............... 973 26.4.9.
Page 17 GD32A508xx User Manual 26.4.46. DMA transmit poll enable register (ENET_DMA_TPEN) ..........1001 26.4.47. DMA receive poll enable register (ENET_DMA_RPEN) ........... 1002 26.4.48. DMA receive descriptor table address register (ENET_DMA_RDTADDR) ...... 1002 26.4.49. DMA transmit descriptor table address register (ENET_DMA_TDTADDR) ..... 1003 26.4.50.
Page 18: List Of Figures
GD32A508xx User Manual List of Figures Figure 1-1. The structure of the Cortex ® -M33 processor ............. 31 Figure 1-2. GD32A508xx system architecture ................. 33 Figure 2-1. Process of page erase operation .................. 45 Figure 2-2. Process of mass erase operation ................. 47 Figure 2-3.
Page 19 GD32A508xx User Manual Figure 13-12. Routine parallel mode on 10 channels ..............243 Figure 13-13. Routine follow-up fast mode on routine sequence (the CTN bit of the ADCs are set) ............................. 243 Figure 13-14. Routine follow-up slow mode on routine sequence channel ......244 Figure 14-1.
Page 20 GD32A508xx User Manual Figure 18-29. Trigger TIMER0 and TIMER2 by the CI0 signal of TIMER2 ....... 337 Figure 18-30. General Level 0 timer block diagram ..............366 Figure 18-31. Timing chart of internal clock divided by 1 ............367 Figure 18-32. Timing chart of PSC value change from 0 to 2 ............ 368 Figure 18-33.
Page 21 GD32A508xx User Manual Figure 19-2. Master_TIMER diagram....................464 Figure 19-3. Counter clock when divided by 32 ................466 Figure 19-4. Counter behavior in single pulse mode ..............467 Figure 19-5. Counter behavior in continuous mode ..............467 Figure 19-6. Repetition counter behavior in continuous mode ..........468 Figure 19-7.
Page 22 GD32A508xx User Manual Figure 19-46. Trigger to ADC selection overview ................. 513 Figure 19-47. Trigger to DAC selection overview ................. 515 Figure 19-48. DMA mode operation flowchart ................517 Figure 20-1. USART module block diagram................... 638 Figure 20-2. USART character frame (8 bits data and 1 stop bit) ..........639 Figure 20-3.
Page 23 GD32A508xx User Manual Figure 21-11. Programming model for master transmitting (10-bit address mode) .... 712 Figure 21-12. Programming model for master receiving using Solution A (10-bit address mode) ............................... 714 Figure 21-13. Programming model for master receiving mode using solution B (10-bit address mode) ..........................
Page 24 GD32A508xx User Manual Figure 22-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ..791 Figure 22-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ..791 Figure 22-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ..792 Figure 22-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ..792 Figure 22-19.
Page 25 GD32A508xx User Manual Figure 22-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ........................798 Figure 22-48. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ........................798 Figure 22-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ........................
Page 26 GD32A508xx User Manual Figure 24-24. Access to none "NCE don’t care" NAND Flash ..........854 Figure 25-1. CAN module block diagram ..................869 Figure 25-2. Transmission register ....................871 Figure 25-3. State of transmit mailbox .................... 872 Figure 25-4. Reception register ......................873 Figure 25-5.
Page 27: List Of Tables
GD32A508xx User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ......32 Table 1-2. Memory map of GD32A508xx devices ................35 Table 1-3. Boot modes ........................... 39 Table 2-1. GD32A508xx base address and size for flash memory ..........42 Table 2-2.
Page 28 GD32A508xx User Manual Table 13-4. t timings depending on resolution ..............239 CONV Table 13-5. Maximum output results for N and M combimations (grayed values indicates truncation) ............................240 Table 13-6. ADC sync mode table ..................... 241 Table 14-1. DAC I/O description ......................261 Table 14-2.
Page 29 GD32A508xx User Manual Table 21-4. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) ........................... 736 Table 21-5. Data setup time and data hold time ................741 Table 21-6. Communication modes to be shut down ..............743 Table 21-7.
Page 30 GD32A508xx User Manual Table 26-8. Source address filtering table ..................922 Table 26-9. Error status decoding in Receive Descriptor0, only used for normal descriptor (DFM=0) ............................947 Table 26-10. Supported time stamp snapshot with PTP register configuration....994 Table 27-1. USBHS signal description ..................1017 Table 27-2.
Page 31: System And Memory Architecture
GD32A508xx User Manual System and memory architecture The devices of GD32A508xx series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M33 processor. The Arm Cortex -M33 processor includes two AHB buses ® ® known as Code and System buses. All memory accesses of the Arm Cortex -M33 processor are executed on these two buses according to the different purposes and the target memory...
Page 32: System Architecture
GD32A508xx User Manual Cortex-M33 processor Cortex-M33 core Nested Interrupts Vectored Floating Point Interrupt Unit(FPU) Controller (NVIC) DSP Extension Data Breakpoint Memory Watchpoint Unit Protection And Trace (BPU) Unit(MPU) (DWT) Serial-Wire Or JTAG Instrumentation Trace Port Debug Port Access port Bus Matrix Trace Macrocell Interface Unit (SWDP or...
Page 33: Figure 1-2. Gd32A508Xx System Architecture
GD32A508xx User Manual CBUS SBUS DMA0 DMA1 ENET OTGHS APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including CBUS, SBUS, DMA0, DMA1, ENET and OTGHS. CBUS is the code bus of the Cortex®-M33 core, which is used for any instruction fetch and data access to the Code region. Similarly, SBUS is the system bus of the Cortex®-M33 core, which is used for instruction/vector fetches, data loading/storing and debugging access of the system regions.
Page 34: Memory Map
GD32A508xx User Manual SW/JTAG TPIU POR/ PDR Flash Flash ARM Cortex-M33 Memory Memory Cbus Processor Controller : 180MHz Fmax:180MHz NVIC Master FMC SQPI TMU CRC 1.1V GP DMA 12 chs Slave AHB Peripherals Master 8MHz ENET SRAM SRAM Master Controller Slave HXTAL OTGHS...
Page 35: Table 1-2. Memory Map Of Gd32A508Xx Devices
GD32A508xx User Manual the software complexity of repeated implementation of different device vendors. In the map, ® ® some regions are used by the Arm Cortex -M33 system peripherals which can not be modified. However, the other regions are available to the vendors. Table 1-2.
Page 36 GD32A508xx User Manual Pre-defined Address Peripherals Regions 0x4002 1000 - 0x4002 13FF 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF Reserved...
Page 37 GD32A508xx User Manual Pre-defined Address Peripherals Regions 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF I2C2 0x4000 8C00 - 0x4000 BFFF Reserved 0x4000 8800 - 0x4000 8BFF CAN2SRAM 0x4000 8400 - 0x4000 87FF USBSRAM_B 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved...
Page 38: On-Chip Sram Memory
GD32A508xx User Manual Pre-defined Address Peripherals Regions 0x2006 0000 - 0x2006 FFFF Reserved 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2000 0000 - 0x2001FFFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF F000 - 0x1FFF F7FF 0x1FFF C010 - 0x1FFF EFFF...
Page 39: Boot Configuration
GD32A508xx User Manual Boot configuration 1.4. The GD32A508xx devices provide three kinds of boot sources which can be selected by the BOOT0 and BOOT1 pins. The details are shown in the following table. The value on the two pins is latched on the 4th rising edge of CK_SYS after a reset. It is up to the user to set the BOOT0 and BOOT1 pins after a power-on reset or a system reset to select the required boot source.
Page 40: Unique Device Id (96 Bits)
GD32A508xx User Manual FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes. Example: 0x0080 indicates 128 Kbytes. 15:0 FLASH_DENSITY Flash memory density [15:0] The value indicates the Flash memory density of the device in Kbytes. Example: 0x0200 indicates 512 Kbytes.
Page 41: System Configuration Registers
GD32A508xx User Manual The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID System configuration registers 1.6. Base address: 0x4002 103C Reset value: 0x0000 0000 Reserved Reserved Reserved Bits Fields Descriptions...
Page 42: Flash Memory Controller (Fmc)
GD32A508xx User Manual Flash memory controller (FMC) Overview 2.1. The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 512K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 43: Read Operations
GD32A508xx User Manual Block Name Address range Size(bytes) Information bloc Boot loader area 0x1FFF B000- 0x1FFF F7FF 18KB Option bytes block Option bytes 0x1FFF F800 - 0x1FFF F80F One-time program block OTP bytes 0x1FFF_7000~0x1FFF_77FF Note: The information block stores the boot loader. This block cannot be programmed or erased by user.
Page 44: Unlock The Fmc_Ctl Register
GD32A508xx User Manual Current buffer: The current buffer is always enabled. Each time read from flash memory, 128-bit data get and store in current buffer. The CPU only need 32-bit or 16-bit in each read operation. So in the case of sequential code, the next data can get from current buffer without repeat fetch from flash memory.
Page 45: Page Erase
GD32A508xx User Manual operations to the FMC_KEY, will set the LK bit to 1, and lock the FMC_CTL register, and lead to a bus error. The OBPG bit and OBER bit in the FMC_CTL are still protected even the FMC_CTL is unlocked.
Page 46: Mass Erase
GD32A508xx User Manual Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Mass erase 2.3.5.
Page 47: Main Flash Programming
GD32A508xx User Manual Since all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or using the debugging tool that accesses the FMC registers directly. Additionally, the mass erase operation will be ignored if any page is erase/program protected.
Page 48: Figure 2-3. Process Of Word Program Operation
GD32A508xx User Manual  Unlock the FMC_CTL register if necessary.  Check the BUSY bit in the FMC_STAT register to confirm that no flash memory operation is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ...
Page 49: Otp Programming
GD32A508xx User Manual Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish Note: Reading the flash should be avoided when a program/erase operation is ongoing in the same bank.
Page 50: Option Bytes Modify
GD32A508xx User Manual  Wait until the OBWEN bit is set in the FMC_CTL register.  Set the OBER bit in the FMC_CTL register.  Send the option bytes erase command to the FMC by setting the START bit in the FMC_CTL register.
Page 51: Page Erase / Program Protection
GD32A508xx User Manual Table 2-3. Option bytes Address Name Description option bytes security protection value 0xA5 : no security protection 0x1fff f800 any value except 0xA5 or 0xCC : protection level low 0xCC : protection level high 0x1fff f801 SPC_N SPC complement value [7:3]: reserved [2]: nRST_STDBY...
Page 52: Security Protection
GD32A508xx User Manual set and the ERRIE bit is also set to 1 to enable the corresponding interrupt, then the flash operation error interrupt will be triggered by the FMC to draw the attention of the CPU. The page protection function can be individually enabled by configuring the WP [31:0] bit field to 0 in the option bytes.
Page 53: Register Definition
GD32A508xx User Manual Register definition 2.4. FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0630 This register has to be accessed by word (32-bit) Reserved Reserved DCRST ICRST DCEN ICEN Reserved PFEN Reserved WSCNT[2:0] Bits...
Page 54: Unlock Key Register (Fmc_Key)
GD32A508xx User Manual 001: 1 wait state added 010: 2 wait state added 011: 3 wait state added 100: 4 wait state added 101 ~111: reserved Unlock key register (FMC_KEY) 2.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) KEY[31:16] KEY[15:0] Bits...
Page 55: Status Register (Fmc_Stat)
GD32A508xx User Manual Status register (FMC_STAT) 2.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ENDF WPERR PGAERR PGERR Reserved BUSY rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 56 GD32A508xx User Manual Reserved ENDIE Reserved ERRIE OBWEN Reserved START OBER OBPG Reserved Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. ENDIE End of operation interrupt enable bit This bit is set or cleared by software 0: no interrupt generated by hardware. 1: end of operation interrupt enable Reserved Must be kept at reset value.
Page 57: Address Register (Fmc_Addr)
GD32A508xx User Manual 1: main flash mass erase command Main flash page erase command bit This bit is set or clear by software 0: no effect 1: main flash page erase command Main flash program command bit This bit is set or clear by software 0: no effect 1: main flash program command Note: This register should be reset after the corresponding flash operation completed.
Page 58: Erase/Program Protection Register (Fmc_Wp)
GD32A508xx User Manual Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:10 DATA[15:0] Store DATA[15:0] of option bytes block after system reset. USER[7:0] Store USER of option bytes block after system reset. Option bytes security protection code 0: no protection 1: protection OBERR...
Page 59 GD32A508xx User Manual Bits Field Descriptions 31:0 PID[31:0] Product reserved ID code register These bits are read only by software. These bits are unchanged constant after power on. These bits are one time program when the chip produced.
Page 60: Backup Registers (Bkp)
GD32A508xx User Manual Backup registers (BKP) Overview 3.1. The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, they are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from Standby mode or system reset do not affect these registers.
Page 61 GD32A508xx User Manual and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection configuration should be set before enable TAMPER pin.
Page 62: Register Definition
GD32A508xx User Manual Register definition 3.4. BKP base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..41) 3.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved DATA [15:0] Bits...
Page 63: Tamper Pin Control Register (Bkp_Tpctl)
GD32A508xx User Manual This bit is reset only by a Backup domain reset. CCOSEL RTC clock output selection 0: RTC clock div 64 1: RTC clock This bit is reset only by a POR. 13:10 Reserved Must be kept at reset value. ROSEL RTC output selection 0: RTC alarm pulse is selected as the RTC output...
Page 64: Tamper Control And Status Register (Bkp_Tpcs)
GD32A508xx User Manual 31:2 Reserved Must be kept at reset value. TPAL TAMPER pin active level 0: The TAMPER pin is active high 1: The TAMPER pin is active low TPEN TAMPER detection enable 0: The TAMPER pin is free for GPIO functions 1: The TAMPER pin is dedicated for the Backup Reset function.
Page 65 GD32A508xx User Manual This bit is always read as 0. Tamper event reset 0: No effect 1: Reset the TEF bit This bit is always read as 0.
Page 66: Power Management Unit (Pmu)
GD32A508xx User Manual Power management unit (PMU) Overview 4.1. The power consumption is regarded as one of the most important issues for the devices of GD32A508xx series. According to the Power management unit (PMU), provides five types of power saving modes, including Sleep, Deep-sleep, Deep-sleep 1, Deep-sleep 2 and Standby mode.
Page 67: Backup Domain
GD32A508xx User Manual Backup Domain Power Switch 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD BREG PB15 WKUPN NRST WKUPF FWDGT SLEEPING Cortex-M33 SLEEPDEEP HXTAL AHB IPs APB IPs 1.1V Domain 1.1V Domain Domain IRC8M IRC40K 3.3V IRC48M PLLs POR/PDR LVD: Low Voltage Detector LDO: Voltage Regulator BPOR: V...
Page 68: Vdd / V Dda
GD32A508xx User Manual of the RTC configuration and operation will be described in the Real-time clock (RTC). When the Backup domain is supplied by V pin is connected to V ), the following functions are available:  Real-time clock (RTC). PC13 can be used as GPIO or RTC function pin described in the ...
Page 69: Figure 4-3. Waveform Of The Lvd Threshold
GD32A508xx User Manual hyst RSTTEMPO Power Reset (Active Low) The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL0). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register(PMU_CS0), indicates if V is higher or lower than the LVD threshold.
Page 70: Power Domain
GD32A508xx User Manual is implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V , and V should be connected to V through the specific circuit independently. Otherwise, when the and V are provided by different power supplies, the difference between V and V...
Page 71: Deep Sleep Mode
GD32A508xx User Manual down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals. Besides, five power saving modes are provided to achieve even lower power consumption, they are Sleep mode, Deep-sleep mode, Deep-sleep 1 mode, Deep-sleep 2 mode and Standby mode.
Page 72 GD32A508xx User Manual Normal-driver / Low-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL0 register. The low-power mode enters depending on the LDOLP bit set in the PMU_CTL0 register. Low-driver / Normal-power: The low-driver mode in Deep-sleep mode when the LDO in normal-power mode depending on the LDOLP bit reset in the PMU_CTL0 register enters by configure LDEN to 0b11 and LDNP to 1 in the PMU_CTL0 register.
Page 73: Table 4-1. Power Saving Mode Summary
GD32A508xx User Manual domain; includes SRAM (except the first 32K). Deep-sleep 2 mode The Deep-sleep 2 mode is based on the SLEEPDEEP mode of the Cortex ® -M33. In Deep- sleep 2 mode, all clocks in the 1.1V domain are off, and all of IRC8M, IRC48M, HXTAL and PLLs are disabled.
Page 74 GD32A508xx User Manual Mode Sleep Deep-sleep Deep-sleep 1 Deep-sleep 2 Standby is off 1.1V domain are off. 1.1V domain are off. domain are off. domain 2. Disable IRC8M, 2. Disable IRC8M, Disable IRC8M, power off. IRC48M, HXTAL IRC48M, HXTAL and IRC48M, HXTAL and Disable...
Page 75: Register Definition
GD32A508xx User Manual Register definition 4.4. PMU base address: 0x4000 7000 Control register 0 (PMU_CTL0) 4.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). LDEN[1:0] Reserved HDEN Reserved LDNP...
Page 76 GD32A508xx User Manual 1: Low-driver mode enabled when LDEN is 11 and use normal power LDO LDLP Low-driver mode when use low power LDO. 0: normal driver when use low power LDO 1: Low-driver mode enabled when LDEN is 11 and use low power LDO Reserved Must be kept at reset value.
Page 77: Control And Status Register 0 (Pmu_Cs0)
GD32A508xx User Manual Note: Some peripherals may work with the IRC8M clock in the Deep-sleep / Deep- sleep 1 / Deep-sleep 2 mode. In this case, the LDO automatically switches from the low power mode to the normal mode and remains in this mode until the peripheral stop working.
Page 78 GD32A508xx User Manual Reserved Must be kept at reset value. WUPEN5 WKUP Pin5(PB5) Enable 0: Disable WKUP pin5 function 1: Enable WKUP pin5 function If WUPEN5 is set before entering the power saving mode, a rising edge on the WKUP pin5 wakes up the system from the power saving mode. As the WKUP pin5 is active high, the WKUP pin5 is internally configured to input pull down mode.
Page 79: Control Register 1 (Pmu_Ctl1)
GD32A508xx User Manual is active high, the WKUP pin0 is internally configured to input pull down mode. And set this bit will trigger a wakup event when the input is aready high. WUPEN6 WKUP Pin6(PB15) Enable 0: Disable WKUP pin6 function 1: Enable WKUP pin6 function If WUPEN6 is set before entering the power saving mode, a rising edge on the WKUP pin6 wakes up the system from the power saving mode.
Page 80: Control And Status Register 1 (Pmu_Cs1)
GD32A508xx User Manual 31:2 Reserved Must be kept at reset value. DPMOD2 Deep-sleep 2 mode enable 0: Not care 1:Go to Deep-sleep 2 mode when SLEEPDEEP bit is set and the STBMOD bit is clear DPMOD1 Deep-sleep 1 mode enable 0: Not care 1:Go to Deep-sleep 1 mode when the SLEEPDEEP bit is set and the STBMOD bit is clear and the DPMOD2 bit is clear...
Page 81: Reset And Clock Unit (Rcu)
GD32A508xx User Manual Reset and clock unit (RCU) Reset control unit (RCTL) 5.1. Overview 5.1.1. GD32A508xx reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 82: Clock Control Unit (Cctl)
GD32A508xx User Manual source (external or internal reset). Figure 5-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us pulse System Reset FWDGT_RSTn generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn OBL_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have...
Page 83 GD32A508xx User Manual CK_PLLUSB USBHS PHY clock 24Mhz to 60Mhz (to USBHS in high-speed mode) PLLUSBPR CK48MSEL[1:0] ESEL PLLUSBMF USBHSDV PLLUSBPREDV 480MHz CK_PLL2 PHSEL CK_IRC48M × 16,17 ,1 /1,2,3 1 48 MHz/ /2,4 16 60MHz PLLUSB CK_USBHS CK_HXTAL USBHS (to USBHS) CK_PLL1 Presacaler PLLUSBPRE...
Page 84 GD32A508xx User Manual I2C2SEL bits in configuration register 2 (RCU_CFG2). The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1). The PLLUSB is clocked by the clock of HXTAL or the clock of IRC48M which defined by PLLUSBPRESEL bit in RCC_ADDCFG register.
Page 85: Characteristics
GD32A508xx User Manual Characteristics 5.2.2.  4 to 32 MHz high speed crystal oscillator (HXTAL).  Internal 8 MHz RC oscillator (IRC8M).  Internal 48 MHz RC oscillator (IRC48M).  32,768 Hz low speed crystal oscillator (LXTAL).  Internal 40KHz RC oscillator (IRC40K). ...
Page 86: Phase Locked Loop (Pll)
GD32A508xx User Manual Internal 8M RC oscillators (IRC8M) The internal 8M RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up. The IRC8M oscillator provides a lower cost type clock source as no external components are required.
Page 87 GD32A508xx User Manual The PLL can be switched on or off by using the PLLEN bit in the RCU_CTL register. The PLLSTB flag in the RCU_CTL register will indicate if the PLL clock is stable. An interrupt can be generated if the related interrupt enable bit, PLLSTBIE, in the RCU_INT Register, is set as the PLL becomes stable.
Page 88: System Clock (Ck_Sys) Selection
GD32A508xx User Manual the RTC and FWDGT counter. Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register. System clock (CK_SYS) selection After the system reset, the default CK_SYS source will be IRC8M and can be switched to HXTAL or CK_PLL by changing the system clock switch bits, SCS, in the clock configuration register 0, RCU_CFG0.
Page 89: Voltage Control
GD32A508xx User Manual Voltage control The 1.1V domain voltage in Deep-sleep mode can be controlled by DSLPVS[2:0] bit in the Deep-sleep mode voltage register (RCU_DSV). Table 5-2. 1.1V domain voltage selected in deep-sleep mode DSLPVS[2:0] Deep-sleep mode voltage(V)
Page 90: Register Definition
GD32A508xx User Manual Register definition 5.3. RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB Reserved...
Page 91 GD32A508xx User Manual Set by hardware to indicate if the PLL output clock is stable and ready for use. 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock.
Page 92: Clock Configuration Register 0 (Rcu_Cfg0)
GD32A508xx User Manual ± 1%. Reserved Must be kept at reset value. IRC8MSTB IRC8M internal 8MHz RC oscillator stabilization flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable...
Page 93 GD32A508xx User Manual 0111: (CK_PLL / 2) clock selected 1000: CK_PLL1 clock selected 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 1100: CK_IRC48M clock selected 1101: (CK_IRC48M / 8) clock selected 1110: (CK_PLLUSB / 32) clock selected 23:22 USBHSPSC[1:0]...
Page 94 GD32A508xx User Manual 010101: (PLL source clock x 22) 010110: (PLL source clock x 23) 010111: (PLL source clock x 24) 011000: (PLL source clock x 25) 011001: (PLL source clock x 26) 011010: (PLL source clock x 27) 011011: (PLL source clock x 28) 011100: (PLL source clock x 29) 011101: (PLL source clock x 30) 011110: (PLL source clock x 31)
Page 95 GD32A508xx User Manual Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0] APB1 prescaler selection Set and reset by software to control the APB1 clock division ratio.
Page 96: Clock Interrupt Register (Rcu_Int)
GD32A508xx User Manual Clock interrupt register (RCU_INT) 5.3.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIC STBIC STBIC STBIC STBIC STBIC STBIC STBIC PLL2 PLL1 HXTAL...
Page 97 GD32A508xx User Manual 1: Reset IRC8MSTBIF flag LXTALSTBIC LXTAL stabilization interrupt clear Write 1 by software to reset the LXTALSTBIF flag. 0: Not reset LXTALSTBIF flag 1: Reset LXTALSTBIF flag IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by software to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag Reserved...
Page 98 GD32A508xx User Manual CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck. Reset when setting the CKMIC bit by software. 0: Clock operating normally 1: HXTAL clock stuck PLL2STBIF PLL2 stabilization interrupt flag Set by hardware when the PLL2 is stable and the PLL2STBIE bit is set. Reset when setting the PLL2STBIC bit by software.
Page 99: Apb2 Reset Register (Rcu_Apb2Rst)
GD32A508xx User Manual IRC40KSTBIE bit is set. Reset when setting the IRC40KSTBIC bit by software. 0: No IRC40K stabilization clock ready interrupt generated 1: IRC40K stabilization interrupt generated APB2 reset register (RCU_APB2RST) 5.3.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 100 GD32A508xx User Manual This bit is set and reset by software. 0: No reset 1: Reset the TIMER9 TIMER8RST Timer 8 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER8 18:15 Reserved Must be kept at reset value. USART0RST USART0 Reset This bit is set and reset by software.
Page 101: Apb1 Reset Register (Rcu_Apb1Rst)
GD32A508xx User Manual 1: Reset the GPIO port F PERST GPIO port E reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port E PDRST GPIO port D reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port D PCRST...
Page 102 GD32A508xx User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DACRST DAC reset This bit is set and reset by software. 0: No reset 1: Reset DAC unit PMURST Power control reset This bit is set and reset by software. 0: No reset 1: Reset power control unit BKPIRST...
Page 103 GD32A508xx User Manual This bit is set and reset by software. 0: No reset 1: Reset the UART4 UART3RST UART3 reset This bit is set and reset by software. 0: No reset 1: Reset the UART3 USART2RST USART2 reset This bit is set and reset by software. 0: No reset 1: Reset the USART2 USART1RST...
Page 104: Ahb Enable Register (Rcu_Ahben)
GD32A508xx User Manual TIMER11RST TIMER11 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER11 TIMER6RST TIMER6 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER6 TIMER5RST TIMER5 reset This bit is set and reset by software.
Page 105 GD32A508xx User Manual ENETTX USBHSE FMCSPE SRAMSP ENETEN ULPIEN Reserved EXMCEN Reserved CRCEN Reserved Reserved DMA1EN DMA0EN Bits Fields Descriptions SQPIEN SQPI clock enable This bit is set and reset by software. 0: Disabled SQPI clock 1: Enabled SQPI clock TMUEN TMUEN clock enable This bit is set and reset by software.
Page 106: Apb2 Enable Register (Rcu_Apb2En)
GD32A508xx User Manual 1: Enabled EXMC clock Reserved Must be kept at reset value. CRCEN CRC clock enable This bit is set and reset by software. 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value. FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software to enable/disable FMC clock during Sleep mode.
Page 107 GD32A508xx User Manual Bits Fields Descriptions CMPEN CMP clock enable This bit is set and reset by software. 0: Disabled CMP clock 1: Enabled CMP clock Reserved Must be kept at reset value SHRTIMEREN SHRTIMER clock enable This bit is set and reset by software. 0: Disabled SHRTIMER clock 1: Enabled SHRTIMER clock USART5EN...
Page 108 GD32A508xx User Manual This bit is set and reset by software. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER0EN TIMER0 clock enable This bit is set and reset by software. 0: Disabled TIMER0 clock 1: Enabled TIMER0 clock ADC1EN ADC1 clock enable This bit is set and reset by software.
Page 109: Apb1 Enable Register (Rcu_Apb1En)
GD32A508xx User Manual PAEN GPIO port A clock enable This bit is set and reset by software. 0: Disabled GPIO port A clock 1: Enabled GPIO port A clock Reserved Must be kept at reset value. AFEN Alternate function IO clock enable This bit is set and reset by software.
Page 110 GD32A508xx User Manual This bit is set and reset by software. 0: Disabled CAN1 clock 1: Enabled CAN1 clock CAN0EN CAN0 clock enable This bit is set and reset by software. 0: Disabled CAN0 clock 1: Enabled CAN0 clock I2C2EN I2C2 clock enable This bit is set and reset by software.
Page 111 GD32A508xx User Manual This bit is set and reset by software. 0: Disabled SPI2 clock 1: Enabled SPI2 clock SPI1EN SPI1 clock enable This bit is set and reset by software. 0: Disabled SPI1 clock 1: Enabled SPI1 clock 13:12 Reserved Must be kept at reset value.
Page 112: Backup Domain Control Register (Rcu_Bdctl)
GD32A508xx User Manual This bit is set and reset by software. 0: Disabled TIMER3 clock 1: Enabled TIMER3 clock TIMER2EN TIMER2 clock enable This bit is set and reset by software. 0: Disabled TIMER2 clock 1: Enabled TIMER2 clock TIMER1EN TIMER1 clock enable This bit is set and reset by software.
Page 113: Reset Source/Clock Register (Rcu_Rstsck)
GD32A508xx User Manual RTCSRC[1:0] RTC clock entry selection Set and reset by software to control the RTC clock source. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. 00: No clock selected 01: CK_LXTAL selected as RTC source clock 10: CK_IRC40K selected as RTC source clock 11: (CK_HXTAL / 128) selected as RTC source clock...
Page 114 GD32A508xx User Manual IRC40K IRC40KE Reserved Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated. Reset by writing 1 to the RSTFC bit. 0: No Low-power management reset generated 1: Low-power management reset generated WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated.
Page 115: Ahb Reset Register (Rcu_Ahbrst)
GD32A508xx User Manual 1: Clear reset flags 23:2 Reserved Must be kept at reset value. IRC40KSTB IRC40K stabilization flag Set by hardware to indicate if the IRC40K output clock is stable and ready for use. 0: IRC40K is not stable 1: IRC40K is stable IRC40KEN IRC40K enable...
Page 116: Clock Configuration Register 1 (Rcu_Cfg1)
GD32A508xx User Manual Reserved Must be kept at reset value. USBHSRST USBHS reset This bit is set and reset by software. 0: No reset 1: Reset the USBHS 11:0 Reserved Must be kept at reset value. Clock configuration register 1 (RCU_CFG1) 5.3.12.
Page 117 GD32A508xx User Manual 1: (CK_PLL2 x 2) selected as I2S2 source clock I2S1SEL I2S1 clock source selection Set and reset by software to control the I2S1 clock source. 0: System clock selected as I2S1 source clock 1: (CK_PLL2 x 2) selected as I2S1 source clock PREDV0SEL PREDV0 input clock source selection Set and reset by software.
Page 118 GD32A508xx User Manual 00xx: Reserve 010x: Reserve 0110: (PLL1 source clock x 8) 0111: (PLL1 source clock x 9) 1000 :(PLL1 source clock x 10) 1001: (PLL1 source clock x 11) 1010: (PLL1 source clock x 12) 1011: (PLL1 source clock x 13) 1100: (PLL1 source clock x 14) 1101: reserve 1110 :(PLL1 source clock x 16)
Page 119: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32A508xx User Manual 1000: PREDV0 input source clock divided by 9 1001: PREDV0 input source clock divided by 10 1010: PREDV0 input source clock divided by 11 1011: PREDV0 input source clock divided by 12 1100: PREDV0 input source clock divided by 13 1101: PREDV0 input source clock divided by 14 1110: PREDV0 input source clock divided by 15 1111: PREDV0 input source clock divided by 16...
Page 120 GD32A508xx User Manual PLLUSBS PLLUSBE USBSWE USBHSS Reserved USBHSDV[2:0] CK48MSEL[1:0] Bits Fields Descriptions 31:24 IRC48MCALIB [7:0] Internal 48MHz RC oscillator calibration value register These bits are load automatically at power on. 23:18 Reserved Must be kept at reset value. IRC48MSTB Internal 48MHz RC oscillator clock stabilization flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use.
Page 121: Additional Clock Configuration Register (Rcu_Addcfg)
GD32A508xx User Manual 1: 60M clock selected as USBHS source clock CK48MSEL[1:0] USB 48M clock source selection 00: not effect (select PLL/USBPRE) 01: CK_IRC48M select as CK48M clock source 10: CK_PLLUSB/USBHSDV select as CK48M clock source 11: CK_PLL2 select as CK48M clock source Additional Clock configuration register (RCU_ADDCFG) 5.3.15.
Page 122: Additional Clock Interrupt Register (Rcu_Addint)
GD32A508xx User Manual 15:4 Reserved Must be kept at reset value. PLLUSBPREDV[3:0] PLLUSBPREDV division factor This bit is set and reset by software. 0000: Reserved 0001: PLLUSBPREDV input source clock divided by 1 0010: PLLUSBPREDV input source clock divided by 2 0011: PLLUSBPREDV input source clock divided by 3 0100: PLLUSBPREDV input source clock divided by 4 0101: PLLUSBPREDV input source clock divided by 5...
Page 123: Pll Clock Spread Spectrum Control Register (Rcu_Pllssctl)
GD32A508xx User Manual Write 1 by software to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag 1: Reset IRC48MSTBIF flag 21:16 Reserved Must be kept at reset value. PLLUSBSTBIE PLLUSB stabilization interrupt enable Set and reset by software to enable/disable the PLLUSB stabilization interrupt 0: Disable the PLLUSB stabilization interrupt 1: Enable the PLLUSB stabilization interrupt IRC48MSTBIE...
Page 124: Clock Configuration Register 2 (Rcu_Cfg2)
GD32A508xx User Manual Where f represents the PLL input clock frequency, f represents the spread spectrum PLLIN modulation frequency, mdamp represents the spread spectrum modulation amplitude expressed as a percentage, PLLN represents the PLL clock frequency multiplication factor. SSCGON SS_TYPE MODSTEP[14:3] Reserved MODSTEP[2:0]...
Page 125: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32A508xx User Manual 00: APB1 clock selected as I2C2 source clock 01: System clock selected as I2C2 source clock 1x: CK_IRC8M clock selected as I2C2 source clock Reserved Must be kept at reset value. USART5SEL[1:0] USART5 clock source selection Set and reset by software to control the USART5 clock source. 00: CK_APB2 selected as USART5 source clock 01: CK_SYS selected as USART5 source clock 10: CK_LXTAL selected as USART5 source clock...
Page 126 GD32A508xx User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). CAN2EN Reserved Reserved Reserved Bits Fields Descriptions CAN2EN CAN2 enable This bit is set and reset by software. 0: Disabled CAN clock 1: Enabled CAN clock 30:28 Reserved Must be kept at reset value.
Page 127: Clock Trim Controller (Ctc)
GD32A508xx User Manual Clock trim controller (CTC) Overview 6.1. The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the frequency of the IRC48M based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 128: Ref Sync Pulse Generator
GD32A508xx User Manual PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 6.3.1. Firstly, the reference signal source can select GPIO(CTC_SYNC) or LXTAL clock by setting REFSEL bits in CTC_CTL1 register.
Page 129: Frequency Evaluation And Automatically Trim Process
GD32A508xx User Manual next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT). The detail is showing in Figure 6-2.
Page 130: Software Program Guide
GD32A508xx User Manual changed.  CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register add 1 when down-counting or sub 1 when up-counting.
Page 131 GD32A508xx User Manual The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 132: Register Definition
GD32A508xx User Manual Register definition 6.4. CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE...
Page 133: Control Register 1 (Ctc_Ctl1)
GD32A508xx User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim warning (CKWARNIF) interrupt enable...
Page 134: Status Register (Ctc_Stat)
GD32A508xx User Manual 00: GPIO (CTC_SYNC) selected 01: LXTAL clock selected 10: Reserved. 11: Reserved Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8...
Page 135 GD32A508xx User Manual When a reference sync pulse occurred, the CTC trim counter value is captured to REFCAP bits. REFDIR CTC trim counter direction when reference sync pulse When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit.
Page 136: Interrupt Clear Register (Ctc_Intc)
GD32A508xx User Manual register is set, an interrupt occur. This bit is cleared by writing 1 to ERRIC bit in CTC_INTC register. 0 : No Error occur 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 137 GD32A508xx User Manual CTC_STAT register. Write 0 is no effect. ERRIC ERRIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear ERRIF, TRIMERR, REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0.
Page 138: Interrupt/Event Controller (Exti)
GD32A508xx User Manual Interrupt/event controller (EXTI) Overview 7.1. ® Cortex -M33 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and power management controls. It’s tightly coupled to the processer core. You can read the -M33 for more details about NVIC.
Page 139: Table 7-1. Nvic Exception Types In Cortex ® -M33
GD32A508xx User Manual ® Table 7-1. NVIC exception types in Cortex -M33 Vector Exception type priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable...
Page 140 GD32A508xx User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ 18 ADC0 and ADC1 global interrupts 0x0000_0088 IRQ 19 CAN0 TX interrupt 0x0000_008C IRQ 20 CAN0 RX0 interrupt 0x0000_0090 IRQ 21 CAN0 RX1 interrupt 0x0000_0094 IRQ 22 CAN0 EWMC interrupt 0x0000_0098 IRQ 23...
Page 141 GD32A508xx User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ 49 reserved 0x0000_0104 IRQ50 TIMER4 global interrupt 0x0000_0108 IRQ51 SPI2 or I2S2ADD global interrupt 0x0000_010C IRQ52 UART3 global interrupt 0x0000_0110 IRQ53 UART4 global interrupt 0x0000_0114 IRQ54 TIMER5 or DAC global interrupt 0x0000_0118 IRQ55 TIMER6 global interrupt...
Page 142: External Interrupt And Event (Exti) Block Diagram
GD32A508xx User Manual External interrupt and event (EXTI) block diagram 7.4. Figure 7-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~21 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External Interrupt and event function overview 7.5.
Page 143: Hardware Trigger
GD32A508xx User Manual Hardware trigger 7.5.1. Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in AFIO module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 144 GD32A508xx User Manual EXTI Line Source Number RTC Alarm USB Wakeup Ethernet Wakeup I2C2 Wakeup USART5 Wakeup...
Page 145: Exti Register
GD32A508xx User Manual EXTI Register 7.6. EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 146: Rising Edge Trigger Enable Register (Exti_Rten)
GD32A508xx User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN21 RTEN20 RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5...
Page 147: Pending Register (Exti_Pd)
GD32A508xx User Manual This register has to be accessed by word(32-bit). Reserved SWIEV21 SWIEV20 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. Interrupt / Event software trigger x (x = 0…21) 21: 0 SWIEVx...
Page 148: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32A508xx User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 8.1. There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions.
Page 149: Gpio Pin Configuration
GD32A508xx User Manual Table 8-1. GPIO configuration table Configuration mode CTL[1:0] SPDy: MD[1:0] OCTL don’t care Analog don’t care Input floating Input x 00 Input pull-down Input pull-up x 00: Reserved Push-pull 0 or 1 General purpose x 01: Speed up to 10MHz Output (GPIO) Open-drain 0 or 1...
Page 150: External Interrupt / Event Lines
GD32A508xx User Manual PA13: JTMS / SWDIO in PU mode. PB4: NJTRST in PU mode. PB3: JTDO in Floating mode. The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen.
Page 151: Output Configuration
GD32A508xx User Manual Alternate Function Input protect I / O pin Input driver Input Read Status Register Output configuration 8.3.5. When GPIO pin is configured as output:  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors are disabled. ...
Page 152: Alternate Function (Af) Configuration
GD32A508xx User Manual Figure 8-4. Basic structure of Analog configuration shows the analog configuration. Figure 8-4. Basic structure of Analog configuration protection Analog ( Input / Output ) I/O pin Alternate function (AF) configuration 8.3.7. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software.
Page 153: Gpio Locking Function
GD32A508xx User Manual GPIOx_CTL0/GPIOx_CTL1 registers. And set output function by configuring MDy bits to 0b01, 0b10, or 0b11 and configuring CTLy bits of corresponding port in GPIOx_CTL0 / GPIOx_CTL1 register to 0b00 (for GPIO push-pull output) or 0b01 (for GPIO open-drain output). Alternate function: Each IO pin can be used for AF input function by configuring MDy bits to 0b00 in GPIOx_CTL0 / GPIOx_CTL1 registers.
Page 154: Main Features
GD32A508xx User Manual Main features 8.4.2.  APB slave interface for register access.  EXTI source selection.  Each pin has up to four alternative functions for configuration. JTAG / SWD alternate function remapping 8.4.3. The debug interface signals are mapped on the GPIO ports as shown in table below. Table 8-2.
Page 155 GD32A508xx User Manual TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 8，9，10，12， function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER0_ETI PA12 TIMER0_CH0 TIMER0_CH1 PE11 TIMER0_CH2 PA10 PE13 TIMER0_CH3 PA11 PE14 TIMER0_BRKI PB12 PE15 TIMER0_CH0_ PB13 TIMER0_CH1_ PB14 PE10...
Page 156: Usart Af Remapping
GD32A508xx User Manual 1(AFIO_PCF1). Table 8-5. TIMER4 alternate function remapping Alternate function TIMER4CH3_IREMAP = 0 TIMER4CH3_IREMAP = 1 IRC40K internal clock is TIMER4_CH3 TIMER4_CH3 is connected to PA3 connected to TIMER4_CH3 input for calibration purpose USART AF remapping 8.4.5. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-6.
Page 157: I2C0 Af Remapping
GD32A508xx User Manual I2C0 AF remapping 8.4.6. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-7. I2C0 alternate function remapping I2C0_SCL I2C0_SDA Register I2C0_REMAP = 0 I2C0_REMAP = 1 SPI0 / SPI2 / I2S AF remapping 8.4.7. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-8.
Page 158: Ethernet Af Remapping
GD32A508xx User Manual Register CAN0 CAN1 PB12(CAN1_RX) CAN1_REMAP = “0” PB13(CAN1_TX) PB5(CAN1_RX) CAN1_REMAP = “1” PB6(CAN1_TX) Ethernet AF remapping 8.4.9. Table 8-10. ENET alternate function remapping Register ENET PA7(RX_DV - CRS_DV) PC4(RXD0) ENET_REMAP = “0” PC5(RXD1) PB0(RXD2) PB1(RXD3) PD8(RX_DV - CRS_DV) PD9(RXD0) ENET_REMAP = “1”...
Page 159: Table 8-13. Osc Pins Configuration
GD32A508xx User Manual Alternate function LXTAL= ON LXTAL= OFF PC14 OSC32_IN PC14 PC15 OSC32_OUT PC15 The HXTAL oscillator pins OSC_IN / OSC_OUT can be used as general-purpose I/O PD0 / PD1. Table 8-13. OSC pins configuration Alternate function HXTAL= ON HXTAL = OFF OSC_IN OSC_OUT...
Page 160: Register Definition
GD32A508xx User Manual Register definition 8.5. GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..G) 8.5.1.
Page 161 GD32A508xx User Manual 23:22 CTL5[1:0] Port 5 configuration bits These bits are set and cleared by software. refer to CTL0[1:0]description 21:20 MD5[1:0] Port 5 mode bits These bits are set and cleared by software. refer to MD0[1:0]description 19:18 CTL4[1:0] Port 4 configuration bits These bits are set and cleared by software.
Page 162: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32A508xx User Manual 00: GPIO output with push-pull 01: GPIO output with open-drain 10: AFIO output with push-pull 11: AFIO output with open-drain MD0[1:0] Port 0 mode bits These bits are set and cleared by software. 00: Input mode (reset state) 01: Output mode(10MHz) 10: Output mode(2MHz) 11: Output mode(50MHz)
Page 163: Port Input Status Register (Gpiox_Istat, X=A
GD32A508xx User Manual 21:20 MD13[1:0] Port 13 mode bits These bits are set and cleared by software. refer to MD0[1:0]description 19:18 CTL12[1:0] Port 12 configuration bits These bits are set and cleared by software. refer to CTL0[1:0]description 17:16 MD12[1:0] Port 12 mode bits These bits are set and cleared by software.
Page 164: Port Output Control Register (Gpiox_Octl, X=A
GD32A508xx User Manual This register has to be accessed by word (32-bit). Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT 0 Bits Fields Descriptions 31:16...
Page 165: Port Bit Clear Register (Gpiox_Bc, X=A
GD32A508xx User Manual CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0...
Page 166: Port Bit Speed Register (Gpiox_ Spd, X=A
GD32A508xx User Manual Reserved LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. Lock sequence key It can only be setted using the Lock Key Writing Sequence. And can always be read. 0: GPIO_LOCK register is not locked and the port configuration is not locked.
Page 167: Event Control Register (Afio_Ec)
GD32A508xx User Manual Note: When the port output speed is more than 50 MHz, the user should enable the I/O compensation cell. Refer to CPS_EN bit in AFIO_CPSCTL register. Event control register (AFIO_EC) 8.5.9. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 168 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). TIMER1I TIMER4C PTP_PPS SPI2_RE ENET_P CAN1_R ENET_R Reserved TI1_REM Reserved SWJ_CFG[2:0] Reserved H3_IREM _REMAP HY_SEL EMAP EMAP PD01_RE TIMER3_ TIMER2_REMAP[1:0 TIMER1_REMAP[1:0 USART2_REMAP[1: USART1_ USART0_ I2C0_RE SPI0_RE CAN0_REMAP[1:0]...
Page 169 GD32A508xx User Manual 0: Disable the remapping function (CAN1_RX/PB12,CAN_TX/PB13) 1: Enable the remapping function (CAN1_RX/PB5,CAN_TX/PB6) ENET_REMAP Ethernet MAC I/O remapping 0: Disable the remapping function (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 1: Enable the remapping function (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) 20:17 Reserved Must be kept at reset value...
Page 170 GD32A508xx User Manual TIMER1_CH1/PB3, TIMER1_CH2/PB10, TIMER1_CH3/PB11) TIMER0_REMAP[1:0 TIMER0 remapping 00: Disable the remapping function (TIMER0_ETI / PA12, TIMER0_CH0 / PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11, TIMER0_BRKIN / PB12, TIMER0_CH0_ON / PB13, TIMER0_CH1_ON / PB14, TIMER0_CH2_ON / PB15) 01: Enable the remapping function partially (TIMER0_ETI / PA12, TIMER0_CH0 / PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11,...
Page 171: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32A508xx User Manual EXTI sources selection register 0 (AFIO_EXTISS0) 8.5.11. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI3_SS[3:0] EXTI2_SS[3:0] EXTI1_SS[3:0] EXTI0_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS [3:0] EXTI 3 sources selection...
Page 172: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32A508xx User Manual Other configurations are reserved. EXTI0_SS [3:0] EXTI 0 sources selection 0000: PA0 pin 0001: PB0 pin 0010: PC0 pin 0011: PD0 pin 0100: PE0 pin 0101: PF0 pin 0110: PG0 pin Other configurations are reserved. EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.12.
Page 173: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32A508xx User Manual 0110: PG6 pin Other configurations are reserved. EXTI5_SS [3:0] EXTI 5 sources selection 0000: PA5 pin 0001: PB5 pin 0010: PC5 pin 0011: PD5 pin 0100: PE5 pin 0101: PF5 pin 0110: PG5 pin Other configurations are reserved. EXTI4_SS [3:0] EXTI 4 sources selection 0000: PA4 pin...
Page 174: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32A508xx User Manual 0101: PF11 pin 0110: PG11 pin Other configurations are reserved. 11:8 EXTI10_SS [3:0] EXTI 10 sources selection 0000: PA10 pin 0001: PB10 pin 0010: PC10 pin 0011: PD10 pin 0100: PE10 pin 0101: PF10 pin 0110: PG10 pin Other configurations are reserved.
Page 175 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI15_SS [3:0] EXTI 15 sources selection 0000: PA15 pin 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin Other configurations are reserved.
Page 176: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32A508xx User Manual AFIO port configuration register 1 (AFIO_PCF1) 8.5.15. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXMC_N TIMER13 IMER12_ TIMER10 TIMER9_ TIMER8_ Reserved CTC_REMAP[1:0] Reserved _REMAP REMAP _REMAP REMAP REMAP Bits Fields...
Page 177: Io Compensation Control Register (Afio_Cpsctl)
GD32A508xx User Manual 0: Disable the remapping function (PB9) 1: Enable the remapping function (PF7) TIMER9_REMAP TIMER9 remapping This bit is set and cleared by software, it controls the mapping of the TIMER9_CH0 alternate function onto the GPIO ports 0: Disable the remapping function (PB8) 1: Enable the remapping function (PF6) TIMER8_REMAP TIMER8 remapping...
Page 178: Afio Port Configuration Register A (Afio_Pcfa)
GD32A508xx User Manual 1: I/O compensation cell is enable AFIO port configuration register A (AFIO_PCFA) 8.5.17. Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). PA15_AF PA10_ AFCFG [1:0] PA9_ AFCFG[1:0] PA8_ AFCFG [1:0] Reserved Reserved PA12_AFCFG [1:0]...
Page 179: Afio Port Configuration Register B (Afio_Pcfb)
GD32A508xx User Manual 11: Configure PA10 alternate function to SHRTIMER 19:18 PA9_AFCFG[1:0] PA9 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PA9 alternate function to SHRTIMER/CAN2/I2C2 01: Configure PA9 alternate function to CAN2 10: Configure PA9 alternate function to I2C2 11: Configure PA9 alternate function to SHRTIMER 17:16...
Page 180 GD32A508xx User Manual PB15_AF Reserved PB14_AFCFG[1:0] PB13_AFCFG[1:0] PB12_AFCFG[1:0] PB11_AFCFG[1:0] PB10_AFCFG[1:0] PB9_AFCFG[1:0] PB8_AFCFG[1:0] PB7_AFC PB6_AFC PB3_ PB0_ Reserved Reserved PB5_AFCFG[1:0] PB4_AFCFG[1:0] Reserved PB2_AFCFG[1:0] PB1_AFCFG[1:0] Reserved AFCFG AFCFG Bits Fields Descriptions Reserved Must be kept at reset value PB15_AFCFG PB15 AF function configuration bit This bit is set and cleared by software.
Page 181 GD32A508xx User Manual 10: Configure PB10 alternate function to USBHS 11: Configure PB10 alternate function to SHRTIMER 19:18 PB9_AFCFG[1:0] PB9 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PB9 alternate function to SHRTIMER/CMP1 01: Configure PB9 alternate function to CMP1 10/11: Configure PB9 alternate function to SHRTIMER 17:16...
Page 182: Afio Port Configuration Register C (Afio_Pcfc)
GD32A508xx User Manual 1: Configure PB3 alternate function to SHRTIMER PB2_AFCFG[1:0] PB2 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PB2 alternate function to SHRTIMER/USBHS 10: Configure PB2 alternate function to USBHS 01/11: Configure PB2 alternate function to SHRTIMER PB1_AFCFG[1:0] PB1 AF function configuration bits...
Page 183 GD32A508xx User Manual These bits are set and cleared by software. 00: Do not configure PC11 alternate to SHRTIMER/I2S2 01/11: Configure PC11 alternate function to SHRTIMER 10: Configure PC11 alternate function to I2S2 Reserved Must be kept at reset value. PC10_AFCFG PC10 AF function configuration bit This bit is set and cleared by software.
Page 184: Afio Port Configuration Register D (Afio_Pcfd)
GD32A508xx User Manual 10: Configure PC2 alternate function to USBHS Reserved Must be kept at reset value. PC0_AFCFG PC0 AF function configuration register This bit is set and cleared by software 0: Do not configure PC0 alternate function to USBHS 1: Configure PC0 alternate function to USBHS AFIO port configuration register D (AFIO_PCFD) 8.5.20.
Page 185 GD32A508xx User Manual PE13_AF PE12_AF PE11_AF PE10_AF PE9_AFC PE8_AFC Reserved Reserved Reserved Reserved Reserved Reserved Reserved PE1_AFCFG[1:0] PE0_AFCFG[1:0] Bits Fields Descriptions 31:27 Reserved Must be kept at reset value. PE13_AFCFG PE13 AF function configuration bit This bit is set and cleared by software. 0: Do not configure PE13 alternate function to CMP1 1: Configure PE13 alternate function to CMP1 Reserved...
Page 186: Afio Port Configuration Register G (Afio_Pcfg)
GD32A508xx User Manual 0: Do not configure PE8 alternate function to CMP1 1: Configure PE8 alternate function to CMP1 15:4 Reserved Must be kept at reset value. PE1_AFCFG[1:0] PE1 AF function configuration bits These bits are set and cleared by software. 00: Do not configure PE1 alternate function to SHRTIMER/CAN2 01: Configure PE1 alternate function to CAN2 10/11: Configure PE1 alternate function to SHRTIMER...
Page 187 GD32A508xx User Manual Reserved Must be kept at reset value. PG12_AFCFG PG12 AF function configuration bit This bit is set and cleared by software. 0: Do not configure PG12 alternate function to SHRTIMER 1: Configure PG12 alternate function to SHRTIMER Reserved Must be kept at reset value.
Page 188: Cyclic Redundancy Checks Management Unit (Crc)
GD32A508xx User Manual Cyclic redundancy checks management unit (CRC) Overview 9.1. A cyclic redundancy check management (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7/8/16/32 bit CRC code within user configurable polynomial.
Page 189: Function Overview
GD32A508xx User Manual Data Input Input Data Register (32 bit) CRC Management Unit configurable polynomial Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) Function overview 9.3.  CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result.
Page 190 GD32A508xx User Manual 32-bit data is divided into 4 groups and reverse implement in group inside. Reversed data: 0x2C6AB3F7 2) half-word reverse: 32-bit data is divided into 2 groups and reverse implement in group inside. Reversed data: 0x6A2CF7B3 3) word reverse: 32-bit data is divided into 1 groups and reverse implement in group inside.
Page 191: Register Definition
GD32A508xx User Manual Register definition 9.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 9.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 192: Control Register (Crc_Ctl)
GD32A508xx User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control register (CRC_CTL) 9.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O REV_I[1:0] PS[1:0] Reserved...
Page 193: Polynomial Register (Crc_Poly)
GD32A508xx User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. Polynomial register (CRC_POLY) 9.4.5.
Page 194: Trigonometric Math Unit (Tmu)
GD32A508xx User Manual Trigonometric Math Unit (TMU) Overview 10.1. The Trigonometric Math Unit (TMU) is a fully configurable block that execute common trigonometric and arithmetic operations. The TMU calculation unit can be used to calculate total 9 kinds of operations. The operation data must meet IEEE 32-Bit Single Precision Floating-Point Format.
Page 195: Data Format
GD32A508xx User Manual pre_process signals Interface data0 result_data Arithmetic Post error_data AHB Bus data1 Process Θ_i Core Θ_o Process Data and Control registers ctrl signals Data format 10.3.2. The operation data and calculation result data format is given in Table 10-2. IEEE 32-Bit Single Precision Floating-Point Format.
Page 196: Mode 0 Description
GD32A508xx User Manual (OVRF) is set to 1. The OVRF flag will remain latched until the next new operation is started. Rounding: There are various rounding formats supported by the IEEE standard. Rounding has no meaning for TMU operations (rounding is inherent in the implementation). Hence rounding mode is ignored by TMU operations.
Page 197: Mode 2 Description
GD32A508xx User Manual Mode 2 description 10.3.5. This operation is equivalent as R0 = √ x. x is the input operation data, R0 is the calculation result. This mode only has OVRF flag and UDRF =0. The OVRF condition is as below: /* Check if input is negative */ If( x <...
Page 198: Mode 4 Description
GD32A508xx User Manual This mode has no neither UDRF nor OVRF. If the result is too small, the result will return 0. Mode 4 description 10.3.7. This mode performs the following equivalent operation: 1. Make PerUnit equal to the fraction of x, PerUnit = fraction(x). 2.
Page 199: Figure 10-2. Calculation Of R1 (Quadrant) And R0 (Ratio) Based On Y And X Values
GD32A508xx User Manual The algorithm for this mode is as follows: if ( ( fabs(Y) == 0.0 ) & ( fabs(X) == 0.0 ) ) { R1( Quadrant ) = 0.0; R0( Ratio ) = 0.0; }else if ( fabs(Y) < = fabs(X) ) { R0( Ratio ) = Y / X;...
Page 200: Mode 7 Description
GD32A508xx User Manual If( (|Y| > |X|) & (Y >= 0) ) { Quadrant = 0.25; Ratio = -X/Y; } 0.125 (PU) = π/4 0.375 (PU) = 3*π/4 0.25 (PU) = π/2 If( (|Y| <= |X|) & (X < 0) & (Y >= 0) ) { Quadrant = 0.5;...
Page 201: Mode 8 Description
GD32A508xx User Manual Mode 8 description 10.3.11. This operation is equivalent as R0 = √x . x and y is the input operation data, R0 is the calculation result. This mode only has OVRF flag and UDRF =0. The OVRF condition is as below: If R0 result is too big for floating-point number (E >...
Page 202 GD32A508xx User Manual Write TMU_IDATA0 Mode==6 or Mode == 7 or Mode ==8 Write TMU_IDATA1 Configure mode and interrupt enable Write 1 into TMUEN bit Interrupt enabled? Polling and Wait Step into interrupt TMUEN==0 routine Read TMU_DATA0 Mode == 6 Read TMU_DATA1...
Page 203: Tmu Register
GD32A508xx User Manual TMU register 10.5. TMU base address: 0x4008 0000 Input data0 register (TMU_IDATA0) 10.5.1. Address offset: 0x00 Reset value: 0x3F80 0000 This register has to be accessed by word (32-bit). IDATA0[31:16] IDATA0[15:0] Bits Fields Descriptions 31:0 IDATA0[31:0] The value of input data Mode0~5: IDATA0 is the only operation data Mode6: IDATA0 is the X value Mode7: IDATA0 is the dividend...
Page 204: Control Register (Tmu_Ctl)
GD32A508xx User Manual mode7: IDATA1 is the divisor mode8: IDATA1 is the X value or Y value IDATA1 must meet IEEE 32-Bit Single Precision Floating-Point Format. Control register (TMU_CTL) 10.5.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CFIF...
Page 205: Data0 Register (Tmu_Data0)
GD32A508xx User Manual Data0 register (TMU_DATA0) 10.5.4. Address offset: 0x0C Reset value: 0x3400 0000 This register has to be accessed by word (32-bit). DATA0[31:16] DATA0[15:0] Bits Fields Descriptions 31:0 DATA0[31:0] The result of calculation Mode 0~5,7,8: TMU_DATA0 is the only result value Mode6: TMU_DATA0=Ratio of X and Y TMU_DATA0 must meet IEEE 32-Bit Single Precision Floating-Point Format.
Page 206 GD32A508xx User Manual This register has to be accessed by word (32-bit). Reserved Reserve UDRF OVRF Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. UDRF The flag of underflow 0: No underflow 1: Underflow This bit is set and cleared by hardware. when the next TMU calculation is started, this bit is cleared by hardware.
Page 207: Direct Memory Access Controller (Dma)
GD32A508xx User Manual Direct memory access controller (DMA) Overview 11.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 208: Function Overview
GD32A508xx User Manual AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state & counter management Transfer request As shown in Figure 11-1.
Page 209 GD32A508xx User Manual 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC 1: Read B3B2B1B0[31:0] @0x0 1: Write B1B0[15:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B5B4[15:0] @0x2 32 bits 16 bits 3: Read BBBAB9B8[31:0] @0x8...
Page 210: Peripheral Handshake
GD32A508xx User Manual – If no register configuration operations of the channel occurs before restart the DMA channel, the DMA will continue to complete the rest of the transmission. – If any register configuration operations occur, the DMA will restart a new transmission.
Page 211: Address Generation
GD32A508xx User Manual Address generation 11.4.4. Two kinds of address generation algorithm are implemented independently for memory and peripheral, including the fixed mode and the increased mode. The PNAGA and MNAGA bit in the DMA_CHxCTL register are used to configure the next address generation algorithm of peripheral and memory.
Page 212: Interrupt
GD32A508xx User Manual Configure the DMA_CHxPADDR register for setting the peripheral base address. Configure the DMA_CHxMADDR register for setting the memory base address. Configure the DMA_CHxCNT register to set the total transfer data number. 10. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the channel. Interrupt 11.4.8.
Page 213: Figure 11-4. Dma0 Request Mapping
GD32A508xx User Manual each channel of DMA0, and Table 11-4. DMA1 requests for each channel lists the support request from peripheral for each channel of DMA1. Figure 11-4. DMA0 request mapping Hardware priority ADC0 TIMER1_CH2 high Channel 0 TIMER3_CH0 SPI0_RX USART2_TX TIMER0_CH0 TIMER1_UP...
Page 214: Figure 11-5. Dma1 Request Mapping
GD32A508xx User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER2_CH3 TIMER2_CH0 ● ● ● ● TIMER2 TIMER2_CH2 TIMER2_UP TIMER2_TG ● ● ● TIMER3 TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_UP ● ● ● ● ●...
Page 215 GD32A508xx User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER7_CH3 TIMER7_CH2 ● TIMER7 TIMER7_TG TIMER7_CH0 TIMER7_CH1 TIMER7_UP TIMER7_CMT ● ● ● DAC_CH0 DAC_CH1 SPI2/I2S2_R ● SPI/I2S SPI2/I2S2_TX I2S2ADD_RX I2S2ADD_TX UART3_RX UART3_TX ● ● ● USART USART5_RX USART5_TX...
Page 216: Register Definition
GD32A508xx User Manual Register definition 11.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 11.5.1.
Page 217: Interrupt Flag Clear Register (Dma_Intc)
GD32A508xx User Manual Interrupt flag clear register (DMA_INTC) 11.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2...
Page 218 GD32A508xx User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 219: Channel X Counter Register (Dma_Chxcnt)
GD32A508xx User Manual CMEN Circular mode enable Software set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’.
Page 220: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer.
Page 221 GD32A508xx User Manual MADDR[15:0] Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 222: Debug (Dbg)
GD32A508xx User Manual Debug (DBG) Introduction 12.1. The GD32A508xx series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSightTM module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm ®...
Page 223: Jtag Daisy Chained Structure
GD32A508xx User Manual The pin assignment are: PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions (NJTRST tied to 1 by hardware).
Page 224: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32A508xx User Manual can debug in deep-sleep mode. When SLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN 12.3.2.
Page 225: Dbg Registers
GD32A508xx User Manual DBG registers 12.4. DEBUG base address: 0xE0044000 ID code register (DBG_ID) 12.4.1. Address offset: 0x00 Read only This register has to be accessed by word (32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software.
Page 226 GD32A508xx User Manual 0: no effect 1: Hold the TIMER10 counter for debug when core halted. TIMER9_HOLD TIMER9 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER9 counter for debug when core halted. TIMER8_HOLD TIMER8 hold bit This bit is set and reset by software.
Page 227 GD32A508xx User Manual 1: Hold the TIMER5 counter for debug when core halted. TIMER4_HOLD TIMER4 hold bit This bit is set and reset by software. 0: no effect 1: Hold the TIMER4 counter for debug when core halted. TIMER7_HOLD TIMER7 hold bit This bit is set and reset by software.
Page 228 GD32A508xx User Manual 0: no effect 1: Hold the WWDGT counter clock for debug when core halted. FWDGT_HOLD FWDGT hold bit This bit is set and reset by software. 0: no effect 1: Hold the FWDGT counter clock for debug when core halted. Reserved Must be kept at reset value.
Page 229: Analog-To-Digital Converter (Adc)
GD32A508xx User Manual Analog-to-digital converter (ADC) Introduction 13.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment(LSB) or the most significant bit alignment(MSB).
Page 230: Pins And Internal Signals
GD32A508xx User Manual  Module supply requirements: the typical power supply voltage is 3.3V: – 1.62V to 2.4V, with ADC maximum frequency is 14MHz. – 2.4V to 3.6V, with ADC maximum frequency is 35MHz.  ≤V ≤V Channel input range: V REF- REF+.
Page 231: Foreground Calibration Function
GD32A508xx User Manual watchdog event 0/1/2 SHRTIMER Analog watchdog watchdog 0/1/2 Trig select event 0/1/2 Interrupt Routine channels Channel Management ADC_IN0 ADC_IN1 GPIO Over Routine data registers ADC_IN15 SAR ADC （16 bits） sampler SENSE REFINT TOVS OVSS[3:0] self calibration REF+ OVSR[2:0] DRES[1:0] REF-...
Page 232: Adc Clock
GD32A508xx User Manual Delay 14 CK_ADC to wait for ADC stability. Set CALNUM. Set RSTCLB (optional). Set CLB=1. Wait until CLB=0. ADC clock 13.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller.
Page 233: Routine Sequence
GD32A508xx User Manual Routine sequence 13.4.5. The channel management circuit can organize the sampling conversion channels into a sequence: routine sequence. The routine sequence supports up to 16 channels, and each channel is called routine channel. The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length. The ADC_RSQ0~ADC_RSQ2 registers specify the selected channels of the routine sequence.
Page 234: Figure 13-3. Continuous Operation Mode
GD32A508xx User Manual set. In this mode, the ADC performs conversion on the channel specified in the RSQ0[4:0]. When the ADCON has been set high, the ADC samples and converts specified channel, once the corresponding software trigger or external trigger is active. The conversion data will be stored in the ADC_RDATA register.
Page 235: Figure 13-4. Scan Operation Mode, Continuous Operation Mode Disable
GD32A508xx User Manual CTN bit in the ADC_CTL1 register is set. Figure 13-4. Scan operation mode, continuous operation mode disable Software procedure for scan conversion on a routine sequence: Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure ADC_RSQx and ADC_SAMPTx registers.
Page 236: Conversion Result Threshold Monitor
GD32A508xx User Manual Software procedure for discontinuous conversion on a routine sequence: Set the DISRC bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register. Configure DISNUM[2:0] bits in the ADC_CTL0 register. Configure ADC_RSQx and ADC_SAMPTx registers. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need.
Page 237: Sample Time Configuration
GD32A508xx User Manual 6-bit resolution data alignment is different from 12-bit/10-bit/8-bit resolution data alignment, shown as Figure 13-8. 6-bit data storage mode Figure 13-8. 6-bit data storage mode Sample time configuration 13.4.9. The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers.
Page 238: Dma Request
GD32A508xx User Manual ETSRC[3:0] Trigger Source Trigger Type 1001 SHRTIMER_ADCTRIG2 1010~1111 reserved DMA request 13.4.11. The DMA request, which is enabled by the DMA bit of ADC_CTL1 register, is used to transfer data of routine sequence for conversion of more than one channel. The ADC generates a DMA request at the end of conversion of a routine channel.
Page 239: Programmable Resolution (Dres)
GD32A508xx User Manual Programmable resolution (DRES) 13.4.13. The resolution is configured by programming the DRES[1:0] bits in the ADC_OVSAMPCTL register. For applications that do not require high data accuracy, lower resolution allows faster conversion time. The DRES[1:0] bits must only be changed when the ADCON bit is reset. Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table 13-4.
Page 240: Figure 13-10. Numerical Example With 5-Bits Shift And Rounding
GD32A508xx User Manual Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. Figure 13-10. Numerical example with 5-bits shift and rounding shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.
Page 241: Adc Sync Mode
GD32A508xx User Manual 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Oversa shift shift shift shift shift shift shift shift shift mpling OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= ratio data 0000 0001 0010 0011 0100 0101 0110 0111 1000 0x1FFE 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x001F...
Page 242: Free Mode
GD32A508xx User Manual Routine data registers Routine （16 bits ） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO Routine Routine data registers ADC_IN15 （16 bits ） channels SENSE Syncl mode control EXTI_11 Routine trigger mux ADC0 (master) Free mode 13.5.1. In this mode , each ADC works independently and does not interfere with each other. Routine parallel mode 13.5.2.
Page 243: Routine Follow-Up Fast Mode
GD32A508xx User Manual Figure 13-12. Routine parallel mode on 10 channels Routine follow-up fast mode 13.5.3. The follow-up fast mode is applicable to sample the same channel of two ADCs. The source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register).
Page 244: Adc Interrupts
GD32A508xx User Manual after 14 ADC clock cycles, after the second 14 ADC clock cycles the ADC1 runs again. Continuous operation mode can’t be used in this mode, because it continuously converts the routine channel. The behavior of follow-up slow mode shows in the Figure 13-14.
Page 245: Adc Registers
GD32A508xx User Manual ADC registers 13.7. ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 Status register (ADC_STAT) 13.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). WDE2 WDE1 Reserved rc_w0 rc_w0 Reserved STRC Reserved...
Page 246: Control Register 0 (Adc_Ctl0)
GD32A508xx User Manual Cleared by software writing 0 to it or by reading the ADC_RDATA register. WDE0 Analog watchdog 0 event flag 0: Analog watchdog 0 event is not happened 1: Analog watchdog 0 event is happening Set by hardware when the converted voltage crosses the values programmed in the ADC_WDLT0 and ADC_WDHT0 registers.
Page 247 GD32A508xx User Manual 15:13 DISNUM[2:0] Number of conversions in discontinuous mode The number of channels to be converted after a trigger will be DISNUM+1 in routine sequence. Reserved Must be kept at reset value. DISRC Discontinuous mode on routine channels 0: Discontinuous operation mode on routine channels disable 1: Discontinuous operation mode on routine channels enable Reserved...
Page 248: Control Register 1 (Adc_Ctl1)
GD32A508xx User Manual 10001: ADC channel17 Other values are reserved. Note: ADC0 analog inputs Channel16 and Channel17 are internally connected to the temperature sensor, and to V inputs. ADC1 analog inputs Channel16, and REFINT Channel17 are internally connected to V Control register 1 (ADC_CTL1) 13.7.3.
Page 249 GD32A508xx User Manual 0110: EXTI Line11 0111: SWRCST 1000: SHRTIMER_ADCTRG0 1001: SHRTIMER_ADCTRG2 Others: Reserved. 16:12 Reserved Must be kept at reset value. Data storage alignment mode 0: LSB alignment 1: MSB alignment 10:9 Reserved Must be kept at reset value. DMA request enable 0: DMA request disable 1: DMA request enable...
Page 250: Sample Time Register 0 (Adc_Sampt0)
GD32A508xx User Manual 1: ADC enable Sample time register 0 (ADC_SAMPT0) 13.7.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved SPT17[2:0] SPT16[2:0] SPT15[2:1] SPT15[0] SPT14[2:0] SPT13[2:0] SPT12[2:0] SPT11[2:0] SPT10[2:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value.
Page 251: Watchdog High Threshold Register 0 (Adc_Wdht0)
GD32A508xx User Manual Reserved SPT9[2:0] SPT8[2:0] SPT7[2:0] SPT6[2:0] SPT5[2:1] SPT5[0] SPT4[2:0] SPT3[2:0] SPT2[2:0] SPT1[2:0] SPT0[2:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:27 SPT9[2:0] refer to SPT0[2:0] description 26:24 SPT8[2:0] refer to SPT0[2:0] description 23:21 SPT7[2:0] refer to SPT0[2:0] description 20:18 SPT6[2:0]...
Page 252: Watchdog Low Threshold Register 0 (Adc_Wdlt0)
GD32A508xx User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 WDHT0[11:0] High threshold for analog watchdog 0 These bits define the high threshold for the analog watchdog 0. Watchdog low threshold register 0 (ADC_WDLT0) 13.7.7. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 253: Routine Sequence Register 1 (Adc_Rsq1)
GD32A508xx User Manual 19:15 RSQ15[4:0] refer to RSQ0[4:0] description 14:10 RSQ14[4:0] refer to RSQ0[4:0] description RSQ13[4:0] refer to RSQ0[4:0] description RSQ12[4:0] refer to RSQ0[4:0] description Routine sequence register 1 (ADC_RSQ1) 13.7.9. Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RSQ11[4:0] RSQ10[4:0]...
Page 254: Routine Data Register (Adc_Rdata)
GD32A508xx User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ5[4:0] refer to RSQ0[4:0] description 24:20 RSQ4[4:0] refer to RSQ0[4:0] description 19:15 RSQ3[4:0] refer to RSQ0[4:0] description 14:10 RSQ2[4:0] refer to RSQ0[4:0] description RSQ1[4:0] refer to RSQ0[4:0] description RSQ0[4:0] The channel number (0..17) is written to these bits to select a channel as the nth conversion in the routine sequence.
Page 255 GD32A508xx User Manual Reserved DRES[1:0] Reserved TOVS OVSS[3:0] OVSR[2:0] Reserved OVSEN Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:12 DRES[1:0] ADC resolution 00: 12bit 01: 10bit 10: 8bit 11: 6bit 11:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software.
Page 256: Watchdog 1 Channel Selection Register (Adc_Wd1Sr)
GD32A508xx User Manual 110: 128x 111: 256x Note: The software allows this bit to be written only when ADCON=0 (this ensures that no conversion is in progress). Reserved Must be kept at reset value. OVSEN Oversampler Enable This bit is set and cleared by software. 0: Oversampler disabled 1: Oversampler enabled Note: The software allows this bit to be written only when ADCON=0 (this ensures...
Page 257: Watchdog 2 Channel Selection Register (Adc_Wd2Sr)
GD32A508xx User Manual Watchdog 2 channel selection register (ADC_WD2SR) 13.7.14. Address offset: 0xA4 Reset value: 0x00000000 This register has to be accessed by word(32-bit). Reserved AWD2CS[17:16] AWD2CS[15:0] Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. 17:0 AWD2CS[17:0] Analog watchdog 2 channel selection These bits are set and cleared by software.
Page 258: Watchdog Threshold Register 2 (Adc_Wdt2)
GD32A508xx User Manual These bits define the high threshold for the analog watchdog 1. Note: Software is allowed to write these bits only when the ADC is disabled (ADCON =0). 15:8 Reserved Must be kept at reset value. WDLT1[7:0] Low threshold for analog watchdog 1 These bits define the high threshold for the analog watchdog 1.
Page 259 GD32A508xx User Manual Reserved DIFCTL[17:16] DIFCTL DIFCTL[14:0] [15] Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. 17:15 DIFCTL[17:15] Differential mode for channel 17..15. These bits are read only. These channels are forced to single-ended input mode (either connected to a single-ended I/O port or to an internal channel). 14:0 DIFCTL[14:0] Differential mode for channel 14..0.
Page 260: Digital-To-Analog Converter (Dac)
GD32A508xx User Manual Digital-to-analog converter (DAC) Overview 14.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 261: Table 14-1. Dac I/O Description
GD32A508xx User Manual Figure 14-1. DAC block diagram DAC control register DBOFFx EXTI_9 TIMERx_ TRGO SHRTIMER_ DACTRIGx SWTRx DAC_ENx OUTx_DH buff Control logic Wave FIFO OUTx_DO (optional) 12-bit 12-bit 12-bit 12-bit Table 14-1. DAC I/O description Name Description Signal type Analog power supply Input, analog supply Ground for analog power supply...
Page 262: Function Overview
GD32A508xx User Manual DAC0 SHRTIMER_DACTRIG2 SHRTIMER Note: The GPIO pins should be configured to analog mode before enable the DAC module. Function overview 14.3. DAC enable 14.3.1. The DAC can be turned on by setting the DENx bit in the DAC_CTL0 register. A t time WAKEUP is needed to startup the analog DAC submodule.
Page 263: Dac Conversion
GD32A508xx User Manual DTSELx[3:0] Trigger Source Trigger Type 4b’0111 SWTR Software trigger 4b’1000 SHRTIMER_DACTRIG0 4b’1001 SHRTIMER_DACTRIG1 Hardware trigger 4b’1010 SHRTIMER_DACTRIG2 4b’1011~1111 Reserved Reserved The TIMERx_TRGO signals are generated from the timers, the SHRTIMER_DACTRIGx signals are generated from the SHRTIMER, while the software trigger can be generated by setting the SWTRx bits in the DAC_SWT register.
Page 264: Dac Output Voltage
GD32A508xx User Manual Figure 14-2. DAC LFSR algorithm Triangle noise mode: a triangle signal is added to the OUTx_DH value, and then the result is stored into the DAC_OUTx_DO register. The minimum value of the triangle signal is 0, while the maximum value of the triangle signal is (2 <<...
Page 265: Dac Concurrent Conversion
GD32A508xx User Manual If the second external trigger arrives before confirming the previous request, the new request will not be serviced, and an underrun error event occurs. The DDUDRx bit in the DAC_STAT0 register is set, an interrupt will be generated if the DDUDRIEx bit in the DAC_CTL0 register is set.
Page 266: Dacx Control Register 0 (Dac_Ctl0)
GD32A508xx User Manual DACx control register 0 (DAC_CTL0) 14.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). DTSEL1 DDUDR DDMA Reserved DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 DTSEL0 DDUDR DDMA Reserved DWBW0[3:0] DWM0[1:0] DTSEL0[2:0] DTEN0 DBOFF0...
Page 267 GD32A508xx User Manual These bits specify the mode selection of the noise wave signal of DACx_OUT1 when external trigger of DACx_OUT1 is enabled (DTEN1=1). 00: wave disabled 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DACx_OUT1 trigger selection These bits are combined with DTSEL1[3] to select the external event used to trigger DAC and only used if bit DTEN1 = 1.
Page 268 GD32A508xx User Manual These bits specify bit width of the noise wave signal of DACx_OUT0. These bits indicate that unmask LFSR bit [n-1, 0] in LFSR noise mode or the amplitude of the triangle is ((2<<(n-1))-1) in triangle noise mode, where n is the bit width of wave. 0000: The bit width of the wave signal is 1 0001: The bit width of the wave signal is 2 0010: The bit width of the wave signal is 3...
Page 269: Dacx Software Trigger Register (Dac_Swt)
GD32A508xx User Manual 1: DACx_OUT0 output buffer turns off DEN0 DACx_OUT0 enable 0: DACx_OUT0 disabled 1: DACx_OUT0 enabled DACx software trigger register (DAC_SWT) 14.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved SWTR1 SWTR0...
Page 270: Dacx_Out0 12-Bit Left-Aligned Data Holding Register (Dac_Out0_L12Dh)
GD32A508xx User Manual 31:12 Reserved Must be kept at reset value. 11:0 OUT0_DH[11:0] DACx_OUT0 12-bit right-aligned data. These bits specify the data that is to be converted by DACx_OUT0. DACx_OUT0 12-bit left-aligned data holding register 14.4.4. (DAC_OUT0_L12DH) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 271: Dacx_Out1 12-Bit Right-Aligned Data Holding Register (Dac_Out1_R12Dh)
GD32A508xx User Manual These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT0. DACx_OUT1 12-bit right-aligned data holding register 14.4.6. (DAC_OUT1_R12DH) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT1_DH[11:0]...
Page 272: Dacx_Out1 8-Bit Right-Aligned Data Holding Register (Dac_Out1_R8Dh)
GD32A508xx User Manual DACx_OUT1 8-bit right-aligned data holding register (DAC_OUT1_R8DH) 14.4.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT1_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. OUT1_DH[7:0] DACx_OUT1 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT1.
Page 273: Dacx Concurrent Mode 12-Bit Left-Aligned Data Holding Register (Dacc_L12Dh)
GD32A508xx User Manual DACx concurrent mode 12-bit left-aligned data holding register 14.4.10. (DACC_L12DH) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) OUT1_DH[11:0] Reserved OUT0_DH[11:0] Reserved Bits Fields Descriptions 31:20 OUT1_DH[11:0] DACx_OUT1 12-bit left-aligned data These bits specify the data that is to be converted by DACx_OUT1.
Page 274: Dacx_Out0 Data Output Register (Dac_Out0_Do)
GD32A508xx User Manual OUT0_DH[7:0] DACx_OUT0 8-bit right-aligned data These bits specify the MSB 8-bit of the data that is to be converted by DACx_OUT0. DACx_OUT0 data output register (DAC_OUT0_DO) 14.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved OUT0_DO[11:0]...
Page 275: Dacx Status Register 0 (Dac_Stat0)
GD32A508xx User Manual DACx status register 0 (DAC_STAT0) 14.4.14. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved DDUDR1 Reserved rc_w1 Reserved DDUDR0 Reserved rc_w1 Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DDUDR1 DACx_OUT1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Page 276: Dacx Status Register 1 (Dac_Stat1)
GD32A508xx User Manual 31:19 Reserved Must be kept at reset value. FIFOUDRIE1 DACx_OUT1 FIFO underflow interrupt enable 0: DACx_OUT1 FIFO underflow interrupt disabled. 1: DACx_OUT1 FIFO underflow interrupt enabled. FIFOOVRIE1 DACx_OUT1 FIFO overflow interrupt enable 0: DACx_OUT1 FIFO overflow interrupt disabled. 1: DACx_OUT1 FIFO overflow interrupt enabled.
Page 277 GD32A508xx User Manual Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. 22:20 FIFONUM1 DACx_OUT1 FIFO length 000: The length of data is 0 001: The length of data is 1 010: The length of data is 2 011: The length of data is 3 100: The length of data is 4 101~111: Reserved...
Page 278 GD32A508xx User Manual FIFOF0 DACx_OUT0 FIFO full flag 0: DACx_OUT0 FIFO is not full. 1: DACx_OUT0 FIFO is full.
Page 279: Comparator (Cmp)
GD32A508xx User Manual Comparator (CMP) Overview 15.1. The general purpose comparator CMP, can work either standalone (all terminal are available on I/Os) or together with the timers. It can be used to provide a trigger source when an analog signal is in a certain condition. 15.2.
Page 280: Cmp Clock
GD32A508xx User Manual Figure 15-1. CMP block diagram CMP1BLK[2:0] Polarity Selection CMP1PL CMP1MSEL[2:0] CMP3BLK[2:0] Polarity Selection CMP3PL CMP3MSEL[2:0] CMP5BLK[2:0] Polarity Selection CMP5PL CMP5MSEL[2:0] Note: V is 1.2V. REFINT CMP clock 15.3.1. The clock of the CMP which is connected to APB bus, is synchronous with PCLK. CMP I / O configuration 15.3.2.
Page 281: Cmp Register Write Protection
GD32A508xx User Manual Refer to pin definitions in datasheet, and the CMP output can be connected to the corresponding I/O port via the alternate function of the GPIO. CMP output internally connect to the TIMER and the connections between them are as follows: ...
Page 282: Cmp Output Blanking
GD32A508xx User Manual CMP output blanking 15.3.4. CMP output blanking function can be used to avoid interference of short pulses in the input signal to CMP output signal. If the CMPxBLK[2:0] bits in the CMPx_CS register are setting to an available value, the CMP output final signal is obtained by ANDing the complementary signal of the selected blanking signal with the raw output of the comparator.
Page 283: Register Definition
GD32A508xx User Manual 15.4. Register definition CMP base address：0x4001 7C00 CMP1 Control / status register (CMP1_CS) 15.4.1. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1MS CMP1LK CMP1O Reserved Reserved CMP1BLK[2:0] Reserved EL[3] CMP1PL Reserved CMP1OSEL[3:0]...
Page 284: Cmp3 Control / Status Register (Cmp3_Cs)
GD32A508xx User Manual CMP1PL Polarity of CMP1 output This bit is used to select the polarity of CMP1 output. 0: Output is not inverted 1: Output is inverted Reserved Must be kept at reset value 13:10 CMP1OSEL[3:0] CMP1 output selection These bits are used to select the destination of the CMP1 output.
Page 285 GD32A508xx User Manual CMP3MS CMP3LK CMP3O Reserved Reserved CMP3BLK[2:0] Reserved EL[3] CMP3PL Reserved CMP3OSEL[3:0] Reserved CMP3MSEL[2:0] Reserved CMP3EN Bits Fields Descriptions CMP3LK CMP3 lock This bit allows to have all control bits of CMP3 as read-only. It can only be set once by software and cleared by a system reset.
Page 286: Cmp5 Control / Status Register (Cmp5_Cs)
GD32A508xx User Manual Note: It is recommended to enable CMP first, and then configure the timer channel, when using TIMER to capture the output signal of the comparator. Reserved Must be kept at reset value CMP3MSEL[2:0] CMP3_IM input selection These bits, together with bit 22, are used to select the source connected to the CMP3_IM input of the CMP3.
Page 287 GD32A508xx User Manual This bit is a copy of CMP5 output state, which is read only. 0: Non-inverting input below inverting input and the output is low 1: Non-inverting input above inverting input and the output is high 29:23 Reserved Must be kept at reset value.
Page 288 GD32A508xx User Manual 0110: Reserved 0111: PB15 1000~1111: Reserved Reserved Must be kept at reset value CMP5EN CMP5 enable 0: CMP5 disabled 1: CMP5 enabled...
Page 289: Watchdog Timer (Wdgt)
GD32A508xx User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 290: Table 16-1. Min/Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32A508xx User Manual Status: PUD 12-Bit Reset IRC40K Prescaler DownCounter /4/8 256 Reload Control register Reload Status: RUD register The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value (0x000), there will be a reset.
Page 291 GD32A508xx User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: When after the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 292: Register Definition
GD32A508xx User Manual Register definition 16.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 293 GD32A508xx User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until...
Page 294 GD32A508xx User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
Page 295: Window Watchdog Timer (Wwdgt)
GD32A508xx User Manual Window watchdog timer (WWDGT) 16.2. Overview 16.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 296: Figure 16-3. Window Watchdog Timing Diagram
GD32A508xx User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set).
Page 297: Table 16-2. Min/Max Timeout Value At 100 Mhz (F Pclk1 )
GD32A508xx User Manual Table 16-2. Min/max timeout value at 100 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0]=0x40 CNT[6:0]=0x7F 40.96 μs 1 / 1 2.62 ms 81.92 μs 1 / 2 5.24 ms 163.84 μs 1 / 4 10.49 ms 327.68 μs...
Page 298: Register Definition
GD32A508xx User Manual Register definition 16.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 299 GD32A508xx User Manual EWIE Early wakeup interrupt enable. If the bit is set, an interrupt occurs when the counter reaches 0x40. It can be cleared by a hardware reset or software reset by setting the WWDGTRST bit of the RCU module. A write operation of ‘0’ has no effect. PSC[1:0] Prescaler.
Page 300: Real-Time Clock (Rtc)
GD32A508xx User Manual Real-time clock (RTC) Overview 17.1. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register.
Page 301: Rtc Reset
GD32A508xx User Manual (stored in the RTC_ALRMH/L register). Figure 17-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK LXTAL RTC_DIV RTC_CNT OVIF NVIC OVIE interrupt IRC40K RTC_Alarm Reload controler COMPARE ALRMIF RTC_PSC ALRMIE...
Page 302: Rtc Flag Assertion
GD32A508xx User Manual registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete.
Page 303: Figure 17-3. Rtc Second And Overflow Waveform Example (Rtc_Psc= 3)
GD32A508xx User Manual Figure 17-3. RTC second and overflow waveform example (RTC_PSC= 3)
Page 304: Rtc Register
GD32A508xx User Manual RTC Register 17.4. RTC base address: 0x4000 2800 RTC interrupt enable register (RTC_INTEN) 17.4.1. Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions 31:3...
Page 305: Rtc Prescaler High Register (Rtc_Psch)
GD32A508xx User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode.
Page 306: Rtc Prescaler Low Register (Rtc_Pscl)
GD32A508xx User Manual 31:4 Reserved Must be kept at reset value. PSC[19:16] RTC prescaler value high RTC prescaler low register (RTC_PSCL) 17.4.4. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits Fields...
Page 307: Rtc Counter High Register (Rtc_Cnth)
GD32A508xx User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved DIV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated.
Page 308: Rtc Alarm High Register (Rtc_Alrmh)
GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] RTC counter value low RTC alarm high register (RTC_ALRMH) 17.4.9. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits...
Page 309: Timer (Timerx)
GD32A508xx User Manual Timer (TIMERx) Table 18-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1~4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit(TIMER1) Counter 16-bit 16-bit 16-bit 16-bit 16-bit(TIMER2~4) UP,DOWN, UP,DOWN, Count mode UP ONLY...
Page 310: Advanced Timer (Timerx, X=0, 7)
GD32A508xx User Manual ITI1: ITI2: ITI3: TIMER13_ TIMER11 ITI0: TIMER3_TRGO TIMER4_TRGO TIMER12_TRGO TRGO Only update events will generate DMA request. Note that TIMER5/6 do not have DMA configuration registers. In connectivity line devices, the source of TIMER1 ITI1 is decided by TIMER1ITI1_REMAP in AFIO port configuration register 0 (AFIO_PCF0) In non-connectivity line devices, the source of TIMER1 ITI1 is internally connected to TIMER7_TRGO;...
Page 311 GD32A508xx User Manual  Break input.  Interrupt output or DMA request on: update, trigger event, compare/capture event, and break input.  Daisy chaining of timer modules allows a single timer to initiate multiple timers.  Timer synchronization allows selected timers to start counting on the same clock cycle. ...
Page 312: Block Diagram
GD32A508xx User Manual Block diagram 18.1.3. Figure 18-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 18-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2...
Page 313: Clock Prescaler
GD32A508xx User Manual Figure 18-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 314: Figure 18-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32A508xx User Manual TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again and an overflow event will be generated.
Page 315: Figure 18-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32A508xx User Manual TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-5. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0...
Page 316: Figure 18-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32A508xx User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated.
Page 317 GD32A508xx User Manual TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set Auto-reload register change CAR Vaule...
Page 318: Figure 18-8. Timing Chart Of Center-Aligned Counting Mode
GD32A508xx User Manual counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear...
Page 319: Figure 18-9. Repetition Timechart For Center-Aligned Counter
GD32A508xx User Manual of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow.
Page 320: Figure 18-12. Channel Input Capture Principle
GD32A508xx User Manual TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 321 GD32A508xx User Manual Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2 ITI3 CI0FED One of channels’...
Page 322: Output Compare Function
GD32A508xx User Manual TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 323: Figure 18-15. Output-Compare In Three Modes
GD32A508xx User Manual (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNEN=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;...
Page 324: Figure 18-16. Timing Chart Of Eapwm
GD32A508xx User Manual CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 325: Pwm Mode1
GD32A508xx User Manual CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Figure 18-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal...
Page 326: Table 18-2. Complementary Outputs Controlled By Parameters
GD32A508xx User Manual field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 327 GD32A508xx User Manual Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP; If the clock for deadtime generator is present, after a deadtime: CHx_O = ISOx, CHx_ON = ISOxN.
Page 328: Figure 18-18. Complementary Output With Dead-Time Insertion
GD32A508xx User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 329: Figure 18-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32A508xx User Manual HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 330: Figure 18-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32A508xx User Manual selection. This means that the counter counts continuously in the interval between 0 and the counter-period value. Therefore, TIMERx_CAR register must be configured before the counter starts to count. Table 18-3. Counting direction in different quadrature decoder mode CI0FE0 CI1FE1 Counting mode...
Page 331: Figure 18-22. Hall Sensor Is Used To Bldc Motor
GD32A508xx User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 18-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in (Advanced/GeneralL0 TIMER) should accept three HALL sensor signals.
Page 332: Table 18-4. Examples Of Slave Mode
GD32A508xx User Manual Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 333: Figure 18-24. Restart Mode
GD32A508xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 110: CI1FE1 the trigger source, used. 111: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by inversion. configuring ETFC and prescaler can be used by configuring ETPSC.
Page 334: Single Pulse Mode
GD32A508xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler TIMER_CK CNT_REG CI0FE0 TRGIF Event mode ETPSC = 1, ETI is The counter will start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. to count when a rising of ETI does not ETIFP is selected.
Page 335: Figure 18-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
GD32A508xx User Manual In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register.
Page 336 GD32A508xx User Manual TIMER 14 TIMER0 TRGS Master ITI0 TRGO mode Prescaler Counter control TIMER 1 Master ITI1 TRGO mode Prescaler Counter control TIMER 2 Trigger Master ITI2 selection TRGO mode Prescaler Counter control CI0F_ED CI0FE0 CI1FE1 ETIFP Other interconnection examples: ...
Page 337: Figure 18-29. Trigger Timer0 And Timer2 By The Ci0 Signal Of Timer2
GD32A508xx User Manual register). Configure TIMER0 in event mode (SMC=3’b110 in the TIMER0_SMCFG register). When the CI0 signal of TIMER2 generates a rising edge, two timer counters start counting synchronously with the internal clock and both TRGIF flags are set. Figure 18-29.
Page 338 GD32A508xx User Manual Timer debug mode When the Cortex®-M33 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register is set to 1, the TIMERx counter stops.
Page 339: Timerx Registers(X=0, 7)
GD32A508xx User Manual TIMERx registers(x=0, 7) 18.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS...
Page 340 GD32A508xx User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or quadrature decode mode, this bit is read only.
Page 341 GD32A508xx User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 342 GD32A508xx User Manual 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit.
Page 343 GD32A508xx User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 344 GD32A508xx User Manual 4’b0001 4’b0010 TIMER_CK 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 345 GD32A508xx User Manual edge, while the direction depends on each other. 100: Restart mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low.
Page 346 GD32A508xx User Manual 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE...
Page 347 GD32A508xx User Manual rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag Refer to CH0OF description CH1OF Channel 1 over capture flag...
Page 348 GD32A508xx User Manual Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs.
Page 349 GD32A508xx User Manual CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 350 GD32A508xx User Manual CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL description CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description...
Page 351 GD32A508xx User Manual 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise.
Page 352 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control...
Page 353 GD32A508xx User Manual Same as Output compare mode Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0]...
Page 354 GD32A508xx User Manual 1: Channel 2 output compare clear enable CH2COMCTL[2:0] Channel 2 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 355 GD32A508xx User Manual 0: Channel 2 output quickly compare disable. 1: Channel 2 output quickly compare enable. CH2MS[1:0] Channel 2 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH2EN bit in TIMERx_CHCTL2 register is reset).).
Page 356 GD32A508xx User Manual 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 357 GD32A508xx User Manual CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable Refer to CH0NEN description CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable Refer to CH0EN description...
Page 358 GD32A508xx User Manual CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT)
Page 359 GD32A508xx User Manual update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 360 GD32A508xx User Manual Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 361 GD32A508xx User Manual shadow register updates every update event. Channel 2 capture/compare value register (TIMERx_CH2CV) Address offset: 0x3C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2...
Page 362 GD32A508xx User Manual compared to the counter. When the corresponding shadow register is enabled, the shadow register updates every update event. Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved POEN OAEN...
Page 363 GD32A508xx User Manual 0: Break inputs disabled 1; Break inputs enabled This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. Run mode “off-state” enable When POEN bit is set (Run mode), this bit can be set to enable the “off-state” for the channels which has been configured in output mode.
Page 364 GD32A508xx User Manual 3’b111 (32+ DTCFG[4:0]) * t DTS_CK Note: 1. t is the period of DTS_CK which is configured by CKDIV[1:0] in DTS_CK TIMERx_CTL0. 2. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000...
Page 365 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 366: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32A508xx User Manual General level0 timer (TIMERx, x=1, 2, 3, 4) 18.2. Overview 18.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 367: Function Overview
GD32A508xx User Manual CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection TIMER_CK DMA REQ/ACK Trigger Selector&Counter ETIFP Edge detector Quadrate Decoder TIMERx_CH0 Prescaler DMA controller...
Page 368: Clock Prescaler
GD32A508xx User Manual CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111( external clock mode 0 ). External input pin source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 369: Figure 18-33. Timing Chart Of Up Counting Mode, Psc=0/2
GD32A508xx User Manual TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again.
Page 370: Figure 18-34. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32A508xx User Manual TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-34. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0...
Page 371: Figure 18-35. Timing Chart Of Down Counting Mode,Psc=0/2
GD32A508xx User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow.
Page 372 GD32A508xx User Manual TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set Auto-reload register change CAR Vaule...
Page 373: Figure 18-37. Timing Chart Of Center-Aligned Counting Mode
GD32A508xx User Manual counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-37. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear...
Page 374: Figure 18-38. Channel Input Capture Principle
GD32A508xx User Manual generated if enabled by CHxIE = 1. Figure 18-38. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal...
Page 375: Figure 18-39. Channel Output Compare Principle (X=0,1,2,3)
GD32A508xx User Manual Result: When you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 376: Figure 18-40. Output-Compare In Three Modes
GD32A508xx User Manual DMA request will be assert, if CxCDE=1. So the process can be divided to several steps as below: Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL.
Page 377: Figure 18-41. Timing Chart Of Eapwm
GD32A508xx User Manual and CAPWM (Centre aligned PWM). The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 18-41. Timing chart of EAPWM shows the EAPWM output and interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV.
Page 378 GD32A508xx User Manual CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal (x=0,1,2,3), when the As is shown in Figure 18-39. Channel output compare principle TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 379: Table 18-5. Examples Of Slave Mode
GD32A508xx User Manual TIMERx_CHCTL0 register. The OxCPRE signal will not return to its active level until the next update event occurs. Quadrature decoder Quadrature decoder. Refer to Hall sensor function Hall sensor function. Refer to Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 380: Figure 18-43. Restart Mode
GD32A508xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-43. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Pause mode TI0S=0 (Non-xor) The counter will be [CH0NP=0, CH0P=0] paused when the TRGS[2:0]=3’b101 CI0FE0 does not Filter is bypassed in trigger input is low, CI0FE0 is selected.
Page 381: Figure 18-45. Event Mode
GD32A508xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-45. Event mode Single pulse mode Single pulse mode. Refer to Timers interconnection Advanced timer (TIMERx, x=0, 7). Refer to Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB;...
Page 382: Timerx Registers(X=1, 2, 3, 4)
GD32A508xx User Manual TIMERx registers(x=1, 2, 3, 4) 18.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 383 GD32A508xx User Manual 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down...
Page 384 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 385 GD32A508xx User Manual 1: When update event occurs, the DMA request of channel x is sent. Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0]...
Page 386 GD32A508xx User Manual 11:8 ETFC[3:0] External trigger filter control The external trigger can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 387 GD32A508xx User Manual These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 388 GD32A508xx User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 389 GD32A508xx User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 390 GD32A508xx User Manual mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs. If Channel0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV. 0: No Channel 0 interrupt occurred 1: Channel 0 interrupt occurred UPIF...
Page 391 GD32A508xx User Manual This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 392 GD32A508xx User Manual This bit-field is writable only when the channel is not active. (CH1EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS.
Page 393 GD32A508xx User Manual pulse mode (when SPM=1) CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 394: Output Compare Mode
GD32A508xx User Manual 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 395 GD32A508xx User Manual Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active.
Page 396 GD32A508xx User Manual If configured in PWM mode, the O2CPRE level changes only when the output compare mode is adjusted from “Timing” mode to “PWM” mode or the comparison result changes. CH2COMSEN Channel 2 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH2CV register, which updates at each update event will be enabled.
Page 397 GD32A508xx User Manual filtering capability. Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH2CAPFLT [3:0] Times...
Page 398 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. CH3NP Channel 3 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description...
Page 399 GD32A508xx User Manual When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0. [CH0NP==0, CH0P==0]: CIxFE0’s rising edge is the active signal for capture or trigger operation in slave mode.
Page 400 GD32A508xx User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 401 GD32A508xx User Manual This bit-filed specifies the auto reload value of the counter. Counter auto reload register (TIMERx_CAR) (x=2,3,4) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 402 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 403 GD32A508xx User Manual This register has to be accessed by word (32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 404 GD32A508xx User Manual Reserved CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 405 GD32A508xx User Manual Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 406 GD32A508xx User Manual DMA transfer buffer register (TIMERx_DMATB)(x=1) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). DMATB[31:16] DMATB[15:0] Bits Fields Descriptions 31:0 DMATB[31:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed.
Page 407 GD32A508xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 408: General Level1 Timer (Timerx, X=8, 11)
GD32A508xx User Manual General level1 timer (TIMERx, x=8, 11) 18.3. Overview 18.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 409: Function Overview
GD32A508xx User Manual CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter Trigger processor TIMERx_TRGO PSC_CLK TIMER_CK Trigger Selector&Counter Quadrate Decoder Output Logic CH0_O generation of outputs signals in compare, PWM,and mixed modes according to initialization, software CH1_O APB BUS...
Page 410: Clock Prescaler
GD32A508xx User Manual CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 ( external clock mode 0 ). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 411: Figure 18-49. Timing Chart Of Up Counting Mode, Psc=0/2
GD32A508xx User Manual TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again.
Page 412: Figure 18-50. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32A508xx User Manual TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-50. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0...
Page 413: Figure 18-51. Channel Input Capture Principle
GD32A508xx User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ...
Page 414: Figure 18-52. Channel Output Compare Principle (X=0,1)
GD32A508xx User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 415: Figure 18-53. Output-Compare Under Three Modes
GD32A508xx User Manual as OxCPRE), CHxEN=1 (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. In Output Compare mode, the TIMERx can generate timed pulses with programmable position, polarity, duration, and frequency.
Page 416: Figure 18-54. Pwm Mode Timechart
GD32A508xx User Manual CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 417: Table 18-6. Examples Of Slave Mode
GD32A508xx User Manual CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Channel output prepare signal Figure 18-52. Channel output compare principle (x=0,1), when the TIMERx As is shown in is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 418: Figure 18-55. Restart Mode
GD32A508xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler TRGS[2:0] For the ITIx, no filter 000: ITI0 If CI0FE0 or CI1FE1 is and prescaler can be 001: ITI1 SMC[2:0] selected as the trigger used. 010: ITI2 3'b100 (restart mode) source, configure the For the CIx, filter can 011: ITI3...
Page 419: Figure 18-56. Pause Mode
GD32A508xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-56. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF CH0P=0, Event mode The counter will start CI0FE0 does not TRGS[2:0]=3’b101 Filter is bypassed in to count when a rising invert.
Page 420: Figure 18-58. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32A508xx User Manual counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0 register. After a trigger rising occurs in the single pulse mode, the OxCPRE signal will immediately be forced to the state which the OxCPRE signal will change to, as the compare match event occurs without taking the comparison result into account.
Page 421: Timerx Registers(X=8, 11)
GD32A508xx User Manual TIMERx registers(x=8, 11) 18.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS...
Page 422 GD32A508xx User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 423 GD32A508xx User Manual 000: ITI0 001: ITI1 010: ITI2 011: ITI3 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode.
Page 424 GD32A508xx User Manual Reserved Must be kept at reset value. CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 425 GD32A508xx User Manual 1: Trigger interrupt occurred. Reserved Must be kept at reset value. Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
Page 426 GD32A508xx User Manual Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 427 GD32A508xx User Manual 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 428 GD32A508xx User Manual 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 429 GD32A508xx User Manual 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 430 GD32A508xx User Manual define the polarity of CI0. Reserved Must be kept at reset value. CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 431 GD32A508xx User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 432 GD32A508xx User Manual Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 433 GD32A508xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 434: General Level2 Timer (Timerx, X=9, 10, 12, 13)
GD32A508xx User Manual General level2 timer (TIMERx, x=9, 10, 12, 13) 18.4. Overview 18.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 435: Function Overview
GD32A508xx User Manual Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector CH0_O Trigger...
Page 436: Figure 18-61. Timing Chart Of Psc Value Change From 0 To 2
GD32A508xx User Manual CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 437: Figure 18-62. Timing Chart Of Up Counting Mode, Psc=0/2
GD32A508xx User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 438: Figure 18-64. Channel Input Capture Principle
GD32A508xx User Manual TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set...
Page 439 GD32A508xx User Manual Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 Rising/Falling Capture Clock Counter presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal First, the channel input signal (CIx) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 440: Figure 18-65. Channel Output Compare Principle
GD32A508xx User Manual software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 441: Figure 18-66. Output-Compare Under Three Modes
GD32A508xx User Manual * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN.
Page 442 GD32A508xx User Manual relative bit definition. Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHxCV values.
Page 443: Timerx Registers(X=9, 10, 12, 13)
GD32A508xx User Manual TIMERx registers(x=9, 10, 12, 13) 18.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 444 GD32A508xx User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 445 GD32A508xx User Manual CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 446 GD32A508xx User Manual Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 447 GD32A508xx User Manual 31:2 Reserved Must be kept at reset value. Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 448 GD32A508xx User Manual compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise.
Page 449 GD32A508xx User Manual filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH0CAPFLT [3:0] Times...
Page 450 GD32A508xx User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 451 GD32A508xx User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 452 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 453 GD32A508xx User Manual 31:2 Reserved Must be kept at reset value. CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved Must be kept at reset value.
Page 454: Basic Timer (Timerx, X=5, 6)
GD32A508xx User Manual Basic timer (TIMERx, x=5, 6) 18.5. Overview 18.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 455: Figure 18-68. Timing Chart Of Internal Clock Divided By 1
GD32A508xx User Manual Figure 18-68. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 456: Figure 18-70. Timing Chart Of Up Counting Mode, Psc=0/2
GD32A508xx User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 457 GD32A508xx User Manual TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set...
Page 458: Timerx Registers(X=5, 6)
GD32A508xx User Manual TIMERx registers(x=5, 6) 18.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved ARSE Reserved UPDIS Bits...
Page 459 GD32A508xx User Manual The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 460 GD32A508xx User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled...
Page 461 GD32A508xx User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically.
Page 462 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 463: Super High-Resolution Timer (Shrtimer)
GD32A508xx User Manual Super High-Resolution Timer (SHRTIMER) Overview 19.1. SHRTIMER has a super high-resolution counting clock and can be used for high-precision timing. It can generate 10 super high resolution and flexible digital signals to control motor or be used for power management applications. The 10 digital signals can be output independently or coupled into 5 pairs of complementary signals.
Page 464: Function Overview
GD32A508xx User Manual Master_TIMER Master_TIMER Interrupt request repetition repetition counter auto counter auto Synchronization DMA mode DMA mode register DMA request DMA request register reload register reload register control output/input control ADC trigger Counter Compare Counter Compare DAC trigger Slave_TIMERx Slave_TIMERx (x= 0..4) (x= 0..4)
Page 465: Table 19-1. The Limitations Of Auto-Reload And Compare Y (Y=0..3) Register
GD32A508xx User Manual Slave_TIMERx(x=0..4) CREP Counter repetition Synchronization Start input counter Reset Counter SHRTIMER_PSCCK Half SHRTIMER_HPCK CMP0 mode 64 * f SHRTIMER_CK SHRTIMER_CK CMP1 (from RCU) SHRTIMER_CK CMP2 CMP3 The auto-reload register and compare y (y=0..3) register have the following limitations: ...
Page 466: Up Counting Mode
GD32A508xx User Manual CNTCKDIV[2:0]+1 SHRTIMER_PSCCK SHRTIMER_HPCK When the CNTCKDIV[3] bit in SHRTIMER_MTACTL register is ‘1’, the CNTCKDIV[2:0] bit-filed can only be configured with ‘3’b000’ and the frequency relationship between SHRTIMER_PSCCK and SHRTIMER_HPCK can be expressed below: SHRTIMER_PSCCK SHRTIMER_HPCK Note: The clock division CNTCKDIV[3:0] cannot be modified once the Master_TIMER is enabled.
Page 467: Figure 19-4. Counter Behavior In Single Pulse Mode
GD32A508xx User Manual reset event will start the counter. When counting up to the counter-reload value, the counter stops and generates a period event. Then the other reset event will reset and restart the counter. During counting process, the reset event will reset and restart the counter if CNTRSTM = 1 in SHRTIMER_MTCTL0 register, otherwise it will be ignored.
Page 468: Figure 19-6. Repetition Counter Behavior In Continuous Mode
GD32A508xx User Manual counter is cleared due to either a roll-over event in continuous mode or a reset event. When the repetition counter has reached zero, the coming roll-over event in continuous mode or reset event will generate a repetition event and reload the value of SHRTIMER_MTCREP register.
Page 469: Counter Reset
GD32A508xx User Manual MTCEN or STxCEN(x=0..4) Reset event CARL CARL Counter when CTNM = 0 CNTRSTM = 1 CREP[7:0] 0x03 Repetition 0x03 0x02 0x01 0x00 0x03 counter Cleared by REPIFC REPIF bit Counter reset The counter can be reset to 0 by software or synchronous input only once the counter is enabled (MTCEN = 1).
Page 470: Table 19-3. Master_Timer Shadow Registers And Update Event
GD32A508xx User Manual SHRTIMER_MTINTF where x=0..3), and a compare interrupt or DMA request is issued if enabled (CMPxIE = 1 or CMPxDEN = 1 bits in SHRTIMER_MTDMAINTEN register where x=0..3). The compare interrupt flag can be cleared by writing 1 to CMPxIFC bit in SHRTIMER_MTINTFC where x=0..3.
Page 471 GD32A508xx User Manual Registers Shadow registers Update event. that contain shadow registers enable bit SHRTIMER_MTDMAINTEN Software(MTSUP bit) SHRTIMER_MTCAR Repetition event(UPREP = 1) DMA mode end event(UPSEL[1:0] = SHRTIMER_MTCREP SHWEN bit in 2’b01) SHRTIMER_MTCT SHRTIMER_MTCMP0V L0 register Roll-over event following a DMA SHRTIMER_MTCMP1V mode end event (UPSEL[1:0] = SHRTIMER_MTCMP2V...
Page 472: Slave_Timerx(X=0
GD32A508xx User Manual Slave_TIMERx(x=0..4) unit 19.4.2. The SHRTIMER has 5 slave timers with similar structure: Slave_TIMERx(x=0..4). Each unit is built around the following components:  16-bit counter. Auto reload register: counting period.  Repetition counter.   Compare y (y=0..3) register. ...
Page 473: Table 19-4. The Limitations Of Counter And Capture Y(Y=0,1) Value Registers
GD32A508xx User Manual The counter and capture y(y=0,1) value registers also have the following limitations: for counter clock division below 64 (CNTCKDIV[3:0] < 4’b0101 or CNTCKDIV[3:0] =4’b1000), Table the least significant bits are not significant. They cannot be written and read 0. Refer to 19-4.
Page 474 GD32A508xx User Manual Up counting mode The counter counts up continuously from 0 to the counter-reload value, which is defined in the SHRTIMER_STxCAR register. There are two counter operating modes: single pulse mode (CTNM = 0 in SHRTIMER_STxCTL0 register) and continuous mode (CTNM = 1 in SHRTIMER_STxCTL0 register).
Page 475 GD32A508xx User Manual 2. Synchronization input start/reset counter. 3. Events configured in SHRTIMER_STxCNTRST register. All these sources are logical ORed, they can be valid simultaneously. If multiple reset events occur in the same t cycle, only the last one is valid. The counter reset requests are SHRTIMER_CK taken into account only once the related Slave_TIMERx are enabled Note: If the external events is configured with level sensitivity, only one external events can...
Page 476: Figure 19-11. Capture 0 Triggered By Exev0 And Exev1
GD32A508xx User Manual SHRTIMER_STxINTFC. The capture 0 trigger events are defined in SHRTIMER_STxCAP0TRG register and the capture 1 trigger events are defined in SHRTIMER_STxCAP1TRG register. All the trigger events are logical ORed and they are all valid when multiple trigger events are selected. Note: If the external events is configured with level sensitivity, only one external events can be enabled in the SHRTIMER_STxCAPyTRG(y=0,1) register.
Page 477: Figure 19-13. Compare Delayed Mode Chart
GD32A508xx User Manual Cleared by CMP1IFC Cleared by CMP1IFC Half mode When HALFM bit in SHRTIMER_STxCTL0 is set to 1, the half mode is enabled. This mode forces the value of compare 0 active register to be half of the counter-reload value, but the value of SHRTIMER_STxCMP0V register is not updated with the SHRTIMER_MTCAR/2 value.
Page 478: Figure 19-14. Compare 1 Delayed Mode 0
GD32A508xx User Manual compared to the counter. Compare 1 is associated with capture 0 and compare 0/2, while compare 3 is associated with capture 1 and compare 0/2. Note: The recalculated value is transferred to an internal register which cannot read. DELCMP3M[1:0] (compare DELCMP1M[1:0]...
Page 479: Figure 19-15. Compare 1 Delayed Mode 1
GD32A508xx User Manual value. If capture 0 trigger occurs first, the later compare 0 event is ignored. If compare 0 event occurs first, the capture 0 trigger after the compare 1 event is ignored. Refer to Figure 19-15. Compare 1 delayed mode Figure 19-15.
Page 480: Figure 19-16. Compare Delayed Mode With Shwen = 0
GD32A508xx User Manual Figure 19-16. Compare delayed mode with SHWEN = 0 MTCEN or STxCEN(x=0..4) previous+ C1 C2+ C1 update event Counter when CTNM = 1 Preload=previous Active=previous + C1 Capture event C a p t u r e C a p t u r e previous register register...
Page 481: Figure 19-18. O0Pre Wave: Set On Cmp0, Reset On Cmp1
GD32A508xx User Manual Only one of them can be chosen. Output prepare signal Slave_TIMERx has a set/reset output module. The module can generate two output prepare signals: O0PRE and O1PRE. O0PRE is controlled by SHRTIMER_STxCH0SET and SHRTIMER_STxCH0RST registers. O1PRE is controlled by SHRTIMER_STxCH1SET and SHRTIMER_STxCH1RST registers.
Page 482: Table 19-5. Slave_Timer Interconnection Event
GD32A508xx User Manual  Master_TIMER: period event and compare y(y=0..3) event.  Slave_TIMERx interconnection event: there are 9 interconnect events from other Slave_TIMERy (for instance x=1, then y=0, 2..4). Refer to Table 19-5. Slave_TIMER interconnection event  External event y(y=0..9): EXEVy conditioned by external event filter in Slave_TIMERx ...
Page 483: Figure 19-19. Arbitration Mechanism During Each T
GD32A508xx User Manual mechanism during each tSHRTMER_CK period Figure 19-19. Arbitration mechanism during each t period SHRTMER_CK Arbiter0: Arbiter0: STx interconnection Arbiter1: only one event Arbiter1: Arbiter2: CMP3> CMP3> Arbiter2: event y(y=0..8) delay and request delay reset> CMP2> CMP2> reset> smaller, smaller, CMP1>...
Page 484: Figure 19-20． Arbitration Mechanism Example
GD32A508xx User Manual From Slave_TIMER0 itself: compare 3 event, period event. Interconnection event to Slave_TIMER0: interconnection event 7 (Slave_TIMER4 compare 2 event), interconnection event 8 (Slave_TIMER4 compare 3 event). Low-precision events: external event 2(EXEV2), external event 3(EXEV3)  The delay: Slave_TIMER4 compare 3 < Slave_TIMER0 compare 3 If the selected events above occur during one t period, the arbitration process and HPTMER_CK...
Page 485: Figure 19-23. Super High-Resolution Oxpre Wave
GD32A508xx User Manual SHRTIMER_CK SHRTIMER_CK OxPRE postponed super high- resolution SHRTIMER_CK OxPRE super high- anticipated resolution super high- OxPRE postponed resolution SHRTIMER_CK super high- OxPRE SHRTIMER_CK resolution anticipated Legend: set request reset request If the “set and reset requests” are generated with an interval including one complete Figure 19-22.
Page 486: Figure 19-24. Oxpre Wave With Cntckdiv[3:0] = 4'B0110
GD32A508xx User Manual When “set and reset requests” from different event sources simultaneously occur in a tSHRTIMER_CK cycle, the “reset request” has the highest priority. In SHRTIMER_PSCCK cycle, subsequent requests override previous requests, and only the last request of that cycle Figure 19-24.
Page 487 GD32A508xx User Manual  SHRTIMER_STxCMP0V = 0x0060  SHRTIMER_STxCMP1V = 0x00E0 Figure 19-25. C0OPRE wave in regular mode SHRTIMER_CK 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0 Counter Compare 0...
Page 488: Figure 19-26. C0Opre And C1Opre Complementary Wave With Dead-Time
GD32A508xx User Manual The channel 1 is similar to channel 0. Figure 19-26. C0OPRE and C1OPRE complementary wave with dead-time shows C0OPRE and C1OPRE wave with O0PRE pulse width greater than the dead-time. Figure 19-26. C0OPRE and C1OPRE complementary wave with dead-time O0PRE O0PRE DTRCFG[15:0]...
Page 489: Figure 19-28. Structure Chart In Balanced Mode
GD32A508xx User Manual O0PRE O0PRE DTRCFG[15:0] DTRCFG[15:0] DTRCFG[15:0] Skip dead-time C0OPRE C0OPRE following rising DTRS = 0 DTRS = 0 DTFS = 0 DTFCFG[15:0] DTFCFG[15:0] DTFS = 0 DTFCFG[15:0] Skip dead-time C1OPRE following falling C1OPRE C0OPRE C0OPRE DTRS = 1 DTRCFG[15:0] DTRS = 1 DTFCFG[15:0]...
Page 490: Figure 19-29. C0Opre And C1Opre Wave In Balanced Mode
GD32A508xx User Manual It is advised to make SHRTIMER_STxCH0SET = SHRTIMER_STxCH1SET and SHRTIMER_STxCH0RST = SHRTIMER_STxCH1RST, in order to achieve a balanced operation with identical waveforms. Still, it is possible to have different programming on both outputs for other uses. The bit CBLNF in SHRTIMER_STxINTF register which is reset when the balanced mode is disabled, indicates which channel is currently outputting the signal (O0PRE or O1PRE).
Page 491: Table 19-6. Crossbar And Idle Control Stage Work Together
GD32A508xx User Manual IDLE control The stage has three ways to control the IDLE state:  Delayed IDLE  Balanced IDLE  IDLE controlled by bunch mode Delayed IDLE and balanced IDLE cannot use at the same time. Balanced IDLE is only available in balanced mode.
Page 492: Figure 19-30. Iso0 = 0 And Chop = 0 In Delayed Idle
GD32A508xx User Manual The delayed IDLE mode can be applied to a single output (CHyOPRE) or to both outputs (CH0OPRE CH1OPRE) decided bit-field DLYISCH[2:0] SHRTIMER_STxCHOCTL register, as follows:  DLYISCH[2:0] = 3’b000: The delayed IDLE mode is applied to CH0OPRE. ...
Page 493: Figure 19-32. Iso0 = 0 And Chop = 1 In Delayed Idle
GD32A508xx User Manual SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 1 CH0P = 0 CH0OPRE RUN State IDLE State RUN State re-enable EXEV6 ISO0 = 1 CH0P = 0 CH0OPRE RUN State RUN State IDLE State Figure 19-32.
Page 494: Figure 19-34. Balanced Idel With Iso0 = 0 And Iso1 = 0
GD32A508xx User Manual SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE re-enable EXEV6 ISO0 = 1 CH0P = 1 CH0OPRE RUN State IDLE State RUN State re-enable EXEV6 ISO0 = 1 CH0P = 1 CH0OPRE RUN State RUN State IDLE State Balanced IDLE Balanced IDLE is only available in balanced mode.
Page 495 GD32A508xx User Manual SHRTIMER_STxCMP1V active value Conuter SHRTIMER_STxCMP0V active value C0OPRE C1OPRE re-enable DLYIIF set Case 0: BLNIF = previous value BLNIF = 0 EXEV6 CH0OPRE ISO0 = 0 Channel 0 RUN State Channel 0 RUN State Channel 0 IDLE State ISO1 = 0 CH1OPRE Channel 1 RUN State...
Page 496: Figure 19-35. Stxchy_O Wave With Chyp=0 Or Chyp=1
GD32A508xx User Manual 19-8. Output during IDEL state controlled by bunch mode. Table 19-8. Output during IDEL state controlled by bunch mode ISOy BMCHyIEN CHyOPRE (y=0,1) No action: the output is not affected by the bunch controller Output inactive during IDLE state controlled by bunch mode Output active during IDLE state controlled by bunch mode Channel output stage Each Slave_TIMERx unit controls a pair of outputs (STxCH0_O and STxCH1_O).
Page 497: Figure 19-36. Carrier-Signal Structure Diagram
GD32A508xx User Manual Compare 1 active value Slave_TIMER0 CHyOPRE(y=0,1) STxChy_O(y=0,1) CHyP=0 STxChy_O(y=0,1) CHyP=1 The output level in the Fault state is configured using CHyFLTOS[1:0] bits in SHRTIMER_STxCHOCTL register, for each output, as follows:  2’b00: output never enters the Fault state and stays in Run or Idle state ...
Page 498 GD32A508xx User Manual Carrier-signal generator 0 CH0CSEN Carrier-signal generator 1 O0PRE CH1CSEN SHRTIMER_CSGCK O1PRE prescaler: CH1CSEN/ CH0CSEN SHRTIMER_CK IDLE CH0OPRE CH1OPRE In carrier-signal mode, it is possible to define a specific pulse width before the beginning of the carrier-signal. The frequency and duty cycle of the carrier-signal are configurable. Refer Figure 19-37.
Page 499: Figure 19-37. Shrtimer Output With Carrier-Signal Mode Enabled
GD32A508xx User Manual Figure 19-37. SHRTIMER output with carrier-signal mode enabled Compare 1 active value Slave_TIMER0 Slave_TIMER0 OyPRE OyPRE Carrier-signal Carrier-signal Carrier signal Carrier signal duty duty Carrier signal period CHyOPRE CHyOPRE First pulse First pulse Synchronization input start/reset counter Synchronous input can generate a counter reset event when SYNIRST set 1 in SHRTIMER_STxCTL0 register.
Page 500: Figure 19-38. Blanking Mode And Windowing Mode
GD32A508xx User Manual contain shadow registers and corresponding update events. Table 19-10. Slave_TIMERx shadow registers and update event Registers Shadow registers Update event. that contain shadow registers enable bit SHRTIMER_STxDMAINTEN Software(STxSUP bit) SHRTIMER_STxCAR Repetition event(UPREP = 1) Counter reset event or roll-over SHRTIMER_STxCREP event(UPRST = 1) Update event from other...
Page 501: Table 19-12. Filtering Signals Mapping In Blanking Mode
GD32A508xx User Manual Figure 19-38. Blanking mode and windowing mode EXEVyC EXEVyC EXEVy EXEVy Blanking mode Windowing mode Blanking signal Windowing signal EXEVyC EXEVyC Blanking signal Windowing signal EXEVy EXEVy EXEV0MEEN = 0 EXEV0MEEN = 0 EXEVy EXEVy EXEV0MEEN = 1 EXEV0MEEN = 1 External event Refer to...
Page 502: Table 19-13. Filtering Signals Mapping In Windowing Mode
GD32A508xx User Manual Slave_TIMER Slave_TIMER Slave_TIMER Slave_TIMER Slave_TIMER From CH1OPRE CH1OPRE compare 3 compare 0 compare 0 STBLKSRC6 Slave_TIMER3 Slave_TIMER3 Slave_TIMER3 Slave_TIMER4 Slave_TIMER3 compare 0 compare 1 CH1OPRE compare 3 compare 3 STBLKSRC7 Slave_TIMER4 Slave_TIMER4 Slave_TIMER4 Slave_TIMER4 Slave_TIMER3 compare 1 compare 0 compare 3 CH1OPRE...
Page 503: Dll Calibrate
GD32A508xx User Manual DAC module. Refer to Trigger to DAC for more information. DLL calibrate 19.4.3. The DLL can produce and calibrate a super high resolution clock SHRTIMER_HPCK = 64 *f ). DLL can calibrate the super high resolution clock SHRTIMER_HPCK SHRTIMER_CK SHRTIMER_HPCK either once or periodically.
Page 504: Figure 19-39. Bunch Mode Timing Chart
GD32A508xx User Manual SHRTIMER_BMCTL register. When the rising edge of the selected clock source signal arrives, BM-counter increments by 1. When BMCLKS[3:0]=4’b1010, the clock source of BM-counter is the f prescaled SHRTIMER_CK by a factor defined with BMPSC[3:0] bit-field in SHRTIMER_BMCTL register. When BMCLKS[3:0]= 4’b0110 to 1001, the clock source of BM-counter is chip internal signal : BMCLKy(y=0..3).
Page 505: Figure 19-40. Regular Entry For Bunch Mode
GD32A508xx User Manual 2. Events from Slave_TIMERx: repetition event, reset/roll-over event, compare 0 and 1 event 3. External event: EXEV6 and EXEV7 4. Slave_TIMER0 period event following EXEV6 5. Slave_TIMER3 period event following EXEV7 6. Chip internal signal: TIMER6_TRGO 7. Software: Writing 1 to the SWTRG bit in SHRTIMER_BMSTRG register. When the trigger event occurs, there are two ways to enter bunch mode: regular entry and delayed entry.
Page 506: Figure 19-41. Delayed Entry For Bunch Mode
GD32A508xx User Manual Compare 1 active value Slave_TIMER0 OyPRE(y=0,1) EXEV Bunch mode termination. CHyOPRE(y=0,1) IDLE in bunch mode RUN in bunch mode ISOy=0 RUN state Bunch mode operation RUN state EXEV Bunch mode termination. IDLE in bunch mode CHyOPRE(y=0,1) ISOy=0 RUN state RUN state Bunch mode operation...
Page 507 GD32A508xx User Manual Compare 1 active value Slave_TIMER0 Slave_TIMER0 O0PRE O0PRE Bunch mode EXEV termination. RUN in bunch mode Rrising Rrising Rrising dead-time dead-time Rrising IDLE in bunch mode dead-time CH0OPRE dead-time CH0OPRE ISO0 = 0 Entry arrives not during ISO0 = 0 Entry arrives not during Falling...
Page 508: Synchronization Input/Output
GD32A508xx User Manual SHRTIMER_STxCMP0CP = {CREP[7:0] = (RUN number of periods - 1); CMP0VAL[15:0] = duty cycle} SHRTIMER_STxCMP0CP = {CREP[7:0] = (IDLE number of periods - 1); CMP0VAL[15:0] = For example, to generate a PWM wave with 2 periods active every 5 PWM periods, the following values can be used: ...
Page 509: External Event
GD32A508xx User Manual single pulse mode with CNTRSTM=0.  2’b11: Slave_TIMER0 compare 0 event The bit-field SYNOPLS[1:0] in SHRTIMER_MTCTL0 register specifies the polarity of the synchronization output signal:  2’b00: Pulse generated disable. No pulse on the synchronization output pad SHRTIMER_SCOUT.
Page 510: Figure 19-43. Extern Event Y(Y=0..4) Processed Diagram
GD32A508xx User Manual Figure 19-43. Extern event y(y=0..4) processed diagram Active/inactive Active/inactive crossbar crossbar Slave_TIMERx(x=0..4) Slave_TIMERx(x=0..4) External event filter: EXEVyC External event filter: EXEVy Slave_TIMERx(x Slave_TIMERx(x No filtering Edge No filtering Edge =0..4) conter =0..4) conter blanking Detector blanking Externa event y Detector reset reset...
Page 511: Fault Input
GD32A508xx User Manual Table 19-15. External events mapping External event EXEVySRC0 EXEVySRC1 EXEVySRC2 EXEVySRC3 External event 0 PC12 Comparator 1 TIMER0_TRGO ADC0_AWD0 PC11 Comparator 3 TIMER1_TRGO ADC0_AWD1 External event 1 External event 2 PB7/PD5 Comparator 5 TIMER2_TRGO ADC0_AWD2 PB6/PG11 ADC1_AWD0 External event 3 External event 4 PB9/PG12...
Page 512: Table 19-16. Fault Channel Mapping
GD32A508xx User Manual Fault channel Fault channel FLTyINEN Digital chip external pin Digital Filter Filter comparator FLTyINP FLTyINP FLTyINSRC FLTyINSRC FLTyINFC[3:0] FLTyINFC[3:0] FLTyEN SystemFault Channel output stage Channel output stage STxCH0_O Idle STxCH1_O CH0P/ CH0P/ CH1P Fault output state CH1P Fault (CH0FLTOS/CH1FLTOS) Fault input is enabled using FLTyEN bit in SHRTIMER_STxFLTCTL register.
Page 513: Trigger To Adc
GD32A508xx User Manual Note: “×” means not available. The polarity of the signal can be configured by the FLTyINP polarity bit in SHRTIMER_FLTINCFG0 and SHRTIMER_FLTINCFG1 registers. If FLTyINP = 0, the signal is active at low level; if FLTyINP = 1, it is active when high. The digital filters of the signal after the polarity setting can be configured by the FLTyINFC[3:0] bit-field in SHRTIMER_FLTINCFG0 and SHRTIMER_FLTINCFG1 registers.
Page 514: Trigger To Dac
GD32A508xx User Manual SHRTIMER SHRTIMER_ADCTRIG0 SHRTIMER_ADCTRIGS0 SHRTIMER_ADCTRIGS1 SHRTIMER_ADCTRIG1 SHRTIMER_ADCTRIG2 SHRTIMER_ADCTRIGS2 SHRTIMER_ADCTRIGS3 SHRTIMER_ADCTRIG3 There are up to 32 events which can be combined (ORed) for each trigger output. They are defined in SHRTIMER_ADCTRIGSy(y=0..3) registers. SHRTIMER_ADCTRIGSy(y=0..3) registers are preloaded and can be updated synchronously with the timer they are related to.
Page 515: Interrupt
GD32A508xx User Manual Figure 19-47. Trigger to DAC selection overview Master_TIMER No trigger Update event SHRTIMER_DACTRIG0 DACTRGS[1:0] in SHRTIMER_MTCTL0 SHRTIMER_DACTRIG1 Slave_TIMERx No trigger SHRTIMER_DACTRIG2 Update event DACTRGS[1:0] in SHRTIMER_STxCTL0 Interrupt 19.4.10. Most events can generate interrupt requests. All interrupt requests are grouped in 7 vectors (SHRTIMER_IRQy,y=0..6).Refer to Table 19-17.
Page 516: Dma Request
GD32A508xx User Manual Interrupt Number Event Control bit Repetition event REPIE in SHRTIMER_STxDMAINTEN Slave_TIMER4: Compare 3 event CMP3IE in SHRTIMER_STxDMAINTEN SHRTIMER_IRQ5 Compare 2 event CMP2IE in SHRTIMER_STxDMAINTEN Compare 1 event CMP1IE in SHRTIMER_STxDMAINTEN Compare 0 event CMP0IE in SHRTIMER_STxDMAINTEN Bunch mode period event BMPERIE in SHRTIMER_INTEN SHRTIMER_IRQ0 DLL calibration completed...
Page 517: Dma Mode
GD32A508xx User Manual DMA mode 19.4.12. Timer’s DMA mode is the function that configures SHRTIMER’s multiple registers by DMA module with a single DMA request. The relative registers (7 registers in total) are as follows:  SHRTIMER_DMAUPMTR: Defines which registers in the Master_TIMER are updated. Most of Master_TIMER control and data registers are associated with a selection bit.
Page 518: Debug Mode
GD32A508xx User Manual The DMA request to write SHRTIMER_DMATB Parse SHRTIMER_DMAUPSTyR(Y=1..4) register and The process is similar to Parse SHRTIMER_DMAUPST0R register Data is transferred to Data is transferred to MTCTL0 bit SHRTIMER_MTCTL0 ST0CTL0bit SHRTIMER_ST0CTL0 is 1? and trigger a new DMA is 1? and trigger a new DMA Data is transferred to...
Page 519: Master_Timer Registers
GD32A508xx User Manual SHRTIMER Master_TIMER registers base address: 0x4001 7400 SHRTIMER Slave_TIMER0 registers base address: 0x4001 7480 SHRTIMER Slave_TIMER1 registers base address: 0x4001 7500 SHRTIMER Slave_TIMER2 registers base address: 0x4001 7580 SHRTIMER Slave_TIMER3 registers base address: 0x4001 7600 SHRTIMER Slave_TIMER4 registers base address: 0x4001 7680 SHRTIMER Common registers base address: 0x4001 7780 Master_TIMER registers 19.5.1.
Page 520 GD32A508xx User Manual Reserved Must be kept at reset value SHWEN Shadow registers enable 0: The shadow registers are disabled 1: The shadow registers are enabled 26:25 DACTRGS[1:0] Trigger source to DAC The timer can also generate a DAC trigger event when an update event occurs. This bit-field specifies which trigger source generates the DAC trigger event.
Page 521 GD32A508xx User Manual 00: Master_TIMER start event. 01: Master_TIMER compare 0 event 10: Slave_TIMER0 reset and start event 11: Slave_TIMER0 compare 0 event 13:12 SYNOPLS[1:0] Synchronization output pulse This bit-field specifies pulse synchronization output SHRTIMER_SCOUT. 00: Pulse generated disable. No pulse on SHRTIMER_SCOUT. 01: Reserved.
Page 522 GD32A508xx User Manual 0: Single pulse mode. The counter stops by hardware when it reaches the SHRTIMER_MTCAR value. 1: Continuous mode. The counter rolls over to zero and count continuously when it reaches the SHRTIMER_MTCAR value CNTCKDIV[2:0] Counter clock division This bit-field can be configured by software to specify division ratio between the super high resolution clock (SHRTIMER_HPCK) and the counter clock (SHRTIMER_PSCCK).
Page 523 GD32A508xx User Manual 1: Update interrupt occurred SYNIIF Synchronization input interrupt flag This flag is set by hardware when synchronization input occurs. 0: No synchronization input interrupt occurred 1: Synchronization input interrupt occurred REPIF Repetition interrupt flag This flag is set by hardware when a repetition event occurs. 0: No repetition interrupt occurred 1: Repetition interrupt occurred CMP3IF...
Page 524 GD32A508xx User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value UPIFC Clear update interrupt flag 0: No effect 1: Clear update interrupt flag SYNIIFC Clear synchronization input interrupt flag 0: No effect 1: Clear synchronization input interrupt flag REPIFC Clear repetition interrupt flag 0: No effect...
Page 525 GD32A508xx User Manual Bits Fields Descriptions 31:23 Reserved Must be kept at reset value UPDEN Update DMA request enable 0: disabled 1: enabled SYNIDEN Synchronization input DMA request enable 0: disabled 1: enabled REPDEN Repetition DMA request enable 0: disabled 1: enabled CMP3DEN Compare 3 DMA request enable...
Page 526 GD32A508xx User Manual CMP2IE Compare 2 interrupt enable 0: disabled 1: enabled CMP1IE Compare 1 interrupt enable 0: disabled 1: enabled CMP0IE Compare 0 interrupt enable 0: disabled 1: enabled SHRTIMER Master_TIMER counter register (SHRTIMER_MTCNT) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0]...
Page 527 GD32A508xx User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CARL[15:0] Counter auto reload value This bit-field specifies the auto reload value of the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 528 GD32A508xx User Manual SHRTIMER Master_TIMER compare 0 value register (SHRTIMER_MTCMP0V) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CMP0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP0VAL[15:0] Compare 0 value This bit-field contains value to be compared to the counter.
Page 529 GD32A508xx User Manual 15:0 CMP1VAL[15:0] Compare 1 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register; otherwise, it holds the content of the shadow register.
Page 530 GD32A508xx User Manual Reserved CMP3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP3VAL[15:0] Compare 3 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 531: Slave_Timerx Registers(X=0
GD32A508xx User Manual When the CNTCKDIV[3] bit in the SHRTIMER_MTACTL is ‘1’ and CNTCKDIV[2:0] can only be configured with ‘3’b000’: f SHRTIMER_PSSCK SHRTIMER_HPCK Note: The CNTCKDIV[3:0] bit-field cannot be modified once the timer is enabled Reserved Must be kept at reset value Slave_TIMERx registers(x=0..4) 19.5.2.
Page 532 GD32A508xx User Manual STxUPIN1. 1000: Update event generated on the update event following the rising edge of STxUPIN2. Other values are reserved Note: (1) The bit-field must reset before writing new value. (2) When UPSEL[3:0] = 4’b0001, 4’b0011, 4’b0100, 4’b0101, it is possible to have multiple concurrent update source.
Page 533 GD32A508xx User Manual with Slave_TIMER2 update event and the active registers of them are updated by the Slave_TIMER2 update event 0: The active registers is not update by Slave_TIMER2. 1: The active registers is update by Slave_TIMER2. Note: This bit does not exist in Slave_TIMER2. UPBST1 Update by Slave_TIMER1 update event When the bit is set, the Slave_TIMERx(x=0,2,3,4) update event are synchronized...
Page 534 GD32A508xx User Manual recalculated value of compare 3 is: (compare 3 active register value + capture 1 value for capture 1 event, or compare 3 active register value + compare 2 value for compare 2 event). Compare match occurs as soon as the counter equals the recalculated value.
Page 535 GD32A508xx User Manual 0: Half mode disable. 1: Half mode enable. CNTRSTM Counter reset mode This bit defines the behavior of the timer counter in single pulse mode. 0: The counter can be reset only if it stops (period elapsed) 1: The counter can be reset at any time (running or stopped).
Page 536 GD32A508xx User Manual CH1ONAI CH0ONAI Reserved DLYIIF RSTIF CH1OAIF CH0OAIF CAP1IF CAP0IF UPIF Reserved REPIF CMP3IF CMP2IF CMP1IF CMP0IF Bits Fields Descriptions 31:22 Reserved Must be kept at reset value CH1F Channel 1 output flag This bit indicates the output level state of channel 1. 0: Channel 1 outputs inactive level.
Page 537 GD32A508xx User Manual Refer to CH0ONAIF description. CH1OAIF Channel 1 output active interrupt flag Refer to CH0OAIF description. CH0ONAIF Channel 0 output inactive interrupt flag This flag is set by hardware when channel 0 output inactive (C0OPRE from active to inactive) occurs. 0: No channel 0 output inactive interrupt occurred 1: Channel 0 output inactive interrupt occurred CH0OAIF...
Page 538 GD32A508xx User Manual CMP1IF Compare 1 interrupt flag This flag is set by hardware when a compare 1 event occurs. 0: No compare 1 interrupt occurred 1: Compare 1 interrupt occurred CMP0IF Compare 0 interrupt flag This flag is set by hardware when a compare 0 event occurs. 0: No compare 0 interrupt occurred 1: Compare 0 interrupt occurred SHRTIMER Slave_TIMERx interrupt flag clear register (SHRTIMER_STxINTC)
Page 539 GD32A508xx User Manual 0: No effect Clear channel output inactive interrupt flag (CH0ONAIF SHRTIMER_STxINTF register) CH0OAIFC Clear channel 0 output active interrupt flag 0: No effect 1: Clear channel 0 output inactive interrupt flag (CH0OAIF in SHRTIMER_STxINTF register) CAP1IFC Clear capture 1 interrupt flag 0: No effect 1: Clear capture 1 interrupt flag (CAP1IF in SHRTIMER_STxINTF register) CAP0IFC...
Page 540 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) CH1ONA CH1OAD CH0ONA CH0OAD CAP1DE CAP0DE CMP3DE CMP2DE CMP1DE CMP0DE Reserved DLYIDEN RSTDEN UPDEN Reserved REPDEN CH1ONAI CH0ONAI Reserved DLYIIE RSTIE CH1OAIE CH0OAIE CAP1IE CAP0IE UPIE Reserved REPIE...
Page 541 GD32A508xx User Manual 1: enabled Reserved Must be kept at reset value REPDEN Repetition DMA request enable 0: disabled 1: enabled CMP3DEN Compare 3 DMA request enable 0: disabled 1: enabled CMP2DEN Compare 2 DMA request enable 0: disabled 1: enabled CMP1DEN Compare 1 DMA request enable 0: disabled...
Page 542 GD32A508xx User Manual 1: enabled CAP0IE Capture 0 interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value REPIE Repetition interrupt enable 0: disabled 1: enabled CMP3IE Compare 3 interrupt enable 0: disabled 1: enabled CMP2IE...
Page 543 GD32A508xx User Manual 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] The current counter value. Writing to it can change the value of the counter only when the Slave_TIMERx is stopped (STxCEN = 0 in SHRTIMER_STxCTL0 register). Note: (1) For counter clock division below 64 (CNTCKDIV[3:0] <...
Page 544 GD32A508xx User Manual This register has to be accessed by word(32-bit) Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-field specifies the repetition event generation rate. When the repetition counter had count down to zero, the coming roll-over event in continuous mode or reset event will generate a repetition event.
Page 545 GD32A508xx User Manual CARL[15:0] >= 0x60 when CNTCKDIV[3:0] = 4’b0000. (2) The maximum value must be less than or equal to 0xFFFF – (1 t ). For SHRTIMER_CK example: CARL[15:0] <= 0xFFDF when CNTCKDIV[3:0] = 4’b0000. SHRTIMER Slave_TIMERx compare composite register (SHRTIMER_STxCMP0CP) Address offset: 0x20...
Page 546 GD32A508xx User Manual This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register; otherwise, it holds the content of the shadow register.
Page 547 GD32A508xx User Manual Reserved CMP3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CMP3VAL[15:0] Compare 3 value This bit-field contains value to be compared to the counter. This register has a shadow register. If the shadow register is disabled (SHWEN = 0), it holds the content of the active register;...
Page 548 GD32A508xx User Manual SHRTIMER Slave_TIMERx capture 1 value register (SHRTIMER_STxCAP1V) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CAP1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CAP1VAL[15:0] Capture 1 value This bit-field indicates the counter value corresponding to the last capture event.
Page 549 GD32A508xx User Manual 0: Protect disable. DTFS and DTFCFG[15:0] are writable. 1: Protect enable. DTFS and DTFCFG[15:0] are read-only. Note: (1) The bit-field DTFCFG[15:9] is in SHRTIMER_STxACTL register. (2) This bit is not preloaded DTFSPROT Dead-time falling edge protection for sign This bit-field specifies the write protection for dead-time falling edge (only sign).
Page 550 GD32A508xx User Manual (SHRTIMER_DTGCK). When DTGCKDIV[3] is ‘0’, f DTGCKDIV[2:0] = (8*f SHRTIMER_DTGCK SHRTIMER_CK When DTGCKDIV[3] is ‘1’, f (DTGCKDIV[2:0]+4) SHRTIMER_DTGCK SHRTIMER_CK 0000: f = 8*f SHRTIMER_DTGCK SHRTIMER_CK 0001: f = (8*f SHRTIMER_DTGCK SHRTIMER_CK 0010: f = (8*f SHRTIMER_DTGCK SHRTIMER_CK 0011: f = (8*f SHRTIMER_DTGCK...
Page 551 GD32A508xx User Manual CH0SEX CH0SEX CH0SEX CH0SEX CH0SEX CH0SEX CH0SEX CH0SEX CH0SEX CH0SEX CH0SST CH0SST CH0SST CH0SST CH0SST CH0SUP CH0SST CH0SST CH0SST CH0SST CH0SMT CH0SMT CH0SMT CH0SMT CH0SMT CH0SCM CH0SCM CH0SCM CH0SCM CH0SPE CH0SRS CH0SSE CMP3 CMP2 CMP1 CMP0 Bits Fields Descriptions Update event generates channel 0 “set request”...
Page 552 GD32A508xx User Manual Slave_TIMERx interconnection event 7 generates channel 0 “set request” CH0SSTEV7 Refer to CH0SSTEV0 description. Slave_TIMERx interconnection event 6 generates channel 0 “set request” CH0SSTEV6 Refer to CH0SSTEV0 description. Slave_TIMERx interconnection event 5 generates channel 0 “set request” CH0SSTEV5 Refer to CH0SSTEV0 description.
Page 553 GD32A508xx User Manual request”. 0: The event cannot generate “set request”. 1: The event can generates “set request”. Slave_TIMERx compare 3 event generates channel 0 “set request” CH0SCMP3 When this bit is set, Slave_TIMERx compare 3 event can generate “set request”. 0: The event cannot generate “set request”.
Page 554: Reset Request
GD32A508xx User Manual SHRTIMER Slave_TIMERx channel reset request register (SHRTIMER_STxCH0RST) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) CH0RSU CH0RSE CH0RSE CH0RSE CH0RSE CH0RSE CH0RSE CH0RSE CH0RSE CH0RSE CH0RSE CH0RSS CH0RSS CH0RSS CH0RSS CH0RSS XEV9 XEV8...
Page 555 GD32A508xx User Manual External event 0 generates channel 0 “reset request” CH0RSEXEV0 When this bit is set, external event 0 can generate channel “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Slave_TIMERx interconnection event 8 generates channel 0 “reset request” CH0RSSTEV8 Refer to CH0RSSTEV0 description.
Page 556 GD32A508xx User Manual 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Master_TIMER compare 0 event generates channel 0 “reset request” CH0RSMTCMP0 When this bit is set, Master_TIMER compare 0 event can generate channel “reset request”.
Page 557 GD32A508xx User Manual software can generate channel “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”. Note: When this bit is set, the reset of other timers does not affect the output. Software event generates channel 0 “reset request” CH0RSSEV This bit is set by software and cleared by hardware automatically.
Page 558 GD32A508xx User Manual Refer to CH1SEXEV0 description. External event 5 generates channel 1 “set request” CH1SEXEV5 Refer to CH1SEXEV0 description. External event 4 generates channel 1 “set request” CH1SEXEV4 Refer to CH1SEXEV0 description. External event 3 generates channel 1 “set request” CH1SEXEV3 Refer to CH1SEXEV0 description.
Page 559 GD32A508xx User Manual Master_TIMER compare 3 event generates channel 1 “set request” CH1SMTCMP3 When this bit is set, Master_TIMER compare 3 event can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”. Master_TIMER compare 2 event generates channel 1 “set request”...
Page 560 GD32A508xx User Manual When this bit is set, Slave_TIMERx period event can generate “set request”. 0: The event cannot generate “set request”. 1: The event can generate “set request”. Slave_TIMERx reset event generates channel 1 “set request” CH1SRST When this bit is set, Slave_TIMERx reset event from synchronous input and software can generate channel 1 “set request”.
Page 561 GD32A508xx User Manual Refer to CH1RSEXEV0 description. External event 7 generates channel 1 “reset request” CH1RSEXEV7 Refer to CH1RSEXEV0 description. External event 6 generates channel 1 “reset request” CH1RSEXEV6 Refer to CH1RSEXEV0 description. External event 5 generates channel 1 “reset request” CH1RSEXEV5 Refer to CH1RSEXEV0 description.
Page 562 GD32A508xx User Manual Slave_TIMERx interconnection event 0 generates channel 1 “reset request” CH1RSSTEV0 When this bit is set, Slave_TIMERx interconnection event 0 can generate channel “reset request”. Refer to Table 19-5. Slave_TIMER interconnection event 0: The event cannot generate “reset request”. 1: The event can generate “reset request”.
Page 563 GD32A508xx User Manual 1: The event can generate “reset request”. Slave_TIMERx compare 1 event generates channel 1 “reset request” CH1RSCMP1 When this bit is set, Slave_TIMERx compare 1 event can generate channel “reset request”. 0: The event cannot generate “reset request”. 1: The event can generate “reset request”.
Page 564 GD32A508xx User Manual EXEV0M EXEV1M EXEV0M EXEV2FM[2:0] Reserved EXEV1FM[3:0] Reserved EXEV0FM[3:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:25 EXEV4FM[3:0] External event 4 filter mode Refer to EXEV0FM[3:0] description. EXEV4MEEN External event 4 memorized enable Refer to EXEV0MEEN description. Reserved Must be kept at reset value 22:19...
Page 565 GD32A508xx User Manual 0101: Blanking mode. The blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC0 0110: Blanking mode. The blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC1 0111: Blanking mode. The blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC2 1000: Blanking mode. The blank is from other Slave_TIMERy(not Slave_TIMERx): STBLKSRC3 1001: Blanking mode.
Page 566 GD32A508xx User Manual EXEV7M EXEV6M EXEV5M EXEV7FM[2:0] Reserved EXEV6FM[3:0] Reserved EXEV5FM[3:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:25 EXEV9FM[3:0] External event 9 filter mode Refer to EXEV0FM[3:0] in SHRTIMER_STxEXEVFCFG0 description. EXEV9MEEN External event 9 memorized enable Refer to EXEV0MEEN in SHRTIMER_STxEXEVFCFG0 description.
Page 567 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) For Slave_TIMER0 ST4CMP ST4CMP ST4CMP ST3CMP ST3CMP ST3CMP ST2CMP ST2CMP ST2CMP ST1CMP ST1CMP ST1CMP EXEV9R EXEV8R EXEV7R Reserved 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST 3RST...
Page 568 GD32A508xx User Manual This bit specifies whether the Slave_TIMER2 compare 0 event can reset the counter. 0: Slave_TIMER2 compare 0 event do not reset counter 1: Slave_TIMER2 compare 0 event resets counter ST1CMP3RST Slave_TIMER1 compare 3 event resets counter Refer to ST1CMP0RST description. ST1CMP1RST Slave_TIMER1 compare 1 event resets counter Refer to ST1CMP0RST description.
Page 569 GD32A508xx User Manual Refer to MTCMP0RST description MTCMP2RST Master_TIMER compare 2 event resets counter Refer to MTCMP0RST description MTCMP1RST Master_TIMER compare 1 event resets counter Refer to MTCMP0RST description MTCMP0RST Master_TIMER compare 0 event resets counter This bit specifies whether the Master_TIMER compare 0 event can reset the counter.
Page 570 GD32A508xx User Manual Reserved Must be kept at reset value ST4CMP3RST Slave_TIMER4 compare 3 event resets counter Refer to ST4CMP0RST description. ST4CMP1RST Slave_TIMER4 compare 1 event resets counter Refer to ST4CMP0RST description. ST4CMP0RST Slave_TIMER4 compare 0 event resets counter This bit specifies whether the Slave_TIMER4 compare 0 event can reset the counter.
Page 571 GD32A508xx User Manual EXEV9RST External event 9 resets counter Refer to EXEV0RST description. EXEV8RST External event 8 resets counter Refer to EXEV0RST description. EXEV7RST External event 7 resets counter Refer to EXEV0RST description. EXEV6RST External event 6 resets counter Refer to EXEV0RST description. EXEV5RST External event 5 resets counter Refer to EXEV0RST description.
Page 572 GD32A508xx User Manual 1: Master_TIMER period event resets counter CMP3RST Slave_TIMER1 compare 3 event resets counter Refer to CMP1RST description CMP1RST Slave_TIMER1 compare 1 event resets counter This bit specifies whether the compare 1 event can reset the counter. 0: Compare 1 event do not reset counter 1: Compare 1 event resets counter UPRST Slave_TIMER1 update event resets counter...
Page 573 GD32A508xx User Manual ST3CMP1RST Slave_TIMER3 compare 1 event resets counter Refer to ST3CMP0RST description. ST3CMP0RST Slave_TIMER3 compare 0 event resets counter This bit specifies whether the Slave_TIMER3 compare 0 event can reset the counter. 0: Slave_TIMER3 compare 0 event do not reset counter 1: Slave_TIMER3 compare 0 event resets counter ST1CMP3RST Slave_TIMER1 compare 3 event resets counter...
Page 574 GD32A508xx User Manual EXEV3RST External event 3 resets counter Refer to EXEV0RST description. EXEV2RST External event 2 resets counter Refer to EXEV0RST description. EXEV1RST External event 1 resets counter Refer to EXEV0RST description. EXEV0RST External event 0 resets counter This bit specifies whether the External event 0 can reset the counter. 0: External event 0 do not reset counter.
Page 575 GD32A508xx User Manual For Slave_TIMER3 ST4CMP ST4CMP ST4CMP ST2CMP ST2CMP ST2CMP ST1CMP ST1CMP ST1CMP ST0CMP ST0CMP ST0CMP EXEV9R EXEV8R EXEV7R Reserved 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST 3RST 1RST 0RST EXEV6R EXEV5R EXEV4R EXEV3R EXEV2R EXEV1R EXEV0R MTCMP3 MTCMP2 MTCMP1...
Page 576 GD32A508xx User Manual 1: Slave_TIMER1 compare 0 event resets counter ST0CMP3RST Slave_TIMER0 compare 3 event resets counter Refer to ST0CMP0RST description. ST0CMP1RST Slave_TIMER0 compare 1 event resets counter Refer to ST0CMP0RST description. ST0CMP0RST Slave_TIMER0 compare 0 event resets counter This bit specifies whether the Slave_TIMER0 compare 0 event can reset the counter.
Page 577 GD32A508xx User Manual MTCMP1RST Master_TIMER compare 1 event resets counter Refer to MTCMP0RST description MTCMP0RST Master_TIMER compare 0 event resets counter This bit specifies whether the Master_TIMER compare 0 event can reset the counter. 0: Master_TIMER compare 0 event do not reset counter 1: Master_TIMER compare 0 event resets counter MTPERRST Master_TIMER period event resets counter...
Page 578 GD32A508xx User Manual ST3CMP1RST Slave_TIMER3 compare 1 event resets counter Refer to ST3CMP0RST description. ST3CMP0RST Slave_TIMER3 compare 0 event resets counter This bit specifies whether the Slave_TIMER3 compare 0 event can reset the counter. 0: Slave_TIMER3 compare 0 event do not reset counter 1: Slave_TIMER3 compare 0 event resets counter ST2CMP3RST Slave_TIMER2 compare 3 event resets counter...
Page 579 GD32A508xx User Manual Refer to EXEV0RST description. EXEV7RST External event 7 resets counter Refer to EXEV0RST description. EXEV6RST External event 6 resets counter Refer to EXEV0RST description. EXEV5RST External event 5 resets counter Refer to EXEV0RST description. EXEV4RST External event 4 resets counter Refer to EXEV0RST description.
Page 580 GD32A508xx User Manual CMP1RST Slave_TIMER4 compare 1 event resets counter This bit specifies whether the compare 1 event can reset the counter. 0: Compare 1 event do not reset counter 1: Compare 1 event resets counter UPRST Slave_TIMER4 update event resets counter This bit specifies whether the update event can reset the counter.
Page 581 GD32A508xx User Manual 010: 25.0% 011: 37.5% 100: 50.0% 101: 62.5% 110: 75.0% 111: 87.5% CSPRD[3:0] Carrier signal period This bit-field defines the period of carrier signal (except the first pulse). t CSPRD (CSPRD[3:0]+1) x t =16 x t SHRTIMER_CSGCK SHRTIMER_CSGCK SHRTIMER_CK 0000: 16 x t...
Page 582 GD32A508xx User Manual Refer to CP0BST0A description. CP0BST3CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER3 This bit reserved only in Slave_TIMER3. Refer to CP0BST0CMP1 description. CP0BST3CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER3 This bit reserved only in Slave_TIMER3. Refer to CP0BST0CMP0 description.
Page 583 GD32A508xx User Manual CP0BST0CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER0 This bit reserved only in Slave_TIMER0. 0: Capture 0 is not triggered by compare 1 event of Slave_TIMER0. 1: Capture 0 is triggered by compare 1 event of Slave_TIMER0. CP0BST0CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER0 This bit reserved only in Slave_TIMER0.
Page 584 GD32A508xx User Manual Refer to CP0BEXEV0 description. CP0BEXEV0 Capture 0 triggered by external event 0 When the bit is set, capture 0 is triggered by external event 0 0: Capture 0 is not triggered by external event 0 1: Capture 0 is triggered by external event 0 CP0BUP Capture 0 triggered by update event When the bit is set, capture 0 is triggered by update event...
Page 585 GD32A508xx User Manual Refer to CP1BST0NA description. CP1BST4A Capture 1 triggered by ST4CH0_O output inactive to active transition This bit reserved only in Slave_TIMER4. Refer to CP1BST0A description. CP1BST3CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER3 This bit reserved only in Slave_TIMER3. Refer to CP1BST0CMP1 description.
Page 586 GD32A508xx User Manual CP1BST1A Capture 1 triggered by ST1CH0_O output inactive to active transition This bit reserved only in Slave_TIMER1. Refer to CP1BST0A description. CP1BST0CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER0 This bit reserved only in Slave_TIMER0. 0: Capture 1 is not triggered by compare 1 event of Slave_TIMER0.
Page 587 GD32A508xx User Manual Refer to CP1BEXEV0 description. CP1BEXEV1 Capture 1 triggered by external event 1 Refer to CP1BEXEV0 description. CP1BEXEV0 Capture 1 triggered by external event 0 When the bit is set, capture 1 is triggered by update external event 0 0: Capture 1 is not triggered by external event 0 1: Capture 1 is triggered by external event 0 CP1BUP...
Page 588 GD32A508xx User Manual by DTFCFG[15:0]. Note: (1) This bit must not be modified once the counter is enabled (STxCEN bit set). (2) This bit can be set only if one of the output idle state is active (ISOy = 1, y=0,1) during IDLE in bunch mode, and the dead-time value is positive (DTFSPROT / DTRSPROT set to 0).
Page 589 GD32A508xx User Manual 001: channel 1 output delayed IDLE on external event 5 010: channel 0 and channel 1 output delayed IDLE on external event 5 011: channel 0 and channel 1 output balanced IDLE on external event 5 in balanced mode (BLNMEN = 1 in SHRTIMER_STyCTL0(y=0,1,2) register) 100: channel 0 output delayed IDLE on external event 6 101: channel 1 output delayed IDLE on external event 6...
Page 590 GD32A508xx User Manual CH0CSEN Channel 0 carrier-signal mode enable 0: Carrier-signal mode of channel 0 is disable. 1: Carrier-signal mode of channel 0 is enable. Note: This bit must not be modified once the counter is enabled (STxCEN bit is set). CH0FLTOS[1:0] Channel 0 Fault output state This bit-field specifies the output state when a fault event happened.
Page 591 GD32A508xx User Manual Reserved FLT4EN FLT3EN FLT2EN FLT1EN FLT0EN Bits Fields Descriptions FLTENPROT Protect fault enable This bit-field specifies whether the write protection function is enable or not. This bit is write-once. It can only be cleared by a system reset once It is set by software. 0: Protect disable.
Page 592: Common Registers
GD32A508xx User Manual Bits Fields Descriptions 31:25 DTFCFG[15:9] Falling edge dead-time value configure This bit-field controls the value of the dead-time following a falling edge of output prepare signal (OyPRE,y=0,1): DTFvalue = DTFCFG[15:0]x t SHRTIMER_DTGCK = 1/ f SHRTIMER_DTGCK SHRTIMER_DTGCK Writing this register can change the high 7-bit of DTFCFG[15:0].
Page 593 GD32A508xx User Manual SHRTIMER control register 0 (SHRTIMER_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved ADTG3USRC[2:0] ADTG2USRC [2:0] ADTG1USRC [2:0] ADTG0USRC [2:0] ST4UPDI ST3UPDI ST2UPDI ST1UPDI ST0UPDI Reserved MTUPDIS Bits Fields Descriptions 31:28 Reserved...
Page 594 GD32A508xx User Manual 011: Slaver_TIMER2 update event 100: Slaver_TIMER3 update event 101: Slaver_TIMER4 update event Other values are reserved 18:16 ADTG0USRC[2:0] SHRTIMER_ADCTRIG0 update source This bit-field can be configured by software to specify the the source to update the SHRTIMER_ADCTRIGS0 register. 000: Master_TIMER update event 001: Slaver_TIMER0 update event 010: Slaver_TIMER1 update event...
Page 595 GD32A508xx User Manual SHRTIMER control register 1 (SHRTIMER_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved ST4SRST ST3SRST ST2SRST ST1SRST ST0SRST MTSRST Reserved ST4SUP ST3SUP ST2SUP ST1SUP ST0SUP MTSUP Bits Fields Descriptions 31:14 Reserved...
Page 596 GD32A508xx User Manual 1: The counter is reset. MTSRST Master_TIMER software reset This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is reset. 0: No effect. 1: The counter is reset. Reserved Must be kept at reset value ST4SUP...
Page 597 GD32A508xx User Manual pending update request is cancelled. 0: No effect. 1: update generated. SHRTIMER interrupt flag register (SHRTIMER_INTF) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DLLCALI Reserved BMPERIF SYSFLTI Reserved FLT4IF FLT3IF FLT2IF FLT1IF...
Page 598 GD32A508xx User Manual FLT3IF Fault 3 interrupt flag Refer to FLT0IF description. FLT2IF Fault 2 interrupt flag Refer to FLT0IF description. FLT1IF Fault 1 interrupt flag Refer to FLT0IF description. FLT0IF Fault 0 interrupt flag This flag is set by hardware when the fault 0 occurred. It is cleared by software writing it at 1.
Page 599 GD32A508xx User Manual Writing 1 to this bit clears the SYSFLTIF in SHRTIMER_INTF register. 0: No effect 1: Clear system fault completed interrupt flag FLT4IFC Clear fault 4 interrupt flag Writing 1 to this bit clears the FLT4IF in SHRTIMER_INTF register. Refer to FLT0IF description.
Page 600 GD32A508xx User Manual 1: Enabled DLLCALIE DLL calibration completed interrupt enable 0: disabled 1: enabled 15:6 Reserved Must be kept at reset value SYSFLTIE System fault interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value SHRTIMER channel output enable register (SHRTIMER_CHOUTEN) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 601 GD32A508xx User Manual ST3CH0EN Slave_TIMER3 channel 0 output (ST3CH0_O) enable Refer to ST0CH0EN description. Note: The disable status corresponds to both Idle and Fault states which is given by ST3CH0DISF bit in the SHRTIMER_CHOUTDISF register. ST2CH1EN Slave_TIMER2 channel 1 output (ST2CH1_O) enable Refer to ST0CH0EN description.
Page 602 GD32A508xx User Manual Reserved ST4CH1 ST4CH0 ST3CH1 ST3CH0 ST2CH1 ST2CH0 ST1CH1 ST1CH0 ST0CH1 ST0CH0 Reserved Bits Fields Descriptions 31:10 Reserved Must be kept at reset value ST4CH1DIS Slave_TIMER4 channel 1 output (ST4CH1_O) disable. Refer to ST0CH0DIS description. ST4CH0DIS Slave_TIMER4 channel 0 output (ST4CH0_O) disable. Refer to ST0CH0DIS description.
Page 603 GD32A508xx User Manual SHRTIMER channel output disable flag register (SHRTIMER_CHOUTDISF) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved ST4CH1 ST4CH0 ST3CH1 ST3CH0 ST2CH1 ST2CH0 ST1CH1 ST1CH0 ST0CH1 ST0CH0 Reserved DISF DISF DISF DISF DISF DISF...
Page 604 GD32A508xx User Manual 1: Slave_TIMER0 channel 0 output ST0CH0_O disabled, in Fault state SHRTIMER bunch mode control register (SHRTIMER_BMCTL) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) BMOPTF Reserved BMST4 BMST3 BMST2 BMST1 BMST0 BMMT rc_w0...
Page 605 GD32A508xx User Manual BMST2 Slave_TIMER2 bunch mode 0: Slave_TIMER2 counter clock(SHRTIMER_PSCCK) is maintained and the counter operates normally 1: Slave_TIMER2 counter clock(SHRTIMER_PSCCK) is stopped and the counter is reset Note: (1) This bit cannot be changed while the bunch mode is enabled. (2) This bit must not be set when the balanced IDLE mode is active (DLYISCH[2:0] = 3’bx11 in SHRTIMER_STxCHOCTL register).
Page 606 GD32A508xx User Manual SHRTIMER clock (SHRTIMER_CK) bunch mode counter (SHRTIMER_BMCNTCK) when BMCLKS[3:0] = 4’b1010 in SHRTIMER_BMCTL register. BMPSC[3:0] SHRTIMER_BMCNTCK SHRTIMER_CK 0000: f SHRTIMER_BMCNTCK SHRTIMER_CK 0001: f SHRTIMER_BMCNTCK SHRTIMER_CK 0010: f SHRTIMER_BMCNTCK SHRTIMER_CK 0011: f SHRTIMER_BMCNTCK SHRTIMER_CK 0100: f SHRTIMER_BMCNTCK SHRTIMER_CK 0101: f SHRTIMER_BMCNTCK SHRTIMER_CK...
Page 607 GD32A508xx User Manual when it reaches the SHRTIMER_BMCAR value BMEN Bunch mode enable The bunch mode controller is ready to receive the bunch mode start trigger when the bit is set. Writing this bit to 0 will terminate bunch mode. 0: Bunch mode disable.
Page 608 GD32A508xx User Manual operation. ST0EXEV6 Slave_TIMER0 period event following external event 6 triggers bunch mode operation Slave_TIMER0 period event following external event 6 is starting the bunch mode operation. 0：No effect on bunch mode operation. 1：Slave_TIMER0 period event following external event 6 is starting bunch mode operation.
Page 609 GD32A508xx User Manual ST1REP Slave_TIMER1 repetition event triggers bunch mode operation Refer to MTREP description. ST1RST Slave_TIMER1 reset event triggers bunch mode operation Refer to MTRST description. ST0CMP1 Slave_TIMER0 compare 1 event triggers bunch mode operation Refer to MTCMP1 description. ST0CMP0 Slave_TIMER0 compare 0 event triggers bunch mode operation Refer to MTCMP0 description.
Page 610 GD32A508xx User Manual SHRTIMER bunch mode compare value register (SHRTIMER_BMCMPV) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved BMCMPVAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 BMCMPVAL[15:0] Bunch mode compare value This bit-field contains value to be compared to the BM-counter and defines the duration of the IDLE.
Page 611 GD32A508xx User Manual Note: This bit-field must not be zero when the burst mode is enabled. SHRTIMER external event configuration register 0 (SHRTIMER_EXEVCFG0) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) EXEV2E Reserved EXEV4EG[1:0] EXEV4P EXEV4SRC[1:0]...
Page 612 GD32A508xx User Manual 13:12 EXEV2SRC[1:0] External event 2 source Refer to EXEV0SRC[1:0] description. Reserved Must be kept at reset value 10:9 EXEV1EG[1:0] External event 1 edge sensitivity Refer to EXEV0EG[1:0] description. EXEV1P External event 1 polarity Refer to EXEV0P description. EXEV1SRC[1:0] External event 1 source Refer to EXEV0SRC[1:0] description.
Page 613 GD32A508xx User Manual EXEV7E EXEV7P EXEV7SRC[1:0] Reserved EXEV6EG[1:0] EXEV6P EXEV6SRC[1:0] Reserved EXEV5EG[1:0] EXEV5P EXEV5SRC[1:0] G[0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:27 EXEV9EG[1:0] External event 9 edge sensitivity Refer to EXEV0EG[1:0] in SHRTIMER_EXEVCFG0 register description. EXEV9P External event 9 polarity Refer to EXEV0P in SHRTIMER_EXEVCFG0 register description.
Page 614 GD32A508xx User Manual EXEV5EG[1:0] External event 5 edge sensitivity Refer to EXEV0EG[1:0] in SHRTIMER_EXEVCFG0 register description. EXEV5P External event 5 polarity Refer to EXEV0P in SHRTIMER_EXEVCFG0 register description. EXEV5SRC[1:0] External event 5 source Refer to EXEV0SRC[1:0] in SHRTIMER_EXEVCFG0 register description. SHRTIMER external event...
Page 615 GD32A508xx User Manual 15:12 EXEV7FC[3:0] External event 7 filter control Refer to EXEV5FC[3:0] description. 11:10 Reserved Must be kept at reset value EXEV6FC[3:0] External event 6 filter control Refer to EXEV5FC[3:0] description. Reserved Must be kept at reset value EXEV5FC[3:0] External event 5 filter control An event counter is used in the digital filter, in which a transition on the output occurs after N input events.
Page 616 GD32A508xx User Manual Bits Fields Descriptions TRG0ST4PER SHRTIMER_ADCTRIG0 on Slave_TIMER4 period event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG0. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 period event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER4 period event.
Page 617 GD32A508xx User Manual TRG0ST2C2 SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 2 event Refer to TRG0ST2C1 description. TRG0ST2C1 SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG0. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER2 compare 1 event.
Page 618 GD32A508xx User Manual Refer to TRG0ST0C1 description. TRG0ST0C2 SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 2 event Refer to TRG0ST0C1 description. TRG0ST0C1 SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG0. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER0 compare 1 event.
Page 619 GD32A508xx User Manual 1: ADC trigger event generated on SHRTIMER Master_TIMER compare 0 event. SHRTIMER trigger source 1 to ADC register (SHRTIMER_ADCTRIGS1) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) TRG1ST4 TRG1ST4 TRG1ST4 TRG1ST4 TRG1ST3...
Page 620 GD32A508xx User Manual This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER3 period event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER3 period event. TRG1ST3C3 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event Refer to TRG1ST3C1 description.
Page 621 GD32A508xx User Manual Refer to TRG1ST1C1 description. TRG1ST1C2 SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 2 event Refer to TRG1ST1C1 description. TRG1ST1C1 SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG1. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event.
Page 622 GD32A508xx User Manual The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG1. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Master_TIMER period event. 1: ADC trigger event generated on SHRTIMER Master_TIMER period event. TRG1MTC3 SHRTIMER_ADCTRIG1 on Master_TIMER compare 3 event Refer to TRG1MTC0 description.
Page 623 GD32A508xx User Manual Refer to TRG2ST4C1 description. TRG2ST4C2 SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 event Refer to TRG2ST4C1 description. TRG2ST4C1 SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG2. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER4 compare 1 event.
Page 624 GD32A508xx User Manual 1: ADC trigger event generated on SHRTIMER Slave_TIMER2 compare 1 event. TRG2ST1RST SHRTIMER_ADCTRIG2 on Slave_TIMER1 reset The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG2. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 reset .
Page 625 GD32A508xx User Manual event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER0 compare 1 event. TRG2EXEV4 SHRTIMER_ADCTRIG2 on external event 4 Refer to TRG2EXEV0 description. TRG2EXEV3 SHRTIMER_ADCTRIG2 on external event 3 Refer to TRG2EXEV0 description. TRG2EXEV2 SHRTIMER_ADCTRIG2 on external event 2 Refer to TRG2EXEV0 description.
Page 626 GD32A508xx User Manual This register has to be accessed by word (32-bit) TRG3ST4 TRG3ST4 TRG3ST4 TRG3ST4 TRG3ST3 TRG3ST3 TRG3ST3 TRG3ST3 TRG3ST3 TRG3ST2 TRG3ST2 TRG3ST2 TRG3ST2 TRG3ST2 TRG3ST1 TRG3ST1 TRG3ST1 TRG3ST1 TRG3ST0 TRG3ST0 TRG3ST0 TRG3ST0 TRG3EX TRG3EX TRG3EX TRG3EX TRG3EX TRG3MT TRG3MT TRG3MT TRG3MT...
Page 627 GD32A508xx User Manual Refer to TRG3ST3C1 description. TRG3ST3C1 SHRTIMER_ADCTRG3 on Slave_TIMER3 compare 1 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRG3. This bit specifies whether the event can generate the ADC trigger event. 0: No ADC trigger event generated on SHRTIMER Slave_TIMER3 compare 1 event.
Page 628 GD32A508xx User Manual 0: No ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event. 1: ADC trigger event generated on SHRTIMER Slave_TIMER1 compare 1 event. TRG3ST0PER SHRTIMER_ADCTRG3 on Slave_TIMER0 period event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRG3. This bit specifies whether the event can generate the ADC trigger event.
Page 629 GD32A508xx User Manual TRG3MTC2 SHRTIMER_ADCTRG3 on Master_TIMER compare 2 event Refer to TRG3MTC0 description. TRG3MTC1 SHRTIMER_ADCTRG3 on Master_TIMER compare 1 event Refer to TRG3MTC0 description. TRG3MTC0 SHRTIMER_ADCTRG3 on Master_TIMER compare 0 event The SHRTIMER can generate an ADC trigger event on SHRTIMER_ADCTRIG3. This bit specifies whether the event can generate the ADC trigger event.
Page 630 GD32A508xx User Manual Writing 1 to the bit starts the DLL calibration when CLBPEREN = 0. This bit is write- only. 0: No effect. 1: DLL calibration start once. Note: CLBPEREN bit and CLBSTRT bit must not be set simultaneously. SHRTIMER fault input configuration register 0 (SHRTIMER_FLTINCFG0) Address offset: 0x50 Reset value: 0x0000 0000...
Page 631 GD32A508xx User Manual FLT2INP Fault 2 input polarity Refer to FLT0INP description. FLT2INEN Fault 2 input enable Refer to FLT0INEN description. FLT1INPROT Protect fault 1 input configuration Refer to FLT0INPROT description. 14:11 FLT1INFC[3:0] Fault 1 input filter control Refer to FLT0INFC[3:0] description. FLT1INSRC Fault 1 input source Refer to FLT0INSRC description.
Page 632 GD32A508xx User Manual 1110: f /32, N=6. SAMP SHRTIMER_FLTFCK 1111: f /32, N=8. SAMP SHRTIMER_FLTFCK Note: (1) This bit-field can be written only when FLT0INEN bit is reset. (2) This bit-field cannot be modified when FLT0INPROT has been programmed. FLT0INSRC Fault 0 input source 0: The source of fault 0 input is chip external pin.
Page 633 GD32A508xx User Manual 00: f SHRTIMER_FLTFCK SHRTIMER_CK 01: f SHRTIMER_FLTFCK SHRTIMER_CK 10: f SHRTIMER_FLTFCK SHRTIMER_CK 11: f SHRTIMER_FLTFCK SHRTIMER_CK Note: This bit must be configured before setting any FLTyINEN(y=0..4). 23:8 Reserved Must be kept at reset value FLT4INPROT Protect fault 4 input configuration Refer to FLT0INPROT in SHRTIMER_FLTINCFG0 register description.
Page 634 GD32A508xx User Manual Refer to MTCTL0 description. MTCMP1V SHRTIMER_MTCMP1V update by DMA mode Refer to MTCTL0 description. MTCMP0V SHRTIMER_MTCMP0V update by DMA mode Refer to MTCTL0 description. MTCREP SHRTIMER_MTCREP update by DMA mode Refer to MTCTL0 description. MTCAR SHRTIMER_MTCAR update by DMA mode Refer to MTCTL0 description.
Page 635 GD32A508xx User Manual Refer to STxCTL0 bit description. 30:21 Reserved Must be kept at reset value STxFLTCTL SHRTIMER_STxFLTCTL update by DMA mode Refer to STxCTL0 bit description. STxCHOCTL SHRTIMER_STxCHOCTL update by DMA mode Refer to STxCTL0 bit description. STxCSCTL SHRTIMER_STxCSCTL update by DMA mode Refer to STxCTL0 bit description.
Page 636 GD32A508xx User Manual Refer to STxCTL0 bit description. STxCNT SHRTIMER_STxCNT update by DMA mode Refer to STxCTL0 bit description. STxDMAINTEN SHRTIMER_STxDMAINTEN update by DMA mode Refer to STxCTL0 bit description. STxINTC SHRTIMER_STxINTC update by DMA mode Refer to STxCTL0 bit description. STxCTL0 SHRTIMER_STxCTL0 update by DMA mode This bit defines if the SHRTIMER_STxCTL0 register is updated by the DMA mode.
Page 637: Universal Synchronous/Asynchronous Receiver /Transmitter (Usart)
GD32A508xx User Manual Universal synchronous/asynchronous receiver /transmitter (USART) Universal synchronous/asynchronous receiver /transmitter 20.1. (USARTx, x=0..4) Overview 20.1.1. The USART provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK(PCLK1 or PCLK2) to produce a dedicated baud rate clock for the USART transmitter and receiver.
Page 638: Function Overview
GD32A508xx User Manual  Synchronous mode and transmitter clock output for synchronous transmission.  ISO 7816-3 compliant smartcard interface. – Character mode (T=0). – Block mode (T=1). – Direct and inverse convention.  Multiprocessor communication. – Enter into mute mode if address match does not occur. –...
Page 639: Figure 20-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32A508xx User Manual CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controler Flow nCTS Controler USART Control Registers USART Address Transmitter Transimit clock Controler /8*(2- Receiver Receiver Wakeup Unit OVSMOD)
Page 640 GD32A508xx User Manual STB[1:0] stop bit length (bit) usage description Normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 641: Figure 20-3. Usart Transmit Procedure
GD32A508xx User Manual After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_DATA when the TBE bit in the USART_STAT0 register is asserted.
Page 642: Usart Receiver
GD32A508xx User Manual USART receiver After power on, the USART receiver can be enabled by the following procedure: Set the UEN bit in USART_CTL0 to enable the USART. Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1 to configure the number of stop bits.
Page 643: Figure 20-5. Configuration Step When Using Dma For Usart Transmission
GD32A508xx User Manual If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value. If they are not the same, the parity error (PERR) bit in USART_STAT0 register will be set.
Page 644: Figure 20-6. Configuration Steps When Using Dma For Usart Reception
GD32A508xx User Manual Clear the TC bit in USART_STAT Set the address of USART_DATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 645: Figure 20-7. Hardware Flow Control Between Two Usarts
GD32A508xx User Manual Set the address of USART_DATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc Enable the DMA channel for USART When the number of the data received by USART reaches the DMA transfer number, an end...
Page 646: Cts Flow Control
GD32A508xx User Manual data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full, and can be cleared by reading the USART_DATA register. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 647: Lin Mode
GD32A508xx User Manual the USART. The status bits are available in the USART_STAT0 register. If the LSB 4 bits of an address frame differ from the ADDR[3:0] bits in the USART_CTL1 register, the hardware sets the RWU bit and enters mute mode automatically. In this situation, the RBNE bit is not set.
Page 648: Figure 20-11. Example Of Usart In Synchronous Mode
GD32A508xx User Manual Synchronous mode The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1. The LMEN bit in USART_CTL1 and SCEN, HDEN, IREN bits in USART_CTL2 should be cleared in synchronous mode. The CK pin is the clock output of the synchronous USART transmitter, and can be only activated when the TEN bit is enabled.
Page 649: Figure 20-13. Irda Sir Endec Module
GD32A508xx User Manual IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode. In IrDA mode, the USART transmission data frame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin.
Page 650: Figure 20-14. Irda Data Modulation
GD32A508xx User Manual pulse width is greater than 1 but smaller than 2 times PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block. Figure 20-14.
Page 651: Figure 20-15. Iso7816-3 Frame Format
GD32A508xx User Manual The smartcard mode is a half-duplex communication protocol. When connected to a smartcard, the TX pin must be configured as open drain mode, and an external pull-up resistor will be needed, which drives a bidirectional line that is also driven by the smartcard. The data frame consists of 1 start bit, 9 data bits (1 parity bit included) and 1.5 stop bits.
Page 652 GD32A508xx User Manual Block (T=1) mode In block (T=1) mode, the NKEN bit in the USART_CTL2 register should be cleared to deactivate the NACK transmission. When requesting a read from the smartcard, the RT[23:0] bits in USART_RT register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. This timeout period is expressed in baud time units.
Page 653: Usart Interrupts
GD32A508xx User Manual USART interrupts The USART interrupt events and flags are listed in Table 20-3. USART interrupt requests. Table 20-3. USART interrupt requests Enable Interrupt event Event flag Control register Control bit Transmit data buffer empty USART_CTL0 TBEIE CTS toggled flag CTSF USART_CTL2 CTSIE...
Page 654 GD32A508xx User Manual IDLEF IDLEIE ORERR RBNEIE PERR PEIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT RBNE RBNEIE TCIE TBEIE CTSF CTSIE...
Page 655: Register Definition
GD32A508xx User Manual Register definition 20.1.4. USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register 0 (USART_STAT0) Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 656 GD32A508xx User Manual register. 0: Transmit data buffer is not empty. 1: Transmit data buffer is empty. Transmission complete This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
Page 657 GD32A508xx User Manual frame. An interrupt occurs if the ERRIE bit in USART_CTL2 is set. Software can clear this bit by reading the USART_STAT0 and USART_DATA registers one by one. 0: The USART does not detect a framing error. 1: The USART has detected a framing error. PERR Parity error flag This bit is set when the parity bit of a receive frame does not match the expected...
Page 658 GD32A508xx User Manual Reserved INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value. 15:4 INTDIV[11:0] Integer part of baud-rate divider. FRADIV[3:0] Fraction part of baud-rate divider. Control register 0 (USART_CTL0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 659 GD32A508xx User Manual 0: wake up by idle frame. 1: wake up by address match. PCEN Parity check function enable 0: Parity check function disabled. 1: Parity check function enabled. Parity mode 0: Even parity. 1: Odd parity. PERRIE Parity error interrupt enable. If this bit is set, an interrupt occurs when the PERR bit in USART_STAT0 is set.
Page 660 GD32A508xx User Manual idle frame has been detected. In wake up by address match mode (WM=1), this bit can be reset by hardware when receiving an address match frame or set by hardware when receiving an address mismatch frame. 0: Receiver in active mode. 1: Receiver in mute mode.
Page 661 GD32A508xx User Manual 0: The CK pin is in low state when the USART is in idle state. 1: The CK pin is in high state when the USART is in idle state. This bit is reserved for UART3/4. CK phase This bit specifies the phase of the CK pin in synchronous mode.
Page 662 GD32A508xx User Manual Bits Fields Descriptions 31:12 Reserved Must be kept the reset value. One sample bit method This bit selects the sample method. The noise detection flag (NF) is disabled when the one sample bit method is selected. 0: Three sample bit method. 1: One sample bit method.
Page 663 GD32A508xx User Manual This bit is reserved for UART3/4. HDEN Half-duplex enable This bit enables the half-duplex USART mode. 0: Half duplex mode is disabled. 1: Half duplex mode is enabled. IRLP IrDA low-power This bit selects low-power mode of IrDA mode. 0: Normal mode.
Page 664 GD32A508xx User Manual 00000000: Reserved - never program this value 00000001: divides by 1 00000010: divides by 2 11111111: divides by 255 When the USART works in IrDA normal mode, these bits must be set to 00000001. When the USART smartcard mode is enabled, the PSC [4:0] bits specify the division factor that is used to divide the peripheral clock (APB1/APB2) to generate the smartcard clock (CK).
Page 665 GD32A508xx User Manual TINV TX pin level inversion This bit specifies the polarity of the TX pin. 0: TX pin signal values are not inverted. 1: TX pin signal values are inverted. This bit field cannot be written when the USART is enabled (UEN=1). RINV RX pin level inversion This bit specifies the polarity of the RX pin.
Page 666 GD32A508xx User Manual BL[7:0] RT[23:16] RT[15:0] Bits Fields Descriptions 31:24 BL[7:0] Block Length These bits specify the block length in Smartcard T=1 Reception. Its value equals to the number of information characters + the length of the Epilogue Field (1-LEC/2- CRC) - 1.
Page 667 GD32A508xx User Manual Bits Fields Descriptions 31:17 Reserved Must be kept the reset value. Busy flag This bit is set when the USART is receiving a data frame. 0: USART reception path is idle. 1: USART reception path is working. 15:13 Reserved Must be kept the reset value.
Page 668 GD32A508xx User Manual 31:17 Reserved Forced by hardware to 0. CDIE Collision detected interrupt enable. 0: Collision detected interrupt disable. 1: Collision detected interrupt enable. 15:9 Reserved Forced by hardware to 0. Collision detected status 0: no collision detected. 1: collision detected in halfduplex mode. Reserved Forced by hardware to 0.
Page 669: Universal Synchronous/Asynchronous Receiver /Transmitter (Usartx, X=5)
GD32A508xx User Manual Universal synchronous/asynchronous receiver /transmitter 20.2. (USARTx, x=5) Overview 20.2.1. The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK(PCLK2, CK_USART5) to produce a dedicated wide range baud rate clock for the USART transmitter and receiver.
Page 670: Function Overview
GD32A508xx User Manual  IrDA support  Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface Character mode (T=0) – Block mode (T=1) – Direct and inverse convention –  Multiprocessor communication Enter into mute mode if address match does not occur –...
Page 671: Figure 20-18. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32A508xx User Manual CPU/DMA Transmit Read Write Shift Buffer Buffer Register SW_RX IrDA Block Receive Shift Read FiFO Register USART Guard Time and Prescaler Register nRTS Hardware CK Controler Flow nCTS Controler USART Control Registers USART Address Transmitter Transimit clock Controler /8*(2- Receiver...
Page 672 GD32A508xx User Manual STB[1:0] stop bit length (bit) usage description Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame. The break frame structure is a number of low bits followed by the configured number of stop bits.
Page 673: Figure 20-19. Usart Transmit Procedure
GD32A508xx User Manual After the TEN bit is set, an idle frame will be sent. The TEN bit should not be cleared while the transmission is ongoing. After power on, the TBE bit is high by default. Data can be written to the USART_TDATA when the TBE bit in the USART_STAT register is asserted.
Page 674: Figure 20-20. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32A508xx User Manual USART receiver After power on, the USART receiver can be enabled by the following procedure: Write the WL bit in USART_CTL0 to set the data bits length. Set the STB[1:0] bits in USART_CTL1. Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. Set the baud rate in USART_BAUD.
Page 675: Figure 20-21. Configuration Step When Using Dma For Usart Transmission
GD32A508xx User Manual If the parity check function is enabled by setting the PCEN bit in the USART_CTL0 register, the receiver calculates the expected parity value while receiving a frame. The received parity bit will be compared with this expected value. If they are not the same, the parity error (PERR) bit in USART_STAT register will be set.
Page 676: Figure 20-22. Configuration Step When Using Dma For Usart Reception
GD32A508xx User Manual Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 677 GD32A508xx User Manual Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc Enable the DMA channel for USART When the number of the data received by USART reaches the DMA transfer number, an end...
Page 678: Figure 20-23. Break Frame Occurs During Idle State
GD32A508xx User Manual bit preceding the MSB bit is detected as the address bit. If the ADDM bit is set and the receive frame is a 7bit data, the LSB 6 bits will be compared with ADDR[5:0]. If the ADDM bit is set and the receive frame is a 9bit data, the LSB 8 bits will be compared with ADDR[7:0].
Page 679: Figure 20-25. Example Of Usart In Synchronous Mode
GD32A508xx User Manual the clock output of the synchronous USART transmitter, and can be only activated when the TEN bit is enabled. No clock pulse will be sent through the CK pin during the transmission of the start bit and stop bit. The CLEN bit in USART_CTL1 can be used to determine whether the clock is output or not during the last (address flag) bit transmission.
Page 680: Figure 20-27. Irda Sir Endec Module
GD32A508xx User Manual Figure 20-27. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 681: Figure 20-29. Iso7816-3 Frame Format
GD32A508xx User Manual Half-duplex communication mode The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 682 GD32A508xx User Manual gap of 2.5 bits time will be inserted before the start of a resented frame. At the end of the last repeated character the TC bit is set immediately without guard time. The USART will stop transmitting and assert the frame error status if it still receives the NACK signal after the programmed number of retries.
Page 683: Modbus Communication
GD32A508xx User Manual The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set). The RT interrupt may occur in case of an error in the block length. Direct and inverse convention The smartcard protocol defines two conventions: direct and inverse.
Page 684: Wakeup From Deep-Sleep Mode
GD32A508xx User Manual Rx Module Rx shift register Rx FIFO EN FIFO 0 Rx Buffer FIFO 1 FIFO 2 FIFO 3 If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out. The PERR/NERR/FERR/EBF flags should be cleared before reading a receive data out.
Page 685: Figure 20-31. Usart Interrupt Mapping Diagram
GD32A508xx User Manual Interrupt event Event flag Enable Control bit Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE Parity error flag PERR PERRIE Break detected flag in LIN LBDF LBDIE mode Reception errors (noise flag, overrun error, framing error) in NERR or ORERR or FERR ERRIE...
Page 686 GD32A508xx User Manual RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ERRIE ORERR LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 687: Register Defintion
GD32A508xx User Manual Register defintion 20.2.4. USART5 base address: 0x4001 7000 Control register 0 (USART_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE Reserved OVSMOD AMIE PCEN PERRIE TBEIE TCIE RBNEIE IDLEIE...
Page 688 GD32A508xx User Manual This bit field cannot be written when the USART is enabled (UEN=1). Wakeup method in mute mode 0: Idle Line 1: Address Mark This bit field cannot be written when the USART is enabled (UEN=1). PCEN Parity control enable. 0: Parity control disabled.
Page 689 GD32A508xx User Manual 1: USART able to wake up the MCU from Deep-sleep mode. Providing that the clock source for the USART must be IRC8M or LXTAL. USART enable 0: USART prescaler and outputs disabled. 1: USART prescaler and outputs enabled. Control register 1 (USART_CTL1) Address offset: 0x04 Reset value: 0x0000 0000...
Page 690 GD32A508xx User Manual 1: Data bit signal values are inverted. This bit field cannot be written when the USART is enabled (UEN=1). TINV TX pin level inversion. 0: TX pin signal values are not inverted. 1: TX pin signal values are inverted. This bit field cannot be written when the USART is enabled (UEN=1).
Page 691 GD32A508xx User Manual 1: The clock pulse of the last data bit (MSB) is output to the CK pin in synchronous mode. This bit field cannot be written when the USART is enabled (UEN=1). Reserved Must be kept at reset value. LBDIE LIN break detection interrupt enable.
Page 692 GD32A508xx User Manual These bits are used to specify the event which activates the WUF (Wakeup from Deep-sleep mode flag) in the USART_STAT register. 00: WUF active on address match, which is defined by ADDR and ADDM. 01: Reserved. 10: WUF active on Start bit. 11: WUF active on RBNE.
Page 693 GD32A508xx User Manual 10:8 Reserved Must be kept at reset value. DENT DMA enable for transmission. 0: DMA mode is disabled for transmission. 1: DMA mode is enabled for transmission. DENR DMA enable for reception. 0: DMA mode is disabled for reception. 1: DMA mode is enabled for reception.
Page 694 GD32A508xx User Manual Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 BRR[15:4] Integer of baud-rate divider INTDIV = BRR[15:4] BRR [3:0] Fraction of baud-rate divider If OVSMOD = 0, FRADIV = BRR [3:0]; If OVSMOD = 1, FRADIV = BRR [2:0], BRR [3] must be reset.
Page 695 GD32A508xx User Manual In smartcard mode, the prescaler value for dividing the system clock is stored in PSC[4:0] bits. And the bits of PSC[7:5] must be kept at reset value. The division factor is twice as the prescaler value. 00000: Reserved - do not program this value. 00001: divides the source clock by 2.
Page 696 GD32A508xx User Manual received character. Command register (USART_CMD) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TXFCMD RXFCMD MMCMD SBKCMD Reserved Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. TXFCMD Transmit data flush request.
Page 697 GD32A508xx User Manual Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknowledge flag. This bit, which is set/reset by hardware, reflects the receive enable state of the USART core logic. 0: The USART core receiving logic has not been enabled. 1: The USART core receiving logic has been enabled.
Page 698 GD32A508xx User Manual Cleared by writing 1 to the AMC in the USART_INTC register. Busy flag 0: USART reception path is idle. 1: USART reception path is working. 15:13 Reserved Must be kept at reset value. End of block flag. 0: End of Block not reached.
Page 699 GD32A508xx User Manual the TBE bit is set. Cleared by writing 1 to TCC bit in USART_INTC register. RBNE Read data buffer not empty. 0: Data is not received. 1: Data is received and ready to be read. An interrupt will occur if the RBNEIE bit is set in USART_CTL0.
Page 700 GD32A508xx User Manual 0: No parity error is detected. 1: Parity error flag is detected. An interrupt will occur if the PERRIE bit is set in USART_CTL0. Set by hardware when a parity error occurs in receiver mode. Cleared by writing 1 to PEC bit in USART_INTC register. Interrupt status clear register (USART_INTC) Address offset: 0x20 Reset value: 0x0000 0000...
Page 701 GD32A508xx User Manual IDLEC Idle line detected clear. Writing 1 to this bit clears the IDLEF bit in the USART_STAT register. OREC Overrun error clear. Writing 1 to this bit clears the ORERR bit in the USART_STAT register. Noise detected clear. Writing 1 to this bit clears the NERR bit in the USART_STAT register.
Page 702 GD32A508xx User Manual Reserved TDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. TDATA[8:0] Transmit Data value. The transmit data character is contained in these bits. The value written in the MSB (bit 7 or bit 8 depending on the data length) will be replaced by the parity, when transmitting with the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
Page 703 GD32A508xx User Manual RFFINT RFCNT[2:0] RFFIE RFEN Reserved ELNACK r_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. RFFINT Receive FIFO full interrupt flag. 14:12 RFCNT[2:0] Receive FIFO counter number. Receive FIFO full flag. 0: Receive FIFO not full. 1: Receive FIFO full.
Page 704: Inter-Integrated Circuit Interface (I2C)
GD32A508xx User Manual Inter-integrated circuit interface (I2C) Inter-integrated circuit interface (I2Cx, x=0, 1) 21.1. Overview 21.1.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL.
Page 705: Table 21-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32A508xx User Manual PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 21-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Description Term...
Page 706: Figure 21-2. Data Validation
GD32A508xx User Manual not fixed and depend on the associated level of V Data validation The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW (see Figure 21-2.
Page 707: Figure 21-4. Clock Synchronization
GD32A508xx User Manual a HIGH wait-state during this time. Figure 21-4. Clock synchronization CLK1 CLK2 Arbitration Arbitration, like synchronization, is part of the protocol where more than one master is used in the system. Slaves are not involved in the arbitration procedure. A master may start a transfer only if the bus is free.
Page 708: Figure 21-6. I2C Communication Flow With 7-Bit Address
GD32A508xx User Manual Address (0x00). The I2C block supports both 7-bit and 10-bit address modes. An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation. Figure 21-6. I2C communication flow with 7-bit address Figure 21-7.
Page 709 GD32A508xx User Manual mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus.
Page 710: Figure 21-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32A508xx User Manual I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND START condition Master sends header Slave sends Acknowledge Set ADDSEND...
Page 711: Figure 21-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32A508xx User Manual STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 21-10. Programming model for slave receiving (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE...
Page 712 GD32A508xx User Manual shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately. The I2C begins to transmit data to I2C bus as soon as the shift register is not empty.
Page 713 GD32A508xx User Manual to ensure the correct ending of data reception. Two solutions for master receiving are provided here for applications: Solution A and B. Solution A requires the software’s quick response to I2C events, while Solution B doesn’t. Solution A First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing.
Page 714: Figure 21-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32A508xx User Manual Figure 21-12. Programming model for master receiving using Solution A (10-bit address mode) Hardware Action I2C Line State Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 715: Figure 21-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32A508xx User Manual If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 716 GD32A508xx User Manual I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address Slave sends Acknowledge...
Page 717: Packet Error Checking
GD32A508xx User Manual to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur. Use DMA for data transfer As is shown in Programming Model, each time TBE or RBNE is asserted, software should write or read a byte, this may cause CPU to be high overloaded. The DMA controller can be used to process TBE and RBNE flags: each time TBE or RBNE is asserted, DMA controller does a read or write operation automatically.
Page 718 GD32A508xx User Manual Each message transmission on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications. I2C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications.
Page 719: Table 21-2. Event Status Flags
GD32A508xx User Manual specific flags and implement the upper protocols described in SMBus specification. Before communication, SMBEN bit in I2C_CTL0 should be set and SMBSEL and ARPEN bits should be configured to desired values. In order to support address resolution protocol (ARP) (ARPEN=1), the software should respond to HSTSMB flag in SMBus Host Mode (SMBSEL =1) or DEFSMB flag in SMBus Device Mode, and implement the function of ARP protocol.
Page 720 GD32A508xx User Manual Error Name Description OUERR Over-run or under-run when SCL stretch is disabled. AERR No acknowledge received CRC value doesn’t match PECERR SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert...
Page 721: Register Definition
GD32A508xx User Manual Register definition 21.1.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved SALT POAP...
Page 722 GD32A508xx User Manual 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent...
Page 723 GD32A508xx User Manual 1: I2C is enabled Control register 1 (I2C_CTL1) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE ERRIE Reserved I2CCLK[6:0] Bits Fields Descriptions 31:13 Reserved...
Page 724 GD32A508xx User Manual 0000000 - 0000001: Not allowed 0000010 - 1011010: 2MHz~90MHz 1011011 - 1111111: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz. In I2C fast mode, the frequencies of APB1 must be equal or greater than 8MHz.
Page 725 GD32A508xx User Manual Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) Address offset: 0x10 Reset value: 0x0000 0000...
Page 726 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode) SMBTO...
Page 727 GD32A508xx User Manual This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail). 0: I2C_DATA is not empty 1: I2C_DATA is empty, software can write RBNE...
Page 728 GD32A508xx User Manual mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA. 0: No START signal sent 1: START signal sent Transfer status register 1 (I2C_STAT1) Address offset: 0x18...
Page 729 GD32A508xx User Manual Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver. It is cleared by hardware after a STOP or a START signal or I2CEN=0 or LOSTARB=1. 0: Receiver 1: Transmitter I2CBSY...
Page 730 GD32A508xx User Manual In fast speed mode or fast mode plus, if DTCY=0: =CLKC*T =2*CLKC*T high PCLK1 PCLK1 In fast speed mode or fast mode plus, if DTCY=1: =9*CLKC*T =16*CLKC*T high PCLK1 PCLK1 Note: If DTCY is 0, when PCLK1 is an integral multiple of 3, the baud rate will be more accurate.
Page 731 GD32A508xx User Manual Rxframe fall flag, cleared by software by writing 0 Txframe rise flag, cleared by software by writing 0 Txframe fall flag, cleared by software by writing 0 11:10 Reserved Must be kept at reset value. Level of rxframe signal Level of txframe signal RFRIE Rxframe rise interrupt enable...
Page 732 GD32A508xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:9 ADDM[6:0] Defines which bits of register ADDRESS[7:1] are compared with an incoming address byte, and which bits are ignored. Any bit set to 1 in ADDM[6:0] enables comparisons with the corresponding bit in ADDRESS[7:1].
Page 733 GD32A508xx User Manual 0: interrupt disable 1: interrupt enable STLOIE Interrupt enable for start lost 0: interrupt disable 1: interrupt enable Reserved Must be kept at reset value. STPSEND Stop condition sent out in master mode This bit is set by hardware and cleared by software write 0 0: No STOP condition sent 1: STOP condition sent STLO...
Page 734 GD32A508xx User Manual STOPFC STOPF status clear When SRCEN bit is set to 1, software can clear the STPDET bit of I2C_STAT0 by writing 1 to this bit ADD10SENDC ADD10SEND status clear When SRCEN bit is set to 1, software can clear the ADD10SEND bit of I2C_STAT0 by writing 1 to this bit BTCC BTC status clear...
Page 735: Inter-Integrated Circuit Interface (I2Cx, X=2)
GD32A508xx User Manual Inter-integrated circuit interface (I2Cx, x=2) 21.2. Overview 21.2.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 736: Table 21-4. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32A508xx User Manual PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter Control Registers SMBA Timing and Control Logic Status Flags...
Page 737: Figure 21-15. Data Validation
GD32A508xx User Manual with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 160ns. Digital filter delay is DNF[3:0]×t I2CCLK The period of PCLK clock t match the conditions as follows:...
Page 738: Figure 21-17. I2C Communication Flow With 10-Bit Address (Master Transmit)
GD32A508xx User Manual START STOP Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. It operates in slave mode by default. When it generates a START signal, the interface automatically switches from slave to master.
Page 739: Figure 21-19. I2C Communication Flow With 7-Bit Address (Master Receive)
GD32A508xx User Manual Figure 21-19. I2C communication flow with 7-bit address (Master Receive) In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent. When HEAD10R=0, the complete 10 bit address read sequence must be excuted with START + header of 10-bit address in write direction + slave address byte 2 + RESTART + header of 10-bit address in read direction, as is shown in...
Page 740: Noise Filter
GD32A508xx User Manual Noise filter Analog noise filter and digital noise filter are integrated in I2C peripherals, the noise filters can be configured before the I2C peripheral is enabled according to the actual requirements. The analog noise filter is disabled by setting the ANOFF bit in I2C_CTL0 register and enabled when ANOFF is 0.
Page 741: Table 21-5. Data Setup Time And Data Hold Time
GD32A508xx User Manual SCLDELY SCL stretched low by the I2C SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t =SDADELY*t where t = ( PSC+1 ) *t SDADELY I2CCLK I2CCLK effects...
Page 742: Data Transfer
GD32A508xx User Manual Standard Fast mode Fast mode SMBus Symbol Parameter mode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000 1000 SCL and SDA falling time of SCL and SDA I2C reset A software reset can be performed by clearing the I2CEN bit in the I2C_CTL0 register.
Page 743: Figure 21-25. Data Reception
GD32A508xx User Manual SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA  Data Reception When receiving data, the data will be received in the shift register first. If RBNE is 0, the data in the shift register will move into I2C_RDATA register. If RBNE is 1, the SCL line wii be stretched until the previous received data in I2C_RDATA is read.
Page 744 GD32A508xx User Manual The number of bytes to be transferred is configured by BYTENUM[7:0] in I2C_CTL1 register. If BYTENUM is greater than 255, or in slave byte control mode, the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register. In reload mode, when BYTENUM counts to 0, the TCR bit will be set, and an interrupt will be generated if TCIE is set.
Page 745 GD32A508xx User Manual before the new data is written to the I2C_TDATA register after the previous data transmission is completed. In slave receiving mode, a new reception is completed but the data in I2C_RDATA  register has not been read. ...
Page 746: Figure 21-26. I2C Initialization In Slave Mode
GD32A508xx User Manual Figure 21-26. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1 Clear ADDRESSEN in I2C_SADDR0 Clear ADDRESS2EN in I2C_SADDR1 Configure ADDRESS[9:0], ADDFORMAT and ADDRESSEN in I2C_SADDR0, ADDRESS2[7:1], ADDMSK2[2:0] and ADDRESS2EN in I2C_SADDR1, ADDM[6:0] in I2C_CTL2...
Page 747: Figure 21-27. Programming Model For Slave Transmitting When Ss=0
GD32A508xx User Manual When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set. In this case, the data in I2C_TDATA register can not be flushed in ADDSEND interrupt service routine. So the first byte to be sent must be programmed in the I2C_TDATA register previously. ...
Page 748: Figure 21-29. Programming Model For Slave Receiving
GD32A508xx User Manual I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND Slave sends DATA(1) Write DATA(2) to I2C_TDATA Master sends Acknowledge Set TI...
Page 749: I2C Master Mode
GD32A508xx User Manual I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1) Slave sends Acknowledge Set RBNE...
Page 750: Figure 21-30. I2C Initialization In Master Mode
GD32A508xx User Manual sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register. If the number of bytes to be transferred is equal to or greater than 255, BYTENUM[7:0] should be configured as 0xFF.
Page 751: Figure 21-31. Programming Model For Master Transmitting (N<=255)
GD32A508xx User Manual is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signal by setting the STOP bit in the I2C_CTL1 register. Or generate a RESTART signal to start a new transfer. The TC bit is cleared when the START / STOP bit is set.
Page 752: Figure 21-33. Programming Model For Master Receiving (N<=255)
GD32A508xx User Manual I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave Write DATA(2) to I2C_TDATA Master sends DATA(1)
Page 753: Figure 21-34. Programming Model For Master Receiving (N>255)
GD32A508xx User Manual I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission） Set RBNE Read DATA(x) Slave sends DATA(N-1) Set RBNE Master sends Acknowledge...
Page 754 GD32A508xx User Manual I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission） Set RBNE Read DATA(x) Slave sends DATA(254) Set RBNE...
Page 755 GD32A508xx User Manual The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’ and used immediately, without restarting the system.
Page 756 GD32A508xx User Manual interval described in the bus idle detection section, the TIMEOUT bit in the I2C_STAT register will be set.  Packet error checking There is a CRC-8 calculator in I2C block to perform Packet Error Checking for I2C data. A PEC (packet error code) byte is appended at the end of each transfer.
Page 757: Figure 21-35. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32A508xx User Manual The SMBus receiver must be able to NACK each command or data it receives. For ACK control in slave mode, slave byte control mode can be enabled by setting SBCTL bit in I2C_CTL0 register. SMBus-specific addresses should be enabled when needed. The SMBus Device Default address (0b1100 001) is enabled by setting the SMBDAEN bit in the I2C_CTL0 register.
Page 758: Figure 21-36. Smbus Master Receiver And Slave Transmitter Communication Flow
GD32A508xx User Manual  If the SMBus master is required to receive PEC at the end of bytes transfer, automatic end mode can be enabled. Before sending a START signal on the bus, PECTRANS bit must be set and slave addresses must be programmed. After receiving BYTENUM-1 data, the next received byte will be compared with the data in the I2C_PEC register automatically.
Page 759: Table 21-7. I2C Error Flags
GD32A508xx User Manual Use DMA for data transfer As is shown in I2C slave mode and I2C master mode, each time TI or RBNE is asserted, software should write or read a byte, this may cause CPU’s high overload. The DMA controller can be used to process TI and RBNE flag: each time TI or RBNE is asserted, DMA controller does a read or write operation automatically.
Page 760 GD32A508xx User Manual I2C debug mode When the microcontroller enters the debug mode (Cortex®-M33 core halted), the SMBus timeout either continues to work normally or stops, depending on the I2Cx_HOLD configuration bits in the DBG module.
Page 761: Register Definition
GD32A508xx User Manual Register definition 21.2.4. I2C2 base address: 0x4000 C000 Control register 0 (I2C_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SMBALT SMBDAE SMBHAE Reserved PECEN GCEN WUEN SBCTL STPDETI DENR DENT Reserved...
Page 762 GD32A508xx User Manual 1 mode and Deep-sleep 2 mode. 0: Wakeup from power saving mode disable. 1: Wakeup from power saving mode enable. Note: WUEN can be set only when DNF[3:0] = 0000 Whether to stretch SCL low when data is not ready in slave mode. This bit is set and cleared by software.
Page 763 GD32A508xx User Manual 0: Stop detection (STPDET) interrupt is disabled 1: Stop detection (STPDET) interrupt is enabled NACKIE NACK received interrupt enable 0: NACK received interrupt is disabled 1: NACK received interrupt is enabled ADDMIE Address match interrupt enable in slave mode 0: Address matchinterrupt is disabled 1: Address matchnterrupt is enabled RBNEIE...
Page 764 GD32A508xx User Manual 1: Transfer PEC Note: This bit has no effect when RELOAD=1, or SBCTL=0 in slave mode. AUTOEND Automatic end mode in master mode 0: TC bit is set when the transfer of BYTENUM[7:0] bytes is completed. 1: a STOP signal is sent automatically when the transfer of BYTENUM[7:0] bytes is completed.
Page 765 GD32A508xx User Manual 1: The 10 bit master receive address sequence is RESTART + header of 10-bit address (read). Note: When the START bit is set, this bit can not be changed. ADD10EN 10-bit addressing mode enable in master mode 0: 7-bit addressing in master mode 1: 10-bit addressing in master mode Note: When the START bit is set, this bit can not be modified.
Page 766 GD32A508xx User Manual 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address 1: 10-bit address Note: When ADDRESSEN is set, this bit should not be written. ADDRESS[9:8] Highest two bits of a 10-bit address Note: When ADDRESSEN is set, this bit should not be written.
Page 767 GD32A508xx User Manual except the reserved address (0b0000xxx and 0b1111xxx). Note: When ADDRESS2EN is set, these bits should not be written. If ADDMSK2 is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if all the bits are matched. ADDRESS2[7:1] Second I2C address for the slave Note: When ADDRESS2EN is set, these bits should not be written.
Page 768 GD32A508xx User Manual Note: These bits can only be used in master mode. SCLL[7:0] SCL low period SCL low period can be generated by configuring these bits. =(SCLL+1)*t SCLL Note: These bits can only be used in master mode. Timeout register (I2C_TIMEOUT) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 769 GD32A508xx User Manual 1: BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle Note: This bit can be written only when TOEN =0. 11:0 BUSTOA[11:0] Bus timeout A When TOIDLE = 0, t =(BUSTOA+1)*2048*t TIMEOUT I2CCLK...
Page 770 GD32A508xx User Manual 0: SMBALERT event is not detected on SMBA pin 1: SMBALERT event is detected on SMBA pin TIMEOUT TIMEOUT flag. When a timeout or extended clock timeout occurred, this bit will be set. It is cleared by software by setting the TIMEOUTC bit and cleared by hardware when I2CEN=0. 0: no timeout or extended clock timeout occur 1: a timeout or extended clock timeout occur PECERR...
Page 771 GD32A508xx User Manual bit or STOP bit is set. 0: Transfer of BYTENUM[7:0] bytes is not completed 1: Transfer of BYTENUM[7:0] bytes is completed STPDET STOP signal detected in slave mode This flag is set by hardware when a STOP signal is detected on the bus. It is cleared by software by setting STPDETC bit and cleared by hardware when I2CEN=0.
Page 772 GD32A508xx User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMBALT TIMEOUT PECERR LOSTAR STPDET ADDSEN Reserved OUERRC BERRC Reserved NACKC Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. SMBALTC SMBus alert flag clear.
Page 773 GD32A508xx User Manual This register has to be accessed by word (32-bit). Reserved Reserved PECV[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. PECV[7:0] Packet Error Checking Value that calculated by hardware when PEC is enabled. PECV is cleared by hardware when I2CEN = 0. Receive data register (I2C_RDATA) Address offset: 0x24 Reset value: 0x0000 0000...
Page 774 GD32A508xx User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value...
Page 775: Serial Peripheral Interface/Inter-Ic Sound (Spi/I2S)
GD32A508xx User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 22.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 776: Spi Block Diagram
GD32A508xx User Manual  Master clock (MCK) can be output.  Transmission and reception using DMA. SPI function overview 22.3. SPI block diagram 22.3.1. Figure 22-1. Block diagram of SPI SYSCLK Clock Generator Control Registers TxRx Control Logic MOSI TX Buffer MISO Shift Register RX Buffer...
Page 777: Quad-Spi Configuration
GD32A508xx User Manual Pin name Direction Description output, suitable for single master application; when NSSDRV=0, it is NSS input, suitable for multi-master application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 778: Figure 22-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32A508xx User Manual sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[2] D[4] D[0] D[1] D[5] D[6] D[7] LF=1 FF16=0 MISO D[2] D[6] D[1] D[5] D[7] D[0] D[3] D[4] In SPI normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. Data length is 16 bits if FF16=1, otherwise is 8 bits.
Page 779: Table 22-3. Nss Function In Slave Mode
GD32A508xx User Manual When slave mode is configured (MSTMOD=0), SPI gets NSS level from NSS pin in hardware NSS mode (SWNSSEN = 0) or from SWNSS bit in software NSS mode (SWNSSEN = 1) and transmits/receives data only when NSS level is low. In software NSS mode, NSS pin is not used.
Page 780: Table 22-5. Spi Operation Modes
GD32A508xx User Manual Mode Register configuration Description NSSDRV: Don’t care configuration error will occur and the CONFERR bit will be 1. MSTMOD = 1 SWNSSEN = 1 The slave can use hardware or SWNSS = 1 software NSS mode. NSSDRV: Don’t care SPI operation modes 22.3.5.
Page 781: Figure 22-4. A Typical Full-Duplex Connection
GD32A508xx User Manual Mode Description Register configuration Data pin usage BDOEN: Don’t care MSTMOD = 0 Slave transmission with RO = 0 MOSI: not used bidirectional connection BDEN = 1 MISO: transmission BDOEN = 1 MSTMOD = 0 Slave reception with RO = 0 MOSI: not used bidirectional connection...
Page 782: Figure 22-7. A Typical Bidirectional Connection
GD32A508xx User Manual Figure 22-7. A typical bidirectional connection Initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 783: Figure 22-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32A508xx User Manual In master mode, software should write the next data into SPI_DATA register before the transmission of current data frame is completed if it desires to generate continuous transmission. Reception sequence After the last valid sample clock, the incoming data will be moved from shift register to the reception buffer and RBNE will be set.
Page 784: Figure 22-10. Timing Diagram Of Ti Slave Mode
GD32A508xx User Manual sample MOSI D[7] D[1] D[0] D[7] D[2] D[6] D[5] D[4] D[3] D[2] D[6] D[5] D[4] D[3] D[1] D[0] D[1] D[0] MISO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] D[7] D[6] D[5] D[4] D[3] D[2] In master TI mode, SPI can perform continuous or non-continuous transfer. If the master writes SPI_DATA register fast enough, the transfer is continuous, otherwise non-continuous.
Page 785: Figure 22-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32A508xx User Manual frame format should follow the normal SPI protocol, select the first clock transition as the data capture edge. In summary, MSTMOD = 1, NSSP = 1, CKPH = 0. When NSS pulse mode is enabled, a pulse duration of at least 1 SCK clock period is inserted between two successive data frames depending on the status of internal data transmission buffer.
Page 786: Figure 22-12. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32A508xx User Manual Figure 22-12. Timing diagram of write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D1[7] D0[7] D0[3] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 787: Nss Pulse Mode
GD32A508xx User Manual Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[0] D1[4] D0[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D1[6] D0[6] D0[2] D1[2] D0[7] D0[3] D1[7] D1[3] SPI disabling sequence Different sequences are used to disable the SPI in different operation modes. MFD SFD wait for the last RBNE flag and then receive the last data.
Page 788: Crc Function
GD32A508xx User Manual DMA function 22.3.6. The DMA frees the application from data writing and reading process during transfer, to improve the system efficiency. DMA function in SPI is enabled by setting DMATEN and DMAREN bits in SPI_CTL1 register. To use DMA function, application should first configure DMA modules correctly, then configure SPI module according to the initialization sequence, at last enable SPI.
Page 789: Table 22-6. Spi Interrupt Requests
GD32A508xx User Manual  Reception buffer not empty flag (RBNE) This bit is set when reception buffer is not empty, which means that one data is received and stored in the reception buffer, and software can read the data by reading the SPI_DATA register.
Page 790: I2S Block Diagram
GD32A508xx User Manual Interrupt Flag Description Clear method enable bit Read SPI_DATA register, then read RXORERR Rx overrun error SPI_STAT register. CRCERR CRC error Write 0 to CRCERR bit FERR TI mode format error Write 0 to FERR bit I2S function overview 22.4.
Page 791: Figure 22-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32A508xx User Manual I2S audio standards 22.4.3. The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time-multiplexed on two channels (the left channel and the right channel).
Page 792: Figure 22-17. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32A508xx User Manual Figure 22-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 22-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 793: Figure 22-22. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32A508xx User Manual frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD Figure 22-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation...
Page 794: Figure 22-27. Msb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32A508xx User Manual frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 22-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 22-28.
Page 795: Figure 22-32. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32A508xx User Manual frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 8-bit 0 24-bit data I2S_SD Figure 22-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 8-bit 0 24-bit data I2S_SD When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or...
Page 796: Figure 22-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32A508xx User Manual configurable using the PCMSMOD bit in the SPI_I2SCTL register. The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard. The timing diagrams for each configuration of the short frame synchronization mode are shown below. Figure 22-35.
Page 797: Figure22-40. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32A508xx User Manual Figure22-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 22-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 22-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 16-bit data...
Page 798: Figure 22-46. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32A508xx User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure 22-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 32 bits I2S_SD Figure 22-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2...
Page 799: Figure 22-51. Block Diagram Of I2S Clock Generator
GD32A508xx User Manual I2S clock 22.4.4. Figure 22-51. Block diagram of I2S clock generator 8-bit I2SCLK Configurable I2S_MCK MCKOEN Divider MCKOEN DIV4 CHLEN Frequency dividing ratio = DIV * 2 + OF I2S_CK DIV2 The block diagram of I2S clock generator is shown as Figure 22-51.
Page 800: Operation Modes
GD32A508xx User Manual Operation 22.4.5. Operation modes The operation mode is selected by the I2SOPMOD[1:0] bits in the SPI_I2SCTL register. There are four available operation modes, including master transmission mode, master reception mode, slave transmission mode, and slave reception mode. The direction of I2S interface signals for each operation mode is shown in the Table 22-9.
Page 801 GD32A508xx User Manual Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD bit to select I2S standard...
Page 802: Figure 22-53. I2S Master Reception Disabling Sequence
GD32A508xx User Manual transmission buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins. The data is parallel loaded into the 16-bit shift register, and shifted out serially to the I2S_SD pin, MSB first. The next data should be written to the SPI_DATA register, when the TBE flag is high.
Page 803 GD32A508xx User Manual Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTD ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle Wait one I2S clock cycle...
Page 804 GD32A508xx User Manual between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication. The reception sequence begins when the external master sends the clock and when the I2S_WS signal indicates a start of the data transfer. In slave mode, I2SCH is sensitive to the I2S_WS signal coming from the external master.
Page 805: Error Conditions
GD32A508xx User Manual  Reception buffer not empty flag (RBNE) This bit is set when reception buffer is not empty, which means that one data is received and stored in the reception buffer, and software can read the data by reading the SPI_DATA register.
Page 806: Register Definition
GD32A508xx User Manual Register definition 22.5. SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 I2S1_ADD base address: 0x4000 3400 I2S2_ADD base address: 0x4000 4000 Control register 0 (SPI_CTL0) 22.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 807 GD32A508xx User Manual CRCNT CRC next transfer 0: Next transfer is data 1: Next transfer is CRC value When the transfer is managed by DMA, CRC value is transferred by hardware. This bit should be cleared. In full-duplex or transmit-only mode, set this bit after the last data is written to SPI_DATA register.
Page 808 GD32A508xx User Manual PCLK means PCLK2 when using SPI0. PCLK means PCLK1 when using SPI1 and SPI2. MSTMOD Master mode enable 0: Slave mode 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle. 1: CLK pin is pulled high when SPI is idle.
Page 809 GD32A508xx User Manual 1: Enable SPI TI mode NSSP SPI NSS pulse mode enable. 0: Disable SPI NSS pulse mode 1: Enable SPI NSS pulse mode NSSDRV Drive NSS output 0: Disable master NSS output 1: Enable master NSS output DMATEN Transmit buffer DMA enable 0: Disable transmit buffer DMA...
Page 810 GD32A508xx User Manual TRANS Transmitting ongoing bit 0: SPI or I2S is idle. 1: SPI or I2S is currently transmitting and/or receiving a frame. This bit is set and cleared by hardware. RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs.
Page 811 GD32A508xx User Manual Data register (SPI_DATA) 22.5.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register.
Page 812 GD32A508xx User Manual default value is 0007h. RX CRC register (SPI_RCRC) 22.5.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 813 GD32A508xx User Manual 31:16 Reserved Must be kept at reset value. 15:0 TCRC[15:0] TX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the transmitted bytes and saves them in TCRC register.If the data frame format is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value in TCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC[15:0].
Page 814 GD32A508xx User Manual 11: Master reception mode This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. PCMSMOD PCM frame synchronization mode 0: Short frame synchronization 1: long frame synchronization This bit has a meaning only when PCM standard is used. This bit should be configured when I2S mode is disabled.
Page 815 GD32A508xx User Manual This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved Reserved MCKOEN DIV[7:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: Disable I2S_MCK output 1: Enable I2S_MCK output This bit should be configured when I2S mode is disabled.
Page 816 GD32A508xx User Manual IO23_DRV Drive IO2 and IO3 enable 0: IO2 and IO3 are not driven in single wire mode. 1: IO2 and IO3 are driven to high in single wire mode. This bit is only available in SPI0. Quad-SPI mode read select. 0: SPI is in quad wire write mode.
Page 817: Table 23-1. Sqpi Controller Mode Definition
GD32A508xx User Manual Serial/Quad Parallel Interface (SQPI) Overview 23.1. Serial/Quad Parallel Interface (SQPI) is a controller for external serial/dual/quad parallel interface memory peripheral. For example: SQPI-PSRAM and SQPI-FLASH. With this controller, users can use external SQPI interface memory as SRAM simply. Characteristics 23.2.
Page 818: Function Overview
GD32A508xx User Manual SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Address Phase SQPI_D0 Output SQPI_D1 Output SQPI_D2 Output SQPI_D3 Output Waitcycle Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout Data Phase SQPI_D0 Inout SQPI_D1 Inout SQPI_D2 Inout SQPI_D3 Inout Note: O –...
Page 819: Figure 23-2. Sqpi_Sc Example
GD32A508xx User Manual SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Command Phase Address Phase Waitcycle Phase Data Phase Sample Time (SQPI_PL=0) Sample Time (SQPI_PL=1) SQPI controller special command 23.3.2. SQPI controller special command (SQPI_SC) function can send only command phase with no address, waitcycle, and data phase.
Page 820: Figure 23-3. Sqpi_Rdid Example (Sqpi_Idlen=00)
GD32A508xx User Manual you should set SQPI_IDLEN bit to 0x00(64bit,this is default), then set the SQPI_RDID bit to 1 and wait it cleared by hardware through polling this bit, and at last read the SQPI_IDL and SQPI_IDH registers. This command is performed in SSS mode by hardware. Figure 23-3.
Page 821: Figure 23-5. Sqpi Sss Mode Timing (Spi)
GD32A508xx User Manual SQPI_RID bit to 1 and wait it reset to 0. The third, user can get ID value by read SQPI_IDL and SQPI_IDH registers. Read/Write operation flow 23.3.7. Six modes of memory access are possible. Access mode should be configured before read/write operations.
Page 822: Figure 23-8. Sqpi Qqq Mode Timing (Qpi)
GD32A508xx User Manual SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase Data Phase Figure 23-8. SQPI QQQ Mode Timing (QPI) SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Byte1 Command Phase Address Phase Waitcycle Phase Data Phase Figure 23-9.
Page 823: Register Definition
GD32A508xx User Manual SQPI_CLK SQPI_CSN SQPI_D0 SQPI_D1 SQPI_D2 SQPI_D3 Byte0 Command Phase Address Phase Waitcycle Phase Data Phase Register definition 23.4. SQPI start address: 0xA000 1000 SQPI Initial Register (SQPI_INIT) 23.4.1. Address offset: 0x00 Reset Value: 0x1805 0000 This register has to be accessed by word (32-bit). SQPI_PL SQPI_IDLEN[1:0] SQPI_ADDRBIT[4:0]...
Page 824 GD32A508xx User Manual Output clock frequency is f /(SQPI_CLKDIV+1) hclk Note: When SQPI_CLKDIV field is even number, the output clock high level time has 1 HCLK period more than low level time. 17:16 SQPI_CMDBIT[1:0] Bit number of SQPI controller command phase 00: 4 bit 01: 8 bit (default) 10: 16 bit...
Page 825 GD32A508xx User Manual Note: Before write 1 to SQPI_RID bit, you must ensure it is cleared and after set SQPI_RID to 1, you must wait SQPI_RID cleared. SQPI Write Command Register (SQPI_WCMD) 23.4.3. Address offset: 0x08 Reset value: 0x0010 0000 This register has to be accessed by word (32-bit).
Page 826 GD32A508xx User Manual SQPI_IDL [15:0] Bits Fields Descriptions 31:0 SQPI_IDL[31:0] ID Low Data saved for SQPI Read ID Command SQPI_IDL[15:0] is valid when SQPI_IDLEN=10 SQPI_IDL[7:0] is valid when SQPI_IDLEN=11. SQPI ID High Register (SQPI_IDH) 23.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 827: Figure 24-1. The Exmc Block Diagram
GD32A508xx User Manual External memory controller (EXMC) Overview 24.1. The external memory controller EXMC, is used as a translator for MCU to access a variety of external memory. By configuring the related registers, it can automatically convert AMBA memory access protocol into a specific memory access protocol, such as SRAM, ROM, NOR Flash, NAND Flash and PC Card.
Page 828: External Device Address Mapping
GD32A508xx User Manual AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NAND-Flash/PC Card NOR-Flash/PSRAM Controller Controller NOR/PSRAM Shared PSRAM NAND NOR/PSRAM PC Card /NAND Pins Pins Pins Pins Pins Shared Pins Basic regulation of EXMC access 24.3.2.
Page 829: Nor/Psram Address Mapping
GD32A508xx User Manual EXMC access space is divided into multiple banks. Each bank is 256 Mbytes. The first bank (Bank0) is further divided into four regions, and each region is 64 Mbytes. Bankx(x=1, 2) is divided into two spaces, the attribute memory space and the common memory space. Bank3 is divided into three spaces, which are the attribute memory space, the common memory space and the I/O memory space.
Page 830: Figure 24-4. Nand/Pc Card Address Mapping
GD32A508xx User Manual Supported memory HADDR[27:26] Address Regions type 0x6000 0000 Region0 NOR/PSRAM 0x63FF FFFF 0x6400 0000 Region1 NOR/PSRAM 0x67FF FFFF 0x6800 0000 Region2 NOR/PSRAM 0x6BFF FFFF 0x6C00 0000 Region3 NOR/PSRAM 0x6FFF FFFF HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency.
Page 831: Figure 24-5. Diagram Of Bank1 Common Space
GD32A508xx User Manual EXMC Memory Address Memory Space Bank 0x7000 0000 Common Memory Space 0x73FF FFFF Bank1 0x7800 0000 Attribute Memory Space 0x7BFF FFFF 0x8000 0000 Common Memory Space 0x83FF FFFF Bank2 0x8800 0000 Attribute Memory Space 0x8BFF FFFF 0x9000 0000 Common Memory Space 0x93FF FFFF...
Page 832: Table 24-1. Nor Flash Interface Signals Description
GD32A508xx User Manual – When HADDR [17:16] = 01, the command area is selected. – When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as follows. –...
Page 833: Table 24-2. Psram Non-Muxed Signal Description
GD32A508xx User Manual EXMC Pin Direction Mode Functional description (non-muxed) Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal EXMC_NL(NADV) Output Async/Sync Address valid Table 24-2. PSRAM non-muxed signal description EXMC Pin Direction Mode...
Page 834: Table 24-4. Nor / Psram Controller Timing Parameters
GD32A508xx User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Async Async Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync Split into 2 EXMC Sync accesses Async Async...
Page 835: Figure 24-6. Mode 1 Read Access
GD32A508xx User Manual Parameter Function Access mode Unit AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 24-5. EXMC_timing models Timing Extend Write timing Read timing Mode description model mode parameter parameter DSET DSET Mode 1 SRAM/PSRAM/CRAM ASET ASET...
Page 836: Figure 24-7. Mode 1 Write Access
GD32A508xx User Manual Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK) Figure 24-7. Mode 1 write access Address (EXMC_A[25:0]) Chip Enable...
Page 837: Figure 24-8. Mode A Read Access
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 0x0000 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge...
Page 838: Table 24-7. Mode A Related Registers Configuration
GD32A508xx User Manual Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The difference between mode A and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode A write timing configuration is independent of its read configuration.
Page 839: Figure 24-10. Mode 2/B Read Access
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30 Reserved 29-28 WASYNCMOD 27-20 Reserved 0x00 Time between EXMC_NE[x] rising edge to 19-16 WBUSLAT EXMC_NE[x] falling edge...
Page 840: Figure 24-12. Mode B Write Access
GD32A508xx User Manual Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET+1 HCLK) (DSET HCLK) Figure 24-12. Mode B write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx)
Page 841: Figure 24-13. Mode C Read Access
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value NRTP 0x2, NOR Flash NRMUX NRBKEN EXMC_SNTCFGx(Read and write in mode 2,read in mode B) 31-30 Reserved 0x0000 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT...
Page 842: Table 24-9. Mode C Related Registers Configuration
GD32A508xx User Manual Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The differences between mode C and mode 1 write timing are that read/write timing is specified by the same set of timing configuration, while mode C write timing configuration is independent of its read configuration, and the toggle of NOE and NADV are different.
Page 843: Mode D - Asynchronous Access With Extended Address
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode C:0x2 27-20 Reserved 0x00 Time between EXMC_NE[x] rising edge to 19-16 WBUSLAT EXMC_NE[x] falling edge...
Page 844: Table 24-10. Mode D Related Registers Configuration
GD32A508xx User Manual Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WAHLD+1 HCLK) (WDSET HCLK) Table 24-10. Mode D related registers configuration Bit Position Bit Name Reference Setting Value...
Page 845: Figure 24-17. Multiplex Mode Read Access
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode D:0x3 27-20 Reserved 0x00 Time between EXMC_NE[x] rising edge to 19-16 WBUSLAT EXMC_NE[x] falling edge Depends on memory and user (WDSET+1HCLK 15-8 WDSET for write)
Page 846 GD32A508xx User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31-20 Reserved 0x000 SYNCWR 18-16 ASYNCWAIT Depends on memory EXMODEN NRWTEN WREN Depends on memory NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 847: Figure 24-19. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32A508xx User Manual )+4HCLK ≥(maxT (25-3) DATA_SETUP WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE Otherwise ≥ 4HCLK (25-4) DATA_SETUP Figure 24-19. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Output Enable (EXMC_NOE) Data...
Page 848 GD32A508xx User Manual 1. Data latency and NOR Flash latency Data latency is the number of EXMC_CLK cycles to wait before sampling the data. The relationship between data latency and NOR Flash specification’s latency parameter is as follows: For NOR Flash’s specification excluding the EXMC_NADV cycle, their relationship should NOR Flash latency=DLAT+2 (25-6) For NOR Flash’s specification including the EXMC_NADV cycle, their relationship should...
Page 849: Figure 24-21. Read Timing Of Synchronous Multiplexed Burst Mode
GD32A508xx User Manual 4. Mode SM - Single burst transmission For synchronous burst transmission, if the needed data of AHB is 16-bit, EXMC will perform a burst transmission whose length is 1. If the needed data of AHB is 32-bit, EXMC will make the transmission divided into two 16-bit transmissions, that is, EXMC performs a burst transmission whose length is 2.
Page 850: Figure 24-22. Write Timing Of Synchronous Multiplexed Burst Mode
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx Reserved NREN Depends on memory NRTP Depends on memory，0x1/0x2 NRMUX 0x1, Depends on memory and users NRBKEN EXMC_SNTCFGx(Read) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1, EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT...
Page 851: Table 24-14. 8-Bit Or 16-Bit Nand Interface Signal
GD32A508xx User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx SYNCWR 0x1, synchronous write enable 18-16 AYSNCWAIT EXMODEN NRWTEN Depends on memory WREN NRWTCFG 0x0(Here must be zero) WRAPEN NTWTPOL Depends on memory SBRSTEN No effect Reserved NREN Depends on memory NRTP NRMUX 0x1, Depends on users...
Page 852: Table 24-15. 16-Bit Pc Card Interface Signal
GD32A508xx User Manual EXMC Pin Direction Functional description EXMC_D[15:0] 16-bit multiplexed, bidirectional address/data bus EXMC_NCE[x] Output Chip select, x = 1, 2 EXMC_NOE(NRE) Output Output enable EXMC_NWE Output Write enable EXMC_NWAIT/ Input NAND Flash ready/busy input signal to the EXMC, x=1, 2 EXMC_INT[x] Table 24-15.
Page 853: Figure 24-23. Access Timing Of Common Memory Space Of Pc Card Controller
GD32A508xx User Manual NAND Flash or PC Card controller timing EXMC can generate the appropriate signal timing for NAND Flash, PC Cards and other devices. Each bank has a corresponding register to manage and control the external memory, such as EXMC_NPCTLx, EXMC_NPINTENx, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 and EXMC_NECCx.
Page 854: Nand Flash Pre-Wait Functionality
GD32A508xx User Manual NAND Flash operation When EXMC sends command or address to NAND Flash, it needs to use the command latch signal (EXMC_A[16]) or address latch signal (EXMC_A[17]), namely, the CPU needs to perform write operation in particular address. Example: NAND Flash read operation steps: Configure EXMC_NPCTLx and EXMC_NPCTCFGx register.
Page 855 GD32A508xx User Manual Write CMD0 into NAND Flash bank common space command area. Write ADD0 into NAND Flash bank common space address area. Write ADD1 into NAND Flash bank common space address area. Write ADD2 into NAND Flash bank common space address area. Write ADD3 into NAND Flash bank common space address area.
Page 856 GD32A508xx User Manual during common space access. Attribute space: EXMC_NCE3_x (x = 0, 1) is the chip enable signal, it indicates whether 8- or 16-bit access operation is being performed. EXMC_NWE and EXMC_NOE dictates whether the on-going operation is a write or read operation, and EXMC_NREG is low during attribute space access.
Page 857: Nor/Psram Controller Registers
GD32A508xx User Manual Registers definition 24.4. EXMC base address: 0xA000 0000 NOR/PSRAM controller registers 24.4.1. SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DX This register has to be accessed by word (32-bit) SYNCWR CPS[2:0]...
Page 858 GD32A508xx User Manual insertion via the NWAIT signal: 0: Disable NWAIT signal 1: Enable NWAIT signal WREN Write enable 0: Disabled write in the bank by the EXMC, otherwise an AHB error is reported 1: Enabled write in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state...
Page 859 GD32A508xx User Manual SRAM/NOR Flash timing configuration registers (EXMC_SNTCFGx) (x=0, 1, 2, Address offset: 0x04 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0FFF FFFF This register has to be accessed by word(32-bit) Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0]...
Page 860 GD32A508xx User Manual This field is meaningful only in asynchronous access. 0x00: Reserved 0x01: Data setup time = 2 * HCLK period …… 0xFF: Data setup time = 256 * HCLK period AHLD[3:0] Address hold time This field is used to set the time of address hold phase, which only used in mode D and multiplexed mode.
Page 861: Nand Flash/Pc Card Controller Registers
GD32A508xx User Manual 11: Mode D access 27:20 Reserved Must be kept at reset value. 19:16 WBUSLAT[3:0] Bus latency Bus latency added at the end of each write transaction to match with the minimum time between consecutive transactions. 0x0: Bus latency = 1 * HCLK period 0x1: Bus latency = 2 * HCLK period ……...
Page 862 GD32A508xx User Manual ATR[2:0] CTR[3:0] Reserved ECCEN NDW[1:0] NDTP NDBKEN NDWTEN Reserved Bits Fields Description 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0]...
Page 863 GD32A508xx User Manual 0: Disable wait function 1: Enable wait function Reserved Must be kept at reset value. NAND Flash/PC Card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0046 (for bank1 and bank2), 0x0000 0040 (for bank3) This register has to be accessed by word (32-bit) In addition to interrupt controlling bits, this register also contains a FIFO empty status bit,...
Page 864 GD32A508xx User Manual 0: Not detect interrupt high-level 1: Detect interrupt high-level INTRS Interrupt rising edge status 0: Not detect interrupt rising edge 1: Detect interrupt rising edge NAND Flash/PC Card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFCFC FCFC This register has to be accessed by word(32-bit)
Page 865 GD32A508xx User Manual …… 0xFE: COMWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: Reserved COMSET[7:0] Common memory setup time Define the time to build address before sending command 0x00: COMSET = 1 * HCLK …… 0xFE: COMSET = 255 * HCLK 0xFF: Reserved NAND Flash/PC Card attribute space timing configuration registers (EXMC_NPATCFGx) (x=1, 2, 3)
Page 866 GD32A508xx User Manual 15:8 ATTWAIT[7:0] Attribute memory wait time Define the minimum time to maintain command 0x00: Reserved 0x01: ATTWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: ATTWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: Reserved ATTSET[7:0] Attribute memory setup time Define the time to build address before sending command 0x00: ATTSET = 1 * HCLK...
Page 867 GD32A508xx User Manual 0x00: Reserved 0x01: IOWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFF: IOWAIT = 256 * HCLK (+NWAIT active cycles) IOSET[7:0] IO space setup time Define the time to build address before sending command 0x00: IOSET = 1 * HCLK ……...
Page 868: Controller Area Network (Can)
GD32A508xx User Manual Controller area network (CAN) Overview 25.1. CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The CAN network interfaces of the GD32A508xx series supports the CAN protocol 2.0A and B,the ISO11898-1:2015 and BOSCH CAN-FD specifications.The CAN interface automatically handles the transmission and the reception of CAN frames.
Page 869: Function Overview
GD32A508xx User Manual  16-bit free timer  Time stamp on SOF reception  Time stamp sent in last two data bytes Function overview 25.3. Figure 25-1. CAN module block diagram shows the CAN block diagram. Figure 25-1. CAN module block diagram CAN0 Transmit Receive...
Page 870: Communication Modes
GD32A508xx User Manual Initial working mode When the configuration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set.
Page 871: Data Transmission
GD32A508xx User Manual Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave. Loopback communication mode is useful for self-test. Loopback and silent communication mode Loopback and silent communication mode means the RX and TX pins are disconnected from the CAN network while the transmitted messages are transferred into the Rx FIFOs.
Page 872: Figure 25-3. State Of Transmit Mailbox
GD32A508xx User Manual Transmit mailbox state A transmit mailbox can be used when it is free (empty state). If the mailbox is filled with data, set TEN bit in CAN_TMIx register to prepare for starting the transmission (pending state). If more than one mailbox is in the pending state, they need scheduling the transmission (scheduled state).
Page 873: Data Reception
GD32A508xx User Manual done immediately. In the transmit state, the abort of transmission does not take effect immediately until the transmission is finished. In case that the transmission is successful, the MTFNERR and MTF in CAN_TSTAT are set and state changes to be empty. In case that the transmission is failed, the state changes to be scheduled and then the abort of transmission can be done immediately.
Page 874 GD32A508xx User Manual Rx FIFO has three mailboxes. The reception frames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of frames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
Page 875: Figure 25-5. 32-Bit Filter
GD32A508xx User Manual Figure 25-5. 32-bit filter. 32-bit: SFID[10:0], EFID[17:0], FF and FT bits. As is shown in Figure 25-5. 32-bit filter Figure 25-6. 16-bit filter. 16-bit: SFID [10:0], FT, FF and EFID[17:15] bits. As is shown in Figure 25-6. 16-bit filter Mask mode For the Identifier of a data frame to be filtered, the mask mode is used to specify which bits must be the same as the preset Identifier and which bits need not be judged.
Page 876: Table 25-1. 32-Bit Filter Number
GD32A508xx User Manual Filter number Filter consists of some filter bank. According to the mode and the scale of each of the filter banks, filter has different effects. For example, there are two filter banks. Bank0 is configured as 32-bit mask mode. Bank1 is Table 25-1.
Page 877 GD32A508xx User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank nunber bank nunber F3DATA1[15:0]-16bits- F5DATA0-32bits-ID F3DATA1[31:16]-16bits- F5DATA1-32bits-ID Mask F7DATA0[15:0]-16bits- F6DATA0[15:0]-16bits-ID F7DATA0[31:16]-16bits- F6DATA0[31:16]-16bits- F7DATA1[15:0]-16bits- F6DATA1[15:0]-16bits-ID F7DATA1[31:16]-16bits- F6DATA1[31:16]-16bits- F8DATA0[15:0]-16bits- F10DATA0[15:0]-16bits- F8DATA0[31:16]-16bits- F10DATA0[31:16]-16bits- Mask F8DATA1[15:0]-16bits- F10DATA1[15:0]-16bits- F8DATA1[31:16]-16bits- F10DATA1[31:16]-16bits- Mask F9DATA0[15:0]-16bits- F11DATA0[15:0]-16bits-ID F9DATA0[31:16]-16bits- F11DATA0[31:16]-16bits- Mask...
Page 878: Communication Parameters
GD32A508xx User Manual Time-triggered communication means that activities are triggered by the elapsing of time segments. In a time-triggered communication system, all time points of message transmission are pre-defined. In this mode, an internal 16-bit counter starts working, incrementing by 1 at each CAN bit time. This internal counter provides time stamps for sending and receiving data, stored in registers CAN _RFIFOMPx and CAN_TMPx.
Page 879: Figure 25-11. The Bit Time
GD32A508xx User Manual Bit segment 2 (BS2): It defines the location of the transmit point. It represents the Phase buffer segment 2 in the CAN standard. Its duration is programmable from 1 to 8 time quanta but it may also be automatically shortened to compensate for negative phase drifts. Figure 25-11.
Page 880 GD32A508xx User Manual frames and FD frames. Whether the current frame is FD or not could be defined by received FDF bit (the previously reserved bit in CAN frames with 11-bit identifiers or the first previously reserved bit in CAN frames with 29-bit identifiers which now is decoded as FDF bit). If FDF bit is recessive, meaning to be the CAN FD frame, otherwise FDF bit is dominant, meaning to be the classical frame.
Page 881: Figure 25-12. Transmitter Delay Measurement
GD32A508xx User Manual of CAN_FDSTAT registers. In case that there is dominant glitch, SSP position would be advanced than expected, leading to a calculated error in compensation measurement. To solve this problem, TDCF bits of CAN_FDTDC register could be used to avoid too small TDCV bits.
Page 882 GD32A508xx User Manual recover when the recovering sequence is detected. CAN interrupts 25.3.11. The CAN bus controller occupies 4 interrupt vectors, which are controlled by the register CAN_INTEN. The interrupt sources can be classified as:  Transmit interrupt  FIFO0 interrupt ...
Page 883: Table 25-3. Can Event / Interrupt Flags
GD32A508xx User Manual  Wakeup: WUIF bit in the CAN_STAT register is set and WIE bit in the CAN_INTEN register is set.  Enter sleep working mode: SLPIF bit in the CAN_STAT register is set and SLPWIE bit in the CAN_INTEN register is set. Table 25-3.
Page 884: Can Registers
GD32A508xx User Manual CAN registers 25.4. CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 CAN2 base address: 0x4000 CC00 Control register (CAN_CTL) 25.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit). Reserved SLPWMO SWRST...
Page 885 GD32A508xx User Manual If this bit is set, the CAN leaves sleep working mode when CAN bus activity is detected, and SLPWMOD bit in CAN_CTL register will be cleared automatically. 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission...
Page 886 GD32A508xx User Manual RX level LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
Page 887 GD32A508xx User Manual 1: CAN is in the state of sleep working mode Initial working state This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed.
Page 888 GD32A508xx User Manual 0: Transmit mailbox 1 not empty 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
Page 889 GD32A508xx User Manual 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when next transmit starts. MAL1 Mailbox 1 arbitration lost This bit is set when the arbitration lost occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register.
Page 890 GD32A508xx User Manual 1: Mailbox 0 transmit finished Receive message FIFO0 register (CAN_RFIFO0) 25.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved...
Page 891 GD32A508xx User Manual Reserved Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RFD1 Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. This bit is reset by hardware when the dequeuing is done.
Page 892 GD32A508xx User Manual SLPWIE Sleep working interrupt enable 0: Sleep working interrupt disabled 1: Sleep working interrupt enabled Wakeup interrupt enable 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled ERRIE Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled 14:12 Reserved Must be kept at reset value.
Page 893 GD32A508xx User Manual 1: Rx FIFO0 full interrupt enabled RFNEIE0 Rx FIFO0 not empty interrupt enable 0: Rx FIFO0 not empty interrupt disabled 1: Rx FIFO0 not empty interrupt enabled TMEIE Transmit mailbox empty interrupt enable 0: Transmit mailbox empty interrupt disabled 1: Transmit mailbox empty interrupt enabled Error register (CAN_ERR) 25.4.7.
Page 894 GD32A508xx User Manual PERR Passive error Whenever the TECNT or RECNT is greater than 127, the bit will be set by hardware. WERR Warning error Whenever the TECNT or RECNT is greater than or equal to 96, the bit will be set by hardware.
Page 895 GD32A508xx User Manual This bit can be configured only when FDEN=1 in CAN_FDCTL register. 12:10 BS1[6:4] Bits 6:4 of BS1 See bits 19:16 of CAN_BT This bit can be configured only when FDEN=1 in CAN_FDCTL register. BAUDPSC[9:0] Baud rate prescaler The CAN baud rate prescaler FD control register (CAN_FDCTL) 25.4.9.
Page 896 GD32A508xx User Manual 0: Protocol exception event detection enabled (to idle) 1: Protocol exception event detection disabled (regarded as a form error) Reserved Must be kept at reset value. FDEN FD operation enable 0: CAN FD function disabled 1: CAN FD function enabled FD status register (CAN_FDSTAT) 25.4.10.
Page 897 GD32A508xx User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. 14:8 TDCO[6:0] Transmitter delay compensation offset These bits are set to the transmitter delay compensation offset value which defines the distance between the measured delay from CANTX to CANRX and the second sample point.
Page 898 GD32A508xx User Manual The CAN baud rate prescaler Transmit mailbox identifier register (CAN_TMIx) (x = 0…2) 25.4.13. Address offset: 0x180 + 0x10 * x Reset value: 0xXXXX XXXX (bit0=0) This register has to be accessed by word(32-bit). SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions...
Page 899 GD32A508xx User Manual TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value. TSEN Time stamp enable 0: Time stamp disabled 1: Time stamp enabled. The TS[15:0] will be transmitted in the DB6 and DB7 in DL. This bit is available when the TTC bit in CAN_CTL is set.
Page 900 GD32A508xx User Manual DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Transmit mailbox data1 register (CAN_TMDATA1x) (x = 0...2) 25.4.16. Address offset: 0x18C + 0x10 * x Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 901 GD32A508xx User Manual EFID[12:0] Reserved Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:1 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame 1: Extended format frame...
Page 902 GD32A508xx User Manual CAN FD frame flag 0: Classical frames 1: FD frames Reserved Must be kept at reset value. Bit rate of data switch 0: Bit rate not switch 1: The bit rate shall be switched from the nominal bit rate of the arbitration phase to the preconfigured bit rate of data of the data phase Error status indicator This bit is valid when ESIMOD bit is 1 in CAN_FDCTL register...
Page 903 GD32A508xx User Manual This register has to be accessed by word(32-bit). DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8 DB5[7:0] Data byte 5 DB4[7:0] Data byte 4 Filter control register (CAN_FCTL) 25.4.21.
Page 904 GD32A508xx User Manual Filter mode configuration register (CAN_FMCFG) 25.4.22. Address offset: 0x204 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set. The filter mode configuration register inCAN0 and CAN1: Reserved FMOD27 FMOD26 FMOD25 FMOD24 FMOD23 FMOD22 FMOD21 FMOD20 FMOD19 FMOD18 FMOD17 FMOD16 FMOD15 FMOD14 FMOD13 FMOD12 FMOD11 FMOD10...
Page 905 GD32A508xx User Manual The filter scale configuration register in CAN0 and CAN1: Reserved FS27 FS26 FS25 FS24 FS23 FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter scale 0: Filter x with 16-bit scale...
Page 906 GD32A508xx User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 FAFx Filter associated FIFO 0: Filter x associated with FIFO0 1: Filter x associated with FIFO1 The filter associated FIFO register in CAN2: Reserved Reserved FAF13 FAF12 FAF11...
Page 907 GD32A508xx User Manual 1: Filter x working enabled The filter working register in CAN2. Reserved Reserved FW13 FW12 FW11 FW10 Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:0 Filter working 0: Filter x working disabled 1: Filter x working enabled Filter x data y register (CAN_FxDATAy) (x = 0…27, y = 0,1) 25.4.26.
Page 908 GD32A508xx User Manual Ethernet (ENET) Overview 26.1. This chapter describes the Ethernet peripheral module. There is a media access controller (MAC) designed in Ethernet module to support 10 / 100Mbps interface speed. For more efficient datas transfer between Ethernet and memory, a DMA controller is designed in this module.
Page 909: Figure 26-1. Enet Module Block Diagram
GD32A508xx User Manual  Support special condition frame discards handling, e.g. late collision, excessive collisions, excessive deferral or underrun.  In the process of frame transmission, support computation and insertion of hardware checksum under store-and-forward mode. DMA Feature  Two types of descriptor addressing: Ring and Chain. ...
Page 910: Figure 26-2. Mac / Tagged Mac Frame Format
GD32A508xx User Manual  TxMTL, used to control, management and store the transmit data. TxFIFO is implemented in this module and used to cache transmitting data from memory for MAC transmission.  The MAC transmission relative control registers, used to control frame transmit. Receiving data module includes: ...
Page 911: Table 26-1. Ethernet Signals (Mii Default)
GD32A508xx User Manual 0x04C11DB7 and this polynomial is used in all 32-bit CRC calculation places in Ethernet module, as follows: G(x) = x + x + 1 Ethernet signal description 26.2.3. Table 26-1. Ethernet signals (MII default) Table 26-2. Ethernet signals (MII remap) Table 26-3.
Page 912: Table 26-3. Ethernet Signals (Rmii Default)
GD32A508xx User Manual Signals Pin mode MII_RXD1 PD10 Floating input (reset state) MII_RXD2 PD11 Floating input (reset state) MII_RXD3 PD12 Floating input (reset state) PPS_OUT AF output push-pull MII_TXD3 AF output push-pull MII_RX_ER PB10 Floating input (reset state) MII_TX_EN PB11 AF output push-pull MII_TXD0 PB12...
Page 913: Figure 26-3. Station Management Interface Signals
GD32A508xx User Manual carry on the PHY management through the SMI interface. SMI: Station management interface SMI is designed to access and configure PHY’s configuration. Station management interface (SMI) is performed through two wires to communicate with the external PHY: one clock line (MDC) and one data line (MDIO) . The maximum number of PHYs supported by this interface is 32.
Page 914: Figure 26-4. Media Independent Interface Signals
GD32A508xx User Manual The application can be aware of whether a transaction is complete or not through checking PB bit. When PB is 1, it means the application should not change the PHY address register contents and the PHY data register contents because of operation is running. Before writing PB bit to 1, application must poll the PB bit until it is 0.
Page 915 GD32A508xx User Manual - MII_TX_CLK: clock signal for transmitting data. For the data transmission speed of 10Mbit / s, the clock is 2.5MHz, for the data transmission speed of 100Mbit / s, the clock is 25MHz. - MII_RX_CLK: Clock signal for receiving data. For the data transmission speed of 10Mbit / s, the clock is 2.5MHz, for the data transmission speed of 100Mbit / s, the clock is 25MHz.
Page 916: Figure 26-5. Reduced Media-Independent Interface Signals
GD32A508xx User Manual - MII_RX_ER: Receive error signal. In order to indicate that MAC detected an error in the receiving process, the MII_RX_ER signal must remain effective for one or more clock cycles (MII_RX_CLK). The specific error reason needs to cooperate with the state of the MII_RX_DV and the MII_RXD[3:0] data value (see Table 26-6.
Page 917 GD32A508xx User Manual TX_EN TXD[1:0] CRS_DV MAC Controller RXD[1:0] REF_CLK RMII clock sources To ensure the synchronization of the clock source, the same clock source is selected for the MAC and external PHY which is called REF_CLK. The REF_CLK input clock can be connected to the external 50MHz crystal or microcontroller CK_OUT0 pin.
Page 918 GD32A508xx User Manual devices are both configured for Full-duplex mode. MAC module can achieve the follows functions: 1) The data packaging (transmission and reception), that includes detecting / decoding frame and delimitating frame boundary; handling source address and destination address; detecting error conditions. 2) The Medium access management in Half-duplex mode, that includes allocating medium in order to prevent conflicts;...
Page 919 GD32A508xx User Manual MAC frame is less than 42), application can configure the MAC for automatically adding a load of content of ‘0’ bit to make the byte length of frame’s data field in accordance with the relevant domain of definition of IEEE802.3 specification. At the same time, if automatically adding zeros function is performed, the MAC will certainly calculate CRC value of the frame and append it to the frame’s FCS field domain no matter what configuration of DCRC bit in the descriptor is.
Page 920 GD32A508xx User Manual immediately. For Half-duplex mode, the gap time counter follows the Truncated Binary Exponential Backoff algorithm. Briefly speaking, the gap time counter starts after the previous frame has completed transmitting on interface or the MAC entered idle state, and there are three conditions may occur during the gap time: ...
Page 921 GD32A508xx User Manual received unicast frame. This filter mode obeys the followings two filtering steps: 1. The MAC calculates the CRC value of the received frame’s destination address. 2. Using the high 6 bits of the calculated CRC value as the index to retrieve the hash list. If the corresponding value of hash list is 1, the received frame passes through the filter, conversely, fail the filter.
Page 922: Table 26-7. Destination Address Filtering Table
GD32A508xx User Manual Table 26-7. Destination address filtering table Table 26-8. Source address filtering table summarize the destination address and source address filters working condition at different configuration. Table 26-7. Destination address filtering table Frame HPFL BFRM HUF DAIFLT HMF MFD DA filter operation Type Pass...
Page 923 GD32A508xx User Manual Pass status on perfect / group filter match but do not drop frames that fail Fail status on perfect / group filter match but do not drop frame Pass on perfect / group filter match and drop frames that fail Fail on perfect / group filter match and drop frames that fail...
Page 924 GD32A508xx User Manual After all data of a frame pop out, receive status word is sent to DMA for writing back to descriptor. In this mode, if a frame has started to forward to application by DMA from FIFO, the forwarding will continue until the frame is end even if frame error is detected. Although the error frame is not discarded, the error status will reflect in descriptor status field.
Page 925 GD32A508xx User Manual When this number is greater than the high threshold (RFA bits in ENET_MAC_FCTH), MAC will set the back pressure pending flag. If this flag is set and a new frame presents on interface, MAC will send a jam pattern to delay receiving this new frame a back pressure time. After this back pressure time is end, external PHY will send this new frame again.
Page 926: Checksum Offload Engine
GD32A508xx User Manual by the MAC. During the pause time period, if MAC received a new pause frame, the new pause time filed value is loaded to the pause time counter immediately. If the new pause time filed is zero, then the pause time counter stops and transmit operation recovers. Application can configure PCFRM bit in ENET_MAC_FRMF register to decide the solving method for such control frame.
Page 927 GD32A508xx User Manual bypassed and these frames will not be processed by the checksum offload module: – Incomplete IPv4 or IPv6 frames. – IP frames with security features (e.g. authentication header, security payload). – IP frames without TCP / UDP / ICMPv4 / ICMPv6 payload. –...
Page 928: Mac Loopback Mode
GD32A508xx User Manual  Any inconsistent between the data type of Ethernet type field and IP header version field.  Received frame length is less than the length indicated in IPv4 header length field, or IPv4 or IPv6 header is less than 20 bytes. Receive checksum offload also identifies the data type of the IP packet is TCP, UDP or ICMP, and calculate their checksum according to TCP, UDP or ICMP specification.
Page 929: Figure 26-6. Descriptor Ring And Chain Structure
GD32A508xx User Manual a frame. When chain structure is set, descriptor table is an explicitly one and when ring structure is set, descriptor table is an implicitly one. Explicit chaining of descriptors is accomplished by configuring the second address chained in both receive and transmit descriptors (configure RCHM bit in the Receive Descriptor1 and TCHM bit in the Transmit Descriptor0), at this time Receive Descriptor2 and Transmit Descriptor2 are stored the data buffer address, Receive Descriptor3 and Transmit Descriptor3 should be stored the next...
Page 930 GD32A508xx User Manual Alignment rule for data buffer address The DMA controller supports all alignment types: byte alignment, half-word alignment and word alignment. This means application can configure the buffer address to any address. But during the operation of the DMA controller, access address is always word align and is different between write and read access.
Page 931 GD32A508xx User Manual When a start of frame (SOF) is received, the FSG bit is set by DMA controller and when the end of the frame (EOF) is received, the LSG bit is set. If the receive buffer size is programmed to be large enough to store the whole frame, the FSG and the LSG bit are set in the same descriptor.
Page 932 GD32A508xx User Manual When the FSG bit is set, the descriptor indicates the start of the frame and when the LSG bit is set, the descriptor indicates the end of the frame. All the buffers among these descriptors store the whole frame data. When the last descriptor is fetched and buffer finished reading, the transmitting status will write back to it.
Page 933 GD32A508xx User Manual resetting the DAV bit after all buffer data pushed into TxFIFO. Then the TxDMA controller waits to write back descriptor status and IEEE 1588 timestamp value if enabled; 7. After the whole frame is transferred, the transmit status bit (TS bit in ENET_DMA_STAT register) is set only when INTC bit in Transmit Descriptor0 is set.
Page 934 GD32A508xx User Manual 8. In suspend state, application can make TxDMA returns to running state by writing any data to ENET_DMA_TPEN register and clearing the transmit underflow flag. Then the TxDMA controller process goes to Step 1 or Step 2. Transmit frame format in buffer According to IEEE 802.3 specification described before, a frame structure is made up of such fields: Preamble, SFD, DA, SA, QTAG (option), LT, DATA, PAD (option), and FCS.
Page 935: Figure 26-7. Transmit Descriptor In Normal Mode
GD32A508xx User Manual given below: Note: When a frame is described by more than one descriptor, only the control bits of the first descriptor are accept by TxDMA controller (except INTC). But the status and timestamp (if enabled) are written back to the last descriptor. Figure 26-7.
Page 936 GD32A508xx User Manual DCRC Disable CRC bit Only when the FSG bit is set, this bit is valid. 0: Allow MAC to insert CRC at the end of transmitted frame automatically 1: Not Allow MAC to insert CRC at the end of transmitted frame DPAD Disable adding pad bit Only when the FSG bit is set, this bit is valid.
Page 937 GD32A508xx User Manual IPHE IP header error bit IP header error occurs when any case of below happen: IPv4 frames: 1) The header length field has a value less than 0x5. 2) The header length field value in transmitting IPv4 frame is mismatch with the number of header bytes.
Page 938 GD32A508xx User Manual 0: No loss of carrier occurred 1: When the frame is transmitting, loss of carrier occurred No carrier bit 0: PHY carrier sense signal is active 1: When the frame is transmitting, the carrier sense signal from the PHY was not active Late collision bit If a collision occurs when 64 bytes (including preamble and SFD) has already...
Page 939 GD32A508xx User Manual This bit shows whether the transmitting frame is deferred because of interface signal CRS is active before MAC transmit frame. Only in Half-duplex mode this bit is valid. 0: No transmission deferred 1:The MAC is deferred before transmission ...
Page 940: Figure 26-8. Transmit Descriptor In Enhanced Mode
GD32A508xx User Manual TB2AP / TTSH[31:16] TB2AP / TTSH[15:0] Bits Fields Descriptions 31:0 TB2AP / TTSH[31:0] Transmit buffer 2 address pointer (or next descriptor address) / Transmit frame timestamp high 32-bit value bits. Before transmitting frame, application must configure these bits for transmit buffer 2 address (TB2AP) or the next descriptor address which is decided by descriptor type is ring or chain.
Page 941 GD32A508xx User Manual  Transmit descriptor4 All bits reserved.  Transmit descriptor5 All bits reserved.  Transmit descriptor6 TTSL[31:16] TTSL[15:0] Bits Fields Descriptions 31:0 TTSL[31:0] Transmit frame timestamp low 32-bit value bits When TTSEN =1 and LSG=1, there bits are updated by TxDMA for recording timestamp low 32-bit value of the current transmitting frame.
Page 942 GD32A508xx User Manual frame, if any one of the below cases occurs the MAC can discard the received frame data in RxFIFO and the RxDMA controller will not forward these data:  The received frame bytes is less than 64. ...
Page 943 GD32A508xx User Manual DERR in Receive Descriptor0 if flushing function is enabled. The RxDMA controller closes current descriptor by resetting DAV bit and sets the LSG bit (if flushing is enabled) or resets the LSG bit (if flushing is disabled). Then the operation goes to Step 8. –...
Page 944: Figure 26-9. Receive Descriptor In Normal Mode
GD32A508xx User Manual be flushed and MSFC counter will not increase until the RxFIFO is full. If the DAV bit is reset in fetched descriptor, the RBU bit in ENET_DMA_STAT register will be set and the RxDMA controller will be still in suspend state. Receive DMA descriptor with IEEE 1588 timestamp format If the IEEE 1588 function enabled, the MAC writes the timestamp value to Receive Descriptor2 and Receive Descriptor3 (DFM=0) or Receive Descriptor6 and Receive...
Page 945 GD32A508xx User Manual DAFF Destination address filter fail bit 0: A frame passed the destination address filter 1: A frame failed the destination address filter 29:16 FRML[13:0] Frame length bits These bits show the byte length of the received frame that was transferred to the buffer (including CRC when received frame is not a type frame.
Page 946 GD32A508xx User Manual 0: No source address filter fail occurred 1: A received frame failed the SA filter LERR Length error bit Only when the FRMT bit is reset, this bit is valid. This bit shows whether the length field in received is mismatch the actual frame length.
Page 947: Table 26-9. Error Status Decoding In Receive Descriptor0, Only Used For Normal Descriptor (Dfm=0)
GD32A508xx User Manual If the received frame is runt frame, this bit is not valid for application. 0: The received frame is an IEEE802.3 frame without tagged. 1: The received frame is an Ethernet-type frame (the length / type field is greater than or equal to 0x0600, or this is a tagged frame) RWDT Receive watchdog timeout bit...
Page 948 GD32A508xx User Manual IEEE 802.3 normal frame (Length field value is less than 0x0600 and not tagged) IPv4 or IPv6 frame, no header checksum error, payload checksum is bypassed because of unsupported payload type IPv4 or IPv6 frame, checksum checking pass IPv4 or IPv6 frame, payload checksum error.
Page 949 GD32A508xx User Manual This bit indicates the final descriptor in table is arrived and the next descriptor address is automatically set to the configured start descriptor address. 0: Current descriptor is not the last descriptor in table 1: Current descriptor is the last descriptor in table RCHM Receive chained mode for second address bit 0: The second address points to the second buffer address.
Page 950: Figure 26-10. Receive Descriptor In Enhanced Mode
GD32A508xx User Manual Bits Fields Descriptions 31:0 RB2AP / RTSH[31:0] Receive buffer 2 address pointer (next descriptor address) / Receive frame timestamp high 32-bit value bits These bits are designed for two different functions: buffer address pointer or next descriptor address (RB1AP) or timestamp high 32-bit value (RTSH). RB2AP: Before fetching this descriptor by RxDMA controller, these bits are configured to the buffer 2 address (RCHM=0) or the next descriptor address (RCHM=1) by application.
Page 951 GD32A508xx User Manual IPPLDER Reserved PTPVF PTPOEF PTPMT[3:0] IPF6 IPF4 IPCKSB IPHERR IPPLDT[2:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. PTPVF PTP version format bit 0: Version 1 format 1: Version 2 format PTPOEF PTP on Ethernet frame bit 0: Received PTP frame is a IP-UDP frame if PTPMT is not zero 1: Received PTP frame is a IEEE802.3 Ethernet frame 11:8...
Page 952 GD32A508xx User Manual This bit can be set by any of below cases: 1) the calculated checksum by hardware mismatch with the TCP, UDP or ICMP checksum field in frame. 2) payload length value in IP header mismatch the received payload length. 0: Payload error not occurred in received frame 1: Payload error occurred in received frame IPHERR...
Page 953 GD32A508xx User Manual RTSH[15:0] Bits Fields Descriptions 31:0 RTSH[31:0] Receive frame timestamp high 32-bit value When timestamp function is enabled and LDES is set, these bits will be written to timestamp high 32-bit value by RxDMA controller if received frame passed the filter and satisfied the snapshoot condition.
Page 954: Magic Packet Detection
GD32A508xx User Manual Magic Packet frame is received. When any type of wakeup frame is present on interface and corresponding wakeup function is enabled, Ethernet will generate a wakeup interrupt and exit power-down state at once. Remote wakeup frame detection Setting WFEN bit in ENET_MAC_WUM register can enable remote wakeup detection.
Page 955: Figure 26-11. Wakeup Frame Filter Register
GD32A508xx User Manual Magic Packet interrupt is enabled, the corresponding interrupt will generate. Precautions during system power-down state When the MCU is in Deep-sleep mode, if external interrupt line 19 is enabled, Ethernet WUM module can still detecting frames. Because the MAC in power-down state needs detecting Magic Packet or remote wakeup frame, the REN bit in ENET_MAC_CFG register must be maintained set.
Page 956: Precision Time Protocol: Ptp
GD32A508xx User Manual Wakeup Frame Filter Filter 0 Byte Mask Register 0 Wakeup Frame Filter Filter 1 Byte Mask Register 1 Wakeup Frame Filter Filter 2 Byte Mask Register 2 Wakeup Frame Filter Filter 3 Byte Mask Register 3 Wakeup Frame Filter Filter 3 Filter 2 Filter 1...
Page 957: Reference Clock Source
GD32A508xx User Manual Reference clock source System reference time in Ethernet is maintained by a 64-bit register whose high 32-bit indicates ‘second’ time and low 32-bit indicates ‘subsecond’, this is defined in IEEE 1588 specification. The input PTP reference clock is used to drive the system reference time (also called system time for short) and capture timestamp value for PTP frame.
Page 958 GD32A508xx User Manual The following concrete example is used to descript the fine correction method how to update the system time: Assuming the accuracy of the system time update circuit required to achieve 25ns, which means the frequency of update is 40MHz. If the reference clock of HCLK is 72MHz, the frequency ratio is calculated as 72 / 40, result is 1.8.
Page 959 GD32A508xx User Manual Calculation: SCLOCKC (n) = SLOCALT (n) - SLOCALT (n-1).  Define the difference between these two count numbers: DIFFCC (n). Calculation: DIFFCC (n) = MCLOCKC (n) - SCLOCKC (n).  Define the slave clock frequency-adjusting factor: SCFAF (n). Calculation: SCFAF (n) = (MCLOCKC (n) + DIFFCC (n)) / SCLOCKC (n).
Page 960 GD32A508xx User Manual 1. Calculate the value of the desired system clock rate corresponding to the addend register (System time calibration has explained before); 2. Program the addend register, and set the TMSARU in ENET_PTP_TSCTL register; 3. Program the target high and low register and reset the TMSTIM of the ENET_MAC_INTMSK register to allow time stamp interrupt;...
Page 961 GD32A508xx User Manual TIMER1 and PTP reference clock (HCLK) are synchronous. PPS output signal Application set PTP_PPS_REMAP bit in the AFIO_PCF0 register to 1 to enable the PPS output function. This function can output a signal with the pulse width of 125ms by default (other width is detailed in PTP PPS control register (ENET_PTP_PPSCTL)) which can be...
Page 962 GD32A508xx User Manual transmit and receive.  If transmitting frames is needed 1. Choose one or more programmed transmitting descriptor, write the transmit frame data into buffer address which is decided in Transmit Descriptor; 2. Set the DAV bit in these one or more transmit frame descriptor; 3.
Page 963: Figure 26-13. Mac Interrupt Scheme
GD32A508xx User Manual MAC interrupts All of the MAC events can be read from ENET_MAC_INTF and each of them has a mask bit for masking corresponding interrupt. The MAC interrupt is logical ORed of all interrupts. Figure 26-13. MAC interrupt scheme DMA controller interrupts The DMA controller has two types of event: Normal and Abnormal.
Page 964 GD32A508xx User Manual TBUIE NISE Normal Interrupt ERIE Ethernet MSCI Interrupt WUMI TMSTI FBEIE Abnormal Interrupt TJTIE TPSIE RBUIE ROIE AISE RPSIE TUIE ETIE RWTIE...
Page 965 GD32A508xx User Manual Register definition 26.4. ENET base addresss: 0x4002 8000 Byte (8-bit) access, half word (16-bit) access and word (32-bit) access are all supported for application. MAC configuration register (ENET_MAC_CFG) 26.4.1. Address offset: 0x0000 Reset value: 0x0000 8000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). This register configures the operation mode of the MAC.
Page 966 GD32A508xx User Manual 19:17 IGBS[2:0] Inter frame gap bit selection bits These bits can select the minimum inter frame gap bit time between two neighboring frames during transmission. 0x0: 96 bit times 0x1: 88 bit times 0x2: 80 bit times 0x3: 72 bit times 0x4: 64 bit times 0x5: 56 bit times (For Half-duplex, must be reserved)
Page 967 GD32A508xx User Manual APCD Automatic pad / CRC drop bit This bit only valid for a non tagged frame and its length field value is equal or less than 1536. 0: The MAC forwards all received frames without modify it 1: The MAC strips the Pad / FCS field on received frames BOL[1:0] Back-off limit bits...
Page 968 GD32A508xx User Manual Reserved Reserved HPFLT SAFLT SAIFLT PCFRM[1:0] BFRMD DAIFLT Bits Fields Descriptions Frames all received bit This bit controls the receive filter function. 0: Only the frame passed the filter can be forwarded to application 1: All received frame are forwarded to application. But filter result will also be updated to receive descriptor status.
Page 969 GD32A508xx User Manual application BFRMD Broadcast frames disable bit 0: Ignore the address filters, and all received broadcast frames is passed. 1: All received broadcast frames is filtered by address filters Multicast filter disable bit 0: Multicast filter is enabled. The filtering mode of multicast frame is determined by HMF bit.
Page 970 GD32A508xx User Manual 31:0 HLH[31:0] Hash list high bits These bits take the high 32-bit value of hash list. MAC hash list low register (ENET_MAC_HLL) 26.4.4. Address offset: 0x000C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). HLL[31:16] HLL[15:0] Bits...
Page 971 GD32A508xx User Manual MDC clock divided factor select which is decided by HCLK frequency range. 0x0: HCLK / 42 (HCLK range: 60-100 MHz) 0x1: HCLK / 62 (HCLK range: 100-150 MHz) 0x2: HCLK / 16 (HCLK range: 20-35 MHz) 0x3: HCLK / 26 (HCLK range: 35-60 MHz) 0x4: HCLK / 102 (HCLK range: 150-180 MHz) other: Reserved PHY write bit...
Page 972 GD32A508xx User Manual This register configures the generation and reception of the control frames. PTM[15:0] FLCB / Reserved DZQP Reserved PLTS[1:0] UPFDT RFCEN TFCEN BKPA Bits Fields Descriptions 31:16 PTM[15:0] Pause time bits These bits configured the pause time filed value in transmit pause control frame. 15:8 Reserved Must be kept at reset value.
Page 973 GD32A508xx User Manual TFCEN Transmit flow control enable bit 0: Disable the flow control operation in the MAC. Both pause frame sending in Full- duplex mode and back-pressure feature in Half-duplex mode are not performed. 1: Enable the flow control operation in the MAC. Both pause frame sending in Full- duplex mode and back-pressure feature in Half-duplex mode can be performed by transmitter.
Page 974: Figure 26-15. Wakeup Frame Filter Register
GD32A508xx User Manual These bits are configured for detecting VLAN frame using 802.1Q VLAN tag format. The format shows below: VLTI[15:13]: UP (user priority) VLTI[12]: CFI (canonical format indicator) VLTI[11:0]: VID (VLAN identifier) When comparison bits (VLTI[11:0] if VLTC=1 or VLTI[15:0] if VLTC=0) are all zeros, VLAN tag comparison is bypassed and every frame with type filed value of 0x8100 is considered a VLAN frame.
Page 975 GD32A508xx User Manual WUFFRP Reserved Reserved Reserved WUFR MPKR Reserved WFEN MPEN rc_r rc_r Bits Fields Descriptions WUFFRPR Wakeup frame filter register pointer reset bit This bit can reset the inner pointer of ENET_MAC_RWFF register by application set it to 1. Hardware clears it when resetting completes. 0: No effect 1: Reset the ENET_MAC_RWFF register inner pointer 30:10...
Page 976 GD32A508xx User Manual occurred, hardware resets this bit. MAC debug register (ENET_MAC_DBG) 26.4.11. Address offset: 0x0034 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). Reserved TXFF TXFNE Reserved TXFW TXFRS[1:0] SOMT[1:0] MTNI Reserved RXFS[1:0] Reserved...
Page 977 GD32A508xx User Manual 0x2: For Full-duplex mode, indicates pause control frame is transmitting 0x3: The MAC transmitter controller is in Reading input frame from FIFO for transmission MTNI MAC transmit state not idle 0: MAC transmitter is in idle state 1: MAC transmitter is not in idle state 15:10 Reserved...
Page 978 GD32A508xx User Manual Reserved TMST Reserved MSCT MSCR Reserved rc_r Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TMST Time stamp trigger status bit This bit is cleared when ENET_PTP_TSF register is read. 0: The system time value is less than the value specified in the the ENET_PTP_ETH and ENET_PTP_ETL registers 1: The system time value is no less than the value specified in the ENET_PTP_ETH and ENET_PTP_ETL registers...
Page 979 GD32A508xx User Manual Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TMSTIM Timestamp trigger interrupt mask bit 0: Unmask the timestamp interrupt generation 1: Mask the timestamp interrupt generation Reserved Must be kept at reset value. WUMIM WUM interrupt mask bit 0: Unmask the interrupt generation due to the WUM bit in ENET_MAC_INTF register...
Page 980 GD32A508xx User Manual ADDR0L[31:16] ADDR0L[15:0] Bits Fields Descriptions 31:0 ADDR0L[31:0] MAC addresss0 low 32-bit These bits contain the low 32-bit (bit 31 to 0) of the 6-byte MAC address0. These bits are used for address filtering in frame reception and address inserting in pause frame transmitting during transmit flow control.
Page 981 GD32A508xx User Manual MB[1]: ENET_MAC_ADDR1L[15:8] MB[0]: ENET_MAC_ADDR1L[7:0] 23:16 Reserved Must be kept at reset value. 15:0 ADDR1H[15:0] MAC address1 high[47:32] bits This field contains the high 16-bit (bit 47 to 32) of the 6-byte MAC address1. MAC address 1 low register (ENET_MAC_ADDR1L) 26.4.17.
Page 982 GD32A508xx User Manual 0: Comparing MAC address2 with the destination address field of the received frame 1: Comparing MAC address2 with the source address field of the received frame 29:24 MB[5:0] Mask byte bits If these bits is set, the destination address / source address corresponding byte of the received frame is not compared with MAC address2.
Page 983 GD32A508xx User Manual ADDR3H[15:0] Bits Fields Descriptions Address filter enable bit 0: MAC address3 is ignored by address filter for filtering 1: MAC address3 is used by address filter for perfect filtering Source address filter bit 0: Comparing MAC address3 with the destination address field of the received frame 1: Comparing MAC address3 with the source address field of the received frame 29:24...
Page 984 GD32A508xx User Manual Bits Fields Descriptions 31:0 ADDR3L[31:0] MAC address3 low 32-bit This field contains the low 32-bit of the 6-byte MAC address3. MAC flow control threshold register (ENET_MAC_FCTH) 26.4.22. Address offset: 0x1080 Reset value: 0x0000 0015 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). Reserved Reserved RFD[2:0]...
Page 985 GD32A508xx User Manual 0x5: 1536 bytes 0x6,0x7: 1792 bytes MSC control register (ENET_MSC_CTL) 26.4.23. Address offset: 0x0100 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). Reserved Reserved AFHPM MCFZ RTOR CTSR Bits Fields Descriptions 31:6...
Page 986 GD32A508xx User Manual 1: Reset all counters MSC receive interrupt flag register (ENET_MSC_RINTF) 26.4.24. Address offset: 0x0104 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). Reserved RGUF Reserved rc_r Reserved RFAE RFCE Reserved rc_r rc_r...
Page 987 GD32A508xx User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. Transmitted good frames bit 0: Good frame transmitted counter is less than half of the maximum value 1: Good frame transmitted counter reaches half of the maximum value 20:16 Reserved Must be kept at reset value.
Page 988 GD32A508xx User Manual 16:7 Reserved Must be kept at reset value. RFAEIM Received frames alignment error interrupt mask bit 0: Unmask the interrupt when the RFAE bit is set 1: Mask the interrupt when the RFAE bit is set RFCEIM Received frame CRC error interrupt mask bit 0: Unmask the interrupt when RFCE bit is set 1: Mask the interrupt when the RFCE bit is set...
Page 989 GD32A508xx User Manual MSC transmitted good frames after a single collision counter register 26.4.28. (ENET_MSC_SCCNT) Address offset: 0x014C Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). This register counts the number of successfully transmitted frames after a single collision in Half-duplex mode.
Page 990: Received Frames
GD32A508xx User Manual single collision. MSC transmitted good frames counter register (ENET_MSC_TGFCNT) 26.4.30. Address offset: 0x0168 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). This register counts the number of good frames transmitted. TGF[31:16] TGF[15:0] Bits...
Page 991 GD32A508xx User Manual received frames with alignment error counter register 26.4.32. (ENET_MSC_RFAECNT) Address offset: 0x0198 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). This register counts the number of received frames with alignment error. RFAER[31:16] RFAER[15:0] Bits...
Page 992 GD32A508xx User Manual Reset value: 0x0000 2000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). This register configures the generation and updating for timestamp. Reserved MAFEN CKNT[1:0] MNMSEN ETMSEN IP4SEN IP6SEN ESEN PFSV SCROM ARFSEN Reserved TMSARU TMSITEN TMSSTU TMSSTI TMSFCU...
Page 993 GD32A508xx User Manual 1: Take snapshot when received non type frame PFSV PTP frame snooping version 0: Version 1 (Revision of IEEE STD. 1588-2002 / 1588-2008) 1: Version 2 (Revision of IEEE STD. 1588-2008) SCROM Subsecond counter rollover mode 0: Binary rollover mode. Subsecond rollovers when reach 0x7FFF_FFFF 1: Digital rollover mode.
Page 994: Table 26-10. Supported Time Stamp Snapshot With Ptp Register Configuration
GD32A508xx User Manual TMSEN Timestamp enable bit 0: Disable timestamp function 1: Enable timestamp function for transmit and receive frames Note: After setting this to 1, application must initialize the system time. Table 26-10. Supported time stamp snapshot with PTP register configuration CKNT (Bit 17:16) MNMSEN...
Page 995 GD32A508xx User Manual PTP time stamp high register (ENET_PTP_TSH) 26.4.36. Address offset: 0x0708 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). STMS[31:16] STMS[15:0] Bits Fields Descriptions 31:0 STMS[31:0] System time second bits These bits show the current second of the system time.
Page 996 GD32A508xx User Manual This register configures the high 32-bit of the time to be written to, added to, or subtracted from the system time value. The timestamp update registers (high and low) initialize or update the system time maintained by the MAC core. Application must write both of these registers before setting the TMSSTI or TMSSTU bits in the timestamp control register.
Page 997 GD32A508xx User Manual Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). This register value is used only in fine update mode for adjusting the clock frequency. This register value is added to a 32-bit accumulator in every clock cycle and the system time updates when the accumulator reaches overflow.
Page 998 GD32A508xx User Manual ETSL[15:0] Bits Fields Descriptions 31:0 ETSL[31:0] Expected time low bits These bits store the expected target nanosecond time (signed). PTP time stamp flag register (ENET_PTP_TSF) 26.4.43. Address offset: 0x0728 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit), half-word(16-bit) or word (32-bit). Reserved Reserved TSSCO...
Page 999 GD32A508xx User Manual Reserved PPSOFC[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. PPSOFC PPS output frequency configure 0x0: 1Hz (Pulse width: 125ms for binary rollover, 100ms for digital rollover) 0x1: 2Hz (Pulse width: 50% duty cycle for binary rollover) 0x2: 4Hz (Pulse width: 50% duty cycle for binary rollover) ….
Page 1000 GD32A508xx User Manual 1: Multiple the PGBL value programmed (bits[22:17] and bits[13:8]) four times for the DMA data number of beats to be transferred Use independent PGBL bit 0: The PGBL value in bits[13:8] is applicable for both TxDMA and RxDMA engines 1: The RxDMA uses the RXDP[5:0] bits as burst length while the PGBL[5:0] is used by TxDMA 22:17...

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