Port Input Status Register (Gpiox_Istat, X=A - GigaDevice Semiconductor GD32VF103 User Manual

17:16 MD12[1:0]
15:14 CTL11[1:0]
13:12 MD11[1:0]
11:10 CTL10[1:0]
9:8 MD10[1:0]
7:6 CTL9[1:0]
5:4 MD9[1:0]
3:2 CTL8[1:0]
1:0 MD8[1:0]
7.5.3. Port input status register (GPIOx_ISTAT, x=A..E)
Address offset: 0x08
Reset value: 0x0000 XXXX
This register has to be accessed by word (32-bit).
31 30 29
15 14 13
refer to CTL0[1:0]description
Port 12 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
Port 11 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
Port 11 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
Port 10 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
Port 10 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
Port 9 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
Port 9 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
Port 8 configuration bits
These bits are set and cleared by software
refer to CTL0[1:0]description
Port 8 mode bits
These bits are set and cleared by software
refer to MD0[1:0]description
28 27 26 25
12 11 10 9
GD32VF103 User Manual
24 23 22 21
Reserved
8 7 6 5
20 19 18 17
4 3 2 1
16
0
116