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GD32F403 Series
GigaDevice Semiconductor GD32F403 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32F403 Series. We have
1
GigaDevice Semiconductor GD32F403 Series manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32F403 Series User Manual (711 pages)
Arm Cortex-M4 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 9 MB
Table of Contents
Table of Contents
2
Gd32F403Xx User Manual List of Figures
16
List of Figures
16
List of Table
23
Arm ® Cortex ® -M4 Processor
26
System and Memory Architecture
26
Figure 1-1. the Structure of the Cortex
27
System Architecture
27
Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
27
Figure 1-2. Gd32F403Xx Series System Architecture
29
Memory Map
29
Table 1-2. Memory Map of Gd32F403Xx Devices
30
Bit-Banding
33
Boot Configuration
34
On-Chip Flash Memory Overview
34
On-Chip SRAM Memory
34
Table 1-3. Boot Modes
34
Device Electronic Signature
36
Memory Density Information
36
Unique Device ID (96 Bits)
36
System Configuration Registers
37
Flash Memory Architecture
39
Flash Memory Controller (FMC)
39
Function Description
39
Introduction
39
Main Features
39
Table 2-1. Gd32F403Xx Base Address and Size for Flash Memory
39
Read Operations
40
Unlock the Fmc_Ctlx Registers
40
Figure 2-1. Process of Page Erase Operation
41
Page Erase
41
Mass Erase
42
Figure 2-2. Process of Mass Erase Operation
43
Main Flash Programming
44
Figure 2-3. Process of Word Program Operation
45
Option Bytes Erase
45
Option Bytes Description
46
Option Bytes Modify
46
Table 2-2. Option Byte
46
Page Erase/Program Protection
47
Security Protection
48
FMC Registers
49
Unlock Key Register 0(FMC_KEY0)
49
Wait State Register (FMC_WS)
49
Option Byte Unlock Key Register (FMC_OBKEY)
50
Status Register 0 (FMC_STAT0)
50
Control Register 0(FMC_CTL0)
51
Address Register 0 (FMC_ADDR0)
52
Erase/Program Protection Register (FMC_WP)
53
Option Byte Status Register (FMC_OBSTAT)
53
Status Register 1 (FMC_STAT1)
54
Unlock Key Register 1(FMC_KEY1)
54
Control Register 1(FMC_CTL1)
55
Address Register 1 (FMC_ADDR1)
56
Wait State Enable Register (FMC_WSEN)
56
Product ID Register (FMC_PID)
57
Characteristics
58
Figure 3-1. Power Supply Overview
58
Function Overview
58
Overview
58
Power Management Unit (PMU)
58
Backup Domain
59
Figure 3-2. Waveform of the por / PDR
60
VDD
60
Figure 3-3. Waveform of the LVD Threshold
61
Power Domain
62
Power Saving Modes
62
Table 3-1. Power Saving Mode Summary
64
Control Register (PMU_CTL)
66
PMU Registers
66
Control and Status Register (PMU_CS)
68
Backup Registers (BKP)
70
Function Description
70
Introduction
70
Main Features
70
RTC Clock Calibration
70
Tamper Detection
70
Backup Data Register X (Bkp_Datax) (X= 0
72
BKP Registers
72
RTC Signal Output Control Register (BKP_OCTL)
72
Tamper Control and Status Register (BKP_TPCS)
73
Tamper Pin Control Register (BKP_TPCTL)
73
Function Overview
75
Overview
75
Reset and Clock Unit (RCU)
75
Reset Control Unit (RCTL)
75
Clock Control Unit (CCTL)
76
Figure 5-1. the System Reset Circuit
76
Overview
76
Figure 5-2. Clock Tree
77
Characteristics
78
Figure 5-3. HXTAL Clock Source
78
Function Overview
78
Figure 5-4. HXTAL Clock Source in Bypass Mode
79
Table 5-1. Clock Output 0 Source Select
81
Table 5-2. 1.2V Domain Voltage Selected in Deep-Sleep Mode
82
Control Register (RCU_CTL)
83
Register Definition
83
Clock Configuration Register 0 (RCU_CFG0)
85
Clock Interrupt Register (RCU_INT)
88
APB2 Reset Register (RCU_APB2RST)
92
APB1 Reset Register (RCU_APB1RST)
94
AHB Enable Register (RCU_AHBEN)
97
APB2 Enable Register (RCU_APB2EN)
98
APB1 Enable Register (RCU_APB1EN)
100
Backup Domain Control Register (RCU_BDCTL)
103
Reset Source/Clock Register (RCU_RSTSCK)
105
AHB Reset Register (RCU_AHBRST)
106
Clock Configuration Register 1 (RCU_CFG1)
107
Additional Clock Control Register (RCU_ADDCTL)
110
Deep-Sleep Mode Voltage Register (RCU_DSV)
110
Additional Clock Interrupt Register (RCU_ADDINT)
111
APB1 Additional Enable Register (RCU_ADDAPB1EN)
112
APB1 Additional Reset Register (RCU_ADDAPB1RST)
112
Characteristics
114
Clock Trim Controller (CTC)
114
Function Overview
114
Overview
114
CTC Trim Counter
115
Figure 6-1. CTC Overview
115
REF Sync Pulse Generator
115
Figure 6-2. CTC Trim Counter
116
Frequency Evaluation and Automatically Trim Process
116
Software Program Guide
117
Control Register 0 (CTC_CTL0)
119
Register Definition
119
Control Register 1 (CTC_CTL1)
120
Status Register (CTC_STAT)
121
Interrupt Clear Register (CTC_INTC)
123
Characteristics
125
Interrupt/Event Controller (EXTI)
125
Interrupts Function Overview
125
Overview
125
Table 7-1. NVIC Exception Types in Cortex-M4
126
Table 7-2. Interrupt Vector Table
126
External Interrupt and Event (EXTI) Block Diagram
129
External Interrupt and Event Function Overview
129
Figure 7-1. Block Diagram of EXTI
129
Table 7-3. EXTI Source
130
Event Enable Register (EXTI_EVEN)
131
EXTI Register
131
Interrupt Enable Register (EXTI_INTEN)
131
Falling Edge Trigger Enable Register (EXTI_FTEN)
132
Rising Edge Trigger Enable Register (EXTI_RTEN)
132
Software Interrupt Event Register (EXTI_SWIEV)
132
Pending Register (EXTI_PD)
133
Characteristics
134
Function Overview
134
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
134
Overview
134
Table 8-1. GPIO Configuration Table
134
Figure 8-1. Basic Structure of a Standard I/O Port Bit
135
GPIO Pin Configuration
135
Alternate Functions (AF)
136
External Interrupt/Event Lines
136
Figure 8-2. Input Configuration
136
Input Configuration
136
Figure 8-3. Output Configuration
137
Output Configuration
137
Alternate Function (AF) Configuration
138
Analog Configuration
138
Figure 8-4. Analog Configuration
138
Figure 8-5. Alternate Function Configuration
138
GPIO I/O Compensation Cell
139
GPIO Locking Function
139
Introduction
139
Remapping Function I/O and Debug Configuration
139
JTAG/SWD Alternate Function Remapping
140
Main Features
140
Table 8-2. Debug Interface Signals
140
Table 8-3. Debug Port Mapping and Pin Availability
140
ADC AF Remapping
141
Table 8-4. ADC0/ADC1 External Trigger Rountine Conversion AF Remapping
141
Table 8-5. Timerx Alternate Function Remapping
141
TIMER AF Remapping
141
Table 8-6. TIMER4 Alternate Function Remapping
142
I2C0 AF Remapping
143
Table 8-7. USART Alternate Function Remapping
143
USART AF Remapping
143
CAN AF Remapping
144
SPI/I2S AF Remapping
144
Table 8-10. CAN Alternate Function Remapping
144
Table 8-8. I2C0 Alternate Function Remapping
144
Table 8-9. SPI/I2S Alternate Function Remapping
144
CLK Pins AF Remapping
145
CTC AF Remapping
145
Ethernet AF Remapping
145
Table 8-11. ENET Alternate Function Remapping
145
Table 8-12. CTC Alternate Function Remapping
145
Table 8-13. OSC32 Pins Configuration
146
Table 8-14. OSC Pins Configuration
146
Port Control Register 0 (Gpiox_Ctl0, X=A
147
Register Definition
147
Port Control Register 1 (Gpiox_Ctl1, X=A
149
Port Input Status Register (Gpiox_Istat, X=A
150
Port Bit Operate Register (Gpiox_Bop , X=A
151
Port Output Control Register (Gpiox_Octl, X=A
151
Port Bit Clear Register (Gpiox_Bc, X=A
152
Port Configuration Lock Register (Gpiox_Lock, X=A
152
Port Bit Speed Register (Gpiox_ SPD, X=A
153
AFIO Port Configuration Register 0 (AFIO_PCF0)
154
Event Control Register (AFIO_EC)
154
EXTI Sources Selection Register 0 (AFIO_EXTISS0)
157
EXTI Sources Selection Register 1 (AFIO_EXTISS1)
159
EXTI Sources Selection Register 2 (AFIO_EXTISS2)
160
EXTI Sources Selection Register 3 (AFIO_EXTISS3)
161
AFIO Port Configuration Register 1 (AFIO_PCF1)
162
IO Compensation Control Register (AFIO_CPSCTL)
164
Characteristics
165
Cyclic Redundancy Checks Management Unit (CRC)
165
Overview
165
Figure 9-1. Block Diagram of CRC Calculation Unit
166
Function Overview
166
Data Register (CRC_DATA)
167
Free Data Register (CRC_FDATA)
167
Register Definition
167
Control Register (CRC_CTL)
168
Characteristics
169
Direct Memory Access Controller (DMA)
169
Overview
169
Block Diagram
170
DMA Operation
170
Figure 10-1. Block Diagram of DMA
170
Function Overview
170
Table 10-1. DMA Transfer Operation
171
Address Generation
172
Arbitration
172
Figure 10-2. Handshake Mechanism
172
Peripheral Handshake
172
Channel Configuration
173
Circular Mode
173
Interrupt
173
Memory to Memory Mode
173
DMA Request Mapping
174
Figure 10-3. DMA Interrupt Logic
174
Table 10-2. Interrupt Events
174
Table 10-3. DMA0 Requests for each Channel
174
Table 10-4. DMA1 Requests for each Channel
174
Figure 10-4. DMA0 Request Mapping
175
Figure 10-5. DMA1 Request Mapping
176
Interrupt Flag Register (DMA_INTF)
178
Register Definition
178
Channel X Control Register (Dma_Chxctl)
179
Interrupt Flag Clear Register (DMA_INTC)
179
Channel X Counter Register (Dma_Chxcnt)
181
Channel X Memory Base Address Register (Dma_Chxmaddr)
182
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
182
Debug (DBG)
184
Introduction
184
JTAG/SW Function Description
184
Pin Assignment
184
Switch JTAG or SW Interface
184
Debug Hold Function Description
185
Debug Reset
185
Debug Support for Power Saving Mode
185
JEDEC-106 ID Code
185
JTAG Daisy Chained Structure
185
Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
186
Control Register 0 (DBG_CTL0)
187
DBG Registers
187
ID Code Register (DBG_ID)
187
Analog-To-Digital Converter (ADC)
191
Characteristics
191
Overview
191
Figure 12-1. ADC Module Block Diagram
192
Pins and Internal Signals
192
Table 12-1. ADC Internal Input Signals
192
Table 12-2. ADC Input Pins Definition
192
Foreground Calibration Function
193
Functional Overview
193
ADC Clock
194
ADC Enable
194
Figure 12-2. Single Operation Mode
194
Operation Modes
194
Routine Sequence
194
Figure 12-3. Continuous Operation Mode
195
Figure 12-4. Scan Operation Mode, Continuous Disable
196
Figure 12-5. Scan Operation Mode, Continuous Enable
196
Conversion Result Threshold Monitor Function
197
Data Storage Mode
197
Figure 12-6. Discontinuous Operation Mode
197
External Trigger Configuration
198
Figure 12-7. 12-Bit Data Storage Mode
198
Figure 12-8. 6-Bit Data Storage Mode
198
Sample Time Configuration
198
Table 12-3. External Trigger Source for ADC0 and ADC1
198
ADC Internal Channels
199
DMA Request
199
Table 12-4. External Trigger Source for ADC2
199
On-Chip Hardware Oversampling
200
Programmable Resolution (DRES)
200
Table 12-5. Tconv Timings Depending on Resolution
200
Figure 12-10. Numerical Example with 5-Bits Shift and Rounding
201
Figure 12-9. 20-Bit to 16-Bit Result Truncation
201
Table 12-6. Maximum Output Results Vs N and M Grayed Values Indicates Truncation
201
ADC Sync Mode
202
Table 12-7. ADC Sync Mode Table
202
Figure 12-11. ADC Sync Block Diagram
203
Free Mode
203
Routine Parallel Mode
203
Figure 12-12. Routine Parallel Mode on 10 Channels
204
Figure 12-13. Routine Follow-Up Fast Mode (the CTN Bit of Adcs Are Set)
204
Routine Follow-Up Fast Mode
204
Routine Follow-Up Slow Mode
204
ADC Interrupts
205
Figure 12-14. Routine Follow-Up Slow Mode
205
ADC Registers
206
Status Register (ADC_STAT)
206
Control Register 0 (ADC_CTL0)
207
Control Register 1 (ADC_CTL1)
208
Sample Time Register 0 (ADC_SAMPT0)
210
Sample Time Register 1 (ADC_SAMPT1)
211
Watchdog High Threshold Register (ADC_WDHT)
212
Watchdog Low Threshold Register (ADC_WDLT)
212
Routine Sequence Register 0 (ADC_RSQ0)
213
Routine Sequence Register 1 (ADC_RSQ1)
213
Routine Sequence Register 2 (ADC_RSQ2)
214
Oversample Control Register (ADC_OVSAMPCTL)
215
Routine Data Register (ADC_RDATA)
215
Characteristics
218
Digital-To-Analog Converter (DAC)
218
Figure 13-1. DAC Block Diagram
218
Introduction
218
DAC Enable
219
DAC Output Buffer
219
Function Description
219
Table 13-1. DAC I/O Description
219
DAC Data Configuration
220
DAC Noise Wave
220
DAC Trigger
220
DAC Workflow
220
Table 13-2. External Triggers of DAC
220
DAC Output Calculate
221
DMA Function
221
Figure 13-2. DAC LFSR Algorithm
221
Figure 13-3. DAC Triangle Noise Wave
221
DAC Concurrent Conversion
222
Control Register (DAC_CTL)
223
DAC Registers
223
Software Trigger Register (DAC_SWT)
225
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)
226
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)
226
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)
227
DAC1 12-Bit Right-Aligned Data Holding Register (DAC1_R12DH)
227
DAC1 12-Bit Left-Aligned Data Holding Register (DAC1_L12DH)
228
DAC1 8-Bit Right-Aligned Data Holding Register (DAC1_R8DH)
228
DAC Concurrent Mode 12-Bit Left-Aligned Data Holding Register (DACC_L12DH)
229
DAC Concurrent Mode 12-Bit Right-Aligned Data Holding Register (DACC_R12DH)
229
DAC Concurrent Mode 8-Bit Right-Aligned Data Holding Register (DACC_R8DH)
230
DAC0 Data Output Register (DAC0_DO)
230
DAC1 Data Output Register (DAC1_DO)
231
Characteristics
232
Free Watchdog Timer (FWDGT)
232
Function Overview
232
Overview
232
Watchdog Timer (WDGT)
232
Figure 14-1. Free Watchdog Block Diagram
233
Table 14-1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
233
Register Definition
235
Characteristics
238
Figure 14-2. Window Watchdog Timer Block Diagram
238
Function Overview
238
Overview
238
Window Watchdog Timer (WWDGT)
238
Figure 14-3. Window Watchdog Timing Diagram
239
Table 14-2. Min/Max Timeout Value at 84 Mhz
240
Register Definition
241
Characteristics
243
Function Overview
243
Overview
243
Real-Time Clock(RTC)
243
Figure 15-1. Block Diagram of RTC
244
RTC Configuration
244
RTC Reading
244
RTC Reset
244
RTC Flag Assertion
245
RTC Control Register(RTC_CTL)
247
RTC Interrupt Enable Register(RTC_INTEN)
247
RTC Register
247
RTC Prescaler High Register (RTC_PSCH)
248
RTC Divider High Register (RTC_DIVH)
249
RTC Divider Low Register (RTC_DIVL)
249
RTC Prescaler Low Register(RTC_PSCL)
249
RTC Counter High Register(RTC_CNTH)
250
RTC Counter Low Register (RTC_CNTL)
250
RTC Alarm High Register(RTC_ALRMH)
251
RTC Alarm Low Register (RTC_ALRML)
251
Table 16-1. Timers (Timerx) Are Divided into Five Sorts
252
Timers(Timerx)
252
Advanced Timer (Timerx, X=0, 7)
253
Characteristics
253
Overview
253
Block Diagram
254
Figure 16-1. Advanced Timer Block Diagram
254
Figure 16-2. Timing Chart of Internal Clock Divided by 1
255
Function Overview
255
Figure 16-3. Timing Chart of PSC Value Change from 0 to 2
256
Figure 16-4. Timing Chart of up Counting Mode, PSC=0/2
257
Figure 16-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
258
Figure 16-6. Timing Chart of down Counting Mode, PSC=0/2
258
Figure 16-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
260
Figure 16-8. Timing Chart of Center-Aligned Counting
260
Figure 16-10. Repetition Timechart for Up-Counter
262
Figure 16-9. Repetition Timechart for Center-Aligned Counter
262
Figure 16-11. Repetition Timechart for Down-Counter
263
Figure 16-12. Channel Input Capture Principle
264
Figure 16-13. Output-Compare under Three Modes
266
Figure 16-14. EAPWM Timechart
266
Figure 16-15. CAPWM Timechart
266
Table 16-2. Complementary Outputs Controlled by Parameters
269
Figure 16-16. Complementary Output with Dead-Time Insertion
270
Figure 16-17. Output Behavior in Response to a Break(the Break High Active)
271
Figure 16-18. Example of Counter Operation in Encoder Interface Mode
272
Figure 16-19. Example of Encoder Interface Mode with CI0FE0 Polarity Inverted
272
Table 16-3. Counting Direction Versus Encoder Signals
272
Figure 16-20. Hall Sensor Is Used to BLDC Motor
273
Figure 16-21. Hall Sensor Timing between Two Timers
274
Figure 16-22. Restart Mode
275
Table 16-4. Slave Mode Example Table
275
Figure 16-23. Pause Mode
276
Figure 16-24. Event Mode
276
Figure 16-25. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
277
Figure 16-26. Timer0 Master/Slave Mode Timer Example
277
Figure 16-27. Triggering TIMER0 with Enable Signal of TIMER2
279
Figure 16-28. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
280
Timerx Registers(X=0, 7)
281
Block Diagram
307
Characteristics
307
Figure 16-29. General Level 0 Timer Block Diagram
307
General Level0 Timer (Timerx, X= 2, 3)
307
Overview
307
Figure 16-30. Timing Chart of Internal Clock Divided by 1
309
Function Overview
309
Figure 16-31. Timing Chart of PSC Value Change from 0 to 2
310
Figure 16-32. Timing Chart of up Counting Mode, PSC=0/2
311
Figure 16-33. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
312
Figure 16-34. Timing Chart of down Counting Mode, PSC=0/2
312
Figure 16-35. Down-Counter Timechart, Change Timerx_Car on the Go
313
Figure 16-36. Timing Chart of Center-Aligned Counting Mode
314
Figure 16-37. Channel Input Capture Principle
316
Figure 16-38. Output-Compare under Three Modes
318
Figure 16-39. EAPWM Timechart
318
Figure 16-40. CAPWM Timechart
318
Table 16-5. Slave Mode Example Table
320
Figure 16-41. Restart Mode
321
Figure 16-42. Pause Mode
321
Figure 16-43. Event Mode
322
Figure 16-44. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
323
Timerx Registers(X=2, 3)
324
General Level1 Timer (Timerx, X=8, 11)
345
Overview
345
Figure 16-45. General Level1 Timer Block Diagram
346
Figure 16-46. Timing Chart of Internal Clock Divided by 1
347
Figure 16-47. Timing Chart of PSC Value Change from 0 to 2
348
Figure 16-48. Timing Chart of up Counting Mode, PSC=0/2
349
Figure 16-49. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
349
Figure 16-50. Channels Input Capture Principle
350
Figure 16-51. Output-Compare under Three Modes
352
Figure 16-52. EAPWM Timechart
353
Figure 16-53. CAPWM Timechart
353
Table 16-6.Slave Mode Example Table
354
Figure 16-54. Restart Mode
355
Figure 16-55. Pause Mode
355
Figure 16-56. Event Mode
356
Figure 16-57. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
356
Figure 16-58. General Level2 Timer Block Diagram
370
Figure 16-59. Timing Chart of Internal Clock Divided by 1
372
Figure 16-60. Timing Chart of PSC Value Change from 0 to 2
373
Figure 16-61. Timing Chart of up Counting Mode, PSC=0/2
374
Figure 16-62. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
374
Figure 16-63. Channels Input Capture Principle
375
Figure 16-64. Output-Compare under Three Modes
377
Figure 16-65. Basic Timer Block Diagram
389
Figure 16-66. Timing Chart of Internal Clock Divided by 1
390
Figure 16-67. Timing Chart of PSC Value Change from 0 to 2
390
Figure 16-68. Timing Chart of up Counting Mode, PSC=0/2
391
Figure 16-69. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
392
Table 16-1. Description of USART Important Pins
399
Figure 16-1. USART Module Block Diagram
400
Figure 16-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
400
Table 16-2. Configuration of Stop Bits
400
Figure 16-3. USART Transmit Procedure
402
Figure 16-4. Receiving a Frame Bit by Oversampling Method
403
Figure 16-5. Configuration Step When Using DMA for USART Transmission
404
Figure 16-6. Configuration Steps When Using DMA for USART Reception
405
Figure 16-7. Hardware Flow Control between Two Usarts
406
Figure 16-8. Hardware Flow Control
406
Figure 16-10. Break Frame Occurs During a Frame
408
Figure 16-11. Example of USART in Synchronous Mode
408
Figure 16-9. Break Frame Occurs During Idle State
408
Figure 16-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
409
Figure 16-13. Irda SIR ENDEC Module
409
Figure 16-14. Irda Data Modulation
410
Figure 16-15. ISO7816-3 Frame Format
411
Figure 16-16. USART Interrupt Mapping Diagram
413
Table 16-3. USART Interrupt Requests
413
Figure 18-1. I2C Module Block Diagram
427
Table 18-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
428
Figure 18-2. Data Validation
429
Figure 18-3. START and STOP Condition
429
Figure 18-4. Clock Synchronization
430
Figure 18-5. SDA Line Arbitration
430
Figure 18-6. I2C Communication Flow with 7-Bit Address
431
Figure 18-7. I2C Communication Flow with 10-Bit Address (Master Transmit)
431
Figure 18-8. I2C Communication Flow with 10-Bit Address (Master Receive)
431
Figure 18-10. Programming Model for Slave Receiving (10-Bit Address Mode)
433
Figure 18-9. Programming Model for Slave Transmitting Mode (10-Bit Address Mode)
433
Figure 18-11. Programming Model for Master Transmitting Mode (10-Bit Address Mode)
434
Figure 18-12. Programming Model for Master Receiving Using Solution a (10-Bit Address Mode)
437
Figure 18-13. Programming Model for Master Receiving Mode Using Solution B
439
Table18-2. Event Status Flags
443
Table18-3. I2C Error Flags
443
Figure 19-1. Block Diagram of SPI
457
Table 19-1. SPI Signal Description
457
Figure 19-2. SPI Timing Diagram in Normal Mode
458
Table 19-2. Quad-SPI Signal Description
458
Figure 19-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
459
Table 19-3. NSS Function in Slave Mode
459
Table 19-4. NSS Function in Master Mode
460
Table 19-5. SPI Operation Modes
460
Figure 19-4. a Typical Full-Duplex Connection
462
Figure 19-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
462
Figure 19-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
462
Figure 19-7. a Typical Bidirectional Connection
462
Figure 19-8. Timing Diagram of TI Master Mode with Discontinuous Transfer
464
Figure 19-10. Timing Diagram of TI Slave Mode
465
Figure 19-9. Timing Diagram of TI Master Mode with Continuous Transfer
465
Figure 19-11. Timing Diagram of NSS Pulse with Continuous Transmit
466
Figure 19-12. Timing Diagram of Quad Write Operation in Quad-SPI Mode
467
Figure 19-13. Timing Diagram of Quad Read Operation in Quad-SPI Mode
468
Table 19-6. SPI Interrupt Requests
470
Figure 19-14. Block Diagram of I2S
471
Figure 19-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
472
Figure 19-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
472
Figure 19-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
473
Figure 19-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
473
Figure 19-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
473
Figure 19-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
473
Figure 19-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
474
Figure 19-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
474
Figure 19-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
474
Figure 19-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
474
Figure 19-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
474
Figure 19-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
475
Figure 19-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
475
Figure 19-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
475
Figure 19-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
475
Figure 19-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
475
Figure 19-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
476
Figure 19-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
476
Figure 19-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
476
Figure 19-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
476
Figure 19-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
477
Figure 19-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
477
Figure 19-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
477
Figure 19-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
477
Figure 19-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
477
Figure 19-41. PCM Standard Short Frame Synchronization Mode Timing Diagram
477
Figure 19-42. PCM Standard Short Frame Synchronization Mode Timing Diagram
477
Figure19-40. PCM Standard Short Frame Synchronization Mode Timing Diagram
477
Figure 19-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
478
Figure 19-45. PCM Standard Long Frame Synchronization Mode Timing Diagram
478
Figure19-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
478
Figure 19-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
479
Figure 19-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
479
Figure 19-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
479
Figure 19-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
479
Figure 19-50. PCM Standard Long Frame Synchronization Mode Timing Diagram
479
Figure 19-51. Block Diagram of I2S Clock Generator
480
Table 19-7. I2S Bitrate Calculation Formulas
480
Figure 19-52. I2S Initialization Sequence
481
Table 19-8. Audio Sampling Frequency Calculation Formulas
481
Table 19-9. Direction of I2S Interface Signals for each Operation Mode
481
Figure 19-53. I2S Master Reception Disabling Sequence
484
Table 19-10. I2S Interrupt
486
Figure 20-1. SDIO "No Response" and "No Data" Operations
499
Figure 20-2. SDIO Multiple Blocks Read Operation
500
Figure 20-3. SDIO Multiple Blocks Write Operation
500
Figure 20-4. SDIO Sequential Read Operation
500
Figure 20-5. SDIO Sequential Write Operation
501
Figure 20-6. SDIO Block Diagram
501
Table 20-1. SDIO I/O Definitions
502
Figure 20-7. Command Token Format
508
Table 20-2. Command Format
508
Table 20-3. Card Command Classes (Cccs)
509
Table 20-4. Basic Commands (Class 0)
511
Table 20-5. Block-Oriented Read Commands (Class 2)
513
Table 20-6. Stream Read Commands (Class 1) and Stream Write Commands (Class 3)
514
Table 20-7. Block-Oriented Write Commands (Class 4)
514
Table 20-8. Erase Commands (Class 5)
515
Table 20-10. Lock Card (Class 7)
516
Table 20-9. Block Oriented Write Protection Commands (Class 6)
516
Table 20-11. Application-Specific Commands (Class 8)
517
Table 20-12. I/O Mode Commands (Class 9)
518
Table 20-13. Switch Function Commands (Class 10)
519
Figure 20-8. Response Token Format
520
Table 20-14. Response R1
520
Table 20-15. Response R2
521
Table 20-16. Response R3
521
Table 20-17. Response R4 for MMC
521
Table 20-18. Response R4 for SD I/O
522
Table 20-19. Response R5 for MMC
522
Table 20-20. Response R5 for SD I/O
522
Table 20-21. Response R6
522
Figure 20-9. 1-Bit Data Bus Width
523
Table 20-22. Response R7
523
Figure 20-10. 4-Bit Data Bus Width
524
Figure 20-11. 8-Bit Data Bus Width
524
Table 20-23. Card Status
525
Table 20-24. SD Status
528
Table 20-25. Performance Move Field
529
Table 20-26. AU_SIZE Field
530
Table 20-27. Maximum AU Size
530
Table 20-28. Erase Size Field
530
Table 20-29. Erase Timeout Field
531
Table 20-30. Erase Offset Field
531
Table 20-31. Lock Card Data Structure
540
Figure 20-12. Read Wait Control by Stopping SDIO_CLK
542
Figure 20-13. Read Wait Operation Using SDIO_DAT[2]
542
Figure 20-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
543
Figure 20-15. Read Interrupt Cycle Timing
544
Figure 20-16. Write Interrupt Cycle Timing
544
Figure 20-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
545
Figure 20-18. Multiple Block 4-Bit Write Interrupt Cycle Timing
545
Figure 20-19. the Operation for Command Completion Disable Signal
546
Table 20-32. Sdio_Respx Register at Different Response Type
551
Figure 21-1. the EXMC Block Diagram
562
Figure 21-2. EXMC Memory Banks
563
Figure 21-3. Four Regions of Bank0 Address Mapping
563
Figure 21-4. NAND/PC Card Address Mapping
565
Figure 21-5. Diagram of Bank1 Common Space
565
Table 21-1. nor Flash Interface Signals Description
566
Table 21-2. PSRAM Non-Muxed Signal Description
567
Table 21-3. EXMC Bank 0 Supports All Transactions
567
Table 21-4. nor / PSRAM Controller Timing Parameters
568
Table 21-5. Exmc_Timing Models
569
Figure 21-6. Mode 1 Read Access
570
Figure 21-7. Mode 1 Write Access
570
Table 21-6. Mode 1 Related Registers Configuration
570
Figure 21-8. Mode a Read Access
571
Figure 21-9. Mode a Write Access
572
Table 21-7. Mode a Related Registers Configuration
572
Figure 21-10. Mode 2/B Read Access
573
Figure 21-11. Mode 2 Write Access
574
Figure 21-12. Mode B Write Access
574
Table 21-8. Mode 2/B Related Registers Configuration
574
Figure 21-13. Mode C Read Access
575
Figure 21-14. Mode C Write Access
576
Table 21-9. Mode C Related Registers Configuration
576
Figure 21-15. Mode D Read Access
577
Figure 21-16. Mode D Write Access
578
Table 21-10. Mode D Related Registers Configuration
578
Figure 21-17. Multiplex Mode Read Access
579
Figure 21-18. Multiplex Mode Write Access
579
Table 21-11. Multiplex Mode Related Registers Configuration
580
Figure 21-19. Read Access Timing Diagram under Async-Wait Signal Assertion
581
Figure 21-20. Write Access Timing Diagram under Async-Wait Signal Assertion
581
Figure 21-21. Read Timing of Synchronous Multiplexed Burst Mode
583
Table 21-12. Timing Configurations of Synchronous Multiplexed Read Mode
583
Figure 21-22. Write Timing of Synchronous Multiplexed Burst Mode
584
Table 21-13. Timing Configurations of Synchronous Multiplexed Write Mode
584
Table 21-14. 8-Bit or 16-Bit NAND Interface Signal
585
Table 21-15. 16-Bit PC Card Interface Signal
586
Table 21-16. Bank1/2/3 of EXMC Support the Memory and Access Mode
586
Figure 21-23. Access Timing of Common Memory Space of PC Card Controller
587
Table 21-17. NAND Flash or PC Card Programmable Parameters
587
Figure 21-24. Access to None "NCE Don't Care" NAND Flash
588
Figure 22-1. CAN Module Block Diagram
603
Figure 22-2. Transmission Register
605
Figure 22-3. State of Transmit Mailbox
606
Figure 22-4. Reception Register
607
Figure 22-10. 16-Bit List Mode Filter
609
Figure 22-5. 32-Bit Filter
609
Figure 22-6. 16-Bit Filter
609
Figure 22-7. 32-Bit Mask Mode Filter
609
Figure 22-8. 16-Bit Mask Mode Filter
609
Figure 22-9. 32-Bit List Mode Filter
609
Table 22-1. 32-Bit Filter Number
610
Table 22-2. Filtering Index
611
Figure 22-11. the Bit Time
613
Figure 23-1. USBFS Block Diagram
636
Table 23-1. USBFS Signal Description
636
Figure 23-2. Connection with Host or Device Mode
637
Figure 23-3. Connection with OTG Mode
638
Figure 23-4. State Transition Diagram of Host Port
638
Figure 23-5. HOST Mode FIFO Space in SRAM
643
Figure 23-6. Host Mode FIFO Access Register Map
643
Figure 23-7. Device Mode FIFO Space in SRAM
644
Figure 23-8. Device Mode FIFO Access Register Map
644
Table 23-2. USBFS Global Interrupt
649
Table 24-1. Revision History
709
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