Inserted Data Register X (Adc_Idatax) (X= 0; Regular Data Register (Adc_Rdata) - GigaDevice Semiconductor GD32VF103 User Manual

11.8.13.

Inserted data register x (ADC_IDATAx) (x= 0..3)

Address offset: 0x3C + 0x4*x,(x=0..3)
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31 30 29
15 14 13
Bits Fields
31:16 Reserved
15:0 IDATAn[15:0]
11.8.14.

Regular data register (ADC_RDATA)

Address offset: 0x4C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
31 30 29
15 14 13
Bits Fields
31:16 ADC1RDTR[15:0]
15:0 RDATA[15:0]
0
28 27 26 25
12 11 10 9
Descriptions
Must be kept at reset value
Inserted number n conversion data
These bits contain the number n conversion result, which is read only.
28 27 26 25
12 11 10 9
Descriptions
ADC1 regular channel data
In ADC0: In sync mode, these bits contain the regular data of ADC1.
In ADC1: these bits are not used.
Regular channel data
These bits contain the conversion result from regular channel, which is read only.
GD32VF103 User Manual
ISQ3
24 23 22 21
Reserved
8 7 6
IDATAn[15:0]
r
24 23 22 21
ADC1RDTR[15:0]
r
8 7 6
RDATA[15:0]
r
20 19 18
5 4 3 2
20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
185