Clock Interrupt Register (Rcu_Int) - GigaDevice Semiconductor GD32VF103 User Manual

3:2 SCSS[1:0]
1:0 SCS[1:0]
5.3.3.

Clock interrupt register (RCU_INT)

Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31 30 29
15 14 13
PLL2 PLL1
Reserved
STBIE STBIE
rw rw
0xxx: CK_SYS selected
1000: (CK_SYS / 2) selected
1001: (CK_SYS / 4) selected
1010: (CK_SYS / 8) selected
1011: (CK_SYS / 16) selected
1100: (CK_SYS / 64) selected
1101: (CK_SYS / 128) selected
1110: (CK_SYS / 256) selected
1111: (CK_SYS / 512) selected
System clock switch status
Set and reset by hardware to indicate the clock source of system clock.
00: select CK_IRC8M as the CK_SYS source
01: select CK_HXTAL as the CK_SYS source
10: select CK_PLL as the CK_SYS source
11: reserved
System clock switch
Set by software to select the CK_SYS source. Because the change of CK_SYS has
inherent latency, software should read SCSS to confirm whether the switching is
complete or not. The switch will be forced to IRC8M when leaving Deep-sleep and
Standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL
is selected directly or indirectly as the clock source of CK_SYS
00: select CK_IRC8M as the CK_SYS source
01: select CK_HXTAL as the CK_SYS source
10: select CK_PLL as the CK_SYS source
11: reserved
28 27 26 25
Reserved
12 11 10
PLL HXTAL IRC8M LXTAL
STBIE STBIE STBIE STBIE
rw rw rw rw
24 23 22
PLL2
CKMIC
STBIC
w w
9 8 7 6
IRC40K PLL2
CKMIF
STBIE STBIF
rw r r
GD32VF103 User Manual
21 20 19
PLL1 PLL HXTAL
STBIC STBIC STBIC
w w w
5 4 3
PLL1 PLL HXTAL
STBIF STBIF STBIF
r r r
18 17 16
IRC8M LXTAL IRC40K
STBIC STBIC STBIC
w w w
2 1 0
IRC8M LXTAL IRC40K
STBIF STBIF STBIF
r r r
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