GigaDevice Semiconductor GD32VF103 User Manual page 255

4 DIR
3 SPM
2 UPS
1 UPDIS
0 CEN
Control register 1 (TIMERx_CTL1)
Address offset: 0x04
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
15 14 13
Reserved ISO3 ISO2N
After the counter is enabled, cannot be switched from 0x00 to non 0x00.
Direction
0: Count up
1: Count down
This bit is read only when the timer is configured in center-aligned mode or encoder
mode.
Single pulse mode.
0: Counter continues after update event.
1: The CEN is cleared by hardware and the counter stops at next update event.
Update source
This bit is used to select the update event sources by software.
0: Any of the following events generate an update interrupt or DMA request:
The UPG bit is set
The counter generates an overflow or underflow event
The slave mode controller generates an update event.
1: Only counter overflow/underflow generates an update interrupt or DMA request.
Update disable.
This bit is used to enable or disable the update event generation.
0: update event enable. The update event is generate and the buffered registers are
loaded with their preloaded values when one of the following events occurs:
The UPG bit is set
The counter generates an overflow or underflow event
The slave mode controller generates an update event.
1: update event disable. The buffered registers keep their value, while the counter
and the prescaler are reinitialized if the UG bit is set or if the slave mode controller
generates a hardware reset event.
Counter enable
0: Counter disable
1: Counter enable
The CEN bit must be set by software when timer works in external clock, pause
mode and encoder mode. While in event mode, the hardware can set the CEN bit
automatically.
12 11 10
ISO2 ISO1N ISO1 ISO0N
9 8 7 6
ISO0 TI0S
GD32VF103 User Manual
5 4 3
MMC[2:0] DMAS
2 1 0
CCUC Reserved CCSE
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