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GigaDevice Semiconductor GD32F10 Series User Manual

GigaDevice Semiconductor GD32F10 Series User Manual

Arm cortex-m3 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32F10x

Arm

Cortex

-M3 32-bit MCU

®

®

User Manual

Revision 2.6

( Jun. 2022 )

Table of Contents

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Summary of Contents for GigaDevice Semiconductor GD32F10 Series

Page 1 GigaDevice Semiconductor Inc. GD32F10x Cortex -M3 32-bit MCU ® ® User Manual Revision 2.6 ( Jun. 2022 )
Page 2: Table Of Contents
GD32F10x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................18 List of Tables ........................ 25 1. System and memory architecture ................ 29 ® ® -M3 processor ..................29 1.1. Cortex System architecture ....................30 1.2.
Page 3 GD32F10x User Manual 2.4.4. Status register 0 (FMC_STAT0) .................... 55 2.4.5. Control register 0 (FMC_CTL0) .................... 56 2.4.6. Address register 0 (FMC_ADDR0) ..................57 2.4.7. Option byte status register (FMC_OBSTAT) ................. 58 2.4.8. Erase/Program Protection register (FMC_WP) ..............58 2.4.9. Unlock key register 1(FMC_KEY1) ..................
Page 4 GD32F10x User Manual Clock control unit (CCTL) ..................80 5.2. 5.2.1. Overview ..........................80 5.2.2. Characteristics ........................82 5.2.3. Function overview ......................... 82 Register definition ..................... 86 5.3. 5.3.1. Control register (RCU_CTL) ....................86 5.3.2. Clock configuration register 0 (RCU_CFG0) ................ 87 5.3.3.
Page 5 GD32F10x User Manual 6.2. Characteristics ......................144 6.3. Function overview ....................144 6.4. External interrupt and event (EXTI) block diagram ..........148 6.5. External Interrupt and Event function overview ............ 149 6.6. Register definition ....................150 6.6.1. Interrupt enable register (EXTI_INTEN) ................150 6.6.2.
Page 6 GD32F10x User Manual 7.5.3. Port input status register (GPIOx_ISTAT, x=A..G) .............. 169 7.5.4. Port output control register (GPIOx_OCTL, x=A..G) ............169 7.5.5. Port bit operate register (GPIOx_BOP, x=A..G)..............170 7.5.6. Port bit clear register (GPIOx_BC, x=A..G) ................ 170 7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..G) ............ 171 7.5.8.
Page 7 GD32F10x User Manual 9.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ........202 9.5.6. Channel x memory base address register (DMA_CHxMADDR) ........202 Debug (DBG) ..................... 204 Overview ....................... 204 10.1. JTAG/SW function overview ................204 10.2. 10.2.1. Switch JTAG or SW interface ..................... 204 10.2.2.
Page 8 GD32F10x User Manual Register definition ....................224 11.7. 11.7.1. Status register (ADC_STAT) ....................224 11.7.2. Control register 0 (ADC_CTL0) ..................225 11.7.3. Control register 1 (ADC_CTL1) ..................226 11.7.4. Sample time register 0 (ADC_SAMPT0) ................228 11.7.5. Sample time register 1 (ADC_SAMPT1) ................229 11.7.6.
Page 9 GD32F10x User Manual Free watchdog timer (FWDGT) ................248 13.1. 13.1.1. Overview ..........................248 13.1.2. Characteristics ........................248 13.1.3. Function overview ....................... 248 13.1.4. Register definition ....................... 251 Window watchdog timer (WWDGT) ..............254 13.2. 13.2.1. Overview ..........................254 13.2.2. Characteristics ........................
Page 10 GD32F10x User Manual 15.2.4. Function overview ....................... 326 15.2.5. Register definition ....................... 342 General level1 timer (TIMERx, x=8, 11) ............... 364 15.3. 15.3.1. Overview ..........................364 15.3.2. Characteristics ........................364 15.3.3. Block diagram ........................365 15.3.4. Function overview ....................... 365 15.3.5.
Page 11 GD32F10x User Manual 16.4.3. Baud rate register (USART_BAUD) ..................446 16.4.4. Control register 0 (USART_CTL0) ..................447 16.4.5. Control register 1 (USART_CTL1) ..................449 16.4.6. Control register 2 (USART_CTL2) ..................450 16.4.7. Guard time and prescaler register (USART_GP) ............... 452 Inter-integrated circuit interface (I2C) .............
Page 12 GD32F10x User Manual 18.3.4. NSS function ........................485 18.3.5. SPI operation modes ......................487 18.3.6. DMA function........................491 18.3.7. CRC function........................491 18.3.8. SPI interrupts ........................492 I2S function overview ..................493 18.4. 18.4.1. I2S block diagram ....................... 493 18.4.2. I2S signal description ......................
Page 13 GD32F10x User Manual 19.6.4. Single block or multiple block read ..................556 19.6.5. Stream write and stream read (MMC only) ................. 557 19.6.6. Erase ........................... 559 19.6.7. Bus width selection ......................560 19.6.8. Protection management ...................... 560 19.6.9. Card Lock/Unlock operation ....................560 Specific operations ....................
Page 14 GD32F10x User Manual 21.2. Characteristics ..................... 623 21.3. Function overview ....................624 21.3.1. Working mode ........................624 21.3.2. Communication modes ....................... 625 21.3.3. Data transmission ....................... 626 21.3.4. Data reception........................628 21.3.5. Filtering function........................630 21.3.6. Time-triggered communication ................... 633 21.3.7.
Page 15 GD32F10x User Manual 22.3.1. Interface configuration ......................661 22.3.2. MAC function overview ....................... 666 22.3.3. MAC statistics counters: MSC .................... 677 22.3.4. Wake up management: WUM ..................... 678 22.3.5. Precision time protocol: PTP ....................681 22.3.6. DMA controller description ....................685 22.3.7.
Page 16 GD32F10x User Manual 22.4.33. PTP time stamp control register (ENET_PTP_TSCTL) ..........733 22.4.34. PTP subsecond increment register (ENET_PTP_SSINC)..........734 22.4.35. PTP time stamp high register (ENET_PTP_TSH) ............735 22.4.36. PTP time stamp low register (ENET_PTP_TSL) ............735 22.4.37. PTP time stamp update high register (ENET_PTP_TSUH) ........... 736 22.4.38.
Page 17 GD32F10x User Manual 23.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in [0..7] 23.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in [0..7] 23.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in [0..7] 23.7.10.
Page 18: List Of Figures
GD32F10x User Manual List of Figures -M3 processor ................. 30 ® Figure 1-1. The structure of the Cortex Figure 1-2. GD32F10x Medium-density series system architecture ............. 32 Figure 1-3. GD32F10x High-density series system architecture ............33 Figure 1-4. GD32F10x Extra-density series system architecture ............34 Figure 1-5.
Page 19 GD32F10x User Manual Figure 11-10. Routine follow-up fast mode (the CTN bit of ADCs are set) ........222 Figure 11-11. Routine follow-up slow mode ..................222 Figure 12-1. DAC block diagram ......................235 Figure 12-2. DAC LFSR algorithm ......................237 Figure 12-3.
Page 20 GD32F10x User Manual Figure 15-35. Timing chart of up counting mode, change TIMERx_CAR ongoing ......329 Figure 15-36. Timing chart of down counting mode, PSC=0/2 ............330 Figure 15-37. Timing chart of down counting mode, change TIMERx_CAR ongoing ...... 331 Figure 15-38.
Page 21 GD32F10x User Manual Figure 15-78. Timing chart of up counting mode, PSC=0/2 ..............420 Figure 15-79. Timing chart of up counting mode, change TIMERx_CAR ongoing ......420 Figure 16-1. USART module block diagram ..................430 Figure 16-2. USART character frame (8 bits data and 1 stop bit) ............430 Figure 16-3.
Page 22 GD32F10x User Manual Figure 18-12. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ..... 495 Figure 18-13. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ..... 496 Figure 18-14. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ..... 496 Figure 18-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ..... 496 Figure 18-16.
Page 23 GD32F10x User Manual CHLEN=1, CKPL=1) ......................... 501 Figure 18-42. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ......................... 502 Figure 18-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ......................... 502 Figure 18-44. Block diagram of I2S clock generator ................502 Figure 18-45.
Page 24 GD32F10x User Manual Figure 20-17. Multiplex mode read access ................... 600 Figure 20-18. Multiplex mode write access ................... 600 Figure 20-19. Read access timing diagram under async-wait signal assertion ....... 602 Figure 20-20. Write access timing diagram under async-wait signal assertion ....... 602 Figure 20-21.
Page 25: List Of Tables
GD32F10x User Manual List of Tables Table 1-1. The interconnection relationship of the AHB interconnect matrix ........30 Table 1-2. Memory map of GD32F10x devices ..................36 Table 1-3. Boot modes ..........................40 Table 2-1. GD32F10x_MD .......................... 44 Table 2-2. GD32F10x_CL and GD32F10x_HD, GD32F10x_XD .............. 45 Table 2-3.
Page 26 GD32F10x User Manual ) ................256 Table 13-2. Min/max timeout value at 54 MHz (f PCLK1 Table 15-1. Timers (TIMERx) are divided into five sorts ..............268 Table 15-2. Complementary outputs controlled by parameters ............285 Table 15-3. Counting direction in different quadrature decoder mode..........288 Table 15-4.
Page 27 GD32F10x User Manual Table 19-16. Response R3 ........................542 Table 19-17. Response R4 for MMC ....................... 542 Table 19-18. Response R4 for SD I/O ..................... 543 Table 19-19. Response R5 for MMC ....................... 543 Table 19-20. Response R5 for SD I/O ..................... 543 Table 19-21.
Page 28 GD32F10x User Manual Table 23-2. Double-buffering buffer flag definition ................758 Table 23-3. Double buffer usage ......................758 Table 23-4. Reception status encoding ....................770 Table 23-5. Endpoint type encoding ...................... 770 Table 23-6. Endpoint kind meaning ....................... 770 Table 23-7. Transmission status encoding ................... 770 Table 24-1.
Page 29: System And Memory Architecture
GD32F10x User Manual System and memory architecture The devices of GD32F10x series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M3 processor. The Arm Cortex -M3 processor includes three AHB buses ® ® known as I-Code, D-Code and System buses. All memory accesses of the Arm Cortex processor are executed on the three buses according to the different purposes and the target memory spaces.
Page 30: System Architecture
GD32F10x User Manual ® Figure 1-1. The structure of the Cortex -M3 processor Cortex-M3 processor Nested Interrupts and Vectored Power control Interrupt Cortex-M3 core Embedded Controller Trace (NVIC) Macrocell (ETM) Wake-up Interrupt Controller Data (WIC) Flash Patch Watchpoint Breakpoint And Trace (FPB) (DWT) Serial-Wire...
Page 31 GD32F10x User Manual IBUS DBUS SBUS DMA0 DMA1 ENET EXMC APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, including IBUS, DBUS, SBUS, DMA0, DMA1 and ENET. IBUS is the instruction bus of the ®...
Page 32: Figure 1-2. Gd32F10X Medium-Density Series System Architecture
GD32F10x User Manual Figure 1-2. GD32F10x Medium-density series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M3 Memory Controller Processor : 108MHz Dbus Fmax:108MHz 1.2V NVIC Master AHB Peripherals Slave 8MHz SRAM GP DMA 7 chs SRAM Controller Master Slave...
Page 33: Figure 1-3. Gd32F10X High-Density Series System Architecture
GD32F10x User Manual Figure 1-3. GD32F10x High-density series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M3 Memory Controller Processor : 108MHz Dbus Fmax:108MHz SDIO 1.2V NVIC Master AHB Peripherals Slave 8MHz SRAM GP DMA 12 chs SRAM Controller Master...
Page 34: Figure 1-4. Gd32F10X Extra-Density Series System Architecture
GD32F10x User Manual Figure 1-4. GD32F10x Extra-density series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M3 Memory Controller : 108MHz Processor Dbus Fmax:108MHz SDIO 1.2V NVIC Master AHB Peripherals Slave 8MHz SRAM GP DMA 12 chs SRAM Controller Master...
Page 35: Memory Map
GD32F10x User Manual Figure 1-5. GD32F10x Connectivity line series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M3 Memory Controller : 108MHz Processor Dbus Fmax:108MHz USBFS 1.2V NVIC Master Slave AHB Peripherals 8 MHz SRAM GP DMA 12 chs SRAM Controller Master...
Page 36: Table 1-2. Memory Map Of Gd32F10X Devices
GD32F10x User Manual reduce the software complexity of repeated implementation of different device vendors. In the ® ® map, some regions are used by the Arm Cortex -M3 system peripherals which can not be modified. However, the other regions are available to the vendors. Table 1-2.
Page 37 GD32F10x User Manual Pre-defined Address Peripherals Regions 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF SDIO 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved...
Page 38 GD32F10x User Manual Pre-defined Address Peripherals Regions 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF CAN1 0x4000 6400 - 0x4000 67FF CAN0 Shared USBD/CAN...
Page 39: Bit-Banding
GD32F10x User Manual Pre-defined Address Peripherals Regions 0x2000 0000 - 0x2000 4FFF 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF B000 - 0x1FFF F7FF Boot loader 0x1FFF 7A10 - 0x1FFF AFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 0000 - 0x1FFF 77FF Reserved...
Page 40: On-Chip Sram Memory
GD32F10x User Manual bit_word_addr = 0x2200 0000 + (0x200 * 32)+ (7 * 4)= 0x2200 401C (1-2) Writing to address 0x2200 401C will cause bit 7 of address 0x2000 0200 change while a read to address 0x2200 401C will return 0x01 or 0x00 according to the value of bit 7 at the SRAM address 0x2000 0200.
Page 41: Device Electronic Signature
GD32F10x User Manual Boot mode selection pins Selected boot source Boot1 Boot0 Boot loader On-chip SRAM Note: When the boot source is hoped to be set as “Main Flash Memory”, the Boot0 pin has to be connected with GND definitely and can not be floating. ®...
Page 42: Memory Density Information
GD32F10x User Manual Memory density information 1.5.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes. Example: 0x0008 indicates 8 Kbytes.
Page 43: System Configuration Registers
GD32F10x User Manual UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID 1.6. System configuration registers Base address: 0x4002 103C Reset value: 0x0000 0000 Reserved...
Page 44: Flash Memory Controller (Fmc)
GD32F10x User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the first 256K bytes of the flash. It also provides page erase, mass erase, and word/half-word program operations for flash memory.
Page 45: Read Operations
GD32F10x User Manual size Block Name Address Range (bytes) Page 1 0x0800 0400 - 0x0800 07FF Page 2 0x0800 0800 - 0x0800 0BFF … … … Page 127 0x0801 FC00 - 0x0801 FFFF Information Block Boot loader area 0x1FFF F000- 0x1FFF F7FF Option bytes Block Option bytes 0x1FFF F800 - 0x1FFF F80F...
Page 46: Unlock The Fmc_Ctlx Registers
GD32F10x User Manual Unlock the FMC_CTLx registers 2.3.3. After reset, the FMC_CTLx registers are not accessible in write mode, and the LK bit in FMC_CTLx register is 1. An unlocking sequence consists of two write operations to the FMC_KEY0 register to open the access to the FMC_CTL0 register. The two write operations are writing 0x45670123 and 0xCDEF89AB to the FMC_KEY0 register.
Page 47: Mass Erase
GD32F10x User Manual will not provide any notification when this exception occurs, additionally, the page erase operation will be ignored on erase/program protected pages. In this condition, a flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTLx registers is set.
Page 48 GD32F10x User Manual register, or only on bank1 by setting MER bit to 1 in the FMC_CTL1 register, or on entire flash by setting MER bits to 1 in FMC_CTL0 register and FMC_CTL1 register. The following steps show the mass erase register access sequence. ...
Page 49: Main Flash Programming
GD32F10x User Manual Figure 2-2. Process of mass erase operation Start Is the LK bit is 0 Unlock the FMC_CTLx Is the BUSY bit is 0 Set the MER bit Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Main flash programming 2.3.6.
Page 50: Option Bytes Erase
GD32F10x User Manual notable that the word/half word programming operation checks the address if it has been erased. If the address has not been erased, PGERR bit in the FMC_STATx registers will be set when programming the address except 0x0. It is notable that the PG bit must be set before the word/half word programming operation.
Page 51: Option Bytes Modify
GD32F10x User Manual The following steps show the erase sequence.  Unlock the FMC_CTL0 register if necessary.  Check the BUSY bit in FMC_STAT0 register to confirm that no Flash memory operation is in progress (BUSY equal to 0). Otherwise, wait until the operation has finished. ...
Page 52: Table 2-3. Option Byte
GD32F10x User Manual system reset, and the option bytes take effect. The complement option bytes are the opposite of option bytes. When option bytes reload, if the complement option byte and option byte do not match, the OBERR bit in FMC_OBSTAT register is set, and the option byte is set to 0xFF. The OBERR bit is not set if both the option byte and its complement byte are 0xFF.The Table 2-3.
Page 53: Page Erase/Program Protection
GD32F10x User Manual Address Name Description GD32F10x_HD, GD32F10x_XD and GD32F10x_CL. Bit 0 configures the first 4KB flash protection, and so on. These bits totally controls the first 124KB flash protection. WP[31]: Bit 31 controls the protection of the remaining flash memory.
Page 54: Register Definition
GD32F10x User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value WSCNT[2:0] Wait state counter...
Page 55: Option Byte Unlock Key Register (Fmc_Obkey)
GD32F10x User Manual 31:0 KEY[31:0] FMC_CTL0 unlock key These bits are only be written by software. Write KEY[31:0] with keys to unlock FMC_CTL0 register Option byte unlock key register (FMC_OBKEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) OBKEY[31:16] OBKEY[15:0] Bits...
Page 56: Control Register 0 (Fmc_Ctl0)
GD32F10x User Manual WPERR Erase/Program protection error flag bit When erase/program on protected pages, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware.
Page 57: Address Register 0 (Fmc_Addr0)
GD32F10x User Manual This bit can be cleared by software. Reserved Must be kept at reset value FMC_CTL0 lock bit This bit is cleared by hardware when right sequence written to FMC_KEY0 register. This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC.
Page 58: Option Byte Status Register (Fmc_Obstat)
GD32F10x User Manual ADDR[31:16] ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase/program command address bits These bits are configured by software. ADDR bits are the address of flash erase/program command Option byte status register (FMC_OBSTAT) 2.4.7. Address offset: 0x1C Reset value: 0x0XXX XXXX. This register has to be accessed by word (32-bit) Reserved DATA[15:6]...
Page 59: Unlock Key Register 1(Fmc_Key1)
GD32F10x User Manual WP[31:16] WP[15:0] Bits Fields Descriptions 31:0 WP[31:0] Store WP of option bytes block after system reset Unlock key register 1(FMC_KEY1) 2.4.9. Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) KEY[31:16] KEY[15:0] Bits...
Page 60: Control Register 1 (Fmc_Ctl1)
GD32F10x User Manual 31:6 Reserved Must be kept at reset value ENDF End of operation flag bit When the operation executed successfully, this bit is set by hardware. The software can clear it by writing 1. WPERR Erase/Program protection error flag bit When erase/program on protected pages, this bit is set by hardware.
Page 61: Address Register 1 (Fmc_Addr1)
GD32F10x User Manual 0: no interrupt generated by hardware. 1: error interrupt enable Reserved Must be kept at reset value FMC_CTL1 lock bit This bit is cleared by hardware when right sequence written to FMC_KEY1 register. This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC.
Page 62: Wait State Enable Register (Fmc_Wsen)
GD32F10x User Manual These bits are configured by software. ADDR bits are the address of flash erase/program command. Wait state enable register (FMC_WSEN) 2.4.13. Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Resrved Reserved WSEN Bits...
Page 63 GD32F10x User Manual programmed during the chip production.
Page 64: Power Management Unit (Pmu)
GD32F10x User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32F10x series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 65: Backup Domain
GD32F10x User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP WKUPR BREG BKP PAD WKUPN NRST WKUPF SLEEPING Cortex-M3 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V...
Page 66: Vdd
GD32F10x User Manual register with an expected alarm time and enable the alarm function to achieve the RTC timer alarm event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. The details of the RTC configuration Real-time Clock (RTC).
Page 67: Figure 3-3. Waveform Of The Lvd Threshold
GD32F10x User Manual Figure 3-2. Waveform of the POR / PDR 50mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register (PMU_CS), indicates if V is higher or lower than the LVD threshold.
Page 68: Power Domain
GD32F10x User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply is implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 69 GD32F10x User Manual two options to select the Sleep mode entry mechanism.  Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.  Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits from the lowest priority ISR.
Page 70: Table 3-1. Power Saving Mode Summary
GD32F10x User Manual Table 3-1. Power saving mode summary Mode Sleep Deep-sleep Standby All clocks in the 1.2V The 1.2V domain is domain are off power off Description Only CPU clock is off Disable IRC8M, Disable IRC8M, HXTAL and PLL HXTAL and PLL On (normal power On (normal or low power...
Page 71: Register Definition
GD32F10x User Manual 3.4. Register definition PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved BKPWEN LVDT[2:0]...
Page 72: Control And Status Register (Pmu_Cs)
GD32F10x User Manual WURST Wakeup Flag Reset 0: No effect 1: Reset the wakeup flag This bit is always read as 0. STBMOD Standby Mode 0: Enter the Deep-sleep mode when the Cortex -M3 enters SLEEPDEEP mode ® 1: Enter the Standby mode when the Cortex -M3 enters SLEEPDEEP mode ®...
Page 73 GD32F10x User Manual STBF Standby Flag 0: The device has not entered the Standby mode 1: The device has been in the Standby mode This bit is cleared only by a POR/PDR or by setting the STBRST bit in the PMU_CTL register.
Page 74: Backup Registers (Bkp)
GD32F10x User Manual Backup registers (BKP) 4.1. Overview The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, there are forty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action from Standby mode or system reset do not affect these registers.
Page 75: Tamper Detection
GD32F10x User Manual Tamper detection 4.3.2. In order to protect the important user data, the MCU provides the tamper detection function, and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal.
Page 76: Register Definition
GD32F10x User Manual 4.4. Register definition BKP base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..41) 4.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit). DATA [15:0] Bits Fields...
Page 77: Tamper Pin Control Register (Bkp_Tpctl)
GD32F10x User Manual COEN RTC clock calibration output enable 0: Disable RTC clock calibration output 1: Enable RTC clock calibration output When enable, the TAMPER pin will output a clock with the frequency f /64. RTCCLK ASOEN has the priority over COEN. When ASOEN is set, the TAMPER pin will output the RTC alarm or second signal whether COEN is set or not.
Page 78 GD32F10x User Manual Bits Fields Descriptions 15:10 Reserved Must be kept at reset value. Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred This bit is reset by writing 1 to the TIR bit or the TPIE bit being 0. Tamper event flag 0: No tamper event occurred 1: A tamper event occurred...
Page 79: Reset And Clock Unit (Rcu)
GD32F10x User Manual Reset and clock unit (RCU) Medium-, High- and extra-density reset and clock control unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. GD32F10x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset.
Page 80: Clock Control Unit (Cctl)
GD32F10x User Manual  Reset generated when entering Deep-sleep mode when resetting nRST_DPSLP bit in user option bytes (OB_DPSLP_RSTn). A system reset resets the processor core and peripheral IP components except for the SW- DP controller and the backup domain. A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset).
Page 81: Figure 5-2. Clock Tree
GD32F10x User Manual Figure 5-2. Clock tree USBD 48 MHz CK_USBD Prescaler (to USBD) SCS[1:0] 1,1.5,2,2.5 CK_I2S CK_IRC8M I2S enable (to I2S1,2) 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M …,32 108 MHz max Prescaler 108 MHz max (to EXMC) EXMC enable ÷...
Page 82: Characteristics
GD32F10x User Manual The FWDGT is clocked by IRC40K clock, which is forced on when FWDGT started. Characteristics 5.2.2.  4 to 16 MHz High Speed crystal oscillator (HXTAL) .  Internal 8 MHz RC oscillator (IRC8M).  32,768 Hz Low Speed crystal oscillator (LXTAL). ...
Page 83: Figure 5-4. Hxtal Clock Source In Bypass Mode
GD32F10x User Manual Figure 5-4. HXTAL clock source in bypass mode OSCIN OSCOUT Exte rnal cl ock Internal 8M RC oscillators (IRC8M) The internal 8M RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up.
Page 84 GD32F10x User Manual domain control register (RCU_BDCTL). The LXTALSTB flag in the backup domain control register (RCU_BDCTL) will indicate if the LXTAL clock is stable. An interrupt can be generated if the related interrupt enable bit, LXTALSTBIE, in the interrupt register RCU_INT is set when the LXTAL becomes stable.
Page 85: Table 5-1. Clock Output 0 Source Select
GD32F10x User Manual Clock output capability The clock output capability is ranging from 4 MHz to 108 MHz. There are several clock signals can be selected via the CK_OUT0 clock source selection bits, CKOUT0SEL, in the clock configuration register 0 (RCU_CFG0). The corresponding GPIO pin should be configured in the properly alternate function I/O (AFIO) mode to output the selected clock signal.
Page 86: Register Definition
GD32F10x User Manual 5.3. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTALB HXTALST HXTALE Reserved PLLSTB PLLEN Reserved...
Page 87: Clock Configuration Register 0 (Rcu_Cfg0)
GD32F10x User Manual state. HXTALBPS High speed crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0. 0: Disable the HXTAL Bypass mode 1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the input clock.
Page 88 GD32F10x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) ADCPSC[ Reserved PLLMF[4] CKOUT0SEL[2:0] USBDPSC[1:0] PLLMF[3:0] PREDV0 PLLSEL ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value. ADCPSC[2] Bit 2 of ADCPSC see bits 15:14 of RCU_CFG0 PLLMF[4] Bit 4 of PLLMF...
Page 89 GD32F10x User Manual 00111: CK_SYS = CK_PLL x 9 01000: CK_SYS = CK_PLL x 10 01001: CK_SYS = CK_PLL x 11 01010: CK_SYS = CK_PLL x 12 01011: CK_SYS = CK_PLL x 13 01100: CK_SYS = CK_PLL x 14 01101: CK_SYS = CK_PLL x 15 01110: CK_SYS = CK_PLL x 16 01111: CK_SYS = CK_PLL x 16 10000: CK_SYS = CK_PLL x 17...
Page 90 GD32F10x User Manual 110: (CK_APB2 / 8) selected 111: (CK_APB2 / 16) selected 13:11 APB2PSC[2:0] APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 10:8...
Page 91: Clock Interrupt Register (Rcu_Int)
GD32F10x User Manual 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_PLL as the CK_SYS source 11: Reserved Clock interrupt register (RCU_INT) 5.3.3. Address offset: 0x08 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTAL IRC8M LXTAL...
Page 92 GD32F10x User Manual 0: Not reset LXTALSTBIF flag 1: Reset LXTALSTBIF flag IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by software to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag 15:13 Reserved Must be kept at reset value PLLSTBIE PLL stabilization interrupt enable Set and reset by software to enable/disable the PLL stabilization interrupt.
Page 93: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F10x User Manual 1: PLL stabilization interrupt generated HXTALSTBIF HXTAL stabilization interrupt flag Set by hardware when the High speed 4 ~ 16 MHz crystal oscillator clock is stable and the HXTALSTBIE bit is set. Reset when setting the HXTALSTBIC bit by software. 0: No HXTAL stabilization interrupt generated 1: HXTAL stabilization interrupt generated IRC8MSTBIF...
Page 94 GD32F10x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value TIMER10RST Timer 10 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER10 TIMER9RST Timer 9 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER9 TIMER8RST...
Page 95 GD32F10x User Manual 1: Reset the ADC1 ADC0RST ADC0 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC0 PGRST GPIO port G reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port G PFRST GPIO port F reset...
Page 96: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F10x User Manual 1: Reset Alternate Function I/O APB1 reset register (RCU_APB1RST) 5.3.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) CAN0RS USBDRS UART4R UART3R USART2 USART1 Reserved DACRST PMURST BKPIRST Reserved Reserved I2C1RST I2C0RST Reserved...
Page 97 GD32F10x User Manual 1: Reset the USBD I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C0 UART4RST UART4 reset This bit is set and reset by software.
Page 98 GD32F10x User Manual 0: No reset 1: Reset the WWDGT 10:9 Reserved Must be kept at reset value TIMER13RST TIMER13 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER13 TIMER12RST TIMER12 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER12 TIMER11RST...
Page 99: Ahb Enable Register (Rcu_Ahben)
GD32F10x User Manual 1: Reset the TIMER1 AHB enable register (RCU_AHBEN) 5.3.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved FMCSPE SRAMSP Reserved SDIOEN Reserved EXMCEN Reserved CRCEN Reserved Reserved DMA1EN DMA0EN Bits Fields...
Page 100: Apb2 Enable Register (Rcu_Apb2En)
GD32F10x User Manual SRAMSPEN SRAM interface clock enable when sleep mode This bit is set and reset by software to enable/disable SRAM interface clock during Sleep mode. 0: Disabled SRAM interface clock during Sleep mode. 1: Enabled SRAM interface clock during Sleep mode DMA1EN DMA1 clock enable This bit is set and reset by software.
Page 101 GD32F10x User Manual 0: Disabled TIMER8 clock 1: Enabled TIMER8 clock 18:16 Reserved Must be kept at reset value ADC2EN ADC2 clock enable This bit is set and reset by software. 0: Disabled ADC2 clock 1: Enabled ADC2 clock USART0EN USART0 clock enable This bit is set and reset by software.
Page 102: Apb1 Enable Register (Rcu_Apb1En)
GD32F10x User Manual 1: Enabled GPIO port F clock PEEN GPIO port E clock enable This bit is set and reset by software. 0: Disabled GPIO port E clock 1: Enabled GPIO port E clock PDEN GPIO port D clock enable This bit is set and reset by software.
Page 103 GD32F10x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value DACEN DAC clock enable This bit is set and reset by software. 0: Disabled DAC clock 1: Enabled DAC clock PMUEN PMU clock enable This bit is set and reset by software. 0: Disabled PMU clock 1: Enabled PMU clock BKPIEN...
Page 104 GD32F10x User Manual 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software. 0: Disabled UART3 clock 1: Enabled UART3 clock USART2EN USART2 clock enable This bit is set and reset by software. 0: Disabled USART2 clock 1: Enabled USART2 clock USART1EN USART1 clock enable...
Page 105: Backup Domain Control Register (Rcu_Bdctl)
GD32F10x User Manual This bit is set and reset by software. 0: Disabled TIMER11 clock 1: Enabled TIMER11 clock TIMER6EN TIMER6 clock enable This bit is set and reset by software. 0: Disabled TIMER6 clock 1: Enabled TIMER6 clock TIMER5EN TIMER5 clock enable This bit is set and reset by software.
Page 106 GD32F10x User Manual LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LXTALEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by software.
Page 107: Reset Source/Clock Register (Rcu_Rstsck)
GD32F10x User Manual Reset source/clock register (RCU_RSTSCK) 5.3.10. Address offset: 0x24 Reset value: 0x0C00 0000, aLL reset flags reset by power reset only, RSTFC/IRC40KEN reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGT Reserved RSTFC Reserved...
Page 108: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F10x User Manual 1: Power reset generated EPRSTF External pin reset flag Set by hardware when an external pin reset generated. Reset by writing 1 to the RSTFC bit. 0: No external pin reset generated 1: External pin reset generated Reserved Must be kept at reset value RSTFC...
Page 109 GD32F10x User Manual 010: The core voltage is 1.0V in Deep-sleep mode 011: The core voltage is 0.9V in Deep-sleep mode 1xx: Reserved...
Page 110: Connectivity Line Devices: Reset And Clock Control Unit (Rcu)
GD32F10x User Manual Connectivity line devices: Reset and clock control unit (RCU) 5.4. Reset control unit (RCTL) Overview 5.4.1. GD32F10x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 111: Clock Control Unit (Cctl)
GD32F10x User Manual A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset). Figure 5-5. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us pulse System Reset FWDGT_RSTn generator SW_RSTn...
Page 112: Figure 5-6. Clock Tree
GD32F10x User Manual Figure 5-6. Clock tree (to FMC) USB OTG 48 MHz CK_USBFS Prescaler (to USBFS) SCS[1:0] 1,1.5,2,2.5 CK_FMC CK_IRC8M 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M …,32 108 MHz max Prescaler EXMC enable 108 MHz max (to EXMC) ÷...
Page 113: Characteristics
GD32F10x User Manual select by ENET_PHY_SEL bit in AFIO_PCF0 register. The RTC is clocked by LXTAL clock or IRC40K clock or HXTAL clock divided by 128 (defined which select by RTCSRC bit in backup domain control register (RCU_BDCTL). After the RTC select HXTAL clock divided by 128, the clock disappeared when the 1.2V core domain power off.
Page 114: Figure 5-8. Hxtal Clock Source In Bypass Mode
GD32F10x User Manual generated if the related interrupt enable bit HXTALSTBIE in the Interrupt register RCU_INT is set. At this point the HXTAL clock can be used directly as the system clock source or the PLL input clock. Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the control register RCU_CTL.
Page 115 GD32F10x User Manual The PLL1 can be switched on or off by using the PLL1EN bit in the RCU_CTL Register. The PLL1STB flag in the RCU_CTL Register will indicate if the PLL1 clock is stable. An interrupt can be generated if the related interrupt enable bit, PLL1STBIE, in the RCU_INT register, is set as the PLL1 becomes stable.
Page 116: Table 5-3. Clock Output 0 Source Select
GD32F10x User Manual source is directly or indirectly (by PLL) used as the CK_SYS, it is not possible to stop it. HXTAL clock monitor (CKM) The HXTAL clock monitor function is enabled by the HXTAL clock monitor enable bit, CKMEN, in the control register (RCU_CTL).
Page 117 GD32F10x User Manual...
Page 118: Register Definition
GD32F10x User Manual 5.6. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.6.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB Reserved...
Page 119 GD32F10x User Manual Set by hardware to indicate if the PLL output clock is stable and ready for use. 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock.
Page 120: Clock Configuration Register 0 (Rcu_Cfg0)
GD32F10x User Manual ± 1%. Reserved Must be kept at reset value. IRC8MSTB Internal 8MHz RC oscillator stabilization flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable...
Page 121 GD32F10x User Manual 1000: CK_PLL1 clock selected 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 23:22 USBFSPSC[1:0] USBFS clock prescaler selection Set and reset by software to control the USBFS clock prescaler value. The USBFS clock must be 48MHz.
Page 122 GD32F10x User Manual 11011: (PLL source clock x 28) 11100: (PLL source clock x 29) 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 32) PREDV0_LSB The LSB of PREDV0 division factor This bit is the same bit as PREDV0 division factor bit [0] from RCU_CFG1.
Page 123: Clock Interrupt Register (Rcu_Int)
GD32F10x User Manual AHBPSC[3:0] AHB prescaler selection Set and reset by software to control the AHB clock division ratio 0xxx: CK_SYS selected 1000: (CK_SYS / 2) selected 1001: (CK_SYS / 4) selected 1010: (CK_SYS / 8) selected 1011: (CK_SYS / 16) selected 1100: (CK_SYS / 64) selected 1101: (CK_SYS / 128) selected 1110: (CK_SYS / 256) selected...
Page 124 GD32F10x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value CKMIC HXTAL clock stuck interrupt clear Write 1 by software to reset the CKMIF flag. 0: Not reset CKMIF flag 1: Reset CKMIF flag PLL2STBIC PLL2 stabilization interrupt clear Write 1 by software to reset the PLL2STBIF flag.
Page 125 GD32F10x User Manual 0: Disable the PLL2 stabilization interrupt 1: Enable the PLL2 stabilization interrupt PLL1STBIE PLL1 stabilization interrupt enable Set and reset by software to enable/disable the PLL1 stabilization interrupt. 0: Disable the PLL1 stabilization interrupt 1: Enable the PLL1 stabilization interrupt PLLSTBIE PLL stabilization interrupt enable Set and reset by software to enable/disable the PLL stabilization interrupt.
Page 126: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F10x User Manual Reset when setting the PLL1STBIC bit by software. 0: No PLL1 stabilization interrupt generated 1: PLL1 stabilization interrupt generated PLLSTBIF PLL stabilization interrupt flag Set by hardware when the PLL is stable and the PLLSTBIE bit is set. Reset when setting the PLLSTBIC bit by software.
Page 127 GD32F10x User Manual USART0 TIMER7R TIMER0R ADC1RS ADC0RS Reserved SPI0RST PGRST PFRST PERST PDRST PCRST PBRST PARST Reserved AFRST Bits Fields Descriptions 31:15 Reserved Must be kept at reset value USART0RST USART0 reset This bit is set and reset by software. 0: No reset 1: Reset the USART0 TIMER7RST...
Page 128: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F10x User Manual 1: Reset the GPIO port F PERST GPIO port E reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port E PDRST GPIO port D reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port D PCRST...
Page 129 GD32F10x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value DACRST DAC reset This bit is set and reset by software. 0: No reset 1: Reset DAC unit PMURST Power control reset This bit is set and reset by software. 0: No reset 1: Reset power control unit BKPIRST...
Page 130 GD32F10x User Manual This bit is set and reset by software. 0: No reset 1: Reset the UART3 USART2RST USART2 reset This bit is set and reset by software. 0: No reset 1: Reset the USART2 USART1RST USART1 reset This bit is set and reset by software. 0: No reset 1: Reset the USART1 Reserved...
Page 131: Ahb Enable Register (Rcu_Ahben)
GD32F10x User Manual 1: Reset the TIMER4 TIMER3RST TIMER3 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER3 TIMER2RST TIMER2 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER2 TIMER1RST TIMER1 reset This bit is set and reset by software.
Page 132 GD32F10x User Manual This bit is set and reset by software. 0: Disabled Ethernet clock 1: Enabled Ethernet clock Reserved Must be kept at reset value USBFSEN USBFS clock enable This bit is set and reset by software. 0: Disabled USBFS clock 1: Enabled USBFS clock 11:9 Reserved...
Page 133: Apb2 Enable Register (Rcu_Apb2En)
GD32F10x User Manual 1: Enabled DMA0 clock APB2 enable register (RCU_APB2EN) 5.6.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved USART0 TIMER7E TIMER0E Reserved SPI0EN ADC1EN ADC0EN PGEN PFEN PEEN PDEN PCEN PBEN...
Page 134 GD32F10x User Manual 0: Disabled ADC0 clock 1: Enabled ADC0 clock PGEN GPIO port G clock enable This bit is set and reset by software. 0: Disabled GPIO port G clock 1: Enabled GPIO port G clock PFEN GPIO port F clock enable This bit is set and reset by software.
Page 135: Apb1 Enable Register (Rcu_Apb1En)
GD32F10x User Manual APB1 enable register (RCU_APB1EN) 5.6.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) UART4E UART3E USART2 USART1 Reserved DACEN PMUEN BKPIEN CAN1EN CAN0EN Reserved I2C1EN I2C0EN Reserved WWDGT TIMER6E TIMER5E TIMER4E...
Page 136 GD32F10x User Manual 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN...
Page 137: Backup Domain Control Register (Rcu_Bdctl)
GD32F10x User Manual TIMER6EN TIMER6 clock enable This bit is set and reset by software. 0: Disabled TIMER6 clock 1: Enabled TIMER6 clock TIMER5EN TIMER5 clock enable This bit is set and reset by software. 0: Disabled TIMER5 clock 1: Enabled TIMER5 clock TIMER4EN TIMER4 clock enable This bit is set and reset by software.
Page 138: Reset Source/Clock Register (Rcu_Rstsck)
GD32F10x User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by software. 0: Disabled RTC clock 1: Enabled RTC clock 14:10...
Page 139 GD32F10x User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDGT FWDGT Reserved RSTFC Reserved RSTF RSTF RSTF RSTF RSTF RSTF IRC40K IRC40KE Reserved Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated. Reset by writing 1 to the RSTFC bit.
Page 140: Ahb Reset Register (Rcu_Ahbrst)
GD32F10x User Manual 1: External pin reset generated Reserved Must be kept at reset value RSTFC Reset flag clear This bit is set by software to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags 23:2 Reserved Must be kept at reset value IRC40KSTB...
Page 141: Clock Configuration Register 1 (Rcu_Cfg1)
GD32F10x User Manual 0: No reset 1: Reset the USBFS 11:0 Reserved Must be kept at reset value Clock configuration register 1 (RCU_CFG1) 5.6.12. Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PREDV0 Reserved I2S2SEL...
Page 142 GD32F10x User Manual 1011: (PLL2 source clock x 13) 1100: (PLL2 source clock x 14) 1101: (PLL2 source clock x 15) 1110: (PLL2 source clock x 16) 1111: (PLL2 source clock x 20) 11:8 PLL1MF[3:0] The PLL1 clock multiplication factor Set and reset by software.
Page 143: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F10x User Manual Bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1. 0000: PREDV0 input source clock not divided 0001: PREDV0 input source clock divided by 2 0010: PREDV0 input source clock divided by 3 0011: PREDV0 input source clock divided by 4 0100: PREDV0 input source clock divided by 5 0101: PREDV0 input source clock divided by 6 0110: PREDV0 input source clock divided by 7...
Page 144: Interrupt/Event Controller (Exti)
GD32F10x User Manual Interrupt/event controller (EXTI) Overview 6.1. Cortex-M3 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the Technical Reference Manual of Cortex-M3 for more details about NVIC.
Page 145: Table 6-1. Nvic Exception Types In Cortex-M3
GD32F10x User Manual Table 6-1. NVIC exception types in Cortex-M3 Vector Exception Type Priority (a) Vector Address Description Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. 0x0000_000C All class of fault HardFault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable 0x0000_0014...
Page 146 GD32F10x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector Address Number Number Interrupt Description Interrupt Description DMA0 channel2 global DMA0 channel2 global IRQ 13 0x0000_0074 interrupt interrupt DMA0 channel3 global DMA0 channel3 global 0x0000_0078 IRQ 14 interrupt interrupt DMA0 channel4 global DMA0 channel4 global IRQ 15 0x0000_007C...
Page 147 GD32F10x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector Address Number Number Interrupt Description Interrupt Description IRQ 39 USART2 global interrupt USART2 global interrupt 0x0000_00DC IRQ 40 EXTI line[15:10] interrupts EXTI line[15:10] interrupts 0x0000_00E0 RTC alarm from EXTI IRQ 41 RTC alarm from EXTI interrupt 0x0000_00E4 interrupt...
Page 148: External Interrupt And Event (Exti) Block Diagram
GD32F10x User Manual Interrupt Vector Non-connectivity devices Connectivity devices Vector Address Number Number Interrupt Description Interrupt Description IRQ65 reserved CAN1 RX1 interrupt 0x0000_0144 IRQ66 reserved CAN1 EWMC interrupt 0x0000_0148 IRQ67 reserved USBFS global interrupt 0x0000_014C Note: 1. IRQ0 ~ 42 are available in MD devices, but when the flash memory is less than 64KB, IRQ30, IRQ33, IRQ34, IRQ36 and IRQ39 are not available.
Page 149: External Interrupt And Event Function Overview
GD32F10x User Manual External Interrupt and Event function overview 6.5. The EXTI contains up to 20 independent edge detectors and generates interrupts request or event to the processer. The EXTI has three trigger types: rising edge, falling edge and both edges.
Page 150: Register Definition
GD32F10x User Manual Register definition 6.6. EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 6.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7...
Page 151: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F10x User Manual 1: Event from Linex is enabled. Rising edge trigger enable register (EXTI_RTEN) 6.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9...
Page 152: Software Interrupt Event Register (Exti_Swiev)
GD32F10x User Manual Software interrupt event register (EXTI_SWIEV) 6.6.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2...
Page 153: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32F10x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 7.1. There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions.
Page 154: Gpio Pin Configuration
GD32F10x User Manual Table 7-1. GPIO configuration table Configuration mode CTL[1:0] MD[1:0] OCTL don’t care Analog don’t care Input floating Input Input pull-down Input pull-up Push-pull 0 or 1 General purpose 00: Reserved Output (GPIO) Open-drain 0 or 1 01: Speed up to 10MHz 10: Speed up to 2MHz don’t care Push-pull...
Page 155: External Interrupt/Event Lines
GD32F10x User Manual port input status register (GPIOx_ISTAT). When the GPIO pins are configured as output pins, user can configure the speed of the ports. And chooses the output driver mode: Push-Pull or Open-Drain mode. The value of the port output control register (GPIOx_OCTL) is output on the I/O pin.
Page 156: Analog Configuration
GD32F10x User Manual  The weak pull-up and pull-down resistors are disabled.  The output buffer is enabled. Open Drain Mode: The pad output low level when a “0” in the output control register.  while the pad leaves Hi-Z when a “1” in the output control register. ...
Page 157: Io Pin Function Selection
GD32F10x User Manual When be configured as alternate function:  The output buffer is enabled in Open-Drain or Push-Pull configuration.  The output buffer is driven by the peripheral.  The schmitt trigger input is enabled.  The weak pull-up and pull-down resistors could be chosen when input. ...
Page 158: Gpio Locking Function
GD32F10x User Manual GPIO locking function 7.3.9. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL0, GPIOx_CTL1. It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK). When the special LOCK sequence has been occurred on LKK bit in GPIOx_LOCK register and the LKy bit is set in GPIOx_LOCK register, the corresponding port is locked and the corresponding port configuration cannot be modified until the next reset.
Page 159: Adc Af Remapping
GD32F10x User Manual Pin Name Function description NJTRST To reduce the number of GPIOs used to debug, user can configure SWJ_CFG [2:0] bits in the AFIO_PCF0 to different value. Refer to table below. Table 7-3. Debug port mapping and Pin availability SWJ_CFG Pin availability JTAG-DP and SW-DP...
Page 160: Timer Af Remapping
GD32F10x User Manual Remap available only for High-density and Extra-density devices TIMER AF remapping 7.4.5. Table 7-5. TIMERx alternate function remapping TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 8，9，10，12， function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER0_ETI...
Page 161: Usart Af Remapping
GD32F10x User Manual TIMERx_REMAP [1:0](x = 0，1，2) TIMERx_REMAP(x = 8，9，10，12， Alternate function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER12_CH0 TIMER13_CH0 TIMER0 remap available only for 100-pin and 144-pin packages. TIMER0 remap not available on 36-pin package. 3.
Page 162: I2C0 Af Remapping
GD32F10x User Manual PD3(USART1_CTS) PD4(USART1_RTS) USART1_REMAP = 1 PD5(USART1_TX) PD6(USART1_RX) PD7(USART1_CK) PB10(USART2_TX) PB11(USART2_RX) USART2_REMAP[1:0] PB12(USART2_CK) = “00” (no remap) PB13(USART2_CTS) PB14(USART2_RTS) PC10(USART2_TX) USART2_REMAP PC11(USART2_RX) [1:0] =“01” (partial PC12(USART2_CK) remap) PB13(USART2_CTS) PB14(USART2_RTS) PD8(USART2_TX) USART2_REMAP PD9(USART2_RX) [1:0] =“11” (full remap) PD10(USART2_CK) PD11(USART2_CTS) PD12(USART2_RTS) Remap available only 100-pin and 144-pin packages 2.
Page 163: Can0/1 Af Remapping
GD32F10x User Manual Register SPI0 SPI2/I2S PA15(SPI0_NSS) PB3(SPI0_SCK) SPI0_REMAP = 1 PB4(SPI0_MISO) PB5(SPI0_MOSI) PA15(SPI2_NSS/I2S2_WS) PB3(SPI2_SCK/I2S2_CK) SPI2_REMAP = 0 PB4(SPI2_MISO) PB5(SPI2_MOSI/I2S2_SD) PA4(SPI2_NSS/I2S2_WS) PC10(SPI2_SCK/I2S2_CK) SPI2_REMAP = 1 PC11(SPI2_MISO) PC12(SPI2_MOSI/I2S2_SD) CAN0/1 AF remapping 7.4.9. The CAN0 signals can be mapped on Port A, Port B or Port D as shown in table below. For port D, remapping is not possible in devices delivered in 64-pin packages.
Page 164: Ethernet Af Remapping
GD32F10x User Manual Ethernet AF remapping 7.4.10. Table 7-11. ENET alternate function remapping Register ENET PA7(RX_DV-CRS_DV) PC4(RXD0) ENET_REMAP = “0” PC5(RXD1) PB0(RXD2) PB1(RXD3) PD8(RX_DV-CRS_DV) PD9(RXD0) ENET_REMAP = “1” PD10(RXD1) PD11(RXD2) PD12(RXD3) CLK pins AF remapping 7.4.11. The LXTAL oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15 individually, when the LXTAL oscillator is off.
Page 165: Register Definition
GD32F10x User Manual Register definition 7.5. GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..G) 7.5.1.
Page 166 GD32F10x User Manual 23:22 CTL5[1:0] Port 5 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 21:20 MD5[1:0] Port 5 mode bits These bits are set and cleared by software refer to MD0[1:0]description 19:18 CTL4[1:0] Port 4 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16...
Page 167: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32F10x User Manual Output mode ( MD[1:0] >00) 00: GPIO output with push-pull 01: GPIO output with open-drain 10: AFIO output with push-pull 11: AFIO output with open-drain MD0[1:0] Port 0 mode bits These bits are set and cleared by software 00: Input mode (reset state) 01: Output mode(10MHz) 10: Output mode(2MHz)
Page 168 GD32F10x User Manual refer to CTL0[1:0]description 21:20 MD13[1:0] Port 13 mode bits These bits are set and cleared by software refer to MD0[1:0]description 19:18 CTL12[1:0] Port 12 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD12[1:0] Port 12 mode bits...
Page 169: Port Input Status Register (Gpiox_Istat, X=A
GD32F10x User Manual Port input status register (GPIOx_ISTAT, x=A..G) 7.5.3. Address offset: 0x08 Reset value: 0x0000 XXXX This register has to be accessed by word (32-bit). Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3...
Page 170: Port Bit Operate Register (Gpiox_Bop, X=A
GD32F10x User Manual Port bit operate register (GPIOx_BOP, x=A..G) 7.5.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4...
Page 171: Port Configuration Lock Register (Gpiox_Lock, X=A
GD32F10x User Manual 1: Clear the corresponding OCTLy bit to 0 Port configuration lock register (GPIOx_LOCK, x=A..G) 7.5.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions...
Page 172: Afio Port Configuration Register 0 (Afio_Pcf0)
GD32F10x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Event output enable Set and cleared by software.When set the EVENTOUT Cortex output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits PORT[2:0] Event output port selection Set and cleared by software.Select the port used to output the Cortex EVENTOUT signal.
Page 173 GD32F10x User Manual 31:29 Reserved Must be kept at reset value. SPI2_REMAP SPI2/I2S2 remapping This bit is set and reset by software. 0: Disable the remapping function (SPI2_NSS-I2S2_WS / PA15, SPI2_SCK- I2S2_CK / PB3, SPI2_MISO / PB4, SPI2_MOSI-I2S_SD / PB5) 1: Enable the remapping function fully (SPI2_NSS-I2S2_WS / PA4, SPI2_SCK- I2S2_CK / PC10, SPI2_MISO / PC11, SPI2_MOSI-I2S_SD / PC12) Note: This bit is available only in Extra-density devices and High-density devices.
Page 174 GD32F10x User Manual These bits are set and reset by software. 00: Disable the remapping function (CAN_RX / PA11, CAN_TX / PA12) 01: Not used 10: Enable the remapping function partially (CAN_RX / PB8, CAN_TX / PB9) 11: Enable the remapping function fully (CAN_RX / PD0,CAN_TX / PD1) TIMER3_REMAP TIMER3 remapping This bit is set and reset by software...
Page 175 GD32F10x User Manual / PE15, TIMER0_CH0_ON / PE8, TIMER0_CH1_ON / PE10, TIMER0_CH2_ON / PE12) USART2_REMAP[1: USART2 remapping These bits are set and reset by software 00: Disable the remapping function (USART2_TX / PB10, USART2_RX / PB11, USART2_CK / PB12, USART2_CTS / PB13, USART2_RTS / PB14) 01: Enable the remapping function partially (USART2_TX / PC10, USART2_RX / PC11, USART2_CK / PC12, USART2_CTS / PB13, USART2_RTS / PB14) 10: Not used...
Page 176 GD32F10x User Manual PD01_RE TIMER3_ TIMER2_REMAP[1:0 TIMER1_REMAP[1:0 TIMER0_ USART2_REMAP[1: USART1_ USART0_ I2C0_RE SPI0_RE CAN0_REMAP[1:0] REMAP REMA[1:0] REMAP REMAP Bits Fields Descriptions Reserved Must be kept at reset value. PTP_PPS_REMAP Ethernet PTP PPS remapping is used as a general-purpose I/O 0: PB5 pin 1: Enale PPT_PPS to be output on PB5 TIMER1ITI1_REMAP TIMER1 input trigger 1 remapping It control the TIMER1_INPTG1 mapping...
Page 177 GD32F10x User Manual 20:17 Reserved Must be kept at reset value TIMER4CH3_IREMA TIMER4 channel3 internal remapping 0: Connect TIMER4_CH3 to PA3. 1:Connect the IRC40K internal clock to TIMER4_CH3 input in order to calibration. PD01_REMAP Port D0/D1 mapping on OSC_IN / OSC_OUT 0: Disable the remapping function 1: PD0 is used as OSC_IN, PD1 is used as OSC_OUT 14:13...
Page 178: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32F10x User Manual PA8, TIMER0_CH1 / PA9, TIMER0_CH2 / PA10, TIMER0_CH3 / PA11, TIMER0_BKIN / PA6, TIMER0_CH0_ON / PA7, TIMER0_CH1_ON / PB0, TIMER0_CH2_ON / PB1) 10: Not used 11: Enable the remapping function fully (TIMER0_ETI / PE7, TIMER0_CH0 / PE9, TIMER0_CH1 / PE11, TIMER0_CH2 / PE13, TIMER0_CH3 / PE14, TIMER0_BKIN / PE15, TIMER0_CH0_ON / PE8, TIMER0_CH1_ON / PE10, TIMER0_CH2_ON / PE12)
Page 179 GD32F10x User Manual Reserved EXTI3_SS[3:0] EXTI2_SS[3:0] EXTI1_SS[3:0] EXTI0_SS[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS [3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin 0011: PD3 pin 0100: PE3 pin 0101: PF3 pin 0110: PG3 pin Other configurations are reserved.
Page 180: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32F10x User Manual 0101: PF0 pin 0110: PG0 pin Other configurations are reserved. EXTI sources selection register 1 (AFIO_EXTISS1) 7.5.11. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI7_SS[3:0] EXTI6_SS[3:0] EXTI5_SS[3:0] EXTI4_SS[3:0] Bits Fields...
Page 181: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32F10x User Manual 0011: PD5 pin 0100: PE5 pin 0101: PF5 pin 0110: PG5 pin Other configurations are reserved. EXTI4_SS [3:0] EXTI 4 sources selection 0000: PA4 pin 0001: PB4 pin 0010: PC4 pin 0011: PD4 pin 0100: PE4 pin 0101: PF4 pin 0110: PG4 pin Other configurations are reserved.
Page 182: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32F10x User Manual 0001: PB10 pin 0010: PC10 pin 0011: PD10 pin 0100: PE10 pin 0101: PF10 pin 0110: PG10 pin Other configurations are reserved. EXTI9_SS [3:0] EXTI 9 sources selection 0000: PA9 pin 0001: PB9 pin 0010: PC9 pin 0011: PD9 pin 0100: PE9 pin 0101: PF9 pin...
Page 183: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32F10x User Manual 15:12 EXTI15_SS [3:0] EXTI 15 sources selection 0000: PA15 pin 0001: PB15 pin 0010: PC15 pin 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin Other configurations are reserved. 11:8 EXTI14_SS [3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin 0010: PC14 pin...
Page 184 GD32F10x User Manual This register has to be accessed by word (32-bit). Reserved EXMC_N TIMER13_ TIMER12_ TIMER10 TIMER9_ TIMER8_ Reserved Reserved REMAP REMAP _REMAP REMAP REMAP Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. EXMC_NADV EXMC_NADV connect/disconnect 0: The pin outputs a NADV signal by default.
Page 185: Cyclic Redundancy Checks Management Unit (Crc)
GD32F10x User Manual Cyclic redundancy checks management unit (CRC) Overview 8.1. A cyclic redundancy checks (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32 bit CRC code with fixed polynomial. Characteristics 8.2.
Page 186: Function Overview
GD32F10x User Manual Function overview 8.3.  CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA.
Page 187: Register Definition
GD32F10x User Manual Register definition 8.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 8.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads.
Page 188: Control Register (Crc_Ctl)
GD32F10x User Manual These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 8.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 189: Direct Memory Access Controller (Dma)
GD32F10x User Manual Direct memory access controller (DMA) Overview 9.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 190: Block Diagram
GD32F10x User Manual Block diagram 9.3. Figure 9-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 191: Table 9-1. Dma Transfer Operation
GD32F10x User Manual Table 9-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 192: Peripheral Handshake
GD32F10x User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 193: Address Generation
GD32F10x User Manual  For channels with equal software priority level, priority is given to the channel with lower channel number. Address generation 9.4.4. Two kinds of address generation algorithm are implemented independently for memory and peripheral, including the fixed mode and the increased mode. The PNAGA and MNAGA bit in the DMA_CHxCTL register are used to configure the next address generation algorithm of peripheral and memory.
Page 194: Interrupt
GD32F10x User Manual 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register. 7. Configure the DMA_CHxPADDR register for setting the peripheral base address. 8. Configure the DMA_CHxMADDR register for setting the memory base address. 9.
Page 195: Figure 9-4. Dma0 Request Mapping
GD32F10x User Manual independently enabled or disabled by programming the registers of the corresponding peripheral. The user has to ensure that only one request is enabled at a time on one channel. Table 9-3. DMA0 requests for each channel lists the support request from peripheral for each channel of DMA0, and Table 9-4.
Page 196: Figure 9-5. Dma1 Request Mapping
GD32F10x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER1_CH1 ● ● ● TIMER1 TIMER1_CH2 TIMER1_UP TIMER1_CH0 TIMER1_CH3 TIMER2_CH3 TIMER2_CH0 ● ● ● ● TIMER2 TIMER2_CH2 TIMER2_UP TIMER2_TG ● ● ● TIMER3 TIMER3_CH0 TIMER3_CH1 TIMER3_CH2 TIMER3_UP...
Page 197 GD32F10x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 TIMER7_UP TIMER7_TG TIMER7_CMT ● ● ● ● ADC2 ADC2 ● ● ● DAC_CH0 DAC_CH1 ● ● ● SPI/I2S SPI2/I2S2_RX SPI2/I2S2_TX ● ● ● USART UART3_RX UART3_TX ●...
Page 198: Register Definition
GD32F10x User Manual Register definition 9.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the following registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 9.5.1.
Page 199: Interrupt Flag Clear Register (Dma_Intc)
GD32F10x User Manual Interrupt flag clear register (DMA_INTC) 9.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2...
Page 200 GD32F10x User Manual Reserved PRIO[1:0] MWIDTH[1:0] PWIDTH[1:0] MNAGA PNAGA CMEN ERRIE HTFIE FTFIE CHEN Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’.
Page 201: Channel X Counter Register (Dma_Chxcnt)
GD32F10x User Manual This bit can not be written when CHEN is ‘1’. CMEN Circular mode enable Software set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral...
Page 202: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F10x User Manual CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer.
Page 203 GD32F10x User Manual Address offset: 0x14 + 0x14 * x Reset value: 0x0000 0000 Note: Do not configure this register when channel is enabled. This register has to be accessed by word (32-bit). MADDR[31:16] MADDR[15:0] Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’.
Page 204: Debug (Dbg)
GD32F10x User Manual Debug (DBG) 10.1. Overview The GD32F10x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm Cortex-M3.
Page 205: Jtag Daisy Chained Structure
GD32F10x User Manual Table 10-1. Pin assignment Debug interface PA15 JTDI PA14 JTCK/SWCLK PA13 JTMS/SWDIO NJTRST JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware).
Page 206: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32F10x User Manual mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in standby mode. When exit the standby mode, a system reset generated. When DSLP_HOLD bit in DBG control register (DBG_CTL) is set and entering the Deep- sleep mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in Deep-sleep mode.
Page 207: Register Definition
GD32F10x User Manual 10.4. Register definition DBG base address: 0xE004 2000 ID code register (DBG_ID) 10.4.1. Address offset: 0x00 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant Control register (DBG_CTL) 10.4.2.
Page 208 GD32F10x User Manual TIMER9_HOLD TIMER9 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER9 counter for debug when core halted. TIMER8_HOLD TIMER8 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER8 counter for debug when core halted.
Page 209 GD32F10x User Manual This bit is set and reset by software 0: no effect 1: hold the TIMER7 counter for debug when core halted. I2C1_HOLD I2C1 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C1 SMBUS timeout for debug when core halted. I2C0_HOLD I2C0 hold bit This bit is set and reset by software...
Page 210 GD32F10x User Manual 1: hold the FWDGT counter clock for debug when core halted. TRACE_MODE[1:0] Trace pin allocation mode This bit is set and reset by software 00: Trace pin used in asynchronous mode. 01: Trace pin used in synchronous mode and the data length is 1. 10: Trace pin used in synchronous mode and the data length is 2.
Page 211: Analog-To-Digital Converter (Adc)
GD32F10x User Manual Analog-to-digital converter (ADC) 11.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment or the most significant bit alignment.
Page 212: Pins And Internal Signals
GD32F10x User Manual 11.3. Pins and internal signals Figure 11-1. ADC module block diagram shows the ADC block diagram Table 11-1. ADC internal input signals Table 11-2. ADC input pins definition gives the ADC pin description. Table 11-1. ADC internal input signals Internal signal name Description Internal temperature sensor output voltage...
Page 213: Function Overview
GD32F10x User Manual 11.4. Function overview Figure 11-1. ADC module block diagram Trig select DMA request Routine sequence Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO ADC_IN15 routine data registers SAR ADC 12bit （16 bits） SENSE REFINT self calibration REFP...
Page 214: Adc Clock
GD32F10x User Manual Set RSTCLB (optional). Set CLB=1. Wait until CLB=0. Note: The Medium-density devices without the Foreground calibration function. ADC clock 11.4.2. The CK_ADC clock is synchronous with the APB2 clock and provided by the clock controller. ADC clock can be divided and configured by RCU controller. 11.4.3.
Page 215: Figure 11-3. Continuous Operation Mode
GD32F10x User Manual After conversion of a single routine channel, the conversion data will be stored in the ADC_RDATA register, the EOC will be set. An interrupt will be generated if the EOCIE bit is set. Software procedure for single operation mode of a routine channel: Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset.
Page 216: Figure 11-4. Scan Operation Mode, Continuous Disable
GD32F10x User Manual Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need. Prepare the DMA module to transfer data from the ADC_RDATA. Set the SWRCST bit, or generate an external trigger for the routine sequence. Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set.
Page 217: Conversion Result Threshold Monitor Function
GD32F10x User Manual is set. In this mode, the ADC performs a short sequence of n conversions (n does not exceed 8) which is a part of the conversions selected in the ADC_RSQ0~ADC_RSQ2 registers. The value of n is configured by the DISNUM[2:0] bits in the ADC_CTL0 register. When the corresponding software trigger or external trigger is active, the ADC samples and converts the next n channels configured in the ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done.
Page 218: Sample Time Configuration
GD32F10x User Manual Figure 11-7. 12-bit Data storage mode Routine channel data D11 D10 DAL=0 D11 D10 DAL=1 11.4.8. Sample time configuration The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers. A different sample time can be specified for each channel.
Page 219: Dma Request
GD32F10x User Manual ETSRC[2:0] Trigger Source Trigger Type TIMER4_CH0 TIMER4_CH2 Software trigger SWRCST DMA request 11.4.10. The DMA request, which is enabled by the DMA bit of ADC_CTL1 register, is used to transfer data of routine sequence for conversion of more than one channel. The ADC generates a DMA request at the end of conversion of a routine channel.
Page 220: Adc Sync Mode
GD32F10x User Manual 11.5. ADC sync mode In devices with more than one ADC, the ADC sync mode can be used. In ADC sync mode, the conversion starts alternately or simultaneously triggered by ADC0 to ADC1, according to the sync mode configurated by the SYNCM[3:0] bits in ADC1_CTL0 register. In sync mode, when configure the conversion which is triggered by an external event, the ADC1 must be configured as triggered by the software.
Page 221: Free Mode
GD32F10x User Manual Free mode 11.5.1. In this mode, each ADC works independently and does not interfere with each other. Routine parallel mode 11.5.2. This mode converts the routine sequence simultaneously. The source of external trigger comes from the ADC0 routine sequence (configured by the ETSRC[2:0] bits in the ADC_CTL1 register) , and ADC1 routine sequence is configured as software trigger mode.
Page 222: Routine Follow-Up Slow Mode
GD32F10x User Manual 32-bit DMA, which transfers to SRAM the ADC_RDATA register containing the ADC1 converted data in the [31: 16] bits field and the ADC0 converted data in the [15: 0] bits field. Note: The sampling time of the routine channel of the two ADCs should be less than 7 ADC clock cycles.
Page 223: Adc Interrupts
GD32F10x User Manual 11.6. ADC interrupts The interrupt can be produced on one of the events:  End of conversion for routine sequence.  The analog watchdog event.
Page 224: Register Definition
GD32F10x User Manual 11.7. Register definition ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 3C00 Status register (ADC_STAT) 11.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved STRC...
Page 225: Control Register 0 (Adc_Ctl0)
GD32F10x User Manual Control register 0 (ADC_CTL0) 11.7.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RWDEN Reserved SYNCM[3:0] DISNUM[2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value.
Page 226: Control Register 1 (Adc_Ctl1)
GD32F10x User Manual 0: All channels have analog watchdog function 1: A single channel has analog watchdog function Scan mode 0: Scan operation mode disable 1: Scan operation mode enable Reserved Must be kept at reset value. WDEIE Interrupt enable for WDE 0: Interrupt disable 1: Interrupt enable EOCIE...
Page 227 GD32F10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved TSVREN SWRCST Reserved ETERC ETSRC[2:0] Reserved Reserved Reserved. Reserved RSTCLB ADCON Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 16 and 17 enable of ADC0. 0: Channel 16 and 17 of ADC0 disable 1: Channel 16 and 17 of ADC0 enable SWRCST...
Page 228: Sample Time Register 0 (Adc_Sampt0)
GD32F10x User Manual 111: SWRCST 16:12 Reserved Must be kept at reset value Data alignment 0: LSB alignment 1: MSB alignment 10:9 Reserved Must be kept at reset value. DMA request enable. 0: DMA request disable 1: DMA request enable Reserved Must be kept at reset value.
Page 229: Sample Time Register 1 (Adc_Sampt1)
GD32F10x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:21 SPT17[2:0] refer to SPT10[2:0] description 20:18 SPT16[2:0] refer to SPT10[2:0] description 17:15 SPT15[2:0] refer to SPT10[2:0] description 14:12 SPT14[2:0] refer to SPT10[2:0] description 11:9 SPT13[2:0] refer to SPT10[2:0] description SPT12[2:0] refer to SPT10[2:0] description...
Page 230: Watchdog High Threshold Register (Adc_Wdht)
GD32F10x User Manual 26:24 SPT8[2:0] refer to SPT0[2:0] description 23:21 SPT7[2:0] refer to SPT0[2:0] description 20:18 SPT6[2:0] refer to SPT0[2:0] description 17:15 SPT5[2:0] refer to SPT0[2:0] description 14:12 SPT4[2:0] refer to SPT0[2:0] description 11:9 SPT3[2:0] refer to SPT0[2:0] description SPT2[2:0] refer to SPT0[2:0] description SPT1[2:0] refer to SPT0[2:0] description...
Page 231: Watchdog Low Threshold Register (Adc_Wdlt)
GD32F10x User Manual Watchdog low threshold register (ADC_WDLT) 11.7.7. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved WDLT[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDLT[11:0] Low threshold for analog watchdog These bits define the low threshold for the analog watchdog.
Page 232: Routine Sequence Register 1 (Adc_Rsq1)
GD32F10x User Manual Routine sequence register 1 (ADC_RSQ1) 11.7.9. Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RSQ11[4:0] RSQ10[4:0] RSQ9[4:1] RSQ9[0] RSQ8[4:0] RSQ7[4:0] RSQ6[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ11[4:0] refer to RSQ0[4:0] description...
Page 233: Routine Data Register (Adc_Rdata)
GD32F10x User Manual 24:20 RSQ4[4:0] refer to RSQ0[4:0] description 19:15 RSQ3[4:0] refer to RSQ0[4:0] description 14:10 RSQ2[4:0] refer to RSQ0[4:0] description RSQ1[4:0] refer to RSQ0[4:0] description RSQ0[4:0] The channel number (0..17) is written to these bits to select a channel as the nth conversion in the routine sequence.
Page 234: Digital-To-Analog Converter (Dac)
GD32F10x User Manual Digital-to-analog converter (DAC) 12.1. Overview The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 235: Function Overview
GD32F10x User Manual pins gives the pin description. Figure 12-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRG O TIMER7_TRG O TIMER6_TRGO TIMER4_TRGO TIMER1_TRG O TIMER3_TRGO EXTI9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Note: The TIMER7_TRGO trigger is replaced by TIMER2_TRGO ,In connectivity line devices. Table 12-1.
Page 236: Dac Output Buffer
GD32F10x User Manual DAC output buffer 12.3.2. For reducing output impedance and driving external loads, an output buffer is integrated inside each DAC module. The output buffer, which is turned on by default, can be turned off by setting the DBOFFx bits in the DAC_CTL register.
Page 237: Dac Noise Wave
GD32F10x User Manual DAC noise wave 12.3.6. There are two methods to add noise wave to the DAC output signal: LFSR noise wave mode and Triangle wave mode. The noise wave mode can be selected by the DWMx bits in the DAC_CTL register.
Page 238: Dac Output Calculate
GD32F10x User Manual DAC output calculate 12.3.7. The output voltage on the DAC pin is determined by the following equation: (12-1) ∗ DAC_DO/4096 DAC_out REF+ The digital input is linearly converted to an analog output voltage, its range is 0 to V REF+ DMA function 12.3.8.
Page 239: Register Definition
GD32F10x User Manual 12.4. Register definition DAC base address: 0x4000 7400 Control register (DAC_CTL) 12.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DDMAEN Reserved DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 DDMAEN Reserved DWBW0[3:0] DWM0[1:0] DTSEL0[2:0]...
Page 240 GD32F10x User Manual These bits specify the mode selection of the noise wave signal of DAC1 when external trigger of DAC1 is enabled (DTEN1=1). 00: wave disabled 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1.
Page 241: Software Trigger Register (Dac_Swt)
GD32F10x User Manual 0110: The bit width of the wave signal is 7 0111: The bit width of the wave signal is 8 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0]...
Page 242: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32F10x User Manual Reserved Reserved SWTR1 SWTR0 Bits Fields Descriptions 31:2 Reserved Must be kept at reset value SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled DAC0 12-bit right-aligned data holding register (DAC0_R12DH)
Page 243: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32F10x User Manual DAC0_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value DAC0 8-bit right-aligned data holding register (DAC0_R8DH) 12.4.5.
Page 244: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32F10x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DAC1_DH[11:0] DAC1 12-bit right-aligned data These bits specify the data that is to be converted by DAC1. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) 12.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 245: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32F10x User Manual DAC1_DH[7:0] DAC1 8-bit right-aligned data These bits specify the MSB bits of the data that is to be converted by DAC1. DAC concurrent mode 12-bit right-aligned data holding register 12.4.9. (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0]...
Page 246: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32F10x User Manual Bits Fields Descriptions 31:20 DAC1_DH[11:0] DAC1 12-bit left-aligned data These bits specify the data that is to be converted by DAC1. 19:16 Reserved Must be kept at reset value 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value DAC concurrent mode 8-bit right-aligned data holding register...
Page 247: Dac1 Data Output Register (Dac1_Do)
GD32F10x User Manual Reserved DAC0_DO [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DAC0_DO [11:0] DAC0 data output These bits, which are read only, reflect the data that is being converted by DAC0. DAC1 data output register (DAC1_DO) 12.4.13.
Page 248: Watchdog Timer (Wdgt)
GD32F10x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 249: Table 13-1. Min/Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32F10x User Manual Figure 13-1. Free watchdog block diagram Status: PUD Reset IRC40K Prescaler 12-Bit /4/8 /256 Downcounter Reload Reload Control register Status: RUD register The free watchdog is enabled by writing the value 0xCCCC in the control register (FWDGT_CTL), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated.
Page 250 GD32F10x User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note：  All the 10x devices. When after the execution of dog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock interval must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 251: Register Definition
GD32F10x User Manual Register definition 13.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 252 GD32F10x User Manual 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 253 GD32F10x User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update. During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
Page 254: Window Watchdog Timer (Wwdgt)
GD32F10x User Manual 13.2. Window watchdog timer (WWDGT) Overview 13.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of downcounter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared).
Page 255: Figure 13-2. Window Watchdog Timer Block Diagram
GD32F10x User Manual Figure 13-2. Window watchdog timer block diagram PCLK1/4096 Prescaler /1/2/4/8 7-Bit Down Counter CNT[6]=0 WDGTEN Reset CNT>WIN Reset Window WIN Write WWDGT_CTL The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register.
Page 256: Figure 13-3. Window Watchdog Timing Diagram
GD32F10x User Manual Figure 13-3. Window watchdog timing diagram Calculate the WWDGT timeout by using the formula below. ×4096 ×2 × ( CNT [ 5:0 ] +1 ) (ms) (13-1) WWDGT PCLK1 where: : WWDGT timeout WWDGT : APB1 clock period measured in ms PCLK1 Refer to Table 13-2.
Page 257: Register Definition
GD32F10x User Manual Register definition 13.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 258 GD32F10x User Manual reaches 0x40. It can be cleared by a hardware reset or software reset by setting the WWDGTRST bit of the RCU module. A write operation of ‘0’ has no effect. PSC[1:0] Prescaler. The time base of the watchdog timer counter. 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4...
Page 259: Real-Time Clock (Rtc)
GD32F10x User Manual Real-time Clock (RTC) Overview 14.1. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register.
Page 260: Rtc Reset
GD32F10x User Manual RTC_INTEN register, the RTC will generate an alarm interrupt when the system time equals to the alarm time (stored in the RTC_ALRMH/L register), Figure 14-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTCCLK RTC_Overflow...
Page 261: Rtc Flag Assertion
GD32F10x User Manual registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete.
Page 262 GD32F10x User Manual RTC second and overflow waveform example (RTC_PSC = 3) Figure 14-3.
Page 263: Register Definition
GD32F10x User Manual 14.4. Register definition RTC base address: 0x4000 2800 RTC interrupt enable register (RTC_INTEN) 14.4.1. Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions Must be kept at reset value...
Page 264: Rtc Prescaler High Register (Rtc_Psch)
GD32F10x User Manual Bits Fields Descriptions Must be kept at reset value 31:6 Reserved LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode.
Page 265: Rtc Prescaler Low Register (Rtc_Pscl)
GD32F10x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value RTC prescaler value high PSC[19:16] RTC prescaler low register (RTC_PSCL) 14.4.4. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits...
Page 266: Rtc Counter High Register (Rtc_Cnth)
GD32F10x User Manual Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved DIV[15:0] Bits Fields Descriptions Must be kept at reset value 31:16 Reserved 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated.
Page 267: Rtc Alarm High Register (Rtc_Alrmh)
GD32F10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value RTC counter value low 15:0 CNT[15:0] RTC alarm high register (RTC_ALRMH) 14.4.9. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits...
Page 268: Timer
GD32F10x User Manual TIMER Table 15-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1/2/3/4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, UP,DOWN, UP,DOWN, Count mode UP ONLY...
Page 269: Advanced Timer (Timerx, X=0, 7)
GD32F10x User Manual 15.1. Advanced timer (TIMERx, x=0, 7) Overview 15.1.1. The advanced timer module (Timer0 & Timer7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 270: Function Overview
GD32F10x User Manual the advanced timer. Figure 15-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK DMA REQ/ACK Polarity selection Trigger Selector&Counter TIMER_CK...
Page 271: Figure 15-2. Timing Chart Of Internal Clock Divided By 1
GD32F10x User Manual Figure 15-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 272: Figure 15-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F10x User Manual Figure 15-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 273: Figure 15-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-5.
Page 274: Figure 15-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F10x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated.
Page 275: Figure 15-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 276: Figure 15-8. Timing Chart Of Center-Aligned Counting Mode
GD32F10x User Manual Figure 15-8. Timing chart of center-aligned counting mode shows some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 277: Figure 15-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32F10x User Manual The new written CREP value will not take effect until the next update event. When the value of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow.
Page 278: Figure 15-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32F10x User Manual Figure 15-11. Repetition counter timing chart of down counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 279: Figure 15-12. Channel Input Capture Principle
GD32F10x User Manual Figure 15-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 280: Figure 15-13. Channel Output Compare Principle (With Complementary Output, X=0,1,2)
GD32F10x User Manual interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 281: Figure 15-15. Output-Compare In Three Modes
GD32F10x User Manual (please refer to the TIMERx_CHCTL2 register for more details). For examples, 1) Configure CHxP=0 (the active level of CHx_O is high, the same as OxCPRE), CHxE=1 (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level.
Page 282 GD32F10x User Manual Figure 15-15. Output-compare in three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 283: Figure 15-16. Timing Chart Of Eapwm
GD32F10x User Manual Figure 15-16. Timing chart of EAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Figure 15-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF...
Page 284 GD32F10x User Manual setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 285: Table 15-2. Complementary Outputs Controlled By Parameters
GD32F10x User Manual Table 15-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable.
Page 286: Figure 15-18. Channel Output Complementary Pwm With Dead-Time Insertion
GD32F10x User Manual The dead time delay insertion ensures that no two complementary signals drive the active state at the same time. When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled Figure 15-18. Channel output because under PWM0 mode.
Page 287: Figure 15-19. Output Behavior In Response To A Break (The Break High Active)
GD32F10x User Manual output else the enable output remains high. The complementary outputs are first put in reset state, and then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead-time. When a break occurs, the BRKIF bit in the TIMERx_INTF register is set.
Page 288: Figure 15-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32F10x User Manual Table 15-3. Counting direction in different quadrature decoder mode CI0FE0 CI1FE1 Counting mode Level Rising Falling Rising Falling CI1FE1=1 Down Quadrature decoder mode 0 SMC[2:0]=3’b000 CI1FE1=0 Down CI0FE0=1 Down Quadrature decoder mode 1 SMC [2:0]=3’b010 CI0FE0=0 Down CI1FE1=1 Down Quadrature decoder mode 2...
Page 289: Figure 15-22. Hall Sensor Is Used To Bldc Motor
GD32F10x User Manual Figure 15-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in (Advanced/GeneralL0 TIMER) should accept three HALL sensor signals. Each of the three input of HALL sensors provides a pulse that applied to an input capture pin, can then be analyzed and both speed and position can be deduced.
Page 290: Figure 15-23. Hall Sensor Timing Between Two Timers
GD32F10x User Manual Figure 15-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 291: Figure 15-24. Restart Mode
GD32F10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 100: CI0F_ED and inversion. CHxCAPFLT, no 101: CI0FE0 If ETIFP is selected as prescaler can be 110: CI1FE1 the trigger source, used. 111: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by...
Page 292: Figure 15-25. Pause Mode
GD32F10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 15-25. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode ETPSC = 1, ETI is The counter will start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. to count when a rising of ETI does not ETIFP is selected.
Page 293: Figure 15-27. Single Pulse Mode, Timerx_Chxcv = 4, Timerx_Car=99
GD32F10x User Manual In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register.
Page 294: Table 15-5. Input Trigger Of Timer0 And Timer7
GD32F10x User Manual Figure 15-28. Timer0 master/slave mode timer example TRGS TIMER0 TIMER 4 Master ITI0 TRGO Prescaler Counter mode control TIMER 1 Master TRGO ITI1 Prescaler Counter mode control TIMER 2 Master ITI2 TRGO Prescaler Counter mode control Trigger selection TIMER 3 Master...
Page 295: Figure 15-29. Triggering Timer0 With Enable Signal Of Timer2
GD32F10x User Manual 1. Configure Timer2 in master mode and select its update event (UPE) as trigger output (MMC=3’b010 in the TIMER2_CTL1 register). Then timer2 drives a periodic signal on each counter overflow. 2. Configure the Timer2 period (TIMER2_CAR registers). 3.
Page 296: Figure 15-30. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F10x User Manual triggered by its CI0 input rises edge. To ensure 2 timers start synchronously, Timer2 must be configured in Master/Slave mode. Do as follow: 1. Configure Timer2 in slave mode to get the input trigger from CI0 (TRGS=3’b100 in the TIMER2_SMCFG register).
Page 297 GD32F10x User Manual TIMERx_DMACFG is 0(1 transfer), then the timer’s DMA request is finished. While if TIMERx_DMATC is not 0, such as 3( 4 transfers), then timer will send 3 more requests to DMA, and DMA will access timer’s registers DMATA+0x4, DMATA+0x8, DMATA+0xc at the next 3 accesses to TIMERx_DMATB.
Page 298: Register Definition
GD32F10x User Manual Register definition 15.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 299 GD32F10x User Manual TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode.
Page 300 GD32F10x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 301 GD32F10x User Manual the UPG bit in the TIMERx_SWEVG register is set 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output.
Page 302 GD32F10x User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 303 GD32F10x User Manual EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
Page 304 GD32F10x User Manual 010: Quadrature decoder mode 1. The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level. 011: Quadrature decoder mode 2. The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other. 100: Restart mode.
Page 305 GD32F10x User Manual 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable...
Page 306 GD32F10x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description...
Page 307 GD32F10x User Manual Channel 3 ‘s capture/compare interrupt flag CH3IF Refer to CH0IF description Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software.
Page 308 GD32F10x User Manual set, the TRGIF flag in TIMERx_INTF register is set, related interrupt or DMA transfer can occur if enabled. 0: No generate a trigger event 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 309 GD32F10x User Manual Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 310 GD32F10x User Manual comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT. 001: Set the channel output. O0CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV.
Page 311 GD32F10x User Manual 00: Channel 0 is programmed as output mode 01: Channel 0 is programmed as input mode, IS0 is connected to CI0FE0 10: Channel 0 is programmed as input mode, IS0 is connected to CI1FE0 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 312 GD32F10x User Manual CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 313 GD32F10x User Manual 01: Channel 3 is programmed as input mode, IS3 is connected to CI3FE3 10: Channel 3 is programmed as input mode, IS3 is connected to CI2FE3 11: Channel 3 is programmed as input mode, IS3 is connected to ITS. Note: When CH3MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 314 GD32F10x User Manual The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00. CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the...
Page 315 GD32F10x User Manual CH2CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear.
Page 316 GD32F10x User Manual 31:14 Reserved Must be kept at reset value CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP Channel 2 complementary output polarity Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description...
Page 317 GD32F10x User Manual 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the IS0 signal polarity. 0: Rising edge: the rising edge of IS0 is captured. When used as extern trigger, IS0 is non-inverted.
Page 318 GD32F10x User Manual PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 319 GD32F10x User Manual Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
Page 320 GD32F10x User Manual Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 321 GD32F10x User Manual This register has to be accessed by word (32-bit) Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 322 GD32F10x User Manual CHxNEN in TIMERx_CHCTL2 register) have been set. 0: Disable channel outputs (CHxO or CHxON). 1: Enabled channel outputs (CHxO or CHxON). Note: This bit is only valid when CHxMS=2’b00. OAEN Output automatic enable 0: The POEN can only be set by software. 1: POEN can be set at the next update event, if the break input is not active.
Page 323 GD32F10x User Manual 01: PROT mode 0.The ISOx/ISOxN bits in TIMERx_CTL1 register and the BRKEN/BRKP/OAEN/DTCFG bits in TIMERx_CCHP register are writing protected. 10: PROT mode 1. In addition of the registers in PROT mode 0, the CHxP/CHxNP bits in TIMERx_CHCTL2 register (if related channel is configured in output mode) and the ROS/IOS bits in TIMERx_CCHP register are writing protected.
Page 324 GD32F10x User Manual Reserved Must be kept at reset value. DMATA [4:0] DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMATB. When access is done through the TIMERx_DMA address first time, this bit-field specifies the address you just access.
Page 325: General Level0 Timer (Timerx, X=1, 2, 3, 4)
GD32F10x User Manual 15.2. General level0 timer (TIMERx, x=1, 2, 3, 4) Overview 15.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 326 GD32F10x User Manual configuration of the general level0 timer. Figure 15-31. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection...
Page 327: Figure 15-32. Timing Chart Of Internal Clock Divided By 1
GD32F10x User Manual Figure 15-32. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 328: Figure 15-33. Timing Chart Of Psc Value Change From 0 To 2
GD32F10x User Manual Figure 15-33. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 329: Figure 15-35. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-34. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-35.
Page 330: Figure 15-36. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F10x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow.
Page 331: Figure 15-37. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-37. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 332: Figure 15-38. Timing Chart Of Center-Aligned Counting Mode
GD32F10x User Manual Figure 15-38. Timing chart of center-aligned counting mode shows some examples of the counter behavior for different clock frequencies when TIMERx_CAR=0x99, TIMERx_PSC=0x0. Figure 15-38. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only...
Page 333: Figure 15-39. Channel Input Capture Principle
GD32F10x User Manual occurs on the channel input, the current value of the counter is captured into the TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by CHxIE = 1. Figure 15-39.
Page 334: Figure 15-40. Channel Output Compare Principle (X=0,1,2,3)
GD32F10x User Manual Result: When you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 335: Figure 15-41. Output-Compare In Three Modes
GD32F10x User Manual And the DMA request will be assert, if CxCDE=1. So the process can be divided to several steps as below: Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL.
Page 336: Figure 15-42. Eapwm Timechart
GD32F10x User Manual and CAPWM (Centre aligned PWM). The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 15-42. EAPWM timechart shows the EAPWM output and interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV.
Page 337 GD32F10x User Manual Figure 15-43. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CAM=2'b10 up only CHxIF CAM=2'b11 up/down CHxIF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 338: Table 15-7. Examples Of Slave Mode
GD32F10x User Manual Quadrature decoder Quadrature decoder. Refer to Hall sensor function Hall sensor function. Refer to Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 339: Figure 15-44. Restart Mode
GD32F10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 15-44. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Pause mode TI0S=0 (Non-xor) The counter will be CH0P=0, paused when the TRGS[2:0]=3’b101 CI0FE0 does not Filter is bypassed in trigger input is low, CI0FE0 is selected.
Page 340: Figure 15-46. Event Mode
GD32F10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 15-46. Event mode Single pulse mode Single pulse mode. Refer to Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt.
Page 341: Table 15-9. Ouput Trigger Of Timerx(X=1,2,3,4)
GD32F10x User Manual Table 15-9. Ouput trigger of Timerx(x=1,2,3,4) TIMER1_TRGO TIMER2_TRGO TIMER3_TRGO TIMER4_TRGO TIMER0 ITI1 ITI2 ITI3 ITI0 TIMER1 ITI2 ITI3 ITI1 ITI3 ITI2 TIMER2 TIMER3 ITI1 ITI2 ITI0 ITI1 ITI2 TIMER4 TIMER7 ITI1 ITI2 ITI3 TIMER8 ITI0 ITI1 TIMER11 ITI0 ITI1 Note: ‘-’...
Page 342 GD32F10x User Manual Register definition 15.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CKDIV[1:0]...
Page 343 GD32F10x User Manual register). Only when counting up, CHxF bit can be set. 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set.
Page 344 GD32F10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 345 GD32F10x User Manual 1: When update event occurs, the DMA request of channel x is sent. Reserved Must be kept at reset value. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved SMC1 ETPSC[1:0]...
Page 346 GD32F10x User Manual 11: The prescaler is 8. 11:8 ETFC[3:0] External trigger filter control The external trigger can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal.
Page 347 GD32F10x User Manual 110: CI1FE1 111: ETIFP These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high.
Page 348 GD32F10x User Manual CH3DEN Channel 3 capture/compare DMA request enable 0: disabled 1: enabled CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN...
Page 349 GD32F10x User Manual Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0...
Page 350 GD32F10x User Manual Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
Page 351 GD32F10x User Manual Refer to CH0G description Channel 1’s capture or compare event generation CH1G Refer to CH0G description Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware.
Page 352 GD32F10x User Manual CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description CH1COMFEN Channel 1 output compare fast enable Refer to CH0COMFEN description CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active.
Page 353 GD32F10x User Manual result changes. CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled. 0: Channel 0 output compare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) CH0COMFEN...
Page 354 GD32F10x User Manual Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH0CAPFLT [3:0] Times...
Page 355 GD32F10x User Manual CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0] CH2CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control...
Page 356 GD32F10x User Manual 010: Clear the channel output. O2CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH2CV. 011: Toggle on match. O2CPRE toggles when the counter is equals to the output compare register TIMERx_CH2CV. 100: Force low.
Page 357 GD32F10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 CH3CAPFLT[3:0] Channel 3 input capture filter control Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control...
Page 358 GD32F10x User Manual Same as output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CH3P CH3EN Reserved CH2P CH2EN Reserved CH1P CH1EN Reserved CH0P CH0EN Bits...
Page 359 GD32F10x User Manual 0: Rising edge: the rising edge of IS0 is captured. When used as extern trigger, IS0 is non-inverted. 1: Falling edge: the falling edge of IS0 is captured. When used as extern trigger, IS0 is inverted. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state.
Page 360 GD32F10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 361 GD32F10x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 362 GD32F10x User Manual CH2VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 363 GD32F10x User Manual Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1).
Page 364 GD32F10x User Manual 15.3. General level1 timer (TIMERx, x=8, 11) Overview 15.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 365: Figure 15-47. General Level1 Timer Block Diagram
GD32F10x User Manual Block diagram 15.3.3. Figure 15-47. General level1 timer block diagram provides details on the internal configuration of the general level1 timer. Figure 15-47. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1 ITI2...
Page 366: Figure 15-48. Timing Chart Of Internal Clock Divided By 1
GD32F10x User Manual Figure 15-48. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 367: Figure 15-49. Timing Chart Of Psc Value Change From 0 To 2
GD32F10x User Manual Figure 15-49. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 368: Figure 15-51. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-50. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-51.
Page 369: Figure 15-52. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F10x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value again. The update event is generated each time when underflows.
Page 370: Figure 15-53. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-53. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 371: Figure 15-54. Timing Chart Of Center-Aligned Counting Mode
GD32F10x User Manual Figure 15-54. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-54. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 372: Figure 15-55. Channel Input Capture Principle
GD32F10x User Manual TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by CHxIE = 1. Figure 15-55. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK...
Page 373: Figure 15-56. Channel Output Compare Principle (X=0,1)
GD32F10x User Manual Result: When you wanted input signal is got, TIMERx_CHxCV will be set by Counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly.
Page 374: Figure 15-57. Output-Compare Under Three Modes
GD32F10x User Manual So the process can be divided to several steps as below: Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE...
Page 375: Figure 15-58. Eapwm Timechart
GD32F10x User Manual Based on the counter mode, we have can also divide PWM into EAPWM (Edge aligned PWM) and CAPWM (Centre aligned PWM). The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 15-58. EAPWM timechart shows the EAPWM output and interrupts waveform.
Page 376 GD32F10x User Manual Figure 15-59. CAPWM timechart CHxVAL PWM MODE0 CHx OUT PWM MODE1 CHx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 377: Figure 15-60. Restart Mode
GD32F10x User Manual TIMERx_CHCTL0 register. The OxCPRE signal will not return to its active level until the next update event occurs. Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register.
Page 378: Figure 15-61. Pause Mode
GD32F10x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler high. Figure 15-61. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode CH0P=0, The counter will start CI0FE0 does not TRGS[2:0]=3’b101 Filter is bypassed in to count when a rising invert.
Page 379: Figure 15-63. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
GD32F10x User Manual a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software. If the CEN bit is cleared to 0 using software, the counter will be stopped and its value held.
Page 380 GD32F10x User Manual Timer debug mode ® When the Cortex -M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL register set to 1, the TIMERx counter stops.
Page 381 GD32F10x User Manual Register definition 15.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4001 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 382 GD32F10x User Manual TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode.
Page 383 GD32F10x User Manual Reserved Reserved TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 384 GD32F10x User Manual trigger. Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved TRGIE Reserved CH1IE CH0IE UPIE Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled...
Page 385 GD32F10x User Manual Reserved CH1OF CH0OF Reserved TRGIF Reserved CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 386 GD32F10x User Manual This register has to be accessed by word (32-bit) Reserved Reserved TRGG Reserved. CH1G CH0G Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 387 GD32F10x User Manual Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 388 GD32F10x User Manual 001: Set the channel output. O0CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV. 011: Toggle on match.
Page 389 GD32F10x User Manual through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection...
Page 390 GD32F10x User Manual 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection Same as Output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 391 GD32F10x User Manual 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value.
Page 392 GD32F10x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 393 GD32F10x User Manual shadow register updates every update event. Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0] Capture or compare value of channel1...
Page 394: Figure 15-64. General Level2 Timer Block Diagram
GD32F10x User Manual 15.4. General level2 timer (TIMERx, x=9, 10, 12, 13) Overview 15.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 395 GD32F10x User Manual Figure 15-64. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes Interrupt collector...
Page 396: Figure 15-65. Timing Chart Of Internal Clock Divided By 1
GD32F10x User Manual Figure 15-65. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 397: Figure 15-67. Up-Counter Timechart, Psc=0/2
GD32F10x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 398: Figure 15-68. Up-Counter Timechart, Change Timerx_Car On The Go
GD32F10x User Manual Figure 15-68. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 399 GD32F10x User Manual in different clock frequencies when TIMERx_CAR=0x99. Figure 15-69. Down-counter timechart, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 400: Figure 15-70. Down-Counter Timechart, Change Timerx_Car On The Go
GD32F10x User Manual Figure 15-70. Down-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 401: Figure 15-71. Center-Aligned Counter Timechart
GD32F10x User Manual Figure 15-71. Center-aligned counter timechart show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-71. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF...
Page 402: Figure 15-72. Channels Input Capture Principle
GD32F10x User Manual TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by CHxIE = 1. Figure 15-72. Channels input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK...
Page 403: Figure 15-73. Channel Output Compare Principle (X=0)
GD32F10x User Manual Result: When you wanted input signal is got, TIMERx_CHxCV will be set by Counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt will be asserted based on the your configuration of CHxIE in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly.
Page 404: Figure 15-74. Output-Compare Under Three Modes
GD32F10x User Manual Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV.
Page 405 GD32F10x User Manual 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 406 GD32F10x User Manual Register definition 15.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CKDIV[1:0]...
Page 407 GD32F10x User Manual register). Only when counting up, CHxF bit can be set. 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set.
Page 408 GD32F10x User Manual This register has to be accessed by word (32-bit) Reserved Reserved MMC[2:0] Reserved Bits Fields Descriptions 31:7 Reserved Must be kept at reset value MMC[2:0] Master mode control These bits control the selection of TRGO signal, which is sent in master mode to slave timers for synchronization function.
Page 409 GD32F10x User Manual Reserved CH0IE UPIE Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved...
Page 410 GD32F10x User Manual 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
Page 411 GD32F10x User Manual Reserved CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved. CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
Page 412 GD32F10x User Manual CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 413 GD32F10x User Manual 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 414 GD32F10x User Manual the capture event in channel0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value...
Page 415 GD32F10x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 416 GD32F10x User Manual shadow register updates every update event.
Page 417: Figure 15-75. Basic Timer Block Diagram
GD32F10x User Manual 15.5. Basic timer (TIMERx, x=5, 6) Overview 15.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 418: Figure 15-76. Timing Chart Of Internal Clock Divided By 1
GD32F10x User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 15-76. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG)
Page 419: Figure 15-77. Timing Chart Of Psc Value Change From 0 To 2
GD32F10x User Manual Figure 15-77. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 420: Figure 15-79. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F10x User Manual Figure 15-78. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 15-79.
Page 421 GD32F10x User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. Once the timer is set to operate in the single pulse mode, it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 422 GD32F10x User Manual Register definition 15.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ARSE Reserved UPDIS Bits Fields...
Page 423 GD32F10x User Manual event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 424 GD32F10x User Manual Reserved Must be kept at reset value. Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value.
Page 425 GD32F10x User Manual UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved...
Page 426 GD32F10x User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock...
Page 427 GD32F10x User Manual value.
Page 428 GD32F10x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) Overview 16.1. The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK to produce a dedicated baud rate lock for the USART transmitter and receiver.
Page 429: Table 16-1. Usart Important Pins Description
GD32F10x User Manual – Enter into mute mode if address match does not occur. – Wake up from mute mode by idle frame or address match detection.  Various status flags: – Flags for transfer detection: receive buffer not empty (RBNE), transmit buffer empty (TBE), transfer complete (TC).
Page 430: Figure 16-1. Usart Module Block Diagram
GD32F10x User Manual Figure 16-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address Transmitter Transimit clock...
Page 431 GD32F10x User Manual STB[1:0] stop bit length (bit) usage description normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 432: Figure 16-3. Usart Transmit Procedure
GD32F10x User Manual register. If a data is written to the USART_DATA register while a transmission is ongoing, it will be firstly stored in the transmit buffer, and transferred to the transmit shift register after the current transmission is done. If a data is written to the USART_DATA register while no transmission is ongoing, the TBE bit will be cleared and set soon, because the data will be transferred to the transmit shift register immediately.
Page 433: Figure 16-4. Oversampling Method Of A Receive Frame Bit
GD32F10x User Manual Set the STB[1:0] bits in USART_CTL1. Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. Set the baud rate in USART_BAUD. Set the REN bit in USART_CTL0. After being enabled, the receiver receives a bit stream after a valid start pulse has been detected.
Page 434: Figure 16-5. Configuration Step When Using Dma For Usart Transmission
GD32F10x User Manual register is set, or if the RBNEIE is set. If a noise error (NERR), parity error (PERR), frame error (FERR) or overrun error (ORERR) is generated during a receiving process, then NERR, PERR, FERR or ORERR will be set at same time with RBNE.
Page 435: Figure 16-6. Configuration Step When Using Dma For Usart Reception
GD32F10x User Manual After all of the data frames are transmitted, the TC bit in USART_STAT is set. An interrupt occurs if the TCIE bit in USART_CTL0 is set. When DMA is used for USART reception, DMA transfers data from the receive data buffer of the USART to the internal sram.
Page 436: Figure 16-7. Hardware Flow Control Between Two Usarts
GD32F10x User Manual Figure 16-7. Hardware flow control between two USARTs TX module RX module nCTS nRTS USART 1 USART 2 RX module TX module nRTS nCTS RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame.
Page 437 GD32F10x User Manual Multi-processor communication 16.3.7. In multiprocessor communication, several USARTs are connected as a network. It will be a big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, software can put an USART module into a mute mode by setting the RWU bit in USART_CTL0 register.
Page 438: Figure 16-9. Break Frame Occurs During Idle State
GD32F10x User Manual As shown in Figure 16-9. Break frame occurs during idle state, if a break frame occurs during the idle state on the RX pin, the USART receiver will receive an all ‘0’ frame, with an asserted FERR status. Figure 16-9.
Page 439: Figure 16-11. Example Of Usart In Synchronous Mode
GD32F10x User Manual Figure 16-11. Example of USART in synchronous mode Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1) Idle Idle frame data (8bit) CK pin (CPL=0, CPH=0) CK pin(CPL=1, CPH=0) CK pin (CPL=0, CPH=1) CK pin (CPL=1, CPH=1) Start Master data output bit0 bit1...
Page 440: Figure 16-13. Irda Sir Endec Module
GD32F10x User Manual Figure 16-13. IrDA SIR ENDEC module inside chip outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 441: Figure 16-15. Iso7816-3 Frame Format
GD32F10x User Manual Half-duplex communication mode 16.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be reset in half-duplex communication mode. In the half-duplex mode the receive line is internally connected to the TX pin, and the RX pin is no longer used.
Page 442: Table 16-3. Usart Interrupt Requests
GD32F10x User Manual minus 12. The TC status is forced reset while the guard time counter is counting up. When the counter reaches the programmed value TC is asserted high. During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits.
Page 443: Figure 16-16. Usart Interrupt Mapping Diagram
GD32F10x User Manual Figure 16-16. USART interrupt mapping diagram IDLEF IDLEIE ORERR RBNEIE PERR PEIE FERR NERR ORERR ERRIE LBDF LBDIE USART_INT RBNE RBNEIE TCIE TBEIE CTSF CTSIE...
Page 444 GD32F10x User Manual 16.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register (USART_STAT) 16.4.1. Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 445 GD32F10x User Manual 0: Transmit data buffer is not empty. 1: Transmit data buffer is empty. Transmission complete This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
Page 446 GD32F10x User Manual frame. An interrupt occurs if the ERRIE bit in USART_CTL2 is set. Software can clear this bit by reading the USART_STAT and USART_DATA registers one by one. 0: The USART does not detect a framing error. 1: The USART has detected a framing error. PERR Parity error flag This bit is set when the parity bit of a receive frame does not match the expected...
Page 447 GD32F10x User Manual Reserved INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 INTDIV[11:0] Integer part of baud-rate divider. FRADIV[3:0] Fraction part of baud-rate divider. Control register 0 (USART_CTL0) 16.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 448 GD32F10x User Manual Parity mode 0: Even parity. 1: Odd parity. PERRIE Parity error interrupt enable If this bit is set, an interrupt occurs when the PERR bit in USART_STAT is set. 0: Parity error interrupt is disabled. 1: Parity error interrupt is enabled. TBEIE Transmitter buffer empty interrupt enable If this bit is set, an interrupt occurs when the TBE bit in USART_STAT is set.
Page 449 GD32F10x User Manual 1: Receiver in mute mode. SBKCMD Send break command Software can set this to send a break frame. Hardware resets this bit automatically when the break frame has been transmitted. 0: Do not transmit a break frame. 1: Transmit a break frame.
Page 450 GD32F10x User Manual 1: The CK pin is in high state when the USART is in idle state. This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4. CK phase This bit specifies the phase of the CK pin in synchronous mode. 0: The capture edge of the LSB bit is the first edge of CK pin.
Page 451 GD32F10x User Manual Reserved CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. CTSIE CTS interrupt enable If this bit is set, an interrupt occurs when the CTSF bit in USART_STAT is set. 0: CTS interrupt is disabled.
Page 452 GD32F10x User Manual 1: Enable NACK transmission. This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4. HDEN Half-duplex enable This bit enables the half-duplex USART mode. 0: Half duplex mode is disabled. 1: Half duplex mode is enabled.
Page 453 GD32F10x User Manual 15:8 GUAT[7:0] Guard time value in smartcard mode TC flag assertion time is delayed by GUAT[7:0] baud clock cycles. This bit field cannot be written when the USART is enabled (UEN=1). These bits are not available for UART3/4. PSC[7:0] When the USART IrDA low-power mode is enabled, these bits specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the...
Page 454: Figure 17-1. I2C Module Block Diagram
GD32F10x User Manual Inter-integrated circuit interface (I2C) 17.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard-mode and fast-mode as well as CRC calculation and checking, SMBus (system management bus) and PMBus (power management bus).
Page 455: Table 17-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32F10x User Manual Figure 17-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register Control Registers Timing and SMBA Control Logic Status Flags DMA/ Interrupts Table 17-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 456: Figure 17-2. Data Validation
GD32F10x User Manual source or pull-up resistor. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collect to perform the wired- AND function. Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in the standard-mode and up to 400 Kbit/s in the fast-mode.
Page 457: Figure 17-4. Clock Synchronization
GD32F10x User Manual Clock synchronization 17.3.4. Two masters can begin transmitting on a free bus at the same time and there must be a method for deciding which master takes control of the bus and completes its transmission. This is done by clock synchronization and bus arbitration. In a single master system, clock synchronization and bus arbitration are unnecessary.
Page 458: Figure 17-5. Sda Line Arbitration
GD32F10x User Manual Figure 17-5. SDA line arbitration I2C communication flow 17.3.6. Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can be operated as either a transmitter or receiver, depending on the function of the device.
Page 459: Figure 17-9. Programming Model For Slave Transmitting Mode (10-Bit Address Mode)
GD32F10x User Manual Programming model 17.3.7. An I2C device such as LCD driver may only be a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer.
Page 460 GD32F10x User Manual After the transmission of the first byte, the TBE bit will be set, the software can write the third byte to the I2C_DATA register and TBE is cleared. After this, any time TBE is set, software can write a byte to I2C_DATA as long as there is still data to be transmitted. During the transmission of the second last byte, software writes the last data to I2C_DATA to clear the TBE flag and doesn’t care TBE anymore.
Page 461: Figure 17-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32F10x User Manual Programming model in slave receiving mode As is shown in Figure 17-10. Programming model for slave receiving (10-bit address mode), the following software procedure should be followed if users wish to receive data in slave receiver mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing.
Page 462: Figure 17-11. Programming Model For Master Transmitting Mode (10-Bit Address Mode)
GD32F10x User Manual Figure 17-10. Programming model for slave receiving (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE Master generates START 1) Software initialization condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND 2) Clear ADDSEND SCL stretched by slave...
Page 463 GD32F10x User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 464 GD32F10x User Manual Figure 17-11. Programming model for master transmitting mode (10-bit address mode) I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends ACK Set ADD10SEND...
Page 465: Figure 17-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32F10x User Manual After sending a START signal, the I2C hardware sets the SBSEND bit in I2C_STAT0 register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared.
Page 466 GD32F10x User Manual address mode) I2C Line State Hardware Software Flow Action 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address Slave sends Acknowledge...
Page 467: Figure 17-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32F10x User Manual the address which has been sent is a header of 10-bit address, the hardware sets ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1.
Page 468 GD32F10x User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 469 GD32F10x User Manual set in transmitting mode, the transmitter stretches the SCL line low until the transfer buffer register is filled with the next data to be transmitted. When the RBNE and BTC bits are set in receiving mode, the receiver stretches the SCL line low until the data in the transfer buffer is read out.
Page 470 GD32F10x User Manual SMBus support 17.3.11. The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two- wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with power source for ON/OFF instructions.It is derived from I2C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data).
Page 471: Table17-2. Event Status Flags
GD32F10x User Manual the address and read/write bit. The polynomial used is x8+x2+x+1 (the CRC-8-ATM HEC algorithm, initialized to zero). SMBus alert The SMBus has an extra optional shared interrupt signal called SMBALERT# which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data.
Page 472 GD32F10x User Manual Error Name Description AERR No acknowledge received CRC value doesn’t match PECERR SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert...
Page 473 GD32F10x User Manual 17.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 17.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PECTRA SRESET Reserved SALT...
Page 474 GD32F10x User Manual byte 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte ACKEN ACK enable This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent...
Page 475 GD32F10x User Manual 1: SMBus mode I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 17.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit) Reserved Reserved DMALST...
Page 476 GD32F10x User Manual Reserved Must be kept at reset value. I2CCLK[6:0] I2C peripheral clock frequency I2CCLK[6:0]should be the frequency of input APB1 clock in MHz which is at least 0d – 1d: Not allowed 2d – 60d: 2 MHz~60MHz 61d – 127d: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 477 GD32F10x User Manual Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) 17.4.5.
Page 478 GD32F10x User Manual LOSTAR ADD10S ADDSEN SMBALT SMBTO Reserved PECERR OUERR AERR BERR RBNE Reserved STPDET SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode)
Page 479 GD32F10x User Manual 0: No bus error 1: A bus error detected I2C_DATA is empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail).
Page 480 GD32F10x User Manual I2C_STAT1. 0: In slave mode, no address is received or the received address does not match witih its own address. In master mode, no address is sent or address has been sent but not received the ACK from slave. 1: In slave mode, address is received and matches witih its own address.
Page 481 GD32F10x User Manual RXGC General call address (0x00) received. This bit is cleared by hardware after a STOP or a START signal or I2CEN=0. 0: No general call address (0x00) received 1: General call address (0x00) received Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver.
Page 482 GD32F10x User Manual 1: T =16/9 high 13:12 Reserved Must be kept the reset value 11:0 CLKC[11:0] I2C clock control in master mode In standard speed mode: T =CLKC*T high PCLK1 In fast speed mode or fast mode plus, if DTCY=0: =CLKC*T =2*CLKC*T high...
Page 483 GD32F10x User Manual Serial peripheral interface / Inter-IC sound (SPI / I2S) 18.1. Overview The SPI / I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 484: Figure 18-1. Block Diagram Of Spi
GD32F10x User Manual 18.3. SPI function overview SPI block diagram 18.3.1. Figure 18-1. Block diagram of SPI SYSCLK Clock Generator Control Registers Control Logic MOSI TX Buffer MISO Shift Register RX Buffer SPI signal description 18.3.2. Normal configuration Table 18-1. SPI signal description Pin name Direction Description...
Page 485: Figure 18-2. Spi Timing Diagram In Normal Mode
GD32F10x User Manual Pin name Direction Description application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Note: The pin as input must be configured as in floating mode. SPI clock timing and data format 18.3.3.
Page 486: Table 18-2. Nss Function In Slave Mode
GD32F10x User Manual Table 18-2. NSS function in slave mode Mode Register configuration Description MSTMOD = 0 SPI slave gets NSS level from NSS Slave hardware NSS mode SWNSSEN = 0 pin. SPI slave NSS level is determined by MSTMOD = 0 the SWNSS bit.
Page 487: Table 18-4. Spi Operation Modes
GD32F10x User Manual Mode Register configuration Description SWNSSEN = 1 software NSS mode. SWNSS = 1 NSSDRV: Don’t care SPI operation modes 18.3.5. Table 18-4. SPI operation modes Mode Description Register configuration Data pin usage MSTMOD = 1 RO = 0 MOSI: transmission Master full-duplex BDEN = 0...
Page 488: Figure 18-3. A Typical Full-Duplex Connection
GD32F10x User Manual Mode Description Register configuration Data pin usage BDEN = 1 BDOEN = 1 MSTMOD = 0 Slave reception with RO = 0 MOSI: not used bidirectional connection BDEN = 1 MISO: reception BDOEN = 0 Figure 18-3. A typical full-duplex connection Figure 18-4.
Page 489: Figure 18-6. A Typical Bidirectional Connection
GD32F10x User Manual Figure 18-6. A typical bidirectional connection Master Slave MTB/MRB SRB/STB MISO MISO MOSI MOSI SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 490 GD32F10x User Manual In master mode, software should write the next data into SPI_DATA register before the transmission of current data frame is completed if it desires to generate continuous transmission. Reception sequence After the last valid sample clock, the incoming data will be moved from shift register to the receive buffer and RBNE will be set.
Page 491 GD32F10x User Manual MRU MRB After getting the second last RBNE flag, read out this data and delay for a SCK clock time and then, disable the SPI by clearing SPIEN bit. Wait until the last RBNE flag is set and read out the last data.
Page 492 GD32F10x User Manual Note: When SPI is in slave mode and CRC function is enable, the CRC calculator is sensitive to input SCK clock whether SPI is enable or not. The software must enable CRC only when the clock is stable to avoid wrong CRC calculation. And when SPI works as a slave, the NSS internal signal needs to be kept low between the data phase and CRC phase.
Page 493: Figure 18-7. Block Diagram Of I2S
GD32F10x User Manual  CRC error (CRCERR) When the CRCEN bit is set, the CRC calculation result of the received data in the SPI_RCRC register is compared with the received CRC value after the last data, the CRCERR is set when they are different.
Page 494 GD32F10x User Manual register handles the serial data transmission and reception on I2S_SD. I2S signal description 18.4.2. There are four pins on the I2S interface, including I2S_CK, I2S_WS, I2S_SD and I2S_MCK. I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS.
Page 495: Figure 18-8. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F10x User Manual Figure 18-8. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD Figure 18-9. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 496: Figure 18-13. I2S Phillips Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32F10x User Manual Figure 18-13. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 497: Figure 18-17. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32F10x User Manual Figure 18-17. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD Figure 18-18. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 498: Figure 18-23. Msb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32F10x User Manual Figure 18-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD LSB justified standard For LSB justified standard, I2S_WS and I2S_SD are updated on the falling edge of I2S_CK. In the case that the channel length is equal to the data length, LSB justified standard and MSB justified standard are exactly the same.
Page 499: Figure 18-27. Lsb Justified Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32F10x User Manual Figure 18-27. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit 0 16-bit data I2S_SD When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame.
Page 500: Figure 18-32. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F10x User Manual (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK I2S_WS 32-bit data I2S_SD Figure 18-32. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 18-33. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 24-bit data...
Page 501: Figure 18-37. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32F10x User Manual (DTLEN=00, CHLEN=0, CKPL=0) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16 bits I2S_SD Figure 18-37. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 18-38. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2...
Page 502: Figure 18-42. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F10x User Manual Figure 18-42. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 18-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) I2S clock 18.4.4. Figure 18-44. Block diagram of I2S clock generator 8-bit I2SCLK Configurable...
Page 503: Table 18-7. Audio Sampling Frequency Calculation Formulas
GD32F10x User Manual Fs = I2S bitrate / (number of bits per channel * number of channels) So, in order to get the desired audio sampling frequency, the clock generator needs to be configured according to the formulas listed in Table 18-7.
Page 504: Figure 18-45. I2S Initialization Sequence
GD32F10x User Manual Figure 18-45. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 505 GD32F10x User Manual TBEIE bit in the SPI_CTL1 register is set. At the beginning, the transmission buffer is empty (TBE is high) and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmission buffer to the shift register (TBE goes high) immediately.
Page 506: Figure 18-46. I2S Master Reception Disabling Sequence
GD32F10x User Manual Figure 18-46. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTDSEL !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 507 GD32F10x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 508: Table 18-9. I2S Interrupt
GD32F10x User Manual Error conditions There are two error conditions:  Transmission underrun error flag (TXURERR) This situation occurs when the transmission buffer is empty when the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the reception buffer is full and a newly incoming data has been completely received.
Page 509 GD32F10x User Manual 18.5. Register definition SPI0 base address: 0x4001 3000 SPI1 / I2S1 base address: 0x4000 3800 SPI2 / I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 18.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 510 GD32F10x User Manual In full-duplex or transmit-only mode, set this bit after the last data is written to SPI_DATA register. In receive only mode, set this bit after the second last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer.
Page 511 GD32F10x User Manual 1: CLK pin is pulled high when SPI is idle CKPH Clock phase selection 0: Capture the first data at the first clock transition. 1: Capture the first data at the second clock transition Control register 1 (SPI_CTL1) 18.5.2.
Page 512 GD32F10x User Manual 0: Disable receive buffer DMA 1: Enable receive buffer DMA, when the RBNE bit in SPI_STAT is set, it will be a DMA request on corresponding DMA channel. Status register (SPI_STAT) 18.5.3. Address offset: 0x08 Reset value: 0x0000 0002 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 513 GD32F10x User Manual TXURERR Transmission underrun error bit 0: No transmission underrun error occurs. 1: Transmission underrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_STAT register. This bit is not used in SPI mode. I2SCH I2S channel side 0: The next data needs to be transmitted or the data just received is channel left.
Page 514 GD32F10x User Manual CRC polynomial register (SPI_CRCPOLY) 18.5.5. Address offset: 0x10 Reset value: 0x0000 0007 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved CRCPOLY[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CRCPOLY[15:0] CRC polynomial register...
Page 515 GD32F10x User Manual This register is reset when the CRCEN bit in SPI_CTL0 register or the SPIxRST bit in RCU reset register is set. TX CRC register (SPI_TCRC) 18.5.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved TCRC[15:0] Bits...
Page 516 GD32F10x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. I2SSEL I2S mode selection 0: SPI mode 1: I2S mode This bit should be configured when SPI mode or I2S mode is disabled. I2SEN I2S enable 0: Disable I2S 1: Enable I2S This bit is not used in SPI mode.
Page 517 GD32F10x User Manual 01: 24 bits 10: 32 bits 11: Reserved These bits should be configured when I2S mode is disabled. These bits are not used in SPI mode. CHLEN Channel length 0: 16 bits 1: 32 bits The channel length must be equal to or greater than the data length. This bit should be configured when I2S mode is disabled.
Page 518 GD32F10x User Manual These bits are not used in SPI mode.
Page 519 GD32F10x User Manual Secure digital input/output interface (SDIO) This section applies to GD32F103xx high-density (HD) devices and extra-density (XD) devices only. 19.1. Overview The secure digital input/output interface (SDIO) defines the SD, SD I/O, MMC and CE-ATA card host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC) and CE-ATA devices.
Page 520: Figure 19-1. Sdio "No Response" And "No Data" Operations
GD32F10x User Manual Each message is represented by one of the following tokens: Command: a command is a token which starts an operation. A command is sent from the host to a card. A command is transferred serially on the CMD line. Response: a response is a token which is sent from the card to the host as an answer to a previously received command.
Page 521: Figure 19-2. Sdio Multiple Blocks Read Operation
GD32F10x User Manual can be configured by the host to use single or multiple data lines. Figure 19-2. SDIO multiple blocks read operation is the multiple blocks read operation and Figure 19-3. SDIO multiple blocks write operation is the multiple block write operation. The block write operation uses a simple busy signal of the write operation duration on the data (DAT0) line.
Page 522: Figure 19-5. Sdio Sequential Write Operation
GD32F10x User Manual Figure 19-5. SDIO sequential write operation 19.4. SDIO functional description The following figure shows the SDIO structure. There are two main parts:  The SDIO adapter block consists of control unit which manage clock, command unit which manage command transfer, data unit which manage data transfer. ...
Page 523: Table 19-1. Sdio I/O Definitions
GD32F10x User Manual a one bit transfer on the command line (SDIO_CMD) and on all the data lines (SDIO_DAT). The SDIO_CLK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3.31, between 0 and 48 MHz for a Multimedia Card V4.2, or between 0 and 25 MHz for an SD/SD I/O card.
Page 524 GD32F10x User Manual receive or transmit data, the host will stop the SDIO_CLK and freeze SDIO state machines to avoid the corresponded error. Only state machines are frozen, the AHB interface is still alive. So, the FIFO can access by AHB bus. Command unit The command unit implements command transfer to the card The data transfer flow is...
Page 525 GD32F10x User Manual CS_Receive Receive the response and check the CRC. → 1.Response Received in CE-ATA mode and interrupt CS_Waitcompl disabled and wait for CE-ATA Command Completion signal enabled → 2.Response Received in CE-ATA mode and interrupt CS_Pend disabled and wait for CE-ATA Command Completion signal disabled →...
Page 526 GD32F10x User Manual → 2.DSM disabled DS_Idle → 3.Data FIFO empty flag is deasserted DS_Send DS_Send Transmit data to the card. → 1.Data block transmitted DS_Busy → 2.DSM disabled DS_Idle → 3.Data FIFO underrun error occurs DS_Idle → 4. Internal CRC error DS_Idle DS_Busy Waits for the CRC status flag.
Page 527 GD32F10x User Manual The interrupt logic generates interrupt when at least one of the selected status flags is high. An interrupt enable register is provided to allow the logic to generate a corresponding interrupt. The DMA interface provides a method for fast data transfers between the SDIO data FIFO and memory.
Page 528 GD32F10x User Manual by AHB bus, the data unit in SDIO adapter read data from transmit FIFO, and then send the data to card. The receive FIFO is used when read data from card and RXRUN in SDIO_STAT register is 1. The data to be transferred is read from the card and then write to receive FIFO. The data in receive FIFO is read to AHB bus when needed.
Page 529: Figure 19-7. Command Token Format
GD32F10x User Manual ask the card to publish a new relative address (RCA). Note: The default value of the RCA register is 0x0001(MMC) or 0x0000(SD/SD I/O). The default value is reserved to set all cards into the Stand-by State with CMD7. DSR register (Optional): The 16-bit driver stage register can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards).
Page 530 GD32F10x User Manual A command always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (host = 1). The next 6 bits indicate the index of the command, this value being interpreted as a binary coded number (between 0 and 63). Some commands need an argument (e.g.
Page 531: Table 19-3. Card Command Classes (Cccs)
GD32F10x User Manual Table 19-3. Card command classes (CCCs) Card command class(CCC) Supporte Class comman description CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28...
Page 532 GD32F10x User Manual Card command class(CCC) Supporte Class comman description CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC.CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card.
Page 533: Table 19-4. Basic Commands (Class 0)
GD32F10x User Manual Detailed command description The following tables describe in detail all bus commands. The responses R1-R7 are defined in Responses. The registers CID, CSD and DSR are described in Card registers. The card shall ignore stuff bits and reserved bits in an argument. Table 19-4.
Page 534: Table 19-5. Block-Oriented Read Commands (Class 2)
GD32F10x User Manual Response type argument Abbreviation Description index format [31:12]reserved Sends Memory Card bits interface condition, which [11:8]supply includes host supply voltage CMD8 SEND_IF_COND voltage(VHS) information and asks the card [7:0]check whether card supports voltage. pattern Reserved bits shall be set to '0'. For MMC only.
Page 535: Table 19-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32F10x User Manual Response type argument Abbreviation Description index format Card, block length CMD16 command does not affect the memory read and write commands. Always 512 Bytes fixed block length is used. In both cases, if block length is set larger than 512Bytes, the card sets the BLOCK_LEN_ERROR bit.
Page 536: Table 19-8. Erase Commands (Class 5)
GD32F10x User Manual Response type argument Abbreviation Description index format Defines the number of blocks which are [31:16] set going to be transferred in the immediately to 0 SET_BLOCK_ succeeding multiple block read or write CMD23 [15:0] COUNT command. If the argument is all 0s, the number of subsequent read/write operation will be blocks...
Page 537: Table 19-9. Block Oriented Write Protection Commands (Class 6)
GD32F10x User Manual Response type argument Abbreviation Description index format address UP_END group within a continuous range to be selected for erase.(MMC) [31:0] stuff CMD38 ERASE Erases all previously selected write blocks. bits Note: 1.CMD34 and CMD37 are reserved in order to maintain backwards compatibility with older versions of the MMC.
Page 538: Table 19-11. Application-Specific Commands (Class 8)
GD32F10x User Manual Table 19-11. Application-specific commands (class 8) Response type argument Abbreviation Description index format [31]reserve d bit Sends host capacity support information [30]HCS (HCS) and asks the accessed card to send [29:24]rese operating condition register(OCR) SD_SEND_OP ACMD41 rved bits content in the response.
Page 539: Table 19-12. I/O Mode Commands (Class 9)
GD32F10x User Manual Response type argument Abbreviation Description index format Note: 1.ACMDx is Application-specific Commands for SD memory. 2. CMD60, CMD61 are Application-specific Commands for CE-ATA device. Table 19-12. I/O mode commands (class 9) Response type argument Abbreviation Description index format Used to write and read 8 bit (register) data fields.
Page 540: Table 19-13. Switch Function Commands (Class 10)
GD32F10x User Manual Response type argument Abbreviation Description index format Byte/Block Count Note: 1.CMD39, CMD40 are only for MMC. 2. CMD52, CMD53 are only for SD I/O card. Table 19-13. Switch function commands (class 10) Response type argument Abbreviation Description index format [31] Mode...
Page 541: Figure 19-8. Response Token Format
GD32F10x User Manual The SD Memory Card support five types of them, R1 / R1b, R2, R3, R6, R7. And the SD I/O Card and MMC supports additional response types named R4 and R5, but they are not exactly the same for SD I/O Card and MMC. Responses format Responses have two formats, as show in Figure 19-8.
Page 542: Table 19-15. Response R2
GD32F10x User Manual R2 (CID, CSD register) Code length is 136 bits. The contents of the CID register are sent as a response to the commands CMD2 and CMD10. The contents of the CSD register are sent as a response to CMD9.
Page 543: Table 19-18. Response R4 For Sd I/O
GD32F10x User Manual Table 19-18. Response R4 for SD I/O [45:40] 39 [38:36] [34:32] 31 [30:8] [7:1] position Width ‘11111 ‘11111 ‘0’ ‘0’ ‘000’ Value 1’ 11’ Number of descripti start transmissi Reserv Memory Stuff Reserv S18A on bit Present Bits functions R5 (Interrupt request)
Page 544: Figure 19-9. 1-Bit Data Bus Width
GD32F10x User Manual start transmission New published RCA card status description CMD3 CRC7 of the card bits:23,22,19,12:0 R7 (Card interface condition) For SD memory only. Code length is 48 bits. The card support voltage information is sent by the response of CMD8. Bits 19-16 indicate the voltage range that the card supports. The card that accepted the supplied voltage returns R7 response.
Page 545: Figure 19-10. 4-Bit Data Bus Width
GD32F10x User Manual 4-bit data packet format Figure 19-10. 4-bit data bus width Start Byte Byte Byte Byte … … DAT3 … … DAT2 … … DAT1 … … DAT0 8-bit data packet format Figure 19-11. 8-bit data bus width Start Byte Byte...
Page 546: Table 19-23. Card Status
GD32F10x User Manual Type •E: Error bit. Send an error condition to the host. These bits are cleared as soon as the response (reporting the error) is sent out. •S: Status bit. These bits serve as information fields only, and do not alter the execution of the command being responded to.
Page 547 GD32F10x User Manual Clear Bits Identifier Type Value Description Condition ‘0’ = card When set, signals that the CARD_IS_LOCKED unlocked card is locked by the host ‘1’ = card locked Set when a sequence or ’0’= no error LOCK_UNLOCK_FAIL password error has been ’1’= error detected in lock/unlock card command.
Page 548 GD32F10x User Manual Clear Bits Identifier Type Value Description Condition The command has been ’0’= enabled CARD_ECC_DISABLE executed without using the ’1’= disabled internal ECC. An erase sequence was cleared before executing ’0’= cleared ERASE_RESET because an out of erase ’1’= set sequence command was received.
Page 549: Table 19-24. Sd Status
GD32F10x User Manual SD status register The SD Status contains status bits that are related to the SD Memory Card proprietary features and may be used for future application-specific usage. The size of the SD Status is one data block of 512 bits. The content of this register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
Page 550 GD32F10x User Manual Clear Bits Identifier Type Value Description Condition Number of AUs to [423:4 ERASE_SIZE be erased at a (See below) time Timeout value for erasing areas [407:4 ERASE_TIMEOUT specified by (See below) UNIT_OF_ERASE Fixed offset value [401:4 ERASE_OFFSET added to erase (See below) time.
Page 551: Table 19-25. Performance Move Field
GD32F10x User Manual move using RUs, Pm should be considered as infinity. Setting to FFh means infinity. The minimum value of Pm is defined in Table 19-25. Performance move field. Table 19-25. Performance move field PERFORMANCE_MOVE Value Definition Sequential Write 1 [MB/sec] 2 [MB/sec] ..
Page 552: Table 19-28. Erase Size Field
GD32F10x User Manual This 16-bit field indicates N . When N of AUs are erased, the timeout value is ERASE ERASE specified by ERASE_TIMEOUT (Refer to ERASE_TIMEOUT). The host should determine proper number of AUs to be erased in one operation so that the host can indicate progress of erase operation.
Page 553 GD32F10x User Manual 3 [sec] 19.6. Programming sequence Card identification 19.6.1. The host will be in card identification mode after reset and while it is looking for new cards on the bus. While in card identification mode the host resets all the cards, validates operation voltage range, identifies cards and asks them to publish Relative Card Address (RCA).
Page 554 GD32F10x User Manual If the card cannot operate on the supplied voltage, it returns no response and stays in idle state. It is mandatory to issue CMD8 prior to ACMD41 to initialize SDHC Card. Receipt of CMD8 makes the cards realize that the host supports the Physical Layer Version 2.00 and the card can enable new functions.
Page 555 GD32F10x User Manual No data commands 19.6.2. To send any non-data command, the software needs to program the SDIO_CMDCTL register and the SDIO_CMDAGMT register with appropriate parameters. Using these two registers, the host forms the command and sends it to the command bus. The host reflects the errors in the command response through the error bits of the SDIO_STAT register.
Page 556 GD32F10x User Manual following Multiple Block Write operation faster compared to the same operation without preceding ACMD23. The host will use this command to define how many number of write blocks are going to be send in the next write operation. Steps involved in a single-block or multiple-block write are: 1.
Page 557 GD32F10x User Manual If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed, the card shall detect a block misalignment at the beginning of the first misaligned block, set the ADDRESS_ERROR error bit in the status register, abort transmission and wait in the Data State for a stop command.
Page 558 GD32F10x User Manual main memory field (defined by the card in the CSD register). Therefore, the maximum clock frequency for the stream write operation is given by the following formula: WRITE_BL_LEN -100*NSAC max write frequence = min (TRAN_SPEED, (19-2) TAAC*R2W_FACTOR TRAN_SPEED: Max bus clock frequency.
Page 559 GD32F10x User Manual READ_BL_LEN: Max read data block length. NSAC: Data read access-time 2 in CLK cycles. TAAC: Data read access-time 1. R2W_FACTOR: Write speed factor. All the parameters are defined in CSD register. If the host attempts to use a higher frequency, the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command.
Page 560 GD32F10x User Manual Bus width selection 19.6.7. After the host has verified the functional pins on the bus it should change the bus width configuration. For MMC, using the SWITCH command (CMD6).The bus width configuration is changed by writing to the BUS_WIDTH byte in the Modes Segment of the EXT_CSD register (using the SWITCH command to do so).
Page 561: Table 19-31. Lock Card Data Structure
GD32F10x User Manual which later will be used for unlocking the card. The password and its size are kept in a 128- bit PWD and 8-bit PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase them. Locked cards respond to (and execute) all commands in the basic command class (class 0), ACMD41, CMD16 and lock card command class (class 7).
Page 562 GD32F10x User Manual  Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the new password. In the case that a password replacement is done, then the block size shall consider that both passwords (the old and the new one) are sent with the command.
Page 563 GD32F10x User Manual  Select a card (CMD7), if not previously selected.  Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the currently used password. ...
Page 564: Figure 19-12. Read Wait Control By Stopping Sdio_Clk
GD32F10x User Manual SDIO_DAT[2] show the Read Wait mode about stop the SDIO_CLK and use SDIO_DAT[2]. Figure 19-12. Read wait control by stopping SDIO_CLK SDIO_CLK Read data 1a Interrupt period Read data 1b 2 CLK 1 CLK 2 CLK Figure 19-13. Read wait operation using SDIO_DAT[2] We can start the Read Wait interval before the data block is received: when the data unit is enabled (SDIO_DATACTL[0] bit set), the SD I/O specific operation is enabled (SDIO_DATACTL[11] bit set), Read Wait starts (SDIO_DATACTL[10] = 0 and...
Page 565: Figure 19-15. Read Interrupt Cycle Timing
GD32F10x User Manual released (BS=0). At this time, a read to function 2 is started. Once that single block read is completed, the resume is issued to function, causing the data transfer to resume (DF=1). Figure 19-14. Function2 read cycle inserted during function1 multiple read cycle When the host sends data to the card, the host can suspend the write operation.
Page 566: Figure 19-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
GD32F10x User Manual When transferring multiple blocks of data in the 4-bit SD mode, a special definition of the interrupt period is required. In order to allow the highest speed of communication, the interrupt period is limited to a 2-clock interrupt period. Card that wants to send an interrupt signal to the host shall assert DAT1 low for the first clock and high for the second clock.
Page 567: Figure 19-19. The Operation For Command Completion Disable Signal
GD32F10x User Manual CE-ATA defines a command completion signal that the device uses to notify the host upon normal ATA command completion or when ATA command termination has occurred due to an error condition the device has encountered. If the ‘enable CMD completion’ bit SDIO_CMDCTL[12] is set and the ‘not interrupt Enable’ bit SDIO_CMDCTL[13] is reset, the CSM waits for the command completion signal in the Waitcompl state.
Page 568 GD32F10x User Manual 19.8. Register definition SDIO base address: 0x4001 8000 Power control register (SDIO_PWRCTL) 19.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value PWRCTL[1:0] SDIO power control bits.
Page 569 GD32F10x User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value HWCLKEN Hardware Clock Control enable bit If this bit is set, hardware controls the SDIO_CLK on/off depending on the system bus is very busy or not. There is no underrun/overrun error when this bit is set, because hardware can close the SDIO_CLK when almost underrun/overrun.
Page 570 GD32F10x User Manual Reset value: 0x0000 0000 This register defines 32-bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits Fields Descriptions 31:0 CMDAGMT[31:0] SDIO card command argument...
Page 571 GD32F10x User Manual ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card. 0: no completion signal 1: have completion signal SUSPEND SD I/O suspend command(SD I/O only) This bit defines whether the CSM to send a suspend command or not.
Page 572: Table 19-32. Sdio_Respx Register At Different Response Type
GD32F10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RSPCMDIDX[5:0] Last response command index Read-only bits field. This field contains the command index of the last command response received.
Page 573 GD32F10x User Manual Data timeout register (SDIO_DATATO) 19.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits Fields Descriptions 31:0 DATATO[31:0] Data timeout period These bits define the data timeout period count by SDIO_CLK. When the DSM enter the state WaitR or BUSY, the internal counter which loads from this register starts decrement.
Page 574 GD32F10x User Manual updated before being written to the data control register when need a data transfer. Data control register (SDIO_DATACTL) 19.8.9. Address offset: 0x2C Reset value: 0x0000 0000 This register controls the DSM. This register has to be accessed by word(32-bit) Reserved TRANS Reserved...
Page 575 GD32F10x User Manual 1001: block size = 2 = 512 bytes 1010: block size = 2 = 1024 bytes 1011: block size = 2 = 2048 bytes 1100: block size = 2 = 4096 bytes 1101: block size = 2 = 8192 bytes 1110: block size = 2 = 16384 bytes...
Page 576 GD32F10x User Manual 31:25 Reserved Must be kept at reset value 24:0 DATACNT[24:0] Data count value Read-only bits field. When these bits are read, the number of remaining data bytes to be transferred is returned. Status register (SDIO_STAT) 19.8.11. Address offset: 0x34 Reset value: 0x0000 0000 This register is read only.
Page 577 GD32F10x User Manual Receive FIFO is half full: at least 8 words can be read in the FIFO Transmit FIFO is half empty: at least 8 words can be written into the FIFO RXRUN Data reception in progress TXRUN Data transmission in progress CMDRUN Command transmission in progress DTBLKEND...
Page 578 GD32F10x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag. 21:11 Reserved Must be kept at reset value...
Page 579 GD32F10x User Manual This register has to be accessed by word(32-bit) ATAENDI SDIOINTI RXDT TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE VALIE CMDRUN DTBLK DTCRC CCRC RFHIE TFHIE RXRUNIE TXRUNIE STBITEIE DTENDIE RXOREIE TXUREIE ENDIE SENDIE RECVIE TMOUTIE TMOUTIE ERRIE ERRIE Bits Fields Descriptions...
Page 580 GD32F10x User Manual Write 1 to this bit to enable the interrupt. DTBLKENDIE Data block end interrupt enable Write 1 to this bit to enable the interrupt. STBITEIE Start bit error interrupt enable Write 1 to this bit to enable the interrupt. DTENDIE Data end interrupt enable Write 1 to this bit to enable the interrupt.
Page 581 GD32F10x User Manual 31:24 Reserved Must be kept at reset value 23:0 FIFOCNT[23:0] FIFO counter. These bits define the remaining number words to be written or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is word- aligned or SDIO_DATALEN[24:2]+1 if SDIO_DATALEN is not word-aligned) when DATAEN is set, and start count decrement when a word write to or read from the FIFO.
Page 582 GD32F10x User Manual External memory controller (EXMC) Overview 20.1. The external memory controller EXMC, is used as a translator for MCU to access a variety of external memory. By configuring the related registers, it can automatically convert AMBA memory access protocol into a specific memory access protocol defined in the configuration register, such as SRAM, ROM, NOR Flash, NAND Flash and PC Card.
Page 583: Figure 20-1. The Exmc Block Diagram
GD32F10x User Manual Figure 20-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NAND-Flash/PC Card NOR-Flash/PSRAM Controller Controller NOR/PSR Share PSRAM PC Card NAND NOR/PSRA AM/NAND d Pins Pins Pins Pins M Pins Shared Pin...
Page 584: Figure 20-2. Exmc Memory Banks
GD32F10x User Manual External device address mapping 20.3.3. Figure 20-2. EXMC memory banks Address Banks Supported memory type 0x6000 0000 Bank0(4x64M) NOR/PSRAM 0x6FFF FFFF 0x7000 0000 Bank1(256M) 0x7FFF FFFF NAND 0x8000 0000 Bank2(256M) 0x8FFF FFFF 0x9000 0000 Bank3(256M) PC Card 0x9FFF FFFF EXMC access space is divided into multiple banks.
Page 585 GD32F10x User Manual Figure 20-3. Four regions of bank0 address mapping HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency. EXMC can adjust HADDR to accommodate the data width of the external memory according to the following rules. –...
Page 586: Figure 20-4. Nand/Pc Card Address Mapping
GD32F10x User Manual Figure 20-4. NAND/PC Card address mapping EXMC Memory Address Memory Space Bank 0x7000 0000 Common Memory Space 0x73FF FFFF Bank1 0x7800 0000 Attribute Memory Space 0x7BFF FFFF 0x8000 0000 Common Memory Space 0x83FF FFFF Bank2 0x8800 0000 Attribute Memory Space 0x8BFF FFFF...
Page 587: Table 20-1. Nor Flash Interface Signals Description
GD32F10x User Manual – When HADDR [17:16] = 00, the data area is selected. – When HADDR [17:16] = 01, the command area is selected. – When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as follows.
Page 588: Table 20-2. Psram Non-Muxed Signal Description
GD32F10x User Manual EXMC Pin Direction Mode Functional description Async/Sync Input/output Address/Data bus (muxed) EXMC_D[15:0] Async/Sync Input/output Data bus (non-muxed) Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal EXMC_NL(NADV) Output Async/Sync...
Page 589 GD32F10x User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Sync Sync Async Use of byte lanes Async EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses PSRAM Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync...
Page 590: Table 20-4. Nor / Psram Controller Timing Parameters
GD32F10x User Manual Table 20-4. NOR / PSRAM controller timing parameters Parameter Function Access mode Unit CKDIV Sync Clock divide ratio Sync HCLK DLAT Data latency Sync EXMC_CLK BUSLAT Bus latency Async/Sync read HCLK DSET Data setup time Async HCLK AHLD Address hold time Async(muxed)
Page 591: Figure 20-6. Mode 1 Read Access
GD32F10x User Manual Asynchronous access timing diagram Mode 1 - SRAM/CRAM Figure 20-6. Mode 1 read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK)
Page 592: Figure 20-8. Mode A Read Access
GD32F10x User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx SBRSTEN Reserved NREN No effect Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 0x0000 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect...
Page 593: Figure 20-9. Mode A Write Access
GD32F10x User Manual Figure 20-9. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The different between mode A and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode A write timing configuration is independent of its read configuration.
Page 594: Figure 20-10. Mode 2/B Read Access
GD32F10x User Manual Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30 Reserved 29-28 WASYNCMOD 27-24 DLAT No effect 23-20...
Page 595: Figure 20-11. Mode 2 Write Access
GD32F10x User Manual Figure 20-11. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET+1 HCLK) (DSET HCLK) Figure 20-12. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 596: Figure 20-13. Mode C Read Access
GD32F10x User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx(Mode 2, Mode B) Depends on memory NRTP 0x2, NOR Flash NRMUX NRBKEN EXMC_SNTCFGx(Read and write in mode 2,read in mode B) 31-30 Reserved 0x0000 29-28 ASYNCMOD Mode B: 0x1 27-24 DLAT No effect...
Page 597: Figure 20-14. Mode C Write Access
GD32F10x User Manual Figure 20-14. Mode C write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The differences between mode C and mode 1 write timing are that read/write timing is specified by the same set of timing configuration, while mode C write timing configuration is independent of its read configuration, and the toggle of NOE and NADV are different.
Page 598: Figure 20-15. Mode D Read Access
GD32F10x User Manual Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode C:0x2 27-24 DLAT No effect 23-20...
Page 599: Figure 20-16. Mode D Write Access
GD32F10x User Manual Figure 20-16. Mode D write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WAHLD+1 HCLK) (WDSET HCLK) Table 20-10.
Page 600: Figure 20-17. Multiplex Mode Read Access
GD32F10x User Manual AHLD Depends on memory and user ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode D:0x3 Don’t care 27-24 DLAT 23-20 CKDIV No effect 19-16 Reserved 15-8 WDSET Depends on memory and user WAHLD Depends on memory and user WASET Depends on memory and user...
Page 601: Table 20-11. Multiplex Mode Related Registers Configuration
GD32F10x User Manual Table 20-11. Multiplex mode related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31-20 Reserved 0x000 SYNCWR 18-16 Reserved ASYNCWAIT Depends on memory EXMODEN NRWTEN WREN Depends on memory NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 602: Figure 20-19. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32F10x User Manual ≥(maxT )+4HCLK (20-3) DATA_SETUP WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE Otherwise ≥ 4HCLK (20-4) DATA_SETUP Figure 20-19. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Output Enable (EXMC_NOE) Data...
Page 603 GD32F10x User Manual 1. Data latency and NOR Flash latency Data latency is the number of EXMC_CLK cycles to wait before sampling the data. The relationship between data latency and NOR Flash specification’s latency parameter is as follows: For NOR Flash’s specification excluding the EXMC_NADV cycle, their relationship should be: NOR Flash latency=DLAT+2 (20-6) For NOR Flash’s specification including the EXMC_NADV cycle, their relationship should be:...
Page 604: Figure 20-21. Read Timing Of Synchronous Multiplexed Burst Mode
GD32F10x User Manual transactions. Synchronous mux burst read timing - NOR, PSRAM (CRAM) Figure 20-21. Read timing of synchronous multiplexed burst mode HCLK Clock (EXMC_CLK) Address Address [25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Wait (EXMC_NWAIT)
Page 605: Figure 20-22. Write Timing Of Synchronous Multiplexed Burst Mode
GD32F10x User Manual 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1, EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge 15-8 DSET No effect AHLD No effect ASET No effect Mode SM –Synchronous mux burst write timing – PSRAM (CRAM) Figure 20-22.
Page 606: Table 20-14. 8-Bit Or 16-Bit Nand Interface Signal
GD32F10x User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx Reserved NREN Depends on memory NRTP NRMUX 0x1, Depends on users NRBKEN EXMC_SNTCFGx(Write) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above: 0x1, EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge...
Page 607: Table 20-16. Bank1/2/3 Of Exmc Support The Memory And Access Mode
GD32F10x User Manual EXMC Pin Direction Functional description Only for 16-bit I/O space data transmission width (Must be EXMC_NIOS16 Input shorted to GND) EXMC_NIORD Output I/O space read enable EXMC_NIOWR Output I/O space write enable Register signal indicating if access is in Common space EXMC_NREG Output or Attribute space...
Page 608: Figure 20-23. Access Timing Of Common Memory Space Of Pc Card Controller
GD32F10x User Manual PC Card Time to keep the data bus high High impedance time of the HCLK impedance after starting write memory data bus (HIZ) operation The number of HCLK clock cycles to keep address valid Memory hold time (HLD) HCLK after sending the command.
Page 609: Figure 20-24. Access To None "Nce Don't Care" Nand Flash
GD32F10x User Manual needed, EXMC_NPATCFGx has to be configured. Send the command of NAND Flash read operation to the common space. Namely, during the valid period of EXMC_NCE and EXMC_NWE, when EXMC_CLE (EXMC_A[16]) becomes valid (high level), data on the I/O pins is regarded as a command by NAND Flash.
Page 610 GD32F10x User Manual period of ATTHLD, NAND Flash waits for EXMC_INTx signal to be busy, and the time period of ATTHLD should be greater than tWB (tWB is defined as the time from EXMC_NWE high to EXMC_INTx low). For NCE-sensitive NAND Flash, after the first command byte following address bytes has been entered, EXMC_NCE must remain low until EXMC_INTx goes from low to high.
Page 611 GD32F10x User Manual 16-bit access operation is being performed. EXMC_NIOWR and EXMC_NIORD dictate whether the on-going operation is a write or read operation, and EXMC_NREG is low during IO space access. AHB access on 16-bit PC/CF card: Common space: It is usually where data are stored, it could be accessible either in byte or in half-word mode, and odd address access is not supported in byte mode.
Page 612 GD32F10x User Manual Register definition 20.4. EXMC base address: 0xA000 0000 NOR/PSRAM controller registers 20.4.1. SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DB for region0, and 0x0000 30D2 for region1, region2, and region3. This register has to be accessed by word (32-bit).
Page 613 GD32F10x User Manual 1: Enabled write in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state 1: NWAIT signal is active during wait state WRAPEN Wrapped burst mode enable 0: Disable wrap burst mode support...
Page 614 GD32F10x User Manual This register has to be accessed by word (32-bit). Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0] DSET[7:0] AHLD[3:0] ASET[3:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:28 ASYNCMOD[1:0] Asynchronous access mode The bits are valid only when the EXMODEN bit in the EXMC_SNCTLx register is 1. 00: Mode A access 01: Mode B access 10: Mode C access...
Page 615 GD32F10x User Manual AHLD[3:0] Address hold time This field is used to set the time of address hold phase, which only used in mode D and multiplexed mode. 0x0: Reserved 0x1: Address hold time = 2 * HCLK …… 0xF: Address hold time = 16 * HCLK ASET[3:0] Address setup time This field is used to set the time of address setup phase.
Page 616 GD32F10x User Manual …… 0xF: Data latency of first burst access is 17 EXMC_CLK 23:20 CKDIV[3:0] Synchronous clock divide ratio. This filed is only effect in synchronous mode. 0x0: Reserved 0x1: EXMC_CLK period = 2 * HCLK period …… 0xF: EXMC_CLK period = 16 * HCLK period 19:16 Reserved Must be kept at reset value.
Page 617 GD32F10x User Manual ATR[2:0] CTR[3:0] Reserved ECCEN NDW[1:0] NDTP NDBKEN NDWTEN Reserved Bits Fields Description 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0]...
Page 618 GD32F10x User Manual 0: Disable wait function 1: Enable wait function Reserved Must be kept at reset value. NAND Flash/PC Card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0040 This register has to be accessed by word (32-bit).
Page 619 GD32F10x User Manual 1: Detect interrupt falling edge INTHS Interrupt high-level status 0: Not detect interrupt high-level 1: Detect interrupt high-level INTRS Interrupt rising edge status 0: Not detect interrupt rising edge 1: Detect interrupt rising edge NAND Flash/PC Card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFFFF FFFF...
Page 620 GD32F10x User Manual Define the minimum time to maintain command 0x00: Reserved 0x01: COMWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: COMWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: COMWAIT = 256 * HCLK (+NWAIT active cycles) COMSET[7:0] Common memory setup time Define the time to build address before sending command...
Page 621 GD32F10x User Manual …… 0xFE: ATTHLD = 254 * HCLK 0xFF: ATTHLD = 255 * HCLK 15:8 ATTWAIT[7:0] Attribute memory wait time Define the minimum time to maintain command 0x00: Reserved 0x01: ATTWAIT = 2 * HCLK (+NWAIT active cycles) ……...
Page 622 GD32F10x User Manual …… 0xFF: IOHLD = 255 * HCLK 15:8 IOWAIT[7:0] IO space wait time Define the minimum time to maintain command 0x00: Reserved 0x01: IOWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFF: IOWAIT = 256 * HCLK (+NWAIT active cycles) IOSET[7:0] IO space setup time Define the time to build address before sending command...
Page 623 GD32F10x User Manual Controller area network (CAN) Overview 21.1. CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A and B.
Page 624: Figure 21-1. Can Module Block Diagram
GD32F10x User Manual  Time Stamp sent in last two data bytes Function overview 21.3. Figure 21-1. CAN module block diagram shows the CAN block diagram. Figure 21-1. CAN module block diagram Transmit Receive CAN0 CAN0 Tx/Rx mailbox[0..2] FIFO[0..1] Transmit Receive CAN1 CAN1 Tx/Rx...
Page 625 GD32F10x User Manual Sleep working mode to Normal working mode: Clear IWMOD and SLPWMOD bit in CAN_CTL register. Initial working mode When the configuration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode.
Page 626 GD32F10x User Manual Loopback communication mode Loopback communication mode means the transmitted messages are transferred into the RX FIFOs, the RX pin is disconnected from the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave.
Page 627: Figure 21-2. Transmission Register
GD32F10x User Manual Figure 21-2. Transmission register Transmit mailbox state A transmit mailbox can be used when it is free (empty state). If the mailbox is filled with data, set TEN bit in CAN_TMIx register to prepare for starting the transmission (pending state). If more than one mailbox is in the pending state, they need scheduling the transmission (scheduled state).
Page 628 GD32F10x User Manual error detected on the CAN bus. Steps of sending a frame To send a frame through the CAN: Step 1: Select one free transmit mailbox. Step 2: Configure four transmission registers with the application’s acquirement. Step 3: Set TEN bit in CAN_TMIx register. Step 4: Check the transmit status.
Page 629: Figure 21-4. Reception Register
GD32F10x User Manual Figure 21-4. Reception register RX FIFO Rx FIFO has three mailboxes. The reception frames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of frames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
Page 630: Figure 21-5. 32-Bit Filter
GD32F10x User Manual Step 3: Set the RFD bit in CAN_RFIFOx register. Filtering function 21.3.5. The CAN receives frames from the CAN bus. If the frame passes the filter, it is stored in the Rx FIFOs. Otherwise, the frame will be discarded without intervention by the software. The identifier of frame is used for the matching of the filter.
Page 631: Figure 21-9. 32-Bit List Mode Filter
GD32F10x User Manual List mode The filter consists of frame identifiers. The filter can determine whether a frame will be discarded or not. When one frame arrived, the filter will check which member can match the identifier of the frame. Figure 21-9.
Page 632: Table 21-2. Filtering Index
GD32F10x User Manual filter number N passes the filters, the filter index is N. It stores in the FI bits in CAN_RFIFOMPx. Filter bank has filter index once it is associated with the FIFO no matter whether the bank is active or not.
Page 633 GD32F10x User Manual 32-bit mode is higher than 16-bit mode. List mode is higher than mask mode. Smaller filter number has the higher priority. Time-triggered communication 21.3.6. The time-triggered CAN protocol is a higher layer protocol on top of the CAN data link layer. Time-triggered communication means that activities are triggered by the elapsing of time segments.
Page 634: Figure 21-11. The Bit Time
GD32F10x User Manual The normal bit time from the CAN protocol has three segments as follows: Synchronization segment (SYNC_SEG): a bit change is expected to occur within this time segment. It has a fixed length of one time quantum (1 × �� ...
Page 635 GD32F10x User Manual �� = 1 × �� (21-3) ��_�� = (1 + ��. ��1) × �� (21-4) ��1 �� = (1 + ��. ��2) × �� (21-5) ��2 �� = (1 + ��. ��) × �� (21-6) ��...
Page 636 GD32F10x User Manual CAN_INTEN register will be set: TX mailbox 0 transmit finished: MTF0 bit in the CAN_TSTAT register is set. – TX mailbox 1 transmit finished: MTF1 bit in the CAN_TSTAT register is set. – TX mailbox 2 transmit finished: MTF2 bit in the CAN_TSTAT register is set. –...
Page 637 GD32F10x User Manual Register definition 21.4. CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 Control register (CAN_CTL) 21.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit) Reserved SLPWMO SWRST Reserved ABOR RFOD IWMOD Bits...
Page 638 GD32F10x User Manual If this bit is set, the CAN leaves sleep working mode when CAN bus activity is detected, and SLPWMOD bit in CAN_CTL register will be cleared automatically. 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission...
Page 639 GD32F10x User Manual 31:12 Reserved Must be kept at reset value. RX level LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved...
Page 640 GD32F10x User Manual mode to normal working mode, this bit will be cleared after receiving 11 consecutive recessive bits from the CAN bus. 0: CAN is not in the state of sleep working mode 1: CAN is in the state of sleep working mode Initial working state This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register.
Page 641 GD32F10x User Manual TME2 Transmit mailbox 2 empty 0: Transmit mailbox 2 not empty 1: Transmit mailbox 2 empty TME1 Transmit mailbox 1 empty 0: Transmit mailbox 1 not empty 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24...
Page 642 GD32F10x User Manual This bit is reset by hardware when the mailbox 1 is empty. 14:12 Reserved Must be kept at reset value. MTE1 Mailbox 1 transmit error This bit is set by hardware when the transmit error occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register.
Page 643 GD32F10x User Manual 1: Mailbox 0 transmit finished with no error MTF0 Mailbox 0 transmit finished This bit is set by hardware when the transmission finishes or aborts. This bit is reset by writting 1 to this bit or TEN bit in CAN_TMI0 is 1. 0: Mailbox 0 transmit is progressing 1: Mailbox 0 transmit finished Receive message FIFO0 register (CAN_RFIFO0)
Page 644 GD32F10x User Manual Receive message FIFO1 register (CAN_RFIFO1) 21.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w0 rc_w1 Bits Fields Descriptions Must be kept at reset value. 31:6 Reserved Rx FIFO1 dequeue...
Page 645 GD32F10x User Manual ERRIE Reserved ERRNIE BOIE PERRIE WERRIE Reserved RFOIE1 RFFIE1 RFNEIE1 RFOIE0 RFFIE0 RFNEIE0 TMEIE Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. SLPWIE Sleep working interrupt enable 0: Sleep working interrupt disabled 1: Sleep working interrupt enabled Wakeup interrupt enable 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled...
Page 646 GD32F10x User Manual 0: Rx FIFO1 not empty interrupt disabled 1: Rx FIFO1 not empty interrupt enabled RFOIE0 Rx FIFO0 overfull interrupt enable 0: Rx FIFO0 overfull interrupt disabled 1: Rx FIFO0 overfull interrupt enabled RFFIE0 Rx FIFO0 full interrupt enable 0: Rx FIFO0 full interrupt disabled 1: Rx FIFO0 full interrupt enabled RFNEIE0...
Page 647 GD32F10x User Manual 011: Acknowledgment error 100: Bit recessive error 101: Bit dominant error 110: CRC error 111: Set by software Reserved Must be kept at reset value. BOERR Bus-Off error Whenever the CAN enters Bus-Off state, the bit will be set by hardware. PERR Passive error Whenever the TECNT or RECNT is greater than 127, the bit will be set by...
Page 648 GD32F10x User Manual Reserved Must be kept at reset value. 22:20 BS2[2:0] Bit segment 2 Bit segment 2 time quantum = BS2[2:0]+1 19:16 BS1[3:0] Bit segment 1 Bit segment 1 time quantum = BS1[3:0]+1 15:10 Reserved Must be kept at reset value. BAUDPSC[9:0] Baud rate prescaler The CAN baud rate prescaler...
Page 649 GD32F10x User Manual This bit is set by software when one frame will be transmitted and reset by hardware when the transmit mailbox is empty. 0: Transmit disabled 1: Transmit enabled Transmit mailbox property register (CAN_TMPx) (x=0..2) 21.4.10. Address offset: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) TS[15:0]...
Page 650 GD32F10x User Manual DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) 21.4.12. Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0]...
Page 651 GD32F10x User Manual SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Reserved Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:1 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame...
Page 652 GD32F10x User Manual 15:8 FI[7:0] Filtering index The index of the filter which the frame passes. Reserved Must be kept at reset value. DLENC[3:0] Data length code DLENC[3:0] is the number of bytes in a frame. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) 21.4.15.
Page 653 GD32F10x User Manual Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8 DB5[7:0] Data byte 5 DB4[7:0] Data byte 4 Filter control register (CAN_FCTL) (Just for CAN0) 21.4.17. Address offset: 0x200 Reset value: 0x2A1C 0E01 This register has to be accessed by word(32-bit) The filter control register with GD32F10x XD/HD/MD : Reserved...
Page 654 GD32F10x User Manual 1: Filter lock disabled Filter mode configuration register (CAN_FMCFG) (Just for CAN0) 21.4.18. Address offset: 0x204 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set. Reserved FMOD27 FMOD26 FMOD25 FMOD24 FMOD23 FMOD22 FMOD21 FMOD20 FMOD19 FMOD18 FMOD17 FMOD16 FMOD15 FMOD14 FMOD13 FMOD12 FMOD11 FMOD10...
Page 655 GD32F10x User Manual 1: Filter x with 32-bit scale Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0) 21.4.20. Address offset: 0x214 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set.
Page 656 GD32F10x User Manual 1: Filter x working enabled Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) (Just for CAN0) 21.4.22. Address offset: 0x240+8*x+4*y, (x=0..27, y=0,1) Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) FD31 FD30 FD29 FD28 FD27 FD26...
Page 657 GD32F10x User Manual Ethernet (ENET) Overview 22.1. This section applies only to GD32F107xx connectivity line devices. This chapter describes the Ethernet peripheral module. There is a media access controller (MAC) designed in Ethernet module to support 10/100Mbps interface speed. For more efficient data transfer between Ethernet and memory, a DMA controller is designed in this module.
Page 658: Figure 22-1. Enet Module Block Diagram
GD32F10x User Manual  Support Ethernet frame time stamping for both transmit and receive operation, which describes in IEEE 1588-2008, and 64 bit time stamps are given in each frame’s status.  Two independent FIFO of 2K Byte for transmitting and receiving. ...
Page 659: Figure 22-2. Mac/Tagged Mac Frame Format
GD32F10x User Manual  TxMTL, used to control, management and store the transmit data. TxFIFO is implemented in this module and used to cache transmitting data from memory for MAC transmission.  The MAC transmission relative control registers, used to control frame transmit. Receiving data module includes: ...
Page 660: Table 22-1. Ethernet Pin Configuration
GD32F10x User Manual The Ethernet frame’s 32-bit CRC calculation value generating polynomial is fixed 0x04C11DB7 and this polynomial is used in all 32-bit CRC calculation places in Ethernet module, as follows: G(x) = x + x + 1 Ethernet signal description 22.2.3.
Page 661: Figure 22-3. Station Management Interface Signals
GD32F10x User Manual (reset state) ETH_MII_TX_EN AF output push-pull PB11 TX_EN TX_EN ETH_RMII_TX_EN highspeed (50 MHz) ETH_MII_TXD0 AF output push-pull PB12 TXD0 TXD0 ETH_RMII_TXD0 highspeed (50 MHz) ETH_MII_TXD1 AF output push-pull PB13 TXD1 TXD1 ETH_RMII_TXD1 highspeed (50 MHz) Floating input ETH_RMII_CRS_DV RX_DV CRS_DV...
Page 662 GD32F10x User Manual SMI write operation Applications need to write transmission data to the ENET_MAC_PHY_DATA register and operate the ENET_MAC_PHY_CTL register as follows: Set the PHY device address and PHY register address, and set PW to 1, so that can select write mode.
Page 663: Figure 22-4. Media Independent Interface Signals
GD32F10x User Manual Table 22-2. Clock range AHB clock MDC clock Selection 20~35MHz AHB clock/16 35~60MHz AHB clock/26 90~108 MHz AHB clock/64 60~90MHz AHB clock/42 MII/RMII selection The application can select the MII or RMII mode through the configuration bit 23 of the AFIO_PCF0 register ENET_PHY_SEL while the Ethernet controller is under reset state or before enabling the clocks.
Page 664: Table 22-3. Rx Interface Signal Encoding
GD32F10x User Manual It is active when either transmit or receive medium is in non idle state. The PHY must ensure that the MII_CRS signal remains asserted throughout the duration of a collision condition. This signal is not required to transition synchronously with respect to the TX and RX clock. - MII_COL: Collision detection signal, only working in Half-duplex mode, controlled by the PHY.
Page 665: Figure 22-5. Reduced Media-Independent Interface Signals
GD32F10x User Manual RMII: Reduced media independent interface The reduced media-independent interface (RMII) specification reduces the pin count during Ethernet communication. According to the IEEE 802.3 standard, an MII contains 16 pins for data and control. The RMII specification is dedicated to reduce the pin count to 7. The RMII block has the following characteristics: ...
Page 666 GD32F10x User Manual MAC function overview 22.3.2. MAC module can achieve the following functions: Data package (transmission and reception)  Frame detecting/decoding and frame boundary delimitation.  Addressing (handling source address and destination address).  Error conditions detect. Medium access management in Half-duplex mode ...
Page 667 GD32F10x User Manual data but the frame is not integrated. This is when the transmit FIFO size is smaller than the Ethernet frame to be transmitted, the frame is popped towards the MAC when the transmit FIFO becomes almost full. Handle special cases In the transmission process, due to the insufficient TxDMA descriptor or misuse of FTF bit in ENET_DMA_CTL register (when this bit is set, it will clear FIFO data and reset the FIFO...
Page 668 GD32F10x User Manual Transmit status word Transmit status word includes many transmit state flags for application and are updated after the complete the transmission of the frame. If timestamp function is enable, the timestamp value is also write back to transmit descriptor along with transmit status. Transmit FIFO flush operation Application can clear TxFIFO and reset the FIFO data pointer by setting FTF bit (bit 20) of ENET_DMA_CTL register.
Page 669 GD32F10x User Manual of time. If the application sets transmit flow control bit TFCEN in ENET_MAC_FCTL register, MAC will generate and transmit a pause frame when either of two conditions is satisfied in Full-duplex mode. There are two conditions to start transmit pause frames: Application sets FLCB/BKPA bit in ENET_MAC_FCTL register to immediately send a pause frame.
Page 670 GD32F10x User Manual 3) The carrier sense signal not active during the whole gap period. In this case, the counter stops after reaches the configured gap time and sends frame if the second frame has pended. Transmit checksum offload The MAC supports transmit checksum offload. This feature can calculate checksum and insert it in the transmit frame, and detect error in the receive frame.
Page 671 GD32F10x User Manual 3) IP frames without TCP/UDP/ICMPv4/ICMPv6 payload. 4) IPv6 frames with routing headers. The checksum offload module calculates the TCP, UDP, or ICMP payload and inserts the result into its corresponding field in the header. It has two modes when working, as follows: 1) TCP, UDP, or ICMPv6 pseudo-header is not included in the checksum calculation and is assumed to be present in the input frame’s checksum field.
Page 672 GD32F10x User Manual but the result will not affect whether current frame passes the filter or not. Unicast frame destination address filter For a unicast frame, application has two modes for filtering: the one is using static physical address (by setting HUF bit to ‘0’), the other is using hash list (by setting HUF bit to ‘1’). ...
Page 673: Table 22-4. Destination Address Filtering Table
GD32F10x User Manual Unicast frame source address filter Enable MAC address 1 to MAC address 3 register and set the corresponding SAF bit in the MAC address high register, the MAC compares and filter the source address (SA) field in the received frame with the values programmed in the SA registers.
Page 674: Table 22-5. Source Address Filtering Table
GD32F10x User Manual Pass on hash filter match and drop PAUSE control frames if PCFRM = 0x Pass on hash or perfect/group filter match and drop PAUSE control frames if PCFRM = 0x Fail on perfect/group filter match and drop PAUSE control frames if PCFRM = Fail on hash filter match and drop PAUSE control frames if PCFRM = 0x Fail on hash or perfect/group filter...
Page 675 GD32F10x User Manual Reception process of MAC Received frames will be pushed to the RxFIFO. The MAC strips the preamble and SFD of the frame, and starts pushing the frame data beginning with the first byte following the SFD to the RxFIFO.
Page 676 GD32F10x User Manual suspending a certain time which is indicated in pause time field of detected pause control frame and then to transmit data. This function can set by RFCEN bit in ENET_MAC_FCTL register. If this function is not enabled, the MAC will ignore the received pause frames. If this function is enabled, MAC can decode this frame.
Page 677 GD32F10x User Manual  If the RxFIFO is configured in Store-and-Forward mode, the MAC can filter and discard all error frames. But according to the configuration of FERF and FUF bit in ENET_DMA_CTL register, RxFIFO can also receive and forward such error frame and the frame that length is less than the minimum length.
Page 678 GD32F10x User Manual and MSC reception counters will automatically update:  Alignment error.  CRC mismatch(calculated CRC value is different from FSC field value).  Runt frame (frame length is shorter than 64 bytes).  Length error (length field value is different from the actual received data bytes). ...
Page 679: Figure 22-6. Wakeup Frame Filter Register
GD32F10x User Manual strongly recommended to operate eight times sequentially. This means continuously write 8 times will configure the filter registers and continuously read 8 times will get the values of filter registers. Figure 22-6. Wakeup frame filter register Wakeup Frame Filter Filter 0 Byte Mask Register 0 Wakeup Frame Filter...
Page 680 GD32F10x User Manual Ethernet block and used to trigger a wakeup event. Setting MPE bit in ENET_MAC_WUM register can enable this function. This type of frame’s format is as follows: starts by 6 continuous bytes of the value 0xFF (0xFFFF FFFF FFFF) in anywhere of the frame behind the destination and source address field, then there are 16 duplicate MAC addresses without any interruption and pause.
Page 681 GD32F10x User Manual Check the RS bit in ENET_DMA_STAT register, waiting receive DMA read out all the frames in the receive FIFO and then close RxDMA. Configure and enable the external interrupt line 19, so that it can generate an interrupt or event.
Page 682: Figure 22-7. System Time Update Using The Fine Correction Method
GD32F10x User Manual System time correction method The 64-bit PTP system time update by the PTP input reference clock. The PTP system time is used as the source to record transmission/reception frame’s timestamp. The system time initialization and calibration support two methods: coarse method and fine method. The purpose of calibration is to correct the frequency offset.
Page 683 GD32F10x User Manual changes to 65/50=1.3, the value to be set in the addend register is 2 /1.30 = 0xC4EC 4EC4. If the reference clock drift higher, for example, up to 85MHz, the value addend register must be 0xA000 0000. Initially, the slave clock frequency is set to Clock Addend Value (0) in the addend register.
Page 684 GD32F10x User Manual Setting bit 9 in the ENET_MAC_INTMSK register to mask the timestamp trigger interrupt Setting bit 0 in the ENET_PTP_TSCTL register to enable timestamp function Configure the subsecond increment register according to the PTP clock frequency precision If application hopes to use fine correction method, configure the timestamp addend register and set bit 5 in the ENET_PTP_TSCTL register to 1.
Page 685 GD32F10x User Manual in the corresponding transmission/reception descriptor. The 64-bit timestamp information of transmission frame is written back to the transmit descriptor and the 64-bit timestamp information of reception frame is written back to the receive descriptor. See the detailed description in Transmit DMA descriptor with IEEE 1588 timestamp format Receive...
Page 686: Figure 22-8. Descriptor Ring And Chain Structure
GD32F10x User Manual table is an implicitly one. Explicit chaining of descriptors is accomplished by configuring the second address chained in both receive and transmit descriptors (RDES1[14] and TDES0[20]), at this time RDES2 and TDES2 are stored the data buffer address, RDES3 and TDES3 should be stored the next descriptor address, this connection method of descriptor table is called chain structure.
Page 687 GD32F10x User Manual be transferred. After starting operating, the DMA controller will read five word addresses which are 0x2000 0AB0, 0x2000 0AB4, 0x2000 0AB8, 0x2000 0ABC and 0x2000 0AC0. But when sending data to the FIFO, the first two bytes (0x2000 0AB0 and 0x2000 0AB1) and the last 3 bytes (0x2000 0AC1, 0x2000 0AC2 and 0x2000 0AC3) will be dropped.
Page 688 GD32F10x User Manual Arbitration for TxDMA and RxDMA controller There are two types of arbitration method designed for improving the efficiency of DMA controller between transmission and reception: fixed-priority and round-robin. When DAB bit in ENET_DMA_BCTL register is reset, arbiter selects round-robin method. The arbiter allocates the data bus in the ratio set by the RTPR bits in ENET_DMA_BCTL, when both of TxDMA and RxDMA controller request access simultaneously.
Page 689 GD32F10x User Manual than TX_CLK, the efficiency of transmitting two frames will be greatly reduced. To avoid the case mentioned above, application can set OSF to 1.If so, the second frame data can be read from the memory and push into FIFO without waiting the first frame’s status writing back.
Page 690 GD32F10x User Manual The TxDMA controller in OSF mode proceeds as follows: Follow steps 1-6 operation in TxDMA default mode The TxDMA controller retrieves the next descriptor without closing the previous frame’s last descriptor in which the LSG bit is set If the DAV bit of the next descriptor is set, the TxDMA controller starts reading the next frame’s data from the buffer address.
Page 691: Figure 22-9. Transmit Descriptor
GD32F10x User Manual store the whole frame data. When the last descriptor is fetched and buffer finished reading, the transmitting status will write back to it. The other descriptors (here means the descriptor whose LSG bit is reset) of the current frame will not be changed by TxDMA controller except the DAV bit will be reset to 0.
Page 692 GD32F10x User Manual Ctrl Ctrl Status[16:0] TDES0 [30:26] [23:20] [19:18] Reserved Buffer 2 byte size Reserved Buffer 1 byte size TDES1 [31:29] [28:16] [15:13] [12:0] Buffer 1 address[31:0]/Timestamp Low[31:0] TDES2 TDES3 Buffer 2 address[31:0] or Next descriptor address[31:0]/Timestamp High[31:0]  TDES0: Transmit descriptor word 0 INTC DCRC...
Page 693 GD32F10x User Manual This is valid only when the first segment (TDES0[28]) is set. 0: The MAC automatic append a CRC to the end of the transmitted frame 1: The MAC does not append a CRC to the end of the transmitted frame DPAD Disable adding pad bit This is valid only when the first segment (TDES0[28]) is set.
Page 694 GD32F10x User Manual IPHE IP header error bit IP header error occurs when any case of below happen: IPv4 frames: 1) The header length field has a value less than 0x5. 2) The header length field value in transmitting IPv4 frame is mismatch with the number of header bytes 3) The version field value does not match the length/type field value IPv6 frames:...
Page 695 GD32F10x User Manual 0:No loss of carrier occurred 1:A loss of carrier occurred during frame transmission No carrier bit 0: PHY carrier sense signal is active 1: The carrier sense signal from the PHY was not asserted during transmission Late collision bit If a collision occurs when 64 bytes (including preamble and SFD) has already transferred, this situation called late collision.
Page 696 GD32F10x User Manual Valid only in Half-duplex mode 0:No transmission deferred 1:The MAC is deferred before transmission  TDES1: Transmit descriptor word 1 Reserved TB2S[12:0] Reserved TB1S[12:0] Bits Fields Descriptions 31:29 Reserved Must be kept at reset value 28:16 TB2S[12:0] Transmit buffer 2 size bits These bits indicate byte size of the second data buffer.
Page 697 GD32F10x User Manual  TDES3: Transmit descriptor word 3 TB2AP/TTSH[31:16] TB2AP/TTSH[15:0] Bits Fields Descriptions 31:0 TB2AP/TTSH[31:0] Transmit buffer 2 address pointer (or next descriptor address) / Transmit frame timestamp high 32-bit value bits Before transmitting frame, application must configure these bits for transmit buffer 2 address (TB2AP) or the next descriptor address which is decided by descriptor type is ring or chain.
Page 698 GD32F10x User Manual closes current descriptor by resetting DAV bit and sets the LSG bit (if flushing is enabled) or resets the LSG bit (if flushing is disabled). Then the operation goes to Step 8. The next descriptor’s DAV bit is set. The RxDMA controller closes current –...
Page 699 GD32F10x User Manual mode, the available time means the complete frame is stored in RxFIFO. During receiving frame, if any one of the below cases occurs the MAC can discard the received frame data in RxFIFO and the RxDMA controller will not forward these data: 1) The received frame bytes is less than 64.
Page 700: Figure 22-10. Receive Descriptor
GD32F10x User Manual Figure 22-10. Receive descriptor  RDES0: Receive descriptor word 0 DAFF FRML[13:0] ERRS DERR SAFF LERR OERR VTAG FDES LDES IPHERR FRMT RWDT RERR DBERR CERR PCERR Bits Fields Descriptions Descriptor available bit This bit indicates the DMA controller can use this descriptor. The DMA clears this bit either when it completes the frame reception or when the buffers in this descriptor are full 0: The descriptor is owned by the CPU...
Page 701 GD32F10x User Manual RDES0[3]: Receive error RDES0[1]: CRC error REDS0[7] = 0, REDS0[5] = 1 and REDS0[0] = 1: payload checksum error REDS0[7] = 1, REDS0[5] = 1 and REDS0[0] = 0: header checksum error REDS0[7] = 1, REDS0[5] = 1 and REDS0[0] = 1: both header and payload checksum errors DERR Descriptor error bit...
Page 702 GD32F10x User Manual This error can be due to inconsistent Ethernet Type field and IP header Version field values, a header checksum mismatch in IPv4, or an Ethernet frame lacking the expected number of IP header bytes. 0: No IPv header checksum error occurred 1: An error in the IPv4 or IPv6 header Late collision bit This bit indicates a collision occurs after 64 bytes have been received...
Page 703: Table 22-6. Error Status Decoding In Rdes0
GD32F10x User Manual received encapsulated TCP, UDP or ICMP segment’s Checksum field or when the received number of payload bytes does not match the value indicated in the Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame.
Page 704 GD32F10x User Manual 0: RS bit in ENET_DMA_STAT register will immediately set after receiving the completed, then if enabled the corresponding interrupt, the interrupt will trigger. 1: RS bit in ENET_DMA_STAT register will not be set after receiving the completed, so the corresponding interrupt will not be triggered. 30:29 Reserved Must be kept at reset value...
Page 705 GD32F10x User Manual used for RxDMA controller to store the received frame if RB1S is not 0. The buffer address alignment has no limitation. RTSL: When timestamp function is enabled and LDES is set, these bits will be changed to timestamp low 32-bit value by RxDMA controller if received frame passed the filter and satisfied the snapshoot condition.
Page 706 GD32F10x User Manual Configure AFIO_PCF0 to define which interface mode is selected (MII or RMII). Configure GPIO module to make selected PADs to alternate function.  Wait the resetting complete Polling the ENET_DMA_BCTL register until the SWR bit is reset. (SWR bit is set by default after power-on reset or system reset).
Page 707: Figure 22-11. Mac Interrupt Scheme
GD32F10x User Manual has stored the receive frame. 3) Handling this receive frame data. 4) Set DAV bit of this descriptor to release this descriptor for new frame receiving. 5) Check next descriptor in table, then goes to Step 2. Ethernet interrupts 22.3.8.
Page 708: Figure 22-12. Ethernet Interrupt Scheme
GD32F10x User Manual DMA controller interrupts The DMA controller has two types of event: Normal and Abnormal. No matter what type the event is, it has an enable bit (just like mask bit) to control the generating interrupt or not. Each event can be cleared by writing 1 to it. When all of the events are cleared or all of the event enable bits are cleared, the corresponding summary interrupt bit is cleared.
Page 709 GD32F10x User Manual Register definition 22.4. ENET base address: 0x4002 8000 MAC configuration register (ENET_MAC_CFG) 22.4.1. Address offset: 0x0000 Reset value: 0x0000 8000 This register configures the operation mode of the MAC. It also configures the MAC receiver and MAC transmitter operating mode. Reserved Reserved IGBS[2:0]...
Page 710 GD32F10x User Manual 0x6: 48 bit times(For Half-duplex, must be reserved) 0x7: 40 bit times(For Half-duplex, must be reserved) Carrier sense disable bit 0: The MAC transmitter generates carrier sense error and aborts the transmission 1: The MAC transmitter ignores the MII CRS signal during frame transmission in Half-duplex mode.
Page 711 GD32F10x User Manual number calculated by following formula : 0≤dt <2 0x0: k = min (n, 10) 0x1: k = min (n, 8) 0x2: k = min (n, 4) 0x3: k = min (n, 1), n = number of times for retransmission attempt Note: This bit is valid only in Half-duplex mode Deferral check bit 0: The deferral check function is disabled.
Page 712 GD32F10x User Manual This bit controls the receive filter function. 0: Only the frame passed the filter can be forwarded to application. 1: All received frame are forwarded to application. But filter result will also be updated to receive descriptor status. 30:11 Reserved Must be kept at reset value.
Page 713 GD32F10x User Manual DAIFLT Destination address inverse filtering bit This bit makes the result of DA filtering inverse 0: Not inverse DA filtering result 1: Inverse DA filtering result Hash multicast filter bit 0: The filter uses perfect mode for filtering multicast frame. 1: The filter uses hash mode for filtering multicast frame Hash unicast filter bit 0: The filter uses perfect mode for filtering unicast frame...
Page 714 GD32F10x User Manual HLL[15:0] Bits Fields Descriptions 31:0 HLL[31:0] Hash list low bits These bits take the low 32-bit value of hash list MAC PHY control register (ENET_MAC_PHY_CTL) 22.4.5. Address offset: 0x0010 Reset value: 0x0000 0000 Reserved PA[4:0] PR[4:0] Reserved CLR[2:0] rc_w1 Bits...
Page 715 GD32F10x User Manual PHY busy bit This bit indicates the running state of operation on PHY. Application sets this bit to 1 and should wait it cleared by hardware. Application must make sure this bit is zero before writing data to ENET_MAC_PHY_CTL register and reading/writing data from/to ENET_MAC_PHY_DATA register MAC PHY data register (ENET_MAC_PHY_DATA) 22.4.6.
Page 716 GD32F10x User Manual 15:8 Reserved Must be kept at reset value. DZQP Disable Zero-quanta pause bit 0: Enable automatic zero-quanta generation function for pause control frame. 1: Disable the automatic zero-quanta generation function for pause control frame Reserved Must be kept at reset value. PLTS[1:0] Pause low threshold bits These bits configure the threshold of the pause timer for retransmitting frames...
Page 717 GD32F10x User Manual For Half-duplex mode, MAC can enter back-pressure state by application setting this bit. When the MAC is in back-pressure state, any frame presented on interface will make the MAC send a JAM pattern to inform outside a collision occurred. MAC flow control threshold register (ENET_MAC_FCTH) 22.4.8.
Page 718 GD32F10x User Manual 0x6,0x7: 1792 bytes MAC VLAN tag register (ENET_MAC_VLT) 22.4.9. Address offset: 0x001C Reset value: 0x0000 0000 This register configures the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC compares the 13 and 14 byte (length/type field) of the receiving frame with 0x8100, and the following 2 bytes (the 15 and 16 byte) are compared with the VLAN tag.
Page 719: Figure 22-13. Wakeup Frame Filter Register
GD32F10x User Manual The MAC remote wakeup frame filter register is actually a pointer to eight (with same address offset) such wakeup frame filter registers. Eight sequential write operations to this address with the offset (0x0028) will write all wakeup frame filter registers. Eight sequential read operations from this address with the offset (0x0028) will read all wakeup frame filter registers.
Page 720 GD32F10x User Manual wakeup frame Reserved Must be kept at reset value. WUFR Wakeup frame received bit This bit is cleared when this register is read 0:Has not received the wake-up frame 1:The wakeup event was generated due to reception of a wakeup frame MPKR Magic packet received bit This bit is cleared when this register is read...
Page 721 GD32F10x User Manual registers 1: The system time value equals or exceeds the value specified in the target time registers Reserved Must be kept at reset value. MSCT MSC transmit status bit 0: All the bits in register ENET_MSC_TINTF are cleared 1: An interrupt is generated in the ENET_MSC_TINTF register MSCR MSC receive status bit...
Page 722 GD32F10x User Manual WUMIM WUM interrupt mask bit 0: Unmask the interrupt generation due to the WUM bit in ENET_MAC_INTF register 1: Mask the interrupt generation due to the WUM bit in ENET_MAC_INTF register Reserved Must be kept at reset value. MAC address 0 high register (ENET_MAC_ADDR0H) 22.4.14.
Page 723 GD32F10x User Manual bits are used for address filtering in frame reception and address inserting in pause frame transmitting during transmit flow control. MAC address 1 high register (ENET_MAC_ADDR1H) 22.4.16. Address offset: 0x0048 Reset value: 0x0000 FFFF MB[5:0] Reserved ADDR1H[15:0] Bits Fields Descriptions...
Page 724 GD32F10x User Manual MAC address 1 low register (ENET_MAC_ADDR1L) 22.4.17. Address offset: 0x004C Reset value: 0xFFFF FFFF ADDR1L[31:16] ADDR1L[15:0] Bits Fields Descriptions 31:0 ADDR1L[31:0] MAC address1 low 32-bit This field contains the low 32-bit of the 6-byte MAC address1 MAC address 2 high register (ENET_MAC_ADDR2H) 22.4.18.
Page 725 GD32F10x User Manual MB[5]: ENET_MAC_ADDR2H [15:8] MB[4]: ENET_MAC_ADDR2H [7:0] MB[3]: ENET_MAC_ADDR2L [31:24] MB[2]: ENET_MAC_ADDR2L[23:16] MB[1]: ENET_MAC_ADDR2L[15:8] MB[0]: ENET_MAC_ADDR2L [7:0] 23:16 Reserved Must be kept at reset value. 15:0 ADDR2H[15:0] MAC address2 high 16-bit This field contains the high 16-bit (bit 47 to 32) of the 6-byte MAC address2 MAC address 2 low register (ENET_MAC_ADDR2L) 22.4.19.
Page 726 GD32F10x User Manual 1:The address filter use the MAC address3 for perfect filtering Source address filter bit 0:The MAC address3[47:0] is used to comparing with the DA fields of the received frame 1:The MAC address3[47:0] is used to comparing with the SA fields of the received frame 29:24 MB[5:0]...
Page 727 GD32F10x User Manual Reserved Reserved MCFZ RTOR CTSR Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. MCFZ MSC counter freeze bit 0: MSC counters are not frozen 1: Freezes all the MSC counters to their current value. RTOR bit can work on this frozen state.
Page 728 GD32F10x User Manual RGUF Received good unicast frames bit 0: Good unicast frame received counter is less than half of the maximum value 1: Good unicast frame received counter reaches half of the maximum value 16:7 Reserved Must be kept at reset value. RFAE Received frames alignment error bit 0: Alignment error frame received counter is less than half of the maximum value...
Page 729 GD32F10x User Manual maximum value 13:0 Reserved Must be kept at reset value. MSC receive interrupt mask register (ENET_MSC_RINTMSK) 22.4.25. Address offset: 0x010C Reset value: 0x0000 0000 The Ethernet MSC receive interrupt mask register maintains the masks for interrupts generated when receive statistic counters reach half their maximum value Reserved RGUFIM Reserved Reserved...
Page 730 GD32F10x User Manual TGFMSCI TGFSCIM Reserved Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. TGFIM Transmitted good frames interrupt mask bit 0: Unmask the interrupt when the TGF bit is set 1:Mask the interrupt when the TGF bit is set 20:16 Reserved Must be kept at reset value.
Page 731 GD32F10x User Manual collision MSC transmitted good frames after more than a single 22.4.28. collision counter register (ENET_MSC_MSCCNT) Address offset: 0x0150 Reset value: 0x0000 0000 This register counts the number of successfully transmitted frames after more than one single collision in Half-duplex mode. MSCC[31:16] MSCC[15:0] Bits...
Page 732 GD32F10x User Manual MSC received frames with CRC error counter register 22.4.30. (ENET_MSC_RFCECNT) Address offset: 0x0194 Reset value: 0x0000 0000 This register counts the number of frames received with CRC error. RFCER[31:16] RFCER[15:0] Bits Fields Descriptions 31:0 RFCER[31:0] Received frames with CRC error counter bits These bits count the number of receive frames with CRC error MSC received frames with alignment error counter register 22.4.31.
Page 733 GD32F10x User Manual MSC received good unicast frames counter register 22.4.32. (ENET_MSC_RGUFCNT) Address offset: 0x01C4 Reset value: 0x0000 0000 This register counts the number of good unicast frames received. RGUF[31:16] RGUF[15:0] Bits Fields Descriptions 31:0 RGUF[31:0] Received good unicast frames counter bits These bits count the number of good unicast frames received.
Page 734 GD32F10x User Manual TMSITEN Timestamp interrupt trigger enable bit 0: Disable timestamp interrupt 1: A timestamp interrupt is generated when the system time becomes greater than the value written in target time register. Note: When the timestamp trigger interrupt generated, this bit is cleared TMSSTU Timestamp system time update bit Both the TMSSTU and TMSSTI bits must be read as zero before application set...
Page 735 GD32F10x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. STMSSI[7:0] System time subsecond increment bits In every update operation, these bits are added to the subsecond value of system time. PTP time stamp high register (ENET_PTP_TSH) 22.4.35.
Page 736 GD32F10x User Manual PTP time stamp update high register (ENET_PTP_TSUH) 22.4.37. Address offset: 0x0710 Reset value: 0x0000 0000 This register configures the high 32-bit of the time to be written to, added to, or subtracted from the system time value. The timestamp update registers (high and low) initialize or update the system time maintained by the MAC core.
Page 737 GD32F10x User Manual PTP time stamp addend register (ENET_PTP_TSADDEND) 22.4.39. Address offset: 0x0718 Reset value: 0x0000 0000 This register value is used only in fine update mode for adjusting the clock frequency. This register value is added to a 32-bit accumulator in every clock cycle and the system time updates when the accumulator reaches overflow.
Page 738 GD32F10x User Manual ETSL[31:16] ETSL[15:0] Bits Fields Descriptions 31:0 ETSL[31:0] Expected time low bits These bits store the expected target nanosecond time (signed). DMA bus control register (ENET_DMA_BCTL) 22.4.42. Address offset: 0x1000 Reset value: 0x0000 2101 Reserved FPBL RXDP[5:0] RTPR[1:0] PGBL[5:0] Reserved DPSL[4:0]...
Page 739 GD32F10x User Manual 22:17 RXDP[5:0] RxDMA PGBL bits If UIP=0, these bits are not valid. Only when UIP=1, these bits is configured for the maximum number of beats to be transferred in one RxDMA transaction. 0x01: max beat number is 1 0x02: max beat number is 2 0x04: max beat number is 4 0x08: max beat number is 8...
Page 740 GD32F10x User Manual DMA arbitration bit This bit indicates the arbitration mode between RxDMA and TxDMA. 0: Round-robin mode and DMA access priority is given in RTPR 1: Fixed mode. RxDMA has higher priority than TxDMA Software reset bit This bit can reset all core internal registers located in CLK_TX and CLK_RX. It is cleared by hardware when the reset operation is complete in all clock domains.
Page 741 GD32F10x User Manual This register is used by the application to make the RxDMA controller poll the receive descriptor table. Writing to this register makes the RxDMA controller exit suspend state. RPE[31:16] rw_wt RPE[15:0] rw_wt Bits Fields Descriptions 31:0 RPE[31:0] Receive poll enable bits Writing to this register with any value makes DMA read the current descriptor address which is indicated in ENET_DMA_CRDADDR register.
Page 742 GD32F10x User Manual transmit descriptor table address register 22.4.46. (ENET_DMA_TDTADDR) Address offset: 0x1010 Reset value: 0x0000 0000 This register points to the start of the transmit descriptor table. The descriptor table is located in the physical memory space and must be word-aligned. This register can only be written when TxDMA controller is in stop state.
Page 743 GD32F10x User Manual This bit indicates a timestamp event occurred. It is cleared by application through clearing TMST bit. If the corresponding interrupt mask bit is reset, an interrupt is generated. 0: Timestamp event has not occurred 1: Timestamp event has occurred WUM status bit This bit indicates a WUM event occurred.
Page 744 GD32F10x User Manual 0x1: Running: Fetching receive transfer descriptor 0x2: Reserved 0x3: Running: Waiting for receive packet 0x4: Suspended: Receive descriptor unavailable 0x5: Running: Closing receive descriptor 0x6: Reserved 0x7: Running: Transferring the receive packet data from receive buffer to host memory Normal interrupt summary The NI bit is logical ORed of the following if the corresponding interrupt bit is...
Page 745 GD32F10x User Manual 12:11 Reserved Must be kept at reset value. Early transmit status bit 0: The frame to be transmitted has not fully transferred into the TxFIFO 1: The frame to be transmitted has fully transferred into the TxFIFO Receive watchdog timeout status bit 0: No received a frame with a length greater than 2048 bytes 1: A frame with a length greater than 2048 bytes is received...
Page 746 GD32F10x User Manual This bit can only be set when both LSG and INTC are set in TDES0. 0: Current frame transmission is not finished 1: Current frame transmission is finished. DMA control register (ENET_DMA_CTL) 22.4.48. Address offset: 0x1018 Reset value: 0x0000 0000 This register configures both the transmitting and receiving operation modes and commands.
Page 747 GD32F10x User Manual don’t care in this mode. Note: This bit can be changed when transmission is in stop state Flush transmit FIFO bit This bit can be set by application to reset TxFIFO inner control register and logic. If set, all data in TxFIFO are flushed. It is cleared by hardware after the flushing operation is finish.
Page 748 GD32F10x User Manual 1: All frame received with error except runt error are forwarded to memory Forward undersized good frames bit 0: The RxFIFO drops all frames whose length is less than 64 bytes. However, if this frame has already started forwarding (may due to lower value of receive threshold in Cut-Through mode), the whole frame will be forwarded.
Page 749 GD32F10x User Manual DMA interrupt enable register (ENET_DMA_INTEN) 22.4.49. Address offset: 0x101C Reset value: 0x0000 0000 This register configures the interrupts which are reflected in ENET_DMA_STAT register. Reserved ERIE FBEIE Reserved ETIE RWTIE RPSIE RBUIE TUIE ROIE TJTIE TBUIE TPSIE Bits Fields Descriptions...
Page 750 GD32F10x User Manual 0: The fatal bus error enable interrupt is disabled 1: The fatal bus error enable interrupt is enabled 12:11 Reserved Must be kept at reset value. ETIE Early transmit interrupt enable bit 0: The early transmit interrupt is disabled 1: The early transmit interrupt is enabled RWTIE Receive watchdog timeout interrupt enable bit...
Page 751 GD32F10x User Manual DMA missed frame and buffer overflow counter register 22.4.50. (ENET_DMA_MFBOCNT) Address offset: 0x1020 Reset value: 0x0000 0000 There are two counters designed in DMA controller for tracking the number of missed frames during receiving. The counter value can be read from this register for debug purpose. OBFOC OBMFC Reserved...
Page 752 GD32F10x User Manual TDAP[31:16] TDAP[15:0] Bits Fields Descriptions 31:0 TDAP[31:0] Transmit descriptor address pointer bits These bits are automatically updated by TxDMA controller during operation. current receive descriptor address register 22.4.52. (ENET_DMA_CRDADDR) Address offset: 0x104C Reset value: 0x0000 0000 This register points to the start descriptor address of the current receive descriptor read by the RxDMA controller.
Page 753 GD32F10x User Manual TBAP[15:0] Bits Fields Descriptions 31:0 TBAP[31:0] Transmit buffer address pointer bits These bits are automatically updated by TxDMA controller during operation. current receive buffer address register 22.4.54. (ENET_DMA_CRBADDR) Address offset: 0x1054 Reset value: 0x0000 0000 This register points to the current receive buffer address being read by the RxDMA controller. RBAP[31:16] RBAP[15:0] Bits...
Page 754: Figure 23-1. Usbd Block Diagram
GD32F10x User Manual Universal Serial Bus full-speed device interface (USBD) The USBD is only available on GD32F103xx series. Overview 23.1. The Universal Serial Bus full-speed device interface (USBD) module provides a device solution for implementing a USB 2.0 full-speed compliant peripheral. It contains a full-speed internal USB PHY and no more external PHY chip is needed.
Page 755: Table 23-1. Usbd Signal Description
GD32F10x User Manual Signal description 23.4. Table 23-1. USBD signal description I/O port Type Description VBUS Input Bus power port Input/Output Differential D- Input/Output Differential D+ Note: As soon as the USBD is enabled, these pins are connected to the USBD internal transceiver automatically.
Page 756 GD32F10x User Manual Function overview 23.6. USB endpoints 23.6.1. USBD supports 8 USB endpoints that can be individually configured. Each endpoint supports:  Single/Double buffer (endpoint 0 can’t use double buffer).  One endpoint buffer descriptor.  Programmable buffer starting address and buffer length. ...
Page 757: Figure 23-2. An Example With Buffer Descriptor Table Usage (Usbd_Baddr = 0)
GD32F10x User Manual Figure 23-2. An example with buffer descriptor table usage (USBD_BADDR = 0) offset 0x1FF IN endpoint 1 double buffer 0 IN endpoint 1 double buffer 1 Endpoint 0 reception buffer Endpoint 0 transmission buffer COUNT1_TX1 ADDR1_TX1 COUNT1_TX0 Endpoint 1 buffer descriptor (double buffer) ADDR1_TX0 COUNT0_RX...
Page 758: Table 23-2. Double-Buffering Buffer Flag Definition
GD32F10x User Manual Table 23-2. Double-buffering buffer flag definition Buffer flag Tx endpoint Rx endpoint TX_DTG (USBD_EPxCS bit 6) RX_DTG (USBD_EPxCS bit 14) SW_BUF RX_DTG (USBD_EPxCS bit 14) TX_DTG (USBD_EPxCS bit 6) The DTG bit and the SW_BUF bit are responsible for the flow control. When a transfer completes, the USB peripheral toggle the DTG bit;...
Page 759 GD32F10x User Manual or expected according to the direction of the transfer. After the transaction process is completed, an endpoint-specific interrupt is generated. In the interrupt routine, the application can process it accordingly. Transaction formatting is performed by the hardware, including CRC generation and checking. Once the endpoint is enabled, endpoint control and status register, buffer address and COUNT filed should not be modified by the application software.
Page 760 GD32F10x User Manual the data buffer, which is controlled by the internal register configured. The received 2-byte CRC is also copied to the packet memory buffer, immediately following data bytes. If the length of data is greater than actually allocated length, the excess data are not copied. This is a buffer overrun situation.
Page 761 GD32F10x User Manual illegal. The application software can implement double-buffering to improve performance. By swapping transmission and reception data packet buffer on each transaction, the application software can copy the data into or out of a buffer, at the same time the USB peripheral handle the data transmission or reception of data in another buffer.
Page 762 GD32F10x User Manual The USB protocol insists on power management by the USB device. This becomes even more important if the device draws power from the bus (bus-powered device). The following constraints should be met by the bus-powered device.  A device in the non-configured state should draw a maximum of 100mA from the USB bus.
Page 763 GD32F10x User Manual 5. Wait for the reset interrupt (RSTIF). 6. In the reset interrupt, initialize default control endpoint 0 to start enumeration process and program USBD_BADDR to set the device address to 0 and enable USB module function. 7. Configure endpoint 0 and prepare to receive SETUP packet. Endpoint initialization sequence 1.
Page 764 GD32F10x User Manual bit in USBD_EPxCS register. Then application will read the data payload from the endpoint data buffer with the start address defined in USBD_EPxRBAR register. Last application will interpret the data and process the corresponding transaction. IN data transfers 1.
Page 765 GD32F10x User Manual Register definition 23.7. USBD base address: 0x4000 5C00 USBD control register (USBD_CTL) 23.7.1. Address offset: 0x40 Reset value: 0x0003 This register can be accessed by half-word (16-bit) or word (32-bit) STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE ESOFIE Reserved RSREQ...
Page 766 GD32F10x User Manual 1: Interrupt generated when ESOFIF bit in USBD_INTF register is set. Reserved Must be kept at reset value RSREQ Resume request The software set a resume request to the USB host, and the USB host should drive the resume sequence according the USB specifications 0: No resume request 1: Send resume request.
Page 767 GD32F10x User Manual This bit set by hardware when a successful transaction completes PMOUIF Packet memory overrun/underrun interrupt flag This bit set by hardware to indicate that the packet memory is inadequate to hold transfer data. The software writes 0 to clear this bit. ERRIF Error interrupt flag This bit set by hardware when an error happens during transaction.
Page 768 GD32F10x User Manual Bits Fields Descriptions RX_DP Receive data + line status Represent the status on the DP line RX_DM Receive data - line status Represent the status on the DM line LOCK Locked the USB Set by the hardware indicate that at the least two consecutive SOF have been received 12:11 SOFLN[1:0]...
Page 769 GD32F10x User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) BAR[12:0] Reserved Bits Fields Descriptions 15:3 BAR[12:0] Buffer address Start address of the allocation buffer(512byte on-chip SRAM), used for buffer descriptor table, packet memory Reserved Must be kept at reset value USBD endpoint x control and status register (USBD_EPxCS), x=[0..7]...
Page 770: Table 23-4. Reception Status Encoding
GD32F10x User Manual EP_KCTL Endpoint kind control The exact meaning depends on the endpoint type Refer to the table below TX_ST Transmission successful transfer Set by hardware when a successful IN transaction complete Clear by software TX_DTG Transmission data PID toggle This bit represent the toggle data bit (0=DATA0,1=DATA1) for non-isochronous endpoint Used to implement the flow control for double-buffered endpoint...
Page 771 GD32F10x User Manual USBD endpoint transmission buffer address register 23.7.7. (USBD_EPxTBADDR), x can be in [0..7] Address offset: [USBD_BADDR] + x * 16 USB local address: [USBD_BADDR] + x * 8 This register can be accessed by half-word (16-bit) or word (32-bit) EPTXBA EPTXBAR[15:1] R[0]...
Page 772 GD32F10x User Manual This register can be accessed by half-word (16-bit) or word (32-bit) EPRBAR[ EPRBAR[15:1] Bits Fields Descriptions 15:1 EPRBAR[15:1] Endpoint reception buffer address Start address of packet buffer containing the data received by the endpoint at the next OUT/SETUP token EPRBAR[0] Must be set to 0 USBD...
Page 773 GD32F10x User Manual Universal serial bus full-speed interface (USBFS) The USBFS is available on GD32F105 and GD32F107 series. 24.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol).
Page 774: Figure 24-1. Usbfs Block Diagram
GD32F10x User Manual 24.3. Block diagram Figure 24-1. USBFS block diagram interrupts AHB Slave Device bus Host Port control Control Data FIFO Transcation Scheduler Control VBUS USB Clock 48MHz 24.4. Signal description Table 24-1. USBFS signal description I/O port Type Description VBUS Input...
Page 775: Figure 24-2. Connection With Host Or Device Mode
GD32F10x User Manual Connection with host or device mode. Figure 24-2. Connection with host or device mode USBFS 5V Power Supply GPIO (needed in host mode) VBUS VBUS When USBFS works in host mode (FHM bit is set and FDM bit is cleared), the VBUS is 5V power, and detecting pin which is using for voltage detection is defined in USB protocol.
Page 776: Figure 24-3. Connection With Otg Mode
GD32F10x User Manual Figure 24-3. Connection with OTG mode USBFS 5V Power GPIO Supply VBus VBUS USB host function 24.5.2. USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state.
Page 777 GD32F10x User Manual Connection, Reset and Speed identification As a USB host, USBFS will trigger a connection flag for application after a connection is detected and will trigger a disconnection flag after a disconnection event. PRST bit is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset.
Page 778 GD32F10x User Manual USBFS supports all the four kinds of transfer types: control, bulk, interrupts and isochronous. USB 2.0 protocol divides these transfers into 2 kinds: non-periodic transfer (control and bulk) and periodic transfer (interrupt and isochronous). Based on this, USBFS includes two request queues: periodic request queue and non-periodic request queue, to perform efficient transaction schedule.
Page 779 GD32F10x User Manual is always 11(full-speed). As describing in by USB 2.0 protocol, USBFS doesn’t support low-speed in device mode. Suspend and Wake-up A USB device will enter into suspend state if the USB bus stays at IDLE state and there is no change on data lines for 3ms.
Page 780 GD32F10x User Manual The Host Negotiation Protocol (HNP) allows the host function to be switched between two directly connected On-The-Go devices and eliminates the necessity of switching the cable connections for the change about control of communications between the devices. HNP will be initialized typically by the user or an application on the On-The-Go B-Device.
Page 781: Figure 24-5. Host Mode Fifo Space In Sram
GD32F10x User Manual transmission packet. All IN channels shares the Rx FIFO for packets reception. All the periodic OUT channels share the periodic Tx FIFO to packets tramsmission. All the non- periodic OUT channels share the non-Periodic FIFO for transmit packets. The size and start offset of these data FIFOs should be configured using these registers: USBFS_GRFLEN, USBFS_HNPTFLEN and USBFS_HPTFLEN.
Page 782: Figure 24-7. Device Mode Fifo Space In Sram
GD32F10x User Manual of 32-bit words. Figure 24-7. Device mode FIFO space in SRAM Start: 0x00 Rx FIFO RXFD IEPTX0RSAR[15:0] Tx FIFO0 IEPTX0FD IEPTX1RSAR[15:0] IEPTX1FD Tx FIFO1 IEPTX3RSAR[15:0] IEPTX3FD Tx FIFO3 End: 0x13F USBFS provides a special register area for the internal data FIFO reading and writing. Figure 24-8.
Page 783 GD32F10x User Manual Operation guide 24.5.6. This section describes the advised operation guide for USBFS. Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the TxFIFO’s empty threshold, etc. GINTEN bit should be kept cleared at this time. 2.
Page 784 GD32F10x User Manual supported by Rx FIFO. 4. Set CEN bit in USBFS_HCHxCTL register to enable the channel. Channel disable sequence Software can disable the channel by setting both CEN and CDIS bits at the same time. USBFS will generate a channel disable request entry in request queue after the register setting operation.
Page 785 GD32F10x User Manual 2. Initialize and enable the channel. 3. Write a packet into the channel’s Tx FIFO (Periodic Tx FIFO or non-periodic Tx FIFO). After the whole packet data is written into the FIFO, USBFS generates a Tx request entry in the corresponding request queue and decreases the TLEN field in USBFS_HCHxLEN register by the written packet’s size.
Page 786 GD32F10x User Manual 8. Wait for ENUMF interrupt in USBFS_GINTF register. Endpoint initialization and enable sequence 1. Program USBFS_DIEPxCTL or USBFS_DOEPxCTL register with desired transfer type, packet size, etc. 2. Program USBFS_DIEPINTEN or USBFS_DOEPINTEN register. Set the desired interrupt enable bits. 3.
Page 787: Table 24-2. Usbfs Global Interrupt
GD32F10x User Manual OUT transfers operation sequence 1. Initialize USBFS global registers. 2. Initialize the endpoint and enable the endpoint. 3. When an OUT token is received, USBFS receives the data packet or response with an NAK handshake based on the status of Rx FIFO and register configuration. If the transaction is finished successfully (USBFS receives and saves the data packet into Rx FIFO successfully...
Page 788 GD32F10x User Manual Interrupt Flag Description Operation Mode USB reset Device mode USB suspend Device mode Early suspend Device mode GONAK Global OUT NAK effective Device mode GNPINAK Global IN Non-Periodic NAK effective Device mode NPTXFEIF Non-Periodic Tx FIFO empty interrupt Host Mode flag RXFNEIF...
Page 789 GD32F10x User Manual 24.7. Register definition USBFS base address: 0x5000 0000 Global control and status registers 24.7.1. Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 790 GD32F10x User Manual 1: Indicates the short debounce interval, when a soft connection is used in HNP protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes.
Page 791 GD32F10x User Manual 0: No session request 1: Session request Note: Only accessible in device mode. SRPS SRP success This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP fails 1: SRP succeeds Note: Only accessible in device mode.
Page 792 GD32F10x User Manual 16:10 Reserved Must be kept at reset value. HNPEND HNP end Set by the core when a HNP ends. Read the HNPS in USBFS_GOTGCS register to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends.
Page 793 GD32F10x User Manual Device mode: 0: TXFEIF will be triggered when the IN endpoint transmit FIFO is half empty 1: TXFEIF will be triggered when the IN endpoint transmit FIFO is completely empty Host mode: 0: NPTXFEIF will be triggered when the non-periodic transmit FIFO is half empty 1: NPTXFEIF will be triggered when the non-periodic transmit FIFO is completely empty 6：1...
Page 794 GD32F10x User Manual Force host mode Setting this bit will force the core to host mode irrespective of the USBFS ID input pin. 0: Normal mode 1: Host mode The application must wait at least 25 ms for the change taking effect after setting the force bit.
Page 795 GD32F10x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non-periodic Tx FIFO is flushed 00001: Only periodic Tx FIFO is flushed 1XXXX: Both periodic and non-periodic Tx FIFOs are flushed Other: Non data FIFO is flushed...
Page 796 GD32F10x User Manual Note: Only accessible in host mode. HCSRST HCLK soft reset Set by the application to reset AHB clock domain circuit. Hardware automatically clears this bit after the reset process completes. After setting this bit, application should wait until this bit is cleared before any other operation on USBFS.
Page 797 GD32F10x User Manual IDPSC ID pin status change Set by the core when ID status changes. Note: Accessible in both device and host modes. Reserved Must be kept at reset value. PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the periodic transmit FIFO is either half or completely empty.
Page 798 GD32F10x User Manual number, and then read the corresponding USBFS_DOEPxINTF register to get the flags of the endpoint that cause the interrupt. This bit will be automatically cleared after the respective endpoint’s flags which cause this interrupt are cleared. Note: Only accessible in device mode. IEPIF IN endpoint interrupt flag Set by USBFS when one of the IN endpoints in device mode has raised an interrupt.
Page 799 GD32F10x User Manual Note: Only accessible in device mode. GNPINAK Global Non-Periodic IN NAK effective Write 1 to SGINAK bit in the USBFS_DCTL register and USBFS will set GNPINAK flag after the writing to SGINAK takes effect. Note: Only accessible in device mode. NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the non-periodic transmit FIFO is either half or...
Page 800 GD32F10x User Manual This register works with the global interrupt flag register (USBFS_GINTF) to interrupt the application. When an interrupt enable bit is disabled, the interrupt associated with that bit is not generated. However, the global Interrupt flag register bit corresponding to that interrupt is still set.
Page 801 GD32F10x User Manual HCIE Host channels interrupt enable 0: Disable host channels interrupt 1: Enable host channels interrupt Note: Only accessible in host mode. HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value.
Page 802 GD32F10x User Manual Note: Only accessible in device mode. ENUMFIE Enumeration finish enable 0: Disable enumeration finish interrupt 1: Enable enumeration finish interrupt Note: Only accessible in device mode. RSTIE USB reset interrupt enable 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode.
Page 803 GD32F10x User Manual Note: Accessible in both device and host modes. OTGIE OTG interrupt enable 0: Disable OTG interrupt 1: Enable OTG interrupt Note: Accessible in both device and host modes. MFIE Mode fault interrupt enable 0: Disable mode fault interrupt 1: Enable mode fault interrupt Note: Accessible in both device and host modes.
Page 804 GD32F10x User Manual 20:17 RPCKST[3:0] Received packet status 0010: IN data packet received 0011: IN transfer completed (generates an interrupt if poped) 0101: Data toggle error (generates an interrupt if poped) 0111: Channel halted (generates an interrupt if poped) Others: Reserved 16:15 DPID[1:0] Data PID...
Page 805 GD32F10x User Manual 00: DATA0 10: DATA1 Others: Reserved 14:4 BCOUNT[10:0] Byte count The byte count of the received data packet. EPNUM[3:0] Endpoint number The endpoint number to which the current received packet belongs. Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit)
Page 806 GD32F10x User Manual r/rw r/rw Host Mode: Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit words. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx RAM start address The start address for non-periodic transmit FIFO RAM is in term of 32-bit words. Device Mode: Bits Fields...
Page 807 GD32F10x User Manual Bits Fields Descriptions Reserved Must be kept at reset value. 30:24 NPTXRQTOP[6:0] Top entry of the non-periodic Tx request queue Entry in the non-periodic transmit request queue. Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token –...
Page 808 GD32F10x User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. SOFOEN SOF output enable 0: SOF pulse output disabled. 1: SOF pulse output enabled. VBUSBCEN The V B-device Comparer enable 0: V B-device comparer disabled 1: V B-device comparer enabled VBUSACEN The VBUS A-device Comparer enable...
Page 809 GD32F10x User Manual Bits Fields Descriptions 31:0 CID[31:0] Core ID Software can write or read this field and uses this field as a unique ID for its application Host periodic transmit FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word 32-bit) r/rw r/rw...
Page 810 GD32F10x User Manual Device IN endpoint transmit FIFO length register (USBFS_DIEPxTFLEN) (x = 1..3, where x is the FIFO_number) Address offset: 0x0104 + (FIFO_number – 1) × 0x04 Reset value: 0x0200 0400 This register has to be accessed by word (32-bit) r/rw r/rw Bits...
Page 811 GD32F10x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CLKSEL[1:0] Clock select for usbclock. 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the frame interval for the current enumerating speed when USBFS controller is enumerating.
Page 812 GD32F10x User Manual Low-Speed: 6MHz Host frame information remaining register (USBFS_HFINFR) Address offset: 0x408 Reset value: 0xBB80 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks. 15:0 FRNUM[15:0] Frame number...
Page 813 GD32F10x User Manual Bits Fields Descriptions 31:24 PTXREQT[7:0] Top entry of the periodic Tx request queue Entry in the periodic transmit request queue. Bits 30:27: Channel Number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel.
Page 814 GD32F10x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN) Address offset: 0x0418 Reset value: 0x0000 0000 This register can be used by software to enable or disable a channel’s interrupt.
Page 815 GD32F10x User Manual 1: Enable channel-n interrupt Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host port control and status register (USBFS_HPCS) Address offset: 0x0440 Reset value: 0x0000 0000 This register controls the port’s behavior and also has some flags which report the status of the port.
Page 816 GD32F10x User Manual Bit 10: State of DP line Bit 11: State of DM line Reserved Must be kept at reset value. PRST Port reset Application sets this bit to start a reset signal on USB port. Application should clear this bit when it wants to stop the reset signal.
Page 817 GD32F10x User Manual 1: Device is connected to the port Host channel-x control register (USBFS_HCHxCTL) (x = 0..7 where x = channel_number) Address offset: 0x0500 + (channel_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) EPTYPE[1:0] Bits Fields...
Page 818 GD32F10x User Manual The transfer type of the endpoint that this channel wants to communicate with. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Low-Speed device The device that this channel wants to communicate with is a Low-Speed Device. Reserved Must be kept at reset value.
Page 819 GD32F10x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. DTER Data toggle error The IN transaction gets a data packet but the PID of this packet doesn’t match DPID [1:0] bits in USBFS_HCHxLEN register. REQOVR Request queue overrun The periodic request queue is full when software starts new transfers.
Page 820 GD32F10x User Manual Host channel-x interrupt enable register (USBFS_HCHxINTEN) (x = 0..7, where x = channel number) Address offset: 0x050C + (channel_number × 0x20) Reset value: 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_HCHxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_HCHxINTF register is able to trigger a channel interrupt.
Page 821 GD32F10x User Manual 0: Disable ACK interrupt 1: Enable ACK interrupt NAKIE NAK interrupt enable 0: Disable NAK interrupt 1: Enable NAK interrupt STALLIE STALL interrupt enable 0: Disable STALL interrupt 1: Enable STALL interrupt Reserved Must be kept at reset value. CHIE Channel halted interrupt enable 0: Disable channel halted interrupt...
Page 822 GD32F10x User Manual field controls the Data PID of the first transmitted packet. For IN transfers, this field controls the expected Data PID of the first received packet, and DTERR will be triggered if the Data PID doesn’t match. After the transfer starts, USBFS changes and toggles this field automatically following the USB protocol.
Page 823 GD32F10x User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:11 EOPFT[1:0] End of periodic frame time This field defines the percentage time point in a frame that the end of periodic frame (EOPF) flag should be triggered. 00: 80% of the frame time 01: 85% of the frame time 10: 90% of the frame time...
Page 824 GD32F10x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. POIF Power-on initialization finished Software should set this bit to notify USBFS that the registers are initialized after waking up from power down state. CGONAK Clear global OUT NAK Software sets this bit to clear GONS bit in this register.
Page 825 GD32F10x User Manual STALL bits. 1: USBFS always responses to IN transaction with a NAK handshake. Soft disconnect Software can use this bit to generate a soft disconnect condition on USB bus. After this bit is set, USBFS switches off the pull up resistor on DP line. This will cause the host to detect a device disconnect.
Page 826 GD32F10x User Manual flag in USBFS_GINTF register is triggered. 11: Full speed Others: reserved SPST Suspend status This bit reports whether device is in suspend state. 0: Device is in suspend state. 1: Device is not in suspend state. Device IN endpoint common interrupt enable register (USBFS_DIEPINTEN) Address offset: 0x810 Reset value: 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_DIEPxINTF register.
Page 827 GD32F10x User Manual 0: Disable control IN timeout interrupt 1: Enable control In timeout interrupt Reserved Must be kept at reset value. EPDISEN Endpoint disabled interrupt enable bit 0: Disable endpoint disabled interrupt 1: Enable endpoint disabled interrupt TFEN Transfer finished interrupt enable bit 0: Disable transfer finished interrupt 1: Enable transfer finished interrupt Device OUT endpoint common interrupt enable register (USBFS_DOEPINTEN)
Page 828 GD32F10x User Manual 0: Disable endpoint Rx FIFO overrun interrupt 1: Enable endpoint Rx FIFO overrun interrupt STPFEN SETUP phase finished (Only for control OUT endpoint) interrupt enable bit 0: Disable SETUP phase finished interrupt 1: Enable SETUP phase finished interrupt Reserved Must be kept at reset value.
Page 829 GD32F10x User Manual IEPITB[3:0] Device all IN endpoint interrupt bits Each bit represents an IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3. Device all endpoints interrupt enable register (USBFS_DAEPINTEN) Address offset: 0x081C Reset value: 0x0000 0000 This register can be used by software to enable or disable an endpoint’s interrupt.
Page 830 GD32F10x User Manual Device VBUS discharge time register (USBFS_DVBUSDT) Address offset: 0x0828 Reset value: 0x0000 17D7 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 DVBUSDT[15:0] Device V discharge time There is a discharge process after V pulsing in SRP protocol.
Page 831 GD32F10x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DVBUSPT[11:0] Device V pulsing time This field defines the pulsing time for V The true pulsing time is BUS. 1024*DVBUSPT[11:0] *T , where T is the period time of USB clock. USBCLOCK USBCLOCK Device...
Page 832 GD32F10x User Manual Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should following the operation guide to disable or enable an endpoint.
Page 833 GD32F10x User Manual This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are cleared: 0: USBFS sends data or handshake packets according to the status of the endpoint’s Tx FIFO. 1: USBFS always sends NAK handshake to the IN token.
Page 834 GD32F10x User Manual Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should following the operation guide to disable or enable an endpoint.
Page 835 GD32F10x User Manual 10: Bulk 11: Interrupt NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GINS bit in USBFS_DCTL register are are cleared: 0: USBFS sends data or handshake packets according to the status of the endpoint’s Tx FIFO.
Page 836 GD32F10x User Manual Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable This bit is fixed to 0 for OUT endpoint 0. 29:28 Reserved Must be kept at reset value.
Page 837 GD32F10x User Manual 1: USBFS always sends NAK handshake for the OUT token. This bit is read-only and software should use CNAK and SNAK in this register to control this bit. Reserved Must be kept at reset value. EPACT Endpoint active This field is fixed to ‘1’...
Page 838 GD32F10x User Manual 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should follow the operation guide to disable or enable an endpoint. SODDFRM Set odd frame (For isochronous OUT endpoints) This bit has effect only if this is an isochronous OUT endpoint.
Page 839 GD32F10x User Manual 01: Isochronous 10: Bulk 11: Interrupt NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register and GONS bit in USBFS_DCTL register are cleared: 0: USBFS sends handshake packets according to the status of the endpoint’s Rx FIFO.
Page 840 GD32F10x User Manual rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TXFE Transmit FIFO empty The Tx FIFO of this IN endpoint has reached the empty threshold value defined by TXFTH field in USBFS_GAHBCS register. IEPNE IN endpoint NAK effective The setting of SNAK bit in USBFS_DIEPxCTL register takes effect.
Page 841 GD32F10x User Manual This register contains the status and events of an OUT endpoint, when an OUT endpoint interrupt occurs, read this register for the respective endpoint to know the source of the interrupt. The flag bits in this register are all set by hardware and cleared by writing 1. This register has to be accessed by word (32-bit) rc_w1/rw rc_w1...
Page 842 GD32F10x User Manual Device IN endpoint 0 transfer length register (USBFS_DIEP0LEN) Address offset: 0x0910 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. 20:19 PCNT[1:0] Packet count The number of data packets desired to be transmitted in a transfer.
Page 843 GD32F10x User Manual Bits Fields Descriptions Reserved Must be kept at reset value. 30:29 STPCNT[1:0] SETUP packet count This field defines the maximum number of back-to-back SETUP packets this endpoint can accept. Program this field before setup transfers. Each time a back-to-back setup packet is received, USBFS decrease this field by one.
Page 844 GD32F10x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions Reserved Must be kept at reset value. 30:29 MCPF[1:0] Multi packet count per frame This field indicates the packet count that must be transmitted per frame for periodic IN endpoints on the USB.
Page 845 GD32F10x User Manual This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions Reserved Must be kept at reset value. 30:29 RXDPID[1:0] Received data PID (For isochronous OUT endpoints) This field saves the PID of the latest received data packet on this endpoint. 00: DATA0 10: DATA1 Others: Reserved...
Page 846 GD32F10x User Manual packet. Device IN endpoint-x transmit FIFO status register (USBFS_DIEPxTFSTAT) (x = 0..3, where x = endpoint_number) Address offset: 0x0918 + (endpoint_number × 0x20) Reset value: 0x0000 0200 This register contains the information of each endpoint’s Tx FIFO. This register has to be accessed by word (32-bit) Bits Fields...
Page 847 GD32F10x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SHCLK Stop HCLK Stop the HCLK to save power. 0: HCLK is not stopped 1: HCLK is stopped SUCLK Stop the USB clock Stop the USB clock to save power. 0: USB clock is not stopped 1: USB clock is stopped...
Page 848: Table 25-1. List Of Abbreviations Used In Register
GD32F10x User Manual Appendix 25.1. List of abbreviations used in register Table 25-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit.
Page 849 GD32F10x User Manual 25.3. Available peripherals For availability of peripherals and their number across all MCU series types, refer to the corresponding device data datasheet.
Page 850: Table 26-1. Revision History
GD32F10x User Manual Revision history Table 26-1. Revision history Revision No. Description Date Initial Release Dec.26, 2014 Adapt To New Name Convention Jun.20, 2017 Remove ADC2 content in connectivity type of chip. Aug.7, 2018 Modify AFIO_PCF0 register in GPIO chapter, refer to AFIO port configuration register 0 (AFIO_PCF0).
Page 851 GD32F10x User Manual VDD / VDDA power domain. Change 16HCLK to 12HCLK in chapter USB host function. Add descriptions of “Just for CAN0” in chapter Register definition. Add I/O state descriptions in standby mode in chapter Power saving modes. Modify bit descriptions of SMBALT in I2C_STAT0 register, refer to Inter-integrated circuit interface (I2C).
Page 852 GD32F10x User Manual digital converter (ADC) . Consistency update of General-purpose and alternate- function I/Os (GPIO and AFIO) chapter. Consistency update of Reset and clock unit (RCU) chapter. 10. Update table Table 20-3. EXMC bank 0 supports all transactions, Figure 20-21.
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