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GigaDevice Semiconductor GD32L23 Series User Manual

Arm cortex-m23 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32L23x

®

Arm

Cortex

-M23 32-bit MCU

®

For GD32L233xx, GD32L235x

User Manual

Revision 2.2

( Mar. 2024 )

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Summary of Contents for GigaDevice Semiconductor GD32L23 Series

Page 1 GigaDevice Semiconductor Inc. GD32L23x ® Cortex -M23 32-bit MCU ® For GD32L233xx, GD32L235x User Manual Revision 2.2 ( Mar. 2024 )
Page 2: Table Of Contents
GD32L23x User Manual Table of Contents Table of Contents ......................2 List of Figures ......................19 List of Tables ........................ 27 1. System and memory architecture ................ 30 ® ® -M23 processor ..................30 1.1. Cortex System architecture ....................... 31 1.2.
Page 3 GD32L23x User Manual 2.3.6. Mass erase ........................... 68 2.3.7. Main flash programming ....................70 2.3.8. Main flash fast programming (only available in GD32L233xx) ........72 2.3.9. OTP programming ......................75 2.3.10. Option bytes erase ......................75 2.3.11. Option bytes modify ......................75 2.3.12.
Page 4 GD32L23x User Manual Clock control unit (CCTL) ................... 119 4.2. 4.2.1. Overview ..........................119 4.2.2. Characteristics ........................122 4.2.3. Function overview ......................122 Register definition......................128 4.3. 4.3.1. Control register (RCU_CTL) ..................... 128 4.3.2. Configuration register 0 (RCU_CFG0) ................130 4.3.3.
Page 5 GD32L23x User Manual External interrupt and event block diagram ............. 181 6.4. External interrupt and Event function overview ............182 6.5. 6.6. Register definition......................186 6.6.1. Interrupt enable register (EXTI_INTEN) ................186 6.6.2. Event enable register (EXTI_EVEN) ................187 6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............
Page 6 GD32L23x User Manual 8.3. Function overview......................212 8.4. Register definition......................214 8.4.1. Data register (CRC_DATA) ....................214 8.4.2. Free data register (CRC_FDATA) ..................214 8.4.3. Control register (CRC_CTL) ..................... 215 8.4.4. Initialization data register (CRC_IDATA) ................. 215 8.4.5. Polynomial register (CRC_POLY) ..................216 9.
Page 7 GD32L23x User Manual 10.9.8. Interrupt flag register (CAU_INTF) .................. 246 10.9.9. Key registers (CAU_KEY0..3(H/L)) .................. 246 10.9.10. Initial vector registers (CAU_IV0..1(H/L)) ............... 249 10.9.11. GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) (x=0..7) ..250 10.9.12. GCM mode context switch register x (CAU_GCMCTXSx) (x=0..7) ......251 Direct memory access controller (DMA) ............
Page 8 GD32L23x User Manual 12.6.2. Request multiplexer channel interrupt flag register (DMAMUX_RM_INTF) ....280 12.6.3. Request multiplexer channel interrupt flag clear register (DMAMUX_RM_INTC) ..281 12.6.4. Request generator channel x configuration register (DMAMUX_RG_CHxCFG) ..282 12.6.5. Request generator channel interrupt flag register (DMAMUX_RG_INTF) ....283 12.6.6.
Page 9 GD32L23x User Manual 14.5.2. Control register 0 (ADC_CTL0) ..................308 14.5.3. Control register 1 (ADC_CTL1) ..................310 14.5.4. Sample time register 0 (ADC_SAMPT0) ................. 314 14.5.5. Sample time register 1 (ADC_SAMPT1) ................. 315 14.5.6. Watchdog high threshold register (ADC_WDHT) ............316 14.5.7.
Page 10 GD32L23x User Manual 16.2.2. Characteristics ........................339 16.2.3. Function overview ......................339 16.2.4. Register definition ......................342 Real time clock (RTC) ..................345 Overview ........................345 17.1. 17.2. Characteristics ......................345 17.3. Function overview ....................346 17.3.1. Block diagram ........................346 17.3.2.
Page 11 GD32L23x User Manual 17.4.17. Alarm 0 sub second register (RTC_ALRM0SS) ............. 377 17.4.18. Alarm 1 sub second register (RTC_ALRM1SS) ............. 378 17.4.19. Backup registers (RTC_BKPx) (x=0..4)................379 Timer (TIMERx) ....................380 18.1. Advanced timer (TIMERx,x=0)................. 381 18.1.1. Overview ..........................381 18.1.2.
Page 12 GD32L23x User Manual 19.4.2. LPTIMER enable ........................ 566 19.4.3. Prescaler ..........................566 19.4.4. Input filter .......................... 567 19.4.5. External inputs high level counter .................. 567 19.4.6. Start counting mode ......................568 19.4.7. External trigger mapping ....................569 19.4.8. Counter operating mode ....................569 19.4.9.
Page 13 GD32L23x User Manual 20.3.14. Receive FIFO ........................611 20.3.15. Wakeup from Deep-sleep mode ..................612 20.3.16. USART interrupts ......................612 Register definition ....................615 20.4. 20.4.1. Control register 0 (USART_CTL0) ................... 615 20.4.2. Control register 1 (USART_CTL1) ................... 617 20.4.3. Control register 2 (USART_CTL2) ...................
Page 14 GD32L23x User Manual 21.4.10. Coherence control register (LPUART_CHC) ..............658 Inter-integrated circuit interface (I2C) ............. 659 22.1. Overview ........................659 22.2. Characteristics ......................659 22.3. Function overview ....................659 22.3.1. Clock requirements ......................660 22.3.2. I2C communication flow ....................661 22.3.3.
Page 15 GD32L23x User Manual 23.3.3. SPI clock timing and data format ..................701 23.3.4. Separate transmission and reception FIFO ..............703 23.3.5. NSS function ........................704 23.3.6. SPI operation modes ......................706 23.3.7. DMA function ........................715 23.3.8. CRC function ........................715 23.3.9.
Page 16 GD32L23x User Manual 25.3.4. SEG/COM Driver ....................... 752 25.3.5. Double buffer memory ..................... 755 25.3.6. ANALOG matrix......................... 755 25.3.7. voltage source ......................757 SLCD Register definition ....................759 25.4. 25.4.1. Control register (SLCD_CTL) ................... 759 25.4.2. Configuration register (SLCD_CFG) ................761 25.4.3.
Page 17 GD32L23x User Manual 27.4. CAN registers ......................794 27.4.1. Control register (CAN_CTL) ..................... 794 27.4.2. Status register (CAN_STAT) .................... 795 27.4.3. Transmit status register (CAN_TSTAT) ................797 27.4.4. Receive message FIFO0 register (CAN_RFIFO0) ............800 27.4.5. Receive message FIFO1 register (CAN_RFIFO1) ............800 27.4.6.
Page 18 GD32L23x User Manual 28.7.7. USBD endpoint x transmission buffer address register (USBD_EPxTBADDR), x can be in [0..7] ............................830 28.7.8. USBD endpoint x transmission buffer byte count register (USBD_EPxTBCNT), x can be in [0..7] ............................831 28.7.9. USBD endpoint x reception buffer address register (USBD_EPxRBADDR), x can be in [0..7] 28.7.10.
Page 19: List Of Figures
GD32L23x User Manual List of Figures -M23 processor ............. 31 ® ® Figure 1-1. The structure of the Arm Cortex Figure 1-2. Series system architecture of GD32L23x(x=3) series ..........33 Figure 1-3. Series system architecture of GD32L23x(x=5) series ..........34 Figure 2-1.
Page 20 GD32L23x User Manual Figure 10-13. AES CTR encryption/decryption ................234 Figure 11-1. Block diagram of DMA ....................253 Figure 11-2. Handshake mechanism ....................255 Figure 11-3. DMA interrupt logic ....................257 Figure 12-1. Block diagram of DMAMUX ..................266 Figure 12-2. Synchronization mode ....................268 Figure 12-3.
Page 21 GD32L23x User Manual Figure 18-19. Output behavior of the channel in response to a break (the break high active) 400 Figure 18-20. Example of counter operation in quadrature decoder interface mode ....401 Figure 18-21. Example of quadrature decoder interface mode with CI0FE0 polarity inverted 401 Figure 18-22.
Page 22 GD32L23x User Manual Figure 18-63. Channel input capture principle ................492 Figure 18-64. Output-compare under three modes ..............494 Figure 18-65. EAPWM timechart ..................... 495 Figure 18-66. CAPWM timechart ..................... 495 Figure 18-67. Restart mode ......................497 Figure 18-68. Pause mode ....................... 497 Figure 18-69.
Page 23 GD32L23x User Manual Figure 19-12. Counter operation in decoder mode 0 with falling-edge-mode ......575 Figure 19-13. Counter operation in decoder mode 1 with non-inverted ........576 Figure 19-14. Counter operation in decoder mode 1 with non-inverted(IN1EIF) ....... 576 Figure 19-15. Counter operation in decoder mode 1 with non-inverted(IN0EIF) ....... 577 Figure 19-16.
Page 24 GD32L23x User Manual Figure 22-12. Data reception ......................667 Figure 22-13. I2C initialization in slave mode ................670 Figure 22-14. Programming model for slave transmitting when SS=0 ........671 Figure 22-15. Programming model for slave transmitting when SS=1 ........672 Figure 22-16.
Page 25 GD32L23x User Manual Figure 23-33. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ..722 Figure 23-34. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ..723 Figure 23-35. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ..723 Figure 23-36. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ..723 Figure 23-37.
Page 26 GD32L23x User Manual Figure 25-3. 1/4 Bias, 1/6 Duty ......................754 Figure 25-4. SLCD dead time (1/3 Bias, 1/4 Duty) ................. 754 Figure 25-5. SLCD Resistr divider network for GD32L233 series ..........756 Figure 25-6. SLCD Resistr divider network for GD32L235 series ..........756 Figure 26-1.
Page 27: List Of Tables
GD32L23x User Manual List of Tables Table 1-1. Bus Interconnection Matrix ..................... 31 Table 1-2. Memory map of GD32L23x(x=3) series ................35 Table 1-3. Memory map of GD32L23x(x=5) series ................37 Table1-4. Boot modes ........................41 Table 2-1. 256KB flash base address and size for flash memory ..........63 Table 2-2.
Page 28 GD32L23x User Manual Table 15-3. Triggers of DAC ......................324 Table 16-1. Min/max FWDGT timeout period at 32KHz (IRC32K) ..........334 Table 16-2. Min-max timeout value at 64 MHz (f ) ..............341 PCLK1 Table 17-1 RTC pin PC13 configuration ..................357 Table 17-2 RTC functions in all lowpower modes ................
Page 29 GD32L23x User Manual Table 23-10. I2S interrupt ........................ 733 Table 24-1 VREF MODES ......................... 747 Table 25-1. The odd frame voltage ....................753 Table 25-2. The even frame voltage ....................753 Table 25-3. The all common signal driver ..................753 Table 26-1 CMP inputs and outputs summary ................
Page 30: System And Memory Architecture
GD32L23x User Manual System and memory architecture ® The GD32L23x series are 32-bit general-purpose microcontrollers based on the Arm ® ® ® Cortex -M23 processor. The Arm Cortex -M23 processor includes AHB buses. All memory ® ® accesses of the Arm Cortex -M23 processor are executed on the AHB buses according to the different purposes and the target memory spaces.
Page 31: System Architecture
GD32L23x User Manual ® ® Figure 1-1. The structure of the Arm Cortex -M23 processor Nested Data Vectored IRQ interface Cortex-M23 Watchpoint Interrupt Processor core And Trace Controller (DWT) (NVIC) Breakpoint Processor Unit Romtable Bus Matrix Single-cycle IO Single Wire AHB Master port Debug interface...
Page 32 GD32L23x User Manual (peripheral bus) to a bus matrix that manages the arbitration between the core and the DMA. DMA bus connects the AHB master interface of the DMA to the bus matrix that manages the access of CPU and DMA to SRAMs, Flash memory and AHB/APB peripherals. There are also several slaves connected with the AHB interconnect matrix, including FMC, SRAM0, SRAM1, AHB1, AHB2.
Page 33: Figure 1-2. Series System Architecture Of Gd32L23X(X=3) Series
GD32L23x User Manual Figure 1-2. Series system architecture of GD32L23x(x=3) series 1.1/0.9V TPIU GPIO Ports POR/PDR/ AHB2: Fma x = 64MHz A, B, C, D, F SBus SRAM ARM Cortex-M23 SRAM0(16K) Controller Processor SBus SBus SRAM : 64MHz SRAM1(16K) Controller SBus Flash 256K...
Page 34: Memory Map
GD32L23x User Manual Figure 1-3. Series system architecture of GD32L23x(x=5) series 1.1/0.9V TPIU GPIO Ports POR/PDR/ AHB2: Fma x = 64MHz A, B, C, D, F SBus SRAM ARM Cortex-M23 SRAM0(8K) Controller Processor SBus SBus SRAM : 64MHz SRAM1(16K) Controller Flash 128K SBus...
Page 35: Table 1-2. Memory Map Of Gd32L23X(X=3) Series
GD32L23x User Manual ® ® 4-Gbyte address space which is the maximum address range of the Arm Cortex -M23 since it has a 32-bit bus address width. Additionally, a pre-defined memory map is provided by the ® ® Cortex -M23 processor to reduce the software complexity of repeated implementation ®...
Page 36 GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 8000 – 0x4001 FFFF Reserved 0x4001 7C00 – 0x4001 7FFF 0x4001 5C00 – 0x4001 7BFF Reserved 0x4001 5800 – 0x4001 5BFF 0x4001 5000 – 0x4001 57FF Reserved 0x4001 4C00 – 0x4001 4FFF TIMER8 0x4001 3C00 –...
Page 37: Table 1-3. Memory Map Of Gd32L23X(X=5) Series
GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4000 3400 – 0x4000 37FF Reserved 0x4000 3000 – 0x4000 33FF FWDGT 0x4000 2C00 – 0x4000 2FFF WWDGT 0x4000 2800 – 0x4000 2BFF 0x4000 2400 – 0x4000 27FF SLCD 0x4000 2000 – 0x4000 23FF Reserved 0x4000 1C00 –...
Page 38 GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x5006 0C00 – 0x5006 0FFF Reserved 0x5006 0800 – 0x5006 0BFF TRNG 0x5006 0400 – 0x5006 07FF Reserved 0x5006 0000 – 0x5006 03FF 0x5005 0400 – 0x5005 FFFF Reserved 0x5005 0000 – 0x5005 03FF Reserved 0x5004 0000 –...
Page 39 GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 3000 – 0x4001 33FF SPI0 0x4001 2C00 – 0x4001 2FFF TIMER0 0x4001 2800 – 0x4001 2BFF Reserved 0x4001 2400 – 0x4001 27FF 0x4001 0800 – 0x4001 23FF Reserved 0x4001 0400 – 0x4001 07FF EXTI 0x4001 0000 –...
Page 40: On-Chip Sram Memory
GD32L23x User Manual Pre-defined ADDRESS Peripherals Regions 0x4000 1400 – 0x4000 17FF TIMER6 0x4000 1000 – 0x4000 13FF TIMER5 0x4000 0800 – 0x4000 0FFF Reserved 0x4000 0400 – 0x4000 07FF TIMER2 0x4000 0000 – 0x4000 03FF TIMER1 0x4000 0000 – 0x4000 03FF Reserved 0x2000 8000 –...
Page 41: Boot Configuration
GD32L23x User Manual can be erased at a time. 1.4. Boot configuration The GD32L23x series provide three kinds of boot sources which can be selected by the BOOT0 and BOOT1 pins. The details are shown in the following table. The value on the two pins is latched on the 4 rising edge of CK_SYS after a reset.
Page 42: System Configuration Registers
GD32L23x User Manual 1.6. System configuration registers SYSCFG base address: 0x4001 0000 System configuration register 0 (SYSCFG_CFG0) 1.6.1. For GD32L233xx devices Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the BOOT1 pin after reset) This register can be accessed by word(32-bit) PB9_HC PB8_HC...
Page 43 GD32L23x User Manual 0: High current capability on the PB6 pin is disabled. 1: High current capability on the PB6 pin is enabled, and the speed control of the pin is bypassed. 15:7 Reserved Must be kept at reset value BOOT0_PD3_RMP BOOT0 and PD3 remapping bit.
Page 44 GD32L23x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value PB9_HCCE PB9 pin high current capability enable When it is set, the PB9 pin can be used to control an infrared LED directly. 0: High current capability on the PB9 pin is disabled. 1: High current capability on the PB9 pin is enabled, and the speed control of the pin is bypassed.
Page 45: Exti Sources Selection Register 0 (Syscfg_Extiss0)
GD32L23x User Manual This bit is set and cleared by software. It controls the mapping of either PA9/10 or PA11/12 pin pair on small pin-count packages. 0: No remap (pin pair PA9/10 mapped on the pins) 1: Remap (pin pair PA11/12 mapped instead of PA9/10) PA11_PA12_PB6_P It controls the mapping of either PA11/PA12/PB6/PB8 or PB3/PB4/PB2/PD3 pin B8_RMP...
Page 46: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32L23x User Manual X001: PB2 pin X010: PC2 pin X011: PD2 pin X100: reserved X101: reserved X110: reserved X111: reserved EXTI1_SS[3:0] EXTI 1 sources selection X000: PA1 pin X001: PB1 pin X010: PC1 pin X011: PD1 pin X100: reserved X101: PF1 pin X110: reserved X111: reserved EXTI0_SS[3:0]...
Page 47: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32L23x User Manual X000: PA7 pin X001: PB7 pin X010: PC7 pin X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved 11:8 EXTI6_SS[3:0] EXTI 6 sources selection X000: PA6 pin X001: PB6 pin X010: PC6 pin X011: PD6 pin X100: reserved X101: reserved X110: reserved...
Page 48 GD32L23x User Manual Reserved EXTI11_SS [3:0] EXTI10_SS [3:0] EXTI9_SS [3:0] EXTI8_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI11_SS[3:0] EXTI 11 sources selection X000: PA11 pin X001: PB11 pin X010: PC11 pin X011: reserved X100: reserved X101: reserved X110: reserved...
Page 49: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32L23x User Manual X100: reserved X101: reserved X110: reserved X111: reserved EXTI sources selection register 3 (SYSCFG_EXTISS3) 1.6.5. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by word(32-bit) Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0] Bits Fields Descriptions...
Page 50: System Configuration Register 1 (Syscfg_Cfg1)
GD32L23x User Manual X100: reserved X101: reserved X110: reserved X111: reserved EXTI12_SS[3:0] EXTI 12 sources selection X000: PA12 pin X001: PB12 pin X010: PC12 pin X011: reserved X100: reserved X101: reserved X110: reserved X111: reserved System configuration register 1 (SYSCFG_CFG1) 1.6.6.
Page 51: Irq Latency Register (Syscfg_Cpu_Irq_Lat)
GD32L23x User Manual 0: No wait-state 1: Insert wait-state Reserved Must be kept at reset value LVD_LOCK LVD lock This bit is set by software and cleared by a system reset. 0: The LVD interrupt is disconnected from the break input of TIMER0/14/40. LVDEN and LVDT[2:0] in the PMU_CTL register can be programmed.
Page 52: Timerx Configuration Register (Syscfg_Timerxcfg, X=0)
GD32L23x User Manual If IRQ_LATENCY is set to 0, interrupts are taken as quickly as possible. For non-zero values, the Arm ® Cortex ® -M23 processor ensures that a minimum of IRQ_LATENCY+1 hclk cycles exist between an interrupt becoming pended in the NVIC and the vector fetch for the interrupt being performed.
Page 53 GD32L23x User Manual 23:20 TSCFG5[3:0] Event mode configuration A rising edge of the trigger input enables the counter. 0000: Event mode disable 0001: Internal trigger input 0 (ITI0) 0010: Internal trigger input 1 (ITI1) 0011: Internal trigger input 2 (ITI2) 0100: Internal trigger input 3 (ITI3) 0101: CI0 edge flag (CI0F_ED) 0110: The filtered output of channel 0 input (CI0FE0)
Page 54: Timerx Configuration Register (Syscfg_Timerxcfg, X=1, 2)
GD32L23x User Manual TSCFG1[3:0] Quadrature decoder mode 1 configuration 0000: Quadrature decoder mode 1 disable Others: The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level TSCFG0[3:0] Quadrature decoder mode 0 configuration 0000: Quadrature decoder mode 0 disable Others: The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 55 GD32L23x User Manual 0110: The filtered output of channel 0 input (CI0FE0) 0111: The filtered output of channel 1 input (CI1FE1) 1000: The filtered output of external trigger input (ETIFP) Others: Reserved 23:20 TSCFG5[3:0] Event mode configuration A rising edge of the trigger input enables the counter. 0000: Event mode disable 0001: Internal trigger input 0 (ITI0) 0010: Internal trigger input 1 (ITI1)
Page 56: Timerx Configuration Register (Syscfg_Timerxcfg, X=8, 11)
GD32L23x User Manual 11:8 TSCFG2[3:0] Quadrature decoder mode 2 configuration 0000: Quadrature decoder mode 2 disable Others: The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other. TSCFG1[3:0] Quadrature decoder mode 1 configuration 0000: Quadrature decoder mode 1 disable Others: The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level TSCFG0[3:0]...
Page 57 GD32L23x User Manual 0001: Internal trigger input 0 (ITI0) 0010: Internal trigger input 1 (ITI1) 0011: Internal trigger input 2 (ITI2) 0100: Internal trigger input 3 (ITI3) 0101: CI0 edge flag (CI0F_ED) 0110: The filtered output of channel 0 input (CI0FE0) 0111: The filtered output of channel 1 input (CI1FE1) 1000: Reserved Others: Reserved...
Page 58: Timerx Configuration Register (Syscfg_Timerxcfg, X=14, 40)
GD32L23x User Manual 0101: CI0 edge flag (CI0F_ED) 0110: The filtered output of channel 0 input (CI0FE0) 0111: The filtered output of channel 1 input (CI1FE1) 1000: Reserved Others: Reserved 11:0 Reserved Must be kept at reset value TIMERx configuration register (SYSCFG_TIMERxCFG, x=14, 40) 1.6.11.
Page 59 GD32L23x User Manual 0111: The filtered output of channel 1 input (CI1FE1) Others: Reserved 23:20 TSCFG5[3:0] Event mode configuration A rising edge of the trigger input enables the counter. 0000: Event mode disable 0001: Internal trigger input 0 (ITI0) 0010: Internal trigger input 1 (ITI1) 0011: Internal trigger input 2 (ITI2) 0100: Internal trigger input 3 (ITI3) 0101: CI0 edge flag (CI0F_ED)
Page 60: Device Electronic Signature
GD32L23x User Manual 1.7. Device electronic signature The device electronic signature contains memory density information and the 96-bit unique device ID. It is stored in the information block of the Flash memory. The 96-bit unique device ID is unique for any device. It can be used as serial numbers, or part of security keys, etc. Memory density information 1.7.1.
Page 61 GD32L23x User Manual 31:0 UNIQUE_ID[31:0] Unique device ID Base address: 0x1FFF F7EC The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit) UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is factory programmed and can never be altered by user.
Page 62: Flash Memory Controller (Fmc)
GD32L23x User Manual Flash memory controller (FMC) Overview 2.1. The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. A little waiting time is needed while CPU executes instructions stored from the 256K bytes of the flash. It also provides page erase, mass erase, and program operations for flash memory.
Page 63: Table 2-1. 256Kb Flash Base Address And Size For Flash Memory
GD32L23x User Manual For GD32L233xx： Table 2-1. 256KB flash base address and size for flash memory Block Name Address range size(bytes) 0x0800 0000 – 0x0800 0FFF Page 0 0x0800 1000 – 0x0800 1FFF Page 1 0x0800 2000 – 0x0800 2FFF Page 2 Main flash block 0x0803 F000 –...
Page 64: Error Checking And Correcting (Ecc) (Only Available In Gd32L235Xx)
GD32L23x User Manual Block Name Address range size(bytes) One-time program block OTP bytes 0x1FFF_7000~0x1FFF_71FF 512B Note: The information block stores the boot loader. This block cannot be programmed or erased by user. Table 2-4. 32KB flash base address and size for flash memory Block Name Address range...
Page 65: Read Operations
GD32L23x User Manual ◼ Two errors detection When one error is detected and corrected: ◼ When ECC error occurs, the ECCCOR bit in FMC_ECCCS register will be set. If the ECCCORIE bit in FMC_ECCCS register is set, an interrupt is generated. The OB_ECC / OTP_ECC / SYS_ECC / MF_ECC notice the space where error occurred.
Page 66: Table 2-7. The Relation Between Wscnt And Ahb Clock Frequency When Ldo Is 0.9V For
GD32L23x User Manual for GD32L233xx AHB clock frequency WSCNT configured <= 32MHz 0 (0 wait state added) <= 64MHz 1 (1 wait state added) Table 2-7. The relation between WSCNT and AHB clock frequency when LDO is 0.9V for GD32L233xx AHB clock frequency WSCNT configured <= 16MHz...
Page 67: Unlock The Fmc_Ctl Register
GD32L23x User Manual Pre-fetch buffer: The pre-fetch buffer is enabled by set the PFEN bit in the FMC_WS register. In the case of sequential code, when CPU execute the current buffer data (64-bit), 32-bit needs at least 2 clocks and 16-bit needs at least 4 clocks. In this case, pre-fetch the data of next double-word address from flash memory and store to pre-fetch buffer.
Page 68: Mass Erase
GD32L23x User Manual Note that a correct target page address must be confirmed. Otherwise, the software may run out of control if the target erase page is being used to fetch codes or access data. The FMC will not provide any notification when that happens. Additionally, the page erase operation will be ignored on erase/program protected pages.
Page 69: Figure 2-2. Process Of Mass Erase Operation
GD32L23x User Manual is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished. ◼ Set the MER bit in the FMC_CTL register if erase entire flash. ◼ Send the mass erase command to the FMC by setting the START bit in the FMC_CTL register.
Page 70: Main Flash Programming
GD32L23x User Manual Figure 2-2. Process of mass erase operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the MER bit Send the command to FMC by set START bit Is the BUSY bit is 0 Finish Main flash programming 2.3.7.
Page 71 GD32L23x User Manual For GD32L233xx: If SBUS program is 32-bit word, the SBUS write once and the data program to flash memory. The data to be programed must be word-aligned. If SBUS program is 16-bit, the SBUS write twice form a 32-bit data and then the 32-bit data program to flash memory. The data to be programed must be word-aligned.
Page 72: Main Flash Fast Programming (Only Available In Gd32L233Xx)
GD32L23x User Manual WPERR bit in the FMC_STAT register to detect which condition occurred in the interrupt Figure 2-3. Process of program operation handler. shows the word programming operation flow. Figure 2-3. Process of program operation Start Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit...
Page 73 GD32L23x User Manual ◼ Set the FSTPG bit in FMC_CTL register. ◼ Write the one row data (32 double-word) to be programed by BUS with desired absolute address (0x08XX XXXX). ◼ Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STAT register.
Page 74: Figure 2-4. Process Of Fast Program Operation
GD32L23x User Manual Figure 2-4. Process of fast program operation Start Is the one row data(32 double-word) Erase flash is all FF Is the LK bit is 0 Unlock the FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by SBUS Is the BUSY bit is 0...
Page 75: Otp Programming
GD32L23x User Manual 6. Because fast program mode cannot check whether the flash memory is FF through hardware, the software must first check whether the flash memory is FF, and a row must not be programmed twice or more between two erase operations. If program one row twice or more between two erase operations, unpredictable result may occur.
Page 76: Option Bytes Description
GD32L23x User Manual ◼ Unlock the option bytes operation bits in the FMC_CTL register if necessary. ◼ Wait until the OBWEN bit is set in the FMC_CTL register. ◼ Set the OBPG bit in the FMC_CTL register. ◼ A 32-bit word/16-bit half word written at desired address by SBUS. The program method is similar to main flash programming.
Page 77: Page Erase / Program Protection
GD32L23x User Manual Address Name Description Note: only available in GD32L235xx [2]: nRST_STDBY 0: generate a reset instead of entering standby mode 1: no reset when entering standby mode [1]: nRST_DPSLP 0: generate a reset instead of entering deep-sleep mode 1: no reset when entering deep-sleep mode [0]: nWDG_HW 0: hardware free watchdog...
Page 78: Security Protection
GD32L23x User Manual Security protection 2.3.14. The FMC provides a security protection function to prevent illegal code/data access to the flash memory. This function is useful for protecting the software/firmware from illegal users. No protection: when setting SPC byte and its complement value to 0x5AA5, no protection performed.
Page 79: Register Definition
GD32L23x User Manual Register definition 2.4. FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. For GD32L233xx devices Address offset: 0x00 Reset value: 0x0000 0630 This register has to be accessed by word (32-bit). Reserved SLEEP_S Reserved RUN_SLP Reserved Reserved PFEN Reserved...
Page 80 GD32L23x User Manual 1: Pre-fetch enable Reserved Must be kept at reset value. WSCNT[2:0] Wait state counter register These bits are set and reset by software. 000: 0 wait state added 001: 1 wait state added 010: 2 wait state added 011: 3 wait state added 010 ~111: reserved For GD32L235xx devices...
Page 81: Unlock Key Register (Fmc_Key)
GD32L23x User Manual 12:5 Reserved Must be kept at reset value. PFEN Pre-fetch enable 0: Pre-fetch disable 1: Pre-fetch enable Reserved Must be kept at reset value. WSCNT[1:0] Wait state counter register These bits are set and reset by software. 00: 0 wait state added 01: 1 wait state added 10: 2 wait state added...
Page 82: Status Register (Fmc_Stat)
GD32L23x User Manual Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_CTL option bytes operation unlock register These bits are only be written by software. Write OBKEY[31:0] with keys to unlock option bytes command in the FMC_CTL register. Status register (FMC_STAT) 2.4.4. For GD32L233xx devices Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 83 GD32L23x User Manual BUSY The flash is busy bit When the operation is in progress, this bit is set to 1. When the operation is end or an error is generated, this bit is cleared to 0. For GD32L235xx devices Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 84: Control Register (Fmc_Ctl)
GD32L23x User Manual When the operation is in progress, this bit is set to 1. When the operation is end or an error is generated, this bit is cleared to 0. Control register (FMC_CTL) 2.4.5. For GD32L233xx devices Address offset: 0x10 Reset value: 0x0000 0080 This register has to be accessed by word (32-bit).
Page 85 GD32L23x User Manual This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared. OBER Option bytes erase command bit This bit is set or clear by software 0: no effect 1: option bytes erase command OBPG...
Page 86 GD32L23x User Manual This bit is set or cleared by software 0: no interrupt generated by hardware. 1: end of operation interrupt enable Reserved Must be kept at reset value. ERRIE Error interrupt enable bit This bit is set or cleared by software 0: no interrupt generated by hardware.
Page 87: Address Register (Fmc_Addr)
GD32L23x User Manual 1: main flash program command Note: This register should be reset after the corresponding flash operation completed. Address register (FMC_ADDR) 2.4.6. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). ADDR[31:16] ADDR[15:0] Bits...
Page 88 GD32L23x User Manual System memory: 0 ~ 0x4FF (10K/8 – 1) ECCCORIE One bit error correct interrupt enable. 0: One bit error correct interrupt disable. 1: One bit error correct interrupt enable. ECCDETIE Two bits errors detect interrupt enable. 0: Two bits errors detect interrupt disable. 1: Two bits errors detect interrupt enable.
Page 89: Option Bytes Status Register (Fmc_Obstat)
GD32L23x User Manual ECCCOR One bit error detected and correct flag. This bit is cleared by writing 1. 0: No ECC error is detected and corrected. 1: An ECC error is detected and corrected. Option bytes status register (FMC_OBSTAT) 2.4.8. Address offset: 0x1C Reset value: 0x0XXX XXXX.
Page 90: Unlock Flash Sleep/Power-Down Mode Key Register (Fmc_Slpkey)
GD32L23x User Manual Bits Fields Descriptions 31:0 WP[31:0] Store WP[31:0] of option bytes block after system reset Unlock flash sleep/power-down mode key register (FMC_SLPKEY) 2.4.10. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SLPKEY[31:16] SLPKEY[15:0] Bits...
Page 91: Power Management Unit (Pmu)
GD32L23x User Manual Power management unit (PMU) Overview 3.1. The power consumption is regarded as one of the most important issues for the devices of GD32L23x series. For GD32L233xx devices, power management unit (PMU) provides ten types of power saving modes, including Run, Run1, Run2, Sleep, Sleep1, Sleep2, Deep- sleep, Deep-sleep 1, Deep-sleep 2 and Standby mode.
Page 92 GD32L23x User Manual Standby modes. ◼ Low power Internal Voltage regulator (LDO) supplies around 0.9V voltage source for 1.1V domain when in Deep-sleep 1 or Deep-sleep 2 mode. ◼ EFLASH can be power-off alone when in run or Deep-sleep mode.
Page 93: Function Overview
GD32L23x User Manual Function overview 3.3. Figure 3-1. Power supply overview of GD32L233xx devices Figure 3-2. Power provide details on the internal configuration of supply overview of GD32L235xx devices the PMU and the relevant power domains. Figure 3-1. Power supply overview of GD32L233xx devices Backup Domain Power Switch 3.3V...
Page 94: Battery Backup Domain
GD32L23x User Manual Figure 3-2. Power supply overview of GD32L235xx devices Backup Domain Power Switch 3.3V LXTAL BPOR PC13 WKUPx WKUPR BKP PAD WKUPN NRST WKUPF FWDGT SLEEPING Cortex-M23 SLEEPDEEP HXTAL POR/PDR NPLDO AHB IPs APB IPs 1.1V Domain LPLDO 1.1V Domain 0.9V Domain...
Page 95: Vdd / V Dda
GD32L23x User Manual up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the Real time clock (RTC) When the Backup domain is supplied by V pin is connected to V ), the following functions are available: ◼...
Page 96: Figure 3-4. Waveform Of The Bor
GD32L23x User Manual Figure 3-3. Waveform of the BOR0 BOR0 40mV hyst BOR0 RSTTEMPO 550us Power Reset (Active Low) The BOR circuit is used to detect V and generate the power reset signal which resets the whole chip except the Backup domain when the supply voltage is lower than the specified threshold which defined in the BOR_TH bits in option bytes.
Page 97: Power Domain
GD32L23x User Manual is enabled by setting the LVDEN bit, and LVDF bit, which in power control and status register (PMU_CS), indicates if V is higher or lower than the LVD threshold. This event is internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through the EXTI registers.
Page 98 GD32L23x User Manual SRAM1 power domain SRAM1(For GD32L233xx devices, 0x20004000~0x20007FFF. For GD32L235xx devices, 0x20002000~0x20005FFF) can be power-off alone and it is power on after system reset by default. SRAM1 can be powered off in order to reduce the power consumption in Run / Run1 / Run2 mode for GD32L233xx devices and reduce the power consumption in Run mode for GD32L235xx devices.
Page 99: Power Saving Modes
GD32L23x User Manual Power saving modes 3.3.4. After a system reset or a power reset, the GD32L23x MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals.
Page 100 GD32L23x User Manual WFI or WFE instruction is executed. ◼ Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits from the lowest priority ISR. Sleep1 mode The Sleep1 mode is corresponding to the SLEEPING mode of the Cortex -M23 When in ®...
Page 101 GD32L23x User Manual Then, the device enters the Deep-sleep 1 mode after a WFI or WFE instruction is executed. If the Deep-sleep 1 mode is entered by executing a WFI instruction, any interrupt from EXTI lines can wake up the system. If it is entered by executing a WFE instruction, any wakeup event from EXTI lines can wake up the system (If SEVONPEND is 1, any interrupt from EXTI lines can wake up the system, refer to Cortex -M23 Technical Reference Manual).
Page 102: Table 3-1. Power Saving Mode Summary (For Gd32L233Xx Devices)
GD32L23x User Manual power domain are lost in Standby mode. When exiting from the Standby mode, a power-on reset occurs and the Cortex ® -M23 will execute instruction code from the 0x00000000 address. or GD32L233xx devices) Table 3-1. Power saving mode summary (f Wakeup Wakeup Mode...
Page 103: Table 3-2. Power Saving Mode Summary(For Gd32L235Xx Devices)
GD32L23x User Manual Wakeup Wakeup Mode Description Entry Wakeup status Latency when SEVONPEND is IRC48M, HXTAL and wakeup 1) from EXTI for WFE PLLs time+Flash 3. LPLDO instead of wakeup time NPLDO 4. COREOFF0 / SRAM1 power-off. 5. For GD32L233xx devices, COREOFF1 power-off.
Page 104 GD32L23x User Manual Wakeup Wakeup Mode Description Entry Wakeup status Latency 1. All clocks in the 1.1V domain are off 2. Disable IRC16M, IRC16M IRC48M, HXTAL and Any interrupt from EXTI wakeup time, PLLs SLEEPDEEP = lines for WFI Deep- 3.
Page 105: Register Definition
GD32L23x User Manual Register definition 3.4. PMU base address: 0x4000 7000 Control register 0 (PMU_CTL0) 3.4.1. For GD32L233xx devices Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode). This register can be accessed by half-word(16-bit) or word(32-bit). Reserved LDNPDS LDOVS[1:0]...
Page 106 GD32L23x User Manual 1: Low-driver mode enabled when use NPLDO. Reserved Must be kept at reset value. BKPWEN Backup Domain Write Enable 0: Disable write access to the registers in Backup domain. 1: Enable write access to the registers in Backup domain. After reset, any write access to the registers in Backup domain is ignored.
Page 107 GD32L23x User Manual Reserved LDNPDS LDOVS[1:0] VCRSEL VCEN LDNP Reserved BKPWEN LVDT[2:0] LVDEN STBRST WURST LPMOD[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. LDO output voltage select 15:14 LDOVS[1:0] These bits are set by software when the main PLL closed. And the LDO output voltage selected by LDOVS bits takes effect when the main PLL enabled.
Page 108: Control And Status Register (Pmu_Cs)
GD32L23x User Manual 001: 2.3V 010: 2.4V 011: 2.6V 100: 2.7V 101: 2.9V 110: 3.0V 111: input analog voltage on PB7 (compared with 0.8V) LVDEN Low Voltage Detector Enable 0: Disable Low Voltage Detector 1: Enable Low Voltage Detector STBRST Standby Flag Reset 0: No effect 1: Reset the standby flag...
Page 109 GD32L23x User Manual 31:17 Reserved Must be kept at reset value. NPRDY NPLDO ready flag 0: NPLDO is not ready. 1: NPLDO is ready. Reserved Must be kept at reset value. LDOVSRF LDO voltage select ready flag. 0: LDO voltage select not ready. 1: LDO voltage select ready.
Page 110 GD32L23x User Manual 1: Enable WKUP pin0 function. If WUPEN0 is set before entering the power saving mode, a rising edge on the WKUP pin0 wakes up the system from the power saving mode. As the WKUP pin0 is active high, the WKUP pin0 is internally configured to input pull down mode. And set this bit will trigger a wakup event when the input is aready high.
Page 111 GD32L23x User Manual 0: NPLDO is not ready. 1: NPLDO is ready. Reserved Must be kept at reset value. LDOVSRF LDO voltage select ready flag. 0: LDO voltage select not ready. 1: LDO voltage select ready. WUPEN5 WKUP Pin5 (PB5) enable 0: Disable WKUP pin5 function 1: Enable WKUP pin5 function If WUPEN5 is set before entering the power saving mode, a rising edge on the...
Page 112: Control Register 1 (Pmu_Ctl1)
GD32L23x User Manual set this bit will trigger a wakup event when the input is aready high. WUPEN0 WKUP Pin0 (PA0) enable 0: Disable WKUP pin0 function. 1: Enable WKUP pin0 function. If WUPEN0 is set before entering the power saving mode, a rising edge on the WKUP pin0 wakes up the system from the power saving mode.
Page 113 GD32L23x User Manual CORE1W CORE1S SRAM1P SRAM1P Reserved Reserved LEEP WAKE SLEEP Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. Power state of SRAM1 when enters Deep-sleep2 mode SRAM1PD2 0: SRAM1 power-off. 1: SRAM1 power same as Run / Run1 / Run2 mode. Note: When wakeup from the Deep-sleep2 mode, the power state of SRAM1 is the same as the power state before entering the Deep-sleep2 mode.
Page 114: Status Register (Pmu_Stat)
GD32L23x User Manual EFDSPS EFPSLEE SRAM1P SRAM1P Reserved Reserved LEEP WAKE SLEEP Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. Power state of SRAM1 when enters Deep-sleep2 mode SRAM1PD2 0: SRAM1 power-off. 1: SRAM1 power same as Run mode. Note: When wakeup from the Deep-sleep2 mode, the power state of SRAM1 is the same as the power state before entering the Deep-sleep2 mode.
Page 115 GD32L23x User Manual CORE1P SRAM1P CORE1P SRAM1P Reserved S_ACTIV S_ACTIV DPF2 Reserved S_SLEEP S_SLEEP rc_w0 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. COREOFF1 domain is in active state. CORE1PS_ACTIVE COREOFF1 domain is in sleep state. CORE1PS_SLEEP SRAM1PS_ACTIVE SRAM1 is in active state.
Page 116: Parameter Register (Pmu_Par)
GD32L23x User Manual Reserved Must be kept at reset value. Parameter register (PMU_PAR) 3.4.5. For GD32L233xx devices Address offset: 0x10 Reset value: 0x040A 2064 This register can be accessed by half-word(16-bit) or word(32-bit). TWKSRA TWKCOR TWKEN TWK_CORE1[7:0] TSW_IRC16MCNT[4:0] M1EN E1EN TWK_SRAM1[7:0] TWK_CORE0[7:0] Bits...
Page 117 GD32L23x User Manual For GD32L235xx devices Address offset: 0x10 Reset value: 0x000A 2064 This register can be accessed by half-word(16-bit) or word(32-bit). TWKEN Reserved TWK_EFLASH[7:0] TSW_IRC16MCNT[4:0] TWK_SRAM1[7:0] TWK_CORE0[7:0] Bits Fields Descriptions Use software value when wake up Deep-sleep2 or not TWKEN 0: use hardware ack signal when wake up Deep-sleep2.
Page 118: Reset And Clock Unit (Rcu)
GD32L23x User Manual Reset and clock unit (RCU) 4.1. Reset control unit (RCTL) Overview 4.1.1. GD32L23x reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, resets the full system except the backup domain during a power up.
Page 119: Clock Control Unit (Cctl)
GD32L23x User Manual Figure 4-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V power on). 4.2. Clock control unit (CCTL) Overview 4.2.1.
Page 120: Figure 4-2. Clock Tree Of Gd32L233Xx Devices
GD32L23x User Manual Figure 4-2. Clock tree of GD32L233xx devices CK_I2S (to I2S) IRC16M CK_IRC1 divide 6MDIV CK_FMC ÷ 1,2,4,8,16 FMC enable SCS[1:0] (to FMC) (by hardware) HCLK CK_IRC16M AHB enable (to AHB bus,Cortex-M23,SRAM,DMA) 16 MHz CK_CST X4,5， CK_PLL CK_SYS CK_AHB IRC16M ÷...
Page 121: Figure 4-3. Clock Tree Of Gd32L235Xx Devices
GD32L23x User Manual Figure 4-3. Clock tree of GD32L235xx devices CK_I2S (to I2S) IRC16M CK_IRC1 divide 6MDIV CK_FMC ÷ 1,2,4,8,16 FMC enable SCS[2:0] (to FMC) (by hardware) HCLK CK_IRC16M AHB enable (to AHB bus,Cortex-M23,SRAM,DMA) 16 MHz CK_CST X4,5， CK_PLL CK_SYS CK_AHB IRC16M ÷...
Page 122: Characteristics
GD32L23x User Manual 1) bits in configuration register 2 (RCU_CFG2). The I2Cx(x = 0, 1, 2) is clocked by IRC16MDIV clock or system clock or APB1 clock, which selected by I2CxSEL(x = 0, 1, 2) bits in configuration register 2 (RCU_CFG2). The RTC is clocked by LXTAL clock or IRC32K clock or HXTAL clock divided by 32 which select by RTCSRC bits in backup domain control register (RCU_BDCTL).
Page 123: Figure 4-4. Hxtal Clock Source
GD32L23x User Manual Figure 4-4. HXTAL clock source The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register, RCU_CTL. The HXTALSTB flag in control register, RCU_CTL indicates if the high- speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released for use until this HXTALSTB bit is set by the hardware.
Page 124 GD32L23x User Manual The frequency accuracy of the IRC16M can be calibrated by the manufacturer, but its operating frequency is still less accurate than HXTAL. The application requirements, environment and cost will determine which oscillator type is selected. If the HXTAL or PLL is the system clock source, to minimize the time required for the system to recover from the Deep-sleep Mode, the hardware forces the IRC16M clock to be the system clock when the system initially wakes-up.
Page 125 GD32L23x User Manual Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the backup domain control register (RCU_BDCTL). The CK_LXTAL is equal to the external clock which drives the OSC32IN pin. LXTAL can be switched on when LPUART / LPUART0 / LPUART1 / USART0 / USART1 uses LXTAL as function clock.
Page 126: Table 4-1. Clock Source Select
GD32L23x User Manual The software must then disable the LCKMEN bit, stop the defective 32 KHz oscillator, and change the RTC clock source, or take any required action to secure the application. A 4-bits plus one counter will work at IRC32K domain when LCKMEN enable. If the LXTAL clock has stuck at 0 / 1 error or slow down about 20KHz, the counter will overflow.
Page 127 GD32L23x User Manual FMC and PMU also have capable of open IRC16M clock or close IRC16M clock, if they work in deep-sleep 1 / 2 mode. To save power in deep-sleep 1 / 2 mode. CK_FMC and LPUART / LPUART0 / LPUART1 / USART0 / USART1 function clock can be gated individually, if they don’t work in deep-sleep 1/2 mode mode.
Page 128: Register Definition
GD32L23x User Manual 4.3. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 4.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC48MS IRC48ME HXTALB HXTALST HXTALE Reserved PLLSTB...
Page 129 GD32L23x User Manual and ready (LXTALSTB flag set by hardware). IRC48MSTB IRC48M oscillator stabilization flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use. 0: IRC48M oscillator is not stable 1: IRC48M oscillator is stable IRC48MEN Internal high speed oscillator enable Set and reset by software.
Page 130: Configuration Register 0 (Rcu_Cfg0)
GD32L23x User Manual MHz ± 1%. Reserved Must be kept at reset value. IRC16MSTB IRC16M high speed internal oscillator stabilization flag Set by hardware to indicate if the IRC16M oscillator is stable and ready for use. 0: IRC16M oscillator is not stable 1: IRC16M oscillator is stable IRC16MEN Internal high speed oscillator enable...
Page 131 GD32L23x User Manual see bits 23:18 of RCU_CFG0 26:24 CKOUTSEL[2:0] CK_OUT clock source selection Set and reset by software. 000: No clock selected 001: Internal 48MHz RC oscillator clock selected 010: Internal 32K RC oscillator clock selected 011: External low speed oscillator clock selected 100: System clock selected 101: Internal 16MHz RC oscillator clock selected 110: External high speed oscillator clock selected...
Page 132 GD32L23x User Manual 1111: (CK_AHB / 17) selected 13:11 APB2PSC[2:0] APB2 prescaler selection Set and reset by software to control the APB2 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0]...
Page 133: Interrupt Register (Rcu_Int)
GD32L23x User Manual Set by software to select the CK_SYS source. Because the change of CK_SYS has inherent latency, software should read SCSS to confirm whether the switching is complete or not. The switch will be forced to IRC16M when leaving Deep-sleep and Standby mode or by HXTAL clock monitor when the HXTAL failure is detected and the HXTAL is selected as the clock source of CK_SYS or PLL.
Page 134 GD32L23x User Manual 1: Reset LCKMIF flag IRC48MSTBIC IRC48M stabilization interrupt clear Write 1 by software to reset the IRC48MSTBIF flag. 0: Not reset IRC48MSTBIF flag 1: Reset IRC48MSTBIF flag PLLSTBIC PLL stabilization interrupt clear Write 1 by software to reset the PLLSTBIF flag. 0: Not reset PLLSTBIF flag 1: Reset PLLSTBIF flag HXTALSTBIC...
Page 135 GD32L23x User Manual HXTALSTBIE HXTAL stabilization interrupt enable Set and reset by software to enable/disable the HXTAL stabilization interrupt 0: Disable the HXTAL stabilization interrupt 1: Enable the HXTAL stabilization interrupt IRC16MSTBIE IRC16M stabilization interrupt enable Set and reset by software to enable/disable the IRC16M stabilization interrupt 0: Disable the IRC16M stabilization interrupt 1: Enable the IRC16M stabilization interrupt LXTALSTBIE...
Page 136: Apb2 Reset Register (Rcu_Apb2Rst)
GD32L23x User Manual 0: No HXTAL stabilization interrupt generated 1: HXTAL stabilization interrupt generated IRC16MSTBIF IRC16M stabilization interrupt flag Set by hardware when the internal 16 MHz RC oscillator clock is stable and the IRC16MSTBIE bit is set. Reset by software when setting the IRC16MSTBIC bit. 0: No IRC16M stabilization interrupt generated 1: IRC16M stabilization interrupt generated LXTALSTBIF...
Page 137 GD32L23x User Manual 1: Reset the TIMER40 TIMER14RST TIMER14 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER14 USART0RST USART0 Reset This bit is set and reset by software. 0: No reset 1: Reset the USART0 Reserved Must be kept at reset value.
Page 138: Apb1 Reset Register (Rcu_Apb1Rst)
GD32L23x User Manual APB1 reset register (RCU_APB1RST) 4.3.5. For GD32L233xx devices Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). UART4R UART3RS LPUARTR USART1 Reserved CTCRST DACRST PMURST Reserved I2C2RST USBDRST I2C1RST I2C0RST Reserved WWDGT SLCDRS...
Page 139 GD32L23x User Manual I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset I2C0 UART4RST UART4 reset This bit is set and reset by software.
Page 140 GD32L23x User Manual This bit is set and reset by software. 0: No reset 1: Reset LPTIMER timer TIMER11RST TIMER11 timer reset This bit is set and reset by software. 0: No reset 1: Reset TIMER11 timer Reserved Must be kept at reset value. TIMER6RST TIMER6 timer reset This bit is set and reset by software.
Page 141 GD32L23x User Manual Bits Fields Descriptions Reserved Must be kept at reset value CTCRST CTC reset This bit is set and reset by software. 0: No reset 1: Reset CTC DACRST DAC reset This bit is set and reset by software. 0: No reset 1: Reset DAC PMURST...
Page 142 GD32L23x User Manual UART3RST UART3 reset This bit is set and reset by software. 0: No reset 1: Reset UART3 LPUART0RST LPUART0 reset This bit is set and reset by software. 0: No reset 1: Reset LPUART0 USART1RST USART1 reset This bit is set and reset by software.
Page 143: Ahb Enable Register (Rcu_Ahben)
GD32L23x User Manual This bit is set and reset by software. 0: No reset 1: Reset TIMER11 timer Reserved Must be kept at reset value. TIMER6RST TIMER6 timer reset This bit is set and reset by software. 0: No reset 1: Reset TIMER6 timer TIMER5RST TIMER5 timer reset...
Page 144 GD32L23x User Manual 0: Disabled GPIO port F clock 1: Enabled GPIO port F clock Reserved Must be kept at reset value. PDEN GPIO port D clock enable This bit is set and reset by software. 0: Disabled GPIO port D clock 1: Enabled GPIO port D clock PCEN GPIO port C clock enable...
Page 145: Apb2 Enable Register (Rcu_Apb2En)
GD32L23x User Manual during Sleep mode. 0: Disabled SRAM0 interface clock during Sleep mode. 1: Enabled SRAM0 interface clock during Sleep mode Reserved Must be kept at reset value. DMAEN DMA clock enable This bit is set and reset by software. 0: Disabled DMA clock 1: Enabled DMA clock APB2 enable register (RCU_APB2EN)
Page 146: Apb1 Enable Register (Rcu_Apb1En)
GD32L23x User Manual USART0EN USART0 clock enable This bit is set and reset by software. 0: Disabled USART0 clock 1: Enabled USART0 clock Reserved Must be kept at reset value. SPI0EN SPI0 clock enable This bit is set and reset by software. 0: Disabled SPI0 clock 1: Enabled SPI0 clock TIMER8EN...
Page 147 GD32L23x User Manual UART4 UART3 LPUARTE USART1 BKPEN CTCEN DACEN PMUEN Reserved I2C2EN USBDEN I2C1EN I2C0EN Reserved WWDGT LPTIMER TIMER11 TIMER6E TIMER5E TIMER2E TIMER1E Reserved SPI1EN Reserved SLCDEN Reserved Reserved Bits Fields Descriptions BKPEN BKP (RTC) clock enable This bit is set and reset by software. 0: Disabled BKP(RTC) clock 1: Enabled BKP (RTC) clock CTCEN...
Page 148 GD32L23x User Manual This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software.
Page 149 GD32L23x User Manual 0: Disabled TIMER11 timer clock 1: Enabled TIMER11 timer clock Reserved Must be kept at reset value. TIMER6EN TIMER6 timer clock enable This bit is set and reset by software. 0: Disabled TIMER6 timer clock 1: Enabled TIMER6 timer clock TIMER5EN TIMER5 timer clock enable This bit is set and reset by software.
Page 150 GD32L23x User Manual CTCEN CTC clock enable This bit is set and reset by software. 0: Disabled CTC clock 1: Enabled CTC clock DACEN DAC clock enable This bit is set and reset by software. 0: Disabled DAC clock 1: Enabled DAC clock PMUEN Power interface clock enable This bit is set and reset by software.
Page 151 GD32L23x User Manual 0: Disabled UART3 clock 1: Enabled UART3 clock LPUART0EN LPUART0 clock enable This bit is set and reset by software. 0: Disabled LPUART0 clock 1: Enabled LPUART0 clock USART1EN USART1 clock enable This bit is set and reset by software. 0: Disabled USART1 clock 1: Enabled USART1 clock CANEN...
Page 152: Backup Domain Control Register (Rcu_Bdctl)
GD32L23x User Manual 1: Enabled TIMER11 timer clock Reserved Must be kept at reset value. TIMER6EN TIMER6 timer clock enable This bit is set and reset by software. 0: Disabled TIMER6 timer clock 1: Enabled TIMER6 timer clock TIMER5EN TIMER5 timer clock enable This bit is set and reset by software.
Page 153: Reset Source /Clock Register (Rcu_Rstsck)
GD32L23x User Manual This bit is set and reset by software. 0: No reset 1: Resets backup domain RTCEN RTC clock enable This bit is set and reset by software. 0: Disabled RTC clock 1: Enabled RTC clock 14:10 Reserved Must be kept at reset value.
Page 154 GD32L23x User Manual reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). WWDGT FWDGTR PORRST LPRSTF SWRSTF EPRSTF Reserved RSTFC V11RSTF Reserved RSTF IRC32K IRC32K Reserved Bits Fields Descriptions LPRSTF Low-power reset flag Set by hardware when Deep-sleep /standby reset generated. Reset by writing 1 to the RSTFC bit.
Page 155: Ahb Reset Register (Rcu_Ahbrst)
GD32L23x User Manual 0: No external PIN reset generated 1: External PIN reset generated Reserved Must be kept at reset value. RSTFC Reset flag clear This bit is set by software to clear all reset flags. 0: Not clear reset flags 1: Clear reset flags V11RSTF 1.1V domain Power reset flag...
Page 156: Configuration Register 1 (Rcu_Cfg1)
GD32L23x User Manual 1: Reset GPIO port F Reserved Must be kept at reset value. PDRST GPIO port D reset This bit is set and reset by software. 0: No reset GPIO port D 1: Reset GPIO port D PCRST GPIO port C reset This bit is set and reset by software.
Page 157: Configuration Register 2 (Rcu_Cfg2)
GD32L23x User Manual SSCS[2] Bit 2 of SSCS, only for GD32L235xx devieces see bits 3:2 of RCU_CFG0 SCS[2] Bit 2 of SCS, only for GD32L235xx devieces see bits 1:0 of RCU_CFG0 15:4 Reserved Must be kept at reset value. PREDV[3:0] PLL source clocks pre-divider This bit is set and reset by software.
Page 158 GD32L23x User Manual 31:30 ADCPSC[3:2] Bit 3 and bit 2 of ADCPSC see bits 15:14 of RCU_CFG0 29:21 Reserved Must be kept at reset value. 20:18 IRC16MDIVSEL CK_IRC16M divided clock selection 0xx: CK_IRC16MDIV select CK_IRC16M 100: CK_IRC16MDIV select CK_IRC16M divided by 2 101: CK_IRC16MDIV select CK_IRC16M divided by 4 110: CK_IRC16MDIV select CK_IRC16M divided by 8 111: CK_IRC16MDIV select CK_IRC16M divided by 16...
Page 159 GD32L23x User Manual 01: CK_I2C2 select CK_SYS 10 / 11: CK_I2C2 select CK_IRC16MDIV I2C1SEL[1:0] CK_I2C1 clock source selection 00: CK_I2C1 select CK_APB1 01: CK_I2C1 select CK_SYS 10 / 11: CK_I2C1 select CK_IRC16MDIV I2C0SEL[1:0] CK_I2C0 clock source selection 00: CK_I2C0 select CK_APB1 01: CK_I2C0 select CK_SYS 10 / 11: CK_I2C0 select CK_IRC16MDIV USART0SEL[1:0]...
Page 160 GD32L23x User Manual Reserved Must be kept at reset value. 22:21 LPTIMER1SEL[1:0] CK_LPTIMER1 clock source selection This bit is set and reset by software. 00: CK_LPTIMER1 select CK_APB1 01: CK_LPTIMER1 select CK_IRC32K 10: CK_LPTIMER1 select CK_LXTAL 11: CK_LPTIMER1 select CK_IRC16MDIV 20:18 IRC16MDIVSEL CK_IRC16M divided clock selection...
Page 161: Ahb2 Enable Register (Rcu_Ahb2En)
GD32L23x User Manual clock of AHB divided by 3, 5, 7, 9, 11, 13, 15, 17 I2C2SEL[1:0] CK_I2C2 clock source selection 00: CK_I2C2 select CK_APB1 01: CK_I2C2 select CK_SYS 10/11: CK_I2C2 select CK_IRC16MDIV I2C1SEL[1:0] CK_I2C1 clock source selection 00: CK_I2C1 select CK_APB1 01: CK_I2C1 select CK_SYS 10/11: CK_I2C1 select CK_IRC16MDIV I2C0SEL[1:0]...
Page 162: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32L23x User Manual CAUEN CAU clock enable This bit is set and reset by software. 0: Disabled CAU clock 1: Enabled CAU clock Reserved Must be kept at reset value. AHB2 reset register (RCU_AHB2RST) 4.3.15. Address offset: 0x38 Reset value: 0x0000 0000. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 163: Low Power Bandgap Mode Register (Rcu_Lpb)
GD32L23x User Manual KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] For GD32L233xx devices The key of RCU_LPB register These bits are written only by software and read as 0. Only after write 0x1A2B3C4D to the RCU_VKEY, the RCU_LPB registers can be written. For GD32L235xx devices The key of RCU_LPB register These bits are written only by software and read as 0.
Page 164 GD32L23x User Manual For GD32L235xx devices Offset: 0x12C Reset value: 0x0000 000F This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved LPBMSEL[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value LPBMSEL[3:0] Low power bandgap mode selection signal. This field can only be written only when right password is written to RCU_VKEY The length of holding phase of sample and hold circuit is controlled.
Page 165: Clock Trim Controller (Ctc)
GD32L23x User Manual Clock trim controller (CTC) Overview 5.1. The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. The CTC unit trim the frequency of the IRC48M based on an external accurate reference signal source. It can automatically adjust the trim value to provide a precise IRC48M clock.
Page 166: Ref Sync Pulse Generator
GD32L23x User Manual Figure 5-1. CTC overview PCLK1 APB1 BUS Register SWREFPUL Reserved GPIO (CTC_SYNC) Prescale (/1,/2,/4, ,/128) LXTAL Reserved REFPSC[2:0] REFSEL[1:0] REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 5.3.1.
Page 167: Frequency Evaluation And Automatically Trim Process
GD32L23x User Manual and then up-count to 128 x CKLIM (defined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 168: Software Program Guide
GD32L23x User Manual If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed. ◼ CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 169 GD32L23x User Manual The typical step size is 0.12%. Where the F is the frequency of correct clock (IRC48M), clock the F is the frequency of reference sync pulse.
Page 170: Register Definition
GD32L23x User Manual Register definition 5.4. CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 5.4.1. Address offset: 0x00 Reset value: 0x0000 4000 This register has to be accessed by word (32-bit). Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[6:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 171: Control Register 1 (Ctc_Ctl1)
GD32L23x User Manual 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim warning (CKWARNIF) interrupt enable 0: CKWARNIF interrupt disable...
Page 172: Status Register (Ctc_Stat)
GD32L23x User Manual 10: Reserved. 11: Reserved. Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4 011: Reference signal divided by 8 100: Reference signal divided by 16 101: Reference signal divided by 32...
Page 173 GD32L23x User Manual When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit. 0: Up-counting 1: Down-counting 14:11 Reserved Must be kept at reset value. TRIMERR Trim value error bit This bit is set by hardware when the TRIMVALUE in CTC_CTL0 register overflow or underflow.
Page 174: Interrupt Clear Register (Ctc_Intc)
GD32L23x User Manual 1: An error occur CKWARNIF Clock trim warning interrupt flag This bit is set by hardware when a clock trim warning occurred. If the CTC trim counter greater or equal to 3 x CKLIM and smaller to 128 x CKLIM when a reference sync pulse detected, this bit will be set.
Page 175 GD32L23x User Manual REFMISS and CKERR bits in CTC_STAT register. Write 0 is no effect. CKWARNIC CKWARNIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear CKWARNIF bit in CTC_STAT register. Write 0 is no effect. CKOKIC CKOKIF interrupt clear bit This bit is written by software and read as 0.
Page 176: Interrupt / Event Controller (Exti)
GD32L23x User Manual Interrupt / event controller (EXTI) 6.1. Overview Cortex -M23 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception ® and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the Technical Reference Manual of Cortex -M23 for more details about NVIC.
Page 177: Table 6-1. Nvic Exception Types In Cortex ® -M23
GD32L23x User Manual ® Table 6-1. NVIC exception types in Cortex -M23 Vector Exception type Priority (a) Vector address Description number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt HardFault 0x0000_000C All class of fault 0x0000_0010 – 4-10 Reserved 0x0000_002B System service call via SWI SVCall...
Page 178 GD32L23x User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ 22 TIMER2 global interrupt 0x0000_0098 IRQ 23 TIMER8 global interrupt 0x0000_009C IRQ 24 TIMER11 global interrupt 0x0000_00A0 IRQ 25 TIMER5 global interrupt 0x0000_00A4 IRQ 26 TIMER6 global interrupt 0x0000_00A8 IRQ 27 USART0 global interrupt...
Page 179: Table 6-3. Interrupt Vector Table For Gd32L235Xx Devices
GD32L23x User Manual Interrupt Vector Peripheral interrupt description Vector address number number IRQ 68 LPTIMER global interrupt 0x0000_0150 Table 6-3. Interrupt vector table for GD32L235xx devices Interrupt Vector Peripheral interrupt description Vector Address number number IRQ 0 WWDGT interrupt 0x0000_0040 IRQ 1 LVD from EXTI interrupt 0x0000_0044...
Page 180 GD32L23x User Manual Interrupt Vector Peripheral interrupt description Vector Address number number IRQ 35 SPI0 global interrupt 0x0000_00CC IRQ 36 SPI1 global interrupt 0x0000_00D0 IRQ 37 DAC interrupt 0x0000_00D4 IRQ 38 Reserved 0x0000_00D8 IRQ 39 I2C2 event interrupt 0x0000_00DC IRQ 40 I2C2 error interrupt 0x0000_00E0 IRQ 41...
Page 181: External Interrupt And Event Block Diagram
GD32L23x User Manual 6.4. External interrupt and event block diagram Figure 6-1. Block diagram of EXTI for GD32L233xx devices Polarity Software Control Trigger EXTI Line0~29 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control...
Page 182: External Interrupt And Event Function Overview
GD32L23x User Manual Figure 6-2. Block diagram of EXTI for GD32L235xx devices Polarity Software Control Trigger EXTI Line0~31 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control 6.5. External interrupt and Event function overview The EXTI contains up to 30 independent edge detectors (for GD32L233xx devices) or 32 independent edge detectors (for GD32L235xx devices) and generates interrupts request or event to the processer.
Page 183 GD32L23x User Manual Hardware trigger Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in SYSCFG module based on application requirement. Configure EXTI_RTEN and EXTI_FTEN to enable the rising or falling detection on related pins.
Page 184: Table 6-5. Exti Source For Gd32L235Xx Devices
GD32L23x User Manual EXTI line Source number USBD wakeup RTC Tamper and Timestamp RTC wakeup CMP0 output CMP1 output I2C0 wakeup I2C2 wakeup USART0 wakeup USART1 wakeup I2C1 wakeup LPUART wakeup LPTIMER wakeup Table 6-5. EXTI source for GD32L235xx devices EXTI line Source number...
Page 185 GD32L23x User Manual EXTI line Source number USART0 wakeup USART1 wakeup I2C1 wakeup LPUART0 wakeup LPTIMER0 wakeup LPUART1 wakeup LPTIMER1 wakeup...
Page 186: Register Definition
GD32L23x User Manual 6.6. Register definition EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 6.6.1. For GD32L233xx devices Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved INTEN29 INTEN28 INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8...
Page 187: Event Enable Register (Exti_Even)
GD32L23x User Manual Event enable register (EXTI_EVEN) 6.6.2. For GD32L233xx devices Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EVEN29 EVEN28 EVEN27 EVEN26 EVEN25 EVEN24 EVEN23 EVEN22 EVEN21 EVEN20 EVEN19 EVEN18 EVEN17 EVEN16 EVEN15...
Page 188: Rising Edge Trigger Enable Register (Exti_Rten)
GD32L23x User Manual Rising edge trigger enable register (EXTI_RTEN) 6.6.3. For GD32L233xx devices Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RTEN29 RTEN28 RTEN27 RTEN26 RTEN25 RTEN24 RTEN23 RTEN22 RTEN21 RTEN20 RTEN19 RTEN18 RTEN17...
Page 189: Falling Edge Trigger Enable Register (Exti_Ften)
GD32L23x User Manual Falling edge trigger enable register (EXTI_FTEN) 6.6.4. For GD32L233xx devices Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved FTEN29 FTEN28 FTEN27 FTEN26 FTEN25 FTEN24 FTEN23 FTEN22 FTEN21 FTEN20 FTEN19 FTEN18 FTEN17...
Page 190: Software Interrupt Event Register (Exti_Swiev)
GD32L23x User Manual Software interrupt event register (EXTI_SWIEV) 6.6.5. For GD32L233xx devices Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SWIEV29 SWIEV28 SWIEV27 SWIEV26 SWIEV25 SWIEV24 SWIEV23 SWIEV22 SWIEV21 SWIEV21 SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7...
Page 191: Pending Register (Exti_Pd)
GD32L23x User Manual Pending register (EXTI_PD) 6.6.6. For GD32L233xx devices Address offset: 0x14 Reset value: 0xXXXX XXXX where X is undefined. This register has to be accessed by word (32-bit). Reserved PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD21 PD19 PD19...
Page 192: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32L23x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 59 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0~PD6，PD8~PD9，PF0, PF1 for the device to implement logic input / output functions.
Page 193: Figure 7-1. Basic Structure Of A General-Pupose I/O
GD32L23x User Manual as floating (no pull-up and pull-down), pull-up or pull-down function by GPIO pull-up/pull-down registers (GPIOx_PUD). Table 7-1. GPIO configuration table PAD TYPE CTLy PUDy Floating GPIO pull-up INPUT pull-down Floating push-pull pull-up GPIO pull-down OUTPUT Floating open-drain pull-up pull-down Floating...
Page 194: Gpio Pin Configuration
GD32L23x User Manual GPIO pin configuration 7.3.1. During or just after the reset period, the alternative functions are all inactive and the GPIO ports are configured into the input floating mode that input disabled without Pull-Up(PU) / Pull- Down(PD) resistors. But the Serial-Wired Debug pins are in input PU / PD mode after reset: PA14: SWCLK in PD mode PA13: SWDIO in PU mode The GPIO pins can be configured as inputs or outputs.
Page 195: Output Configuration
GD32L23x User Manual ◼ The schmitt trigger input is enabled. ◼ The weak pull-up and pull-down resistors could be chosen. ◼ Every AHB clock cycle the data present on the I/O pin is got to the port input status register. ◼...
Page 196: Alternate Function (Af) Configuration
GD32L23x User Manual ◼ The weak pull-up and pull-down resistors are disabled. ◼ The output buffer is disabled. ◼ The schmitt trigger input is disabled. ◼ The port input status register of this I/O port bit is “0”. shows the analog configuration. Figure 7-4.
Page 197: Gpio Locking Function
GD32L23x User Manual GPIO locking function 7.3.9. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD and GPIOx_AFSELy (y=0, 1). It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK).
Page 198: Register Definition
GD32L23x User Manual 7.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOF base address: 0x4800 1400 Port control register (GPIOx_CTL, x=A..D,F) 7.4.1. Address offset: 0x00 Reset value: 0x2800 0000 for port A;...
Page 199: Port Output Mode Register (Gpiox_Omode, X=A
GD32L23x User Manual Refer to CTL0[1:0] description 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 15:14 CTL7[1:0] Pin 7 configuration bits...
Page 200 GD32L23x User Manual This register has to be accessed by word (32-bit) Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. OM15 Pin 15 output mode bit These bits are set and cleared by software. Refer to OM0 description OM14 Pin 14 output mode bit...
Page 201: Port Output Speed Register (Gpiox_Ospd, X=A
GD32L23x User Manual These bits are set and cleared by software. Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 3 output mode bit These bits are set and cleared by software.
Page 202 GD32L23x User Manual These bits are set and cleared by software. Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 25:24 OSPD12[1:0] Pin 12 output max speed bits These bits are set and cleared by software.
Page 203: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32L23x User Manual Refer to OSPD0[1:0] description OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits These bits are set and cleared by software. X0: Output max speed 2M (reset value) 01: Output max speed 10M 11: Output max speed 50M...
Page 204 GD32L23x User Manual These bits are set and cleared by software. Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 17:16 PUD8[1:0] Pin 8 pull-up or pull-down bits These bits are set and cleared by software.
Page 205: Port Input Status Register (Gpiox_Istat, X=A
GD32L23x User Manual Port input status register (GPIOx_ISTAT, x=A..D,F) 7.4.5. Address offset: 0x10 Reset value: 0x0000 XXXX This register has to be accessed by word (32-bit) Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3 ISTAT2 ISTAT1 ISTAT0...
Page 206: Port Configuration Lock Register (Gpiox_Lock, X=A
GD32L23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port clear bit y(y=0..15)
Page 207: Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
GD32L23x User Manual sequence. 15:0 Port lock bit y(y=0..15) These bits are set and cleared by software. 0: Port configuration not locked 1: Port configuration locked Alternate function selected register 0 (GPIOx_AFSEL0, x=A..D,F) 7.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) SEL7[3:0] SEL6[3:0]...
Page 208: Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
GD32L23x User Manual Refer to SEL0[3:0] description SEL0[3:0] Pin 0 alternate function selected These bits are set and cleared by software. 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected 0100: AF4 selected 0101: AF5 selected 0110: AF6 selected 0111: AF7 selected 1000: AF8 selected...
Page 209: Bit Clear Register (Gpiox_Bc, X=A
GD32L23x User Manual Refer to SEL8[3:0] description 15:12 SEL11[3:0] Pin 1 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description 11:8 SEL10[3:0] Pin 10 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description SEL9[3:0] Pin 9 alternate function selected...
Page 210: Port Bit Toggle Register (Gpiox_Tg, X=A
GD32L23x User Manual These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x=A..D,F) 7.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved TG15 TG14...
Page 211: Cyclic Redundancy Checks Management Unit (Crc)
GD32L23x User Manual Cyclic redundancy checks management unit (CRC) Overview 8.1. A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 7 / 8 / 16 / 32 bit CRC code within user configurable polynomial Characteristics 8.2.
Page 212: Function Overview
GD32L23x User Manual Figure 8-1. Block diagram of CRC calculation unit Data Input Input Data Register (32 bit) CRC Calculation Unit configurable polynomial Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) Function overview 8.3.
Page 213 GD32L23x User Manual 1) byte reverse: 32-bit data is divided into 4 groups and reverse implement in group inside. Reversed data: 0x2C6AB3F7 2) half-word reverse: 32-bit data is divided into 2 groups and reverse implement in group inside. Reversed data: 0x6A2CF7B3 3) word reverse: 32-bit data is divided into 1 groups and reverse implement in group inside.
Page 214: Register Definition
GD32L23x User Manual Register definition 8.4. CRC base address: 0x4002 3000 Data register (CRC_DATA) 8.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software writes and reads.
Page 215: Control Register (Crc_Ctl)
GD32L23x User Manual by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control register (CRC_CTL) 8.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved REV_O REV_I[1:0] PS[1:0] Reserved...
Page 216: Polynomial Register (Crc_Poly)
GD32L23x User Manual This register has to be accessed by word (32-bit). IDATA[31:16] IDATA[15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value. Polynomial register (CRC_POLY) 8.4.5.
Page 217: True Random Number Generator (Trng)
GD32L23x User Manual True random number generator (TRNG) Overview 9.1. The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. Characteristics 9.2. ◼ About 40 periods of TRNG_CLK are needed between two consecutive random numbers. ◼...
Page 218: Operation Flow
GD32L23x User Manual The 32-bit value of LFSR will transfer into TRNG_DATA register after a sufficient number of seeds have been sent to the LFSR. At the same time, the analog seed and TRNG_CLK clock are monitored. When an analog seed error or a clock error occurs, the corresponding status bit in TRNG_STAT will be set and an interrupt will generate if the IE bit in TRNG_CTL is set.
Page 219: Register Definition
GD32L23x User Manual Register definition 9.4. TRNG base address: 0x5006 0800 Control register (TRNG_CTL) 9.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved TRNGIE TRNGEN Reserved Bits Fields Descriptions Must be kept at reset value.
Page 220: Data Register (Trng_Data)
GD32L23x User Manual Must be kept at reset value. 31:7 Reserved SEIF Seed error interrupt flag This bit will be set if more than 64 consecutive same bit or more than 32 consecutive 01 (or 10) changing are detected. 0: No fault detected 1: Seed error has been detected.
Page 221 GD32L23x User Manual Bits Fields Descriptions 31:0 TRNGDATA[31:0] 32-bit random data...
Page 222: Cryptographic Acceleration Unit (Cau)
GD32L23x User Manual 10. Cryptographic Acceleration Unit (CAU) Overview 10.1. The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ◼...
Page 223: Cau Data Type And Initialization Vectors
GD32L23x User Manual and OFB modes. ◼ 8*32-bit input and output FIFO. ◼ Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping. ◼ Data can be transferred by DMA, CPU during interrupts, or without both of them. 10.3.
Page 224: Initialization Vectors
GD32L23x User Manual Figure 10-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping Initialization vectors 10.3.2. The initialization vectors are used in CBC, CTR, GCM, GMAC, CCM, CFB and OFB modes to XOR with data blocks.
Page 225: Des / Tdes Cryptographic Acceleration Processor
GD32L23x User Manual Figure 10-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_GCMCC CAU_GCM CAU_ CAU_ CAU_ CAU_ STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 MCTXS0...7 CTXS0...7 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Config 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core (DES / TDES / AES) DES / TDES cryptographic acceleration processor 10.4.1.
Page 226: Figure 10-4. Des / Tdes Ecb Encryption
GD32L23x User Manual DES / TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1.
Page 227: Figure 10-5. Des / Tdes Ecb Decryption
GD32L23x User Manual Figure 10-5. DES / TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES / TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors.
Page 228: Figure 10-6. Des / Tdes Cbc Encryption
GD32L23x User Manual Figure 10-6. DES / TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES / TDES CBC decryption In DES/TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3.
Page 229: Aes Cryptographic Acceleration Processor
GD32L23x User Manual Figure 10-7. DES / TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 10.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce.
Page 230: Figure 10-8. Aes Ecb Encryption
GD32L23x User Manual Figure 10-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption.
Page 231: Figure 10-9. Aes Ecb Decryption
GD32L23x User Manual Figure 10-9. AES ECB decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt SWAP CAU_DO Plaintext AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the AEA and encrypted using the 128-, 192-, 256-bit key.
Page 232: Figure 10-10. Aes Cbc Encryption
GD32L23x User Manual Figure 10-10. AES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0..1(H/L) CAU_KEY0..3 AEA, encrypt SWAP CAU_DO Ciphertext AES-CBC mode decryption Similar to that in AES-ECB mode decryption, the key derivation also must be completed first to prepare the decryption keys, the input of the key schedule should be the same to that used in encryption.
Page 233: Figure 10-11. Aes Cbc Decryption
GD32L23x User Manual Figure 10-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) SWAP CAU_DO Plaintext AES-CTR mode In counter mode, a counter is used in addition with a nonce value to be encrypted and decrypted in AEA, and the result will be used for the XOR operation with the plaintext or the ciphertext.
Page 234 GD32L23x User Manual Figure 10-13. AES CTR encryption/decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext AES-GCM mode The AES Galois/counter mode (GCM) can be used to encrypt or authenticate message, and then ciphertext and tag can be obtained. This algorithm is based on AES CTR mode to ensure confidentiality.
Page 235 GD32L23x User Manual Repeat (h) until all AAD data are supplied, wait until BUSY bit is cleared. 3. GCM encryption/decryption phase This phase must be performed after GCM AAD phase. In this phase, the message is authenticated and encrypted/decrypted. Configure GCM_CCMPH[1:0] bits to ‘10’. (k) Configure the computation direction in CAUDIR.
Page 236 GD32L23x User Manual 1. CCM prepare phase In this phase, B0 packet (the first packet) is programmed into the CAU_DI register. CAU_DO never contain data in this phase. (a) Clear the CAUEN bit to make sure CAU is disabled. (b) Configure the ALGM[3:0] bits to ‘1001’. (c) Configure GCM_CCMPH[1:0] bits to ‘00’.
Page 237: Operating Modes
GD32L23x User Manual AES-CFB mode The Cipher Feedback (CFB) mode is a confidentiality mode that features the feedback of successive ciphertext segments into the input blocks of the forward cipher to generate output blocks that are exclusive-Ored with the plaintext to produce the ciphertext, and vice versa. AES-OFB mode The Output Feedback (OFB) mode is a confidentiality mode that features the iteration of the forward cipher on an IV to generate a sequence of output blocks that are exclusive-Ored with...
Page 238: Cau Dma Interface
GD32L23x User Manual 6. Enable the CAU by set the CAUEN bit as 1. 7. Wait until the BUSY and CAUEN bit return to 0 to make sure that the decryption keys are prepared. 8. Configure the algorithm (DES / TDES / AES) and the chaining mode (ECB / CBC / CTR / GCM / GMAC / CCM / CFB / OFB) by writing the ALGM[3:0] bit in the CAU_CTL register.
Page 239: Cau Suspended Mode
GD32L23x User Manual Any of input and output FIFO interrupt can be enabled or disabled by configuring the Interrupt Enable register CAU_INTEN. Value 1 of the register enable the interrupts. Input FIFO interrupt The input FIFO interrupt is asserted when the number of words in the input FIFO is less than four words, then ISTA is asserted.
Page 240 GD32L23x User Manual CAU_DO register and before the next CAU_DI write access so that the message is suspended at the end of a block processing. 2. Disable the CAU by clearing the CAUEN bit in the CAU_CTL register. 3. Save the configuration, including the key size, data type, operation mode, direction, GCM CCM phase and the key values.
Page 241: Register Definition
GD32L23x User Manual 10.9. Register definition CAU access base address: 0x5006 0000 Control register (CAU_CTL) 10.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved NBPILB[3:0] ALGM[3] Reserved GCM_CCMPH[1:0] CAUEN FFLUSH Reserved KEYM[1:0] DATAM[1:0] ALGM[2:0]...
Page 242 GD32L23x User Manual 13:10 Reserved Must be kept at reset value. KEYM[1:0] AES key size mode configuration, must be configured when BUSY=0 00: 128-bit key length 01: 192-bit key length 10: 256-bit key length 11: never use DATAM[1:0] Data swapping type mode configuration, must be configured when BUSY=0 00: No swapping 01: Half-word swapping 10: Byte swapping...
Page 243: Status Register 0 (Cau_Stat0)
GD32L23x User Manual Status register 0 (CAU_STAT0) 10.9.2. Address offset: 0x04 Reset value: 0x0000 0003 This register has to be accessed by word (32-bit). Reserved Reserved BUSY Bits Fields Descriptions 31:5 Reserved Must be kept at reset value. BUSY Busy bit 0: No processing.
Page 244: Data Output Register (Cau_Do)
GD32L23x User Manual out and returned. If the CAUEN is 1, the returned value is undefined. Once it is read, then the FIFO must be flushed. This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Data input...
Page 245: Interrupt Enable Register (Cau_Inten)
GD32L23x User Manual Reserved DMAOEN DMAIEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. DMAOEN DMA output enable 0: DMA for OUT FIFO data is disabled 1: DMA for OUT FIFO data is enabled DMAIEN DMA input enable 0: DMA for IN FIFO data is disabled 1: DMA for IN FIFO data is enabled Interrupt enable register (CAU_INTEN)
Page 246: Interrupt Flag Register (Cau_Intf)
GD32L23x User Manual Reserved Reserved OSTA ISTA Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. OSTA OUT FIFO interrupt status 0: OUT FIFO interrupt status not pending 1: OUT FIFO interrupt status pending ISTA IN FIFO interrupt status 0: IN FIFO interrupt not pending 1: IN FIFO interrupt flag pending Interrupt flag register (CAU_INTF)
Page 247 GD32L23x User Manual This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0. In DES mode, only CAU_KEY1 is used. In TDES mode, CAU_KEY1, CAU_KEY2 and CAU_KEY3 are used. In AES-128 mode, KEY2H[31:0] || KEY2L[31:0] is used as AES_KEY[0:63], and KEY3H[31:0] || KEY3L[31:0] is used as AES_KEY[64:127].
Page 248 GD32L23x User Manual KEY1H[31:16] KEY1H[15:0] CAU_KEY1L Address offset: 0x2C Reset value: 0x0000 0000 KEY1L[31:16] KEY1L[15:0] CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0] CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000...
Page 249: Initial Vector Registers (Cau_Iv0
GD32L23x User Manual KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000 KEY3L[31:16] KEY3L[15:0] Bits Fields Descriptions KEY0...3(H / L) The key for DES, TDES, AES 31:0 Initial vector registers (CAU_IV0..1(H/L)) 10.9.10. Address offset: 0x40 to 0x4C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0.
Page 250: Gcm Or Ccm Mode Context Switch Register X (Cau_Gcmccmctxsx) (X=0
GD32L23x User Manual CAU_IV0L Address offset: 0x44 Reset value: 0x0000 0000 IV0L[31:16] IV0L[15:0] CAU_IV1H Address offset: 0x48 Reset value: 0x0000 0000 IV1H[31:16] IV1H[15:0] CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000 IV1L[31:16] IV1L[15:0] Bits Fields Descriptions IV0...1(H / L) The initialization vector for DES, TDES, AES 31:0 GCM or CCM mode context switch register x (CAU_GCMCCMCTXSx) 10.9.11.
Page 251: Gcm Mode Context Switch Register X (Cau_Gcmctxsx) (X=0
GD32L23x User Manual CTXx[31:16] CTXx[15:0] Bits Fields Descriptions 31:0 CTXx[31:0] The internal status of the CAU core. Read and save the register data when a high- priority task is coming to be processed, and restore the saved data back to the registers to resume the suspended processing.
Page 252: Direct Memory Access Controller (Dma)
GD32L23x User Manual Direct memory access controller (DMA) 11.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and / or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 253: Block Diagram
GD32L23x User Manual 11.3. Block diagram Figure 11-1. Block diagram of DMA AHB slave interface Configuration … dma_req Channel 6 dma_ack master interface Channel 2 dma_req Master dma_ack Port Channel 1 dma_req dma_ack Channel 0 dma_req dma_ack Memory control state & counter management Peripheral control Arbiter...
Page 254: Table 11-1. Dma Transfer Operation
GD32L23x User Manual Table 11-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 255: Peripheral Handshake
GD32L23x User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register. ◼ If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 256: Address Generation
GD32L23x User Manual ◼ Software priority: Four levels, including low, medium, high and ultra-high by configuring the PRIO bits in the DMA_CHxCTL register. ◼ For channels with equal software priority level, priority is given to the channel with lower channel number. Address generation 11.4.4.
Page 257: Interrupt
GD32L23x User Manual 5. Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register. 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register. 7.
Page 258: Dma Request Mapping
GD32L23x User Manual DMA request mapping 11.4.9. The DMA requests of a channel are coming from the AHB / APB peripherals through the corresponding channel output of DMAMUX request multiplexer, refers to Table 12-2. Request multiplexer input mapping.
Page 259: Register Definition
GD32L23x User Manual 11.5. Register definition DMA base address: 0x4002 0000 Interrupt flag register (DMA_INTF) 11.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ERRIF6 HTFIF6 FTFIF6 GIF6 ERRIF5 HTFIF5 FTFIF5 GIF5 ERRIF4 HTFIF4...
Page 260: Channel X Control Register (Dma_Chxctl)
GD32L23x User Manual Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0 Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 27 / 23 / 19 / ERRIFCx Clear bit for error flag of channel x (x = 0…6)
Page 261 GD32L23x User Manual 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’. 11:10 MWIDTH[1:0] Transfer data size of memory...
Page 262: Channel X Counter Register (Dma_Chxcnt)
GD32L23x User Manual 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Software set and cleared 0: Disable the channel error interrupt 1: Enable the channel error interrupt HTFIE...
Page 263: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32L23x User Manual transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode. Channel x peripheral base address register (DMA_CHxPADDR) 11.5.5. x = 0...6, where x is a channel number Address offset: 0x10 + 0x14 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 264 GD32L23x User Manual When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these bits are ignored. Access is automatically aligned to a word address.
Page 265: Dma Request Multiplexer (Dmamux)
GD32L23x User Manual DMA request multiplexer (DMAMUX) 12.1. Overview DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer is used for routing a DMA request line between the peripherals / generated DMA request (from the DMAMUX request generator) and the DMA controller. Each DMAMUX request multiplexer channel selects a unique DMA request line, unconditionally or synchronously with events from its DMAMUX synchronization inputs.
Page 266: Block Diagram
GD32L23x User Manual 12.3. Block diagram Figure 12-1. Block diagram of DMAMUX Request multiplexer Slave Port Channel 6 Channel 2 … … Channel 1 Peri_reqx To DMA controller: … Channel 0 Reqx_out … … Sync Counter underrun: Reqx_in … Evtx_out Configuration Register …...
Page 267: Function Overview
GD32L23x User Manual 12.5. Function overview As shown in Figure 12-1. Block diagram of DMAMUX, DMAMUX includes two sub-blocks: ◼ DMAMUX request multiplexer. DMAMUX request multiplexer inputs (Reqx_in) source from: – Peripherals (Peri_reqx). – DMAMUX request generator outputs (Gen_reqx). DMAMUX request multiplexer outputs (Reqx_out) is connected to channels of DMA controller.
Page 268: Figure 12-2. Synchronization Mode
GD32L23x User Manual Note: The NBR[4:0] bits value shall only be written by software when both synchronization enable bit SYNCEN and event generation enable EVGEN bit of the corresponding request multiplexer channel x are disabled. When synchronization mode is enabled A channel x in synchronization mode, when a rising/falling edge on the selected synchronization input is detected, the pending selected input DMA request line is routed to the multiplexer channel x output.
Page 269: Figure 12-3. Event Generation
GD32L23x User Manual be routed to the DMAMUX multiplexer channel output until a synchronization input event occurs again. Channel event generation Each DMA request line multiplexer channel has an event output called Evtx_out, which is the DMA request multiplexer counter underrun event. Signals Evt0_out ~ Evt3_out can be used for DMA request chaining.
Page 270: Dmamux Request Generator
GD32L23x User Manual DMAMUX request generator 12.5.2. The DMAMUX request generator produces DMA requests upon trigger input event. Its component unit is the request generator channels. DMA request trigger inputs are connected in parallel to all request generator channels. And there is a built-in DMAMUX request generator counter for each request generator channel.
Page 271: Interrupt
GD32L23x User Manual Set and configure the DMA channel x completely, except enabling the channel x. Set and configure the related DMAMUX channel y completely. Configure the CHEN bit with ‘1’ in the DMA_CHxCTL register to enable the DMA channel Interrupt 12.5.4.
Page 272 GD32L23x User Manual MUXID[6:0] bits in the DMAMUX_RM_CHxCFG register for the DMAMUX request multiplexer channel x. Table 12-2. Request multiplexer input mapping for GD32L233x Request multiplexer channel input identification Source MUXID[5:0] Gen_req0 Gen_req1 Gen_req2 Gen_req3 Reserved Reserved Reserved I2C0_RX I2C0_TX I2C1_RX I2C1_TX I2C2_RX...
Page 273: Table 12-3. Request Multiplexer Input Mapping For Gd32L235Xx
GD32L23x User Manual Request multiplexer channel input identification Source MUXID[5:0] TIMER2_UP Reserved Reserved Reserved Reserved TIMER5_UP TIMER6_UP CAU_IN CAU_OUT Reserved Reserved Reserved Reserved USART0_RX USART0_TX USART1_RX USART1_TX UART3_RX UART3_TX UART4_RX UART4_TX LPUART_RX LPUART_TX Reserved Reserved Reserved Reserved Table 12-3. Request multiplexer input mapping for GD32L235xx Request multiplexer channel input identification Source...
Page 274 GD32L23x User Manual Request multiplexer channel input identification Source MUXID[6:0] Reserved I2C0_RX I2C0_TX I2C1_RX I2C1_TX I2C2_RX I2C2_TX SPI0_RX SPI0_TX SPI1_RX SPI1_TX Reserved Reserved Reserved Reserved Reserved TIMER1_CH0 TIMER1_CH1 TIMER1_CH2 TIMER1_CH3 TIMER1_TRIG TIMER1_UP Reserved TIMER2_CH0 TIMER2_CH1 TIMER2_CH2 TIMER2_CH3 TIMER2_TRIG TIMER2_UP Reserved Reserved Reserved Reserved...
Page 275 GD32L23x User Manual Request multiplexer channel input identification Source MUXID[6:0] Reserved Reserved USART0_RX USART0_TX USART1_RX USART1_TX UART3_RX UART3_TX UART4_RX UART4_TX LPUART0_RX LPUART0_TX LPUART1_RX LPUART1_TX Reserved Reserved TIMER0_CH0 TIMER0_CH1 TIMER0_CH2 TIMER0_CH3 TIMER0_TRIG TIMER0_UP TIMER0_COM TIMER14_CH0 TIMER14_CH1 TIMER14_TRIG TIMER14_UP TIMER14_COM TIMER40_CH0 TIMER40_CH1 TIMER40_TRIG TIMER40_UP TIMER40_COM...
Page 276: Table 12-4. Trigger Input Mapping
GD32L23x User Manual Table 12-4. Trigger input mapping Trigger input identification Source TID[4:0] EXTI_0 EXTI_1 EXTI_2 EXTI_3 EXTI_4 EXTI_5 EXTI_6 EXTI_7 EXTI_8 EXTI_9 EXTI_10 EXTI_11 EXTI_12 EXTI_13 EXTI_14 EXTI_15 Evt0_out Evt1_out Evt2_out Evt3_out Reserved Reserved TIMER11_CH0_O Reserved Synchronization input mapping The synchronization input is selected by SYNCID[4:0] bits in the DMAMUX_RM_CHxCFG register, the sources can refer to Table 12-5.
Page 277 GD32L23x User Manual Synchronization input Source identification SYNCID[4:0] EXTI_7 EXTI_8 EXTI_9 EXTI_10 EXTI_11 EXTI_12 EXTI_13 EXTI_14 EXTI_15 Evt0_out Evt1_out Evt2_out Evt3_out Reserved Reserved TIMER11_CH0_O Reserved...
Page 278: Register Definition
GD32L23x User Manual 12.6. Register definition DMAMUX base address: 0x4002 0800 Request multiplexer channel configuration register 12.6.1. (DMAMUX_RM_CHxCFG) For GD32L233xx devices x = 0...6, where x is a channel number Address offset: 0x00 + 0x04 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 279 GD32L23x User Manual EVGEN Event generation enable 0: Disable event generation 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt Reserved Must be kept at reset value. MUXID[5:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources. For GD32L235xx devices x = 0...6, where x is a channel number Address offset: 0x00 + 0x04 * x...
Page 280: Request Multiplexer Channel Interrupt Flag Register (Dmamux_Rm_Intf)
GD32L23x User Manual 1: Enable synchronization 15:10 Reserved Must be kept at reset value. EVGEN Event generation enable 0: Disable event generation 1: Enable event generation SOIE Synchronization overrun interrupt enable 0: Disable interrupt 1: Enable interrupt Reserved Must be kept at reset value. MUXID[6:0] Multiplexer input identification Selects the input DMA request in multiplexer input sources.
Page 281: Request Multiplexer Channel Interrupt Flag Clear Register (Dmamux_Rm_Intc)
GD32L23x User Manual Refers to SOIF0 descriptions. SOIF0 Synchronization overrun event flag of request multiplexer channel 0 If a synchronization event occurs when the DMAMUX request counter value is lower than NBR[4:0], the flag is set. It is cleared by writing 1 to the corresponding SOIFC0 bit in DMAMUX_RM_INTC register.
Page 282: Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
GD32L23x User Manual Request generator channel configuration register 12.6.4. (DMAMUX_RG_CHxCFG) x = 0...3, where x is a channel number Address offset: 0x100 + 0x04 * x Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved NBRG[4:0] RGTP[1:0] RGEN...
Page 283: Request Generator Channel Interrupt Flag Register (Dmamux_Rg_Intf)
GD32L23x User Manual Request generator channel interrupt flag register (DMAMUX_RG_INTF) 12.6.5. Address offset: 0x140 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved TOIF3 TOIF2 TOIF1 TOIF0 Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. TOIF3 Trigger overrun event flag of request generator channel 3 Refers to TOIF0 descriptions.
Page 284 GD32L23x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. TOIFC3 Clear bit for trigger overrun event flag of request generator channel 3 Refers to TOIFC0 descriptions. TOIFC2 Clear bit for trigger overrun event flag of request generator channel 2 Refers to TOIFC0 descriptions.
Page 285: Debug (Dbg)
GD32L23x User Manual Debug (DBG) 13.1. Overview The GD32L23x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M23.
Page 286: Debug Support For Timer, Lptimer, I2C, Rtc, Wwdgt And Fwdgt
GD32L23x User Manual deep-sleep mode, the clock of AHB bus and system clock are provided by CK_IRC16M, and the debugger can debug in deep-sleep mode. When the SLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set, and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode.
Page 287: Register Definition
GD32L23x User Manual 13.4. Register definition DBG base address: 0x4001 5800 ID code register (DBG_ID) 13.4.1. Address offset: 0x00 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by software.
Page 288 GD32L23x User Manual TIMER8_HOLD TIMER 8 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER 8 counter for debugging when the core is halted. Reserved Must be kept at reset value. TIMER6_HOLD TIMER 6 hold bit This bit is set and reset by software.
Page 289 GD32L23x User Manual FWDGT_HOLD FWDGT hold bit This bit is set and reset by software. 0: no effect 1: hold the FWDGT counter clock for debugging when the core is halted. Reserved Must be kept at reset value. STB_HOLD Standby mode hold bit This bit is set and reset by software.
Page 290 GD32L23x User Manual 1: hold the TIMER 14 counter for debugging when the core is halted. TIMER11_HOLD TIMER 11 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER 11 counter for debugging when the core is halted. 25:24 Reserved Must be kept at reset value.
Page 291: Control Register 1 (Dbg_Ctl1)
GD32L23x User Manual This bit is set and reset by software. 0: no effect 1: hold the TIMER 1 counter for debugging when the core is halted. TIMER0_HOLD TIMER 0 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER 0 counter for debugging when the core is halted.
Page 292 GD32L23x User Manual I2C2_HO LPTIMER Reserved. _HOLD RTC_HO Reserved Reserved Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. I2C2_HOLD I2C2 hold bit This bit is set and reset by software. 0: no effect 1: hold the I2C2 status to avoid SMBUS timeout for debugging when the core is halted.
Page 293 GD32L23x User Manual 0: no effect 1: hold the LPTIMER1 counter for debugging when the core is halted. I2C2_HOLD I2C2 hold bit This bit is set and reset by software. 0: no effect 1: hold the I2C2 status to avoid SMBUS timeout for debugging when the core is halted.
Page 294: Analog To Digital Converter (Adc)
GD32L23x User Manual Analog to digital converter (ADC) 14.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 4 internal channels. The 20 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment or the most significant bit alignment.
Page 295: Pins And Internal Signals
GD32L23x User Manual 16-bit data register. Oversampling ratio adjustable from 2x to 256x. Programmable data shift up to 8-bits. ◼ Channel input range: V ≤ V ≤ V 14.3. Pins and internal signals Figure 14-1. ADC module block diagram Table 14-1. ADC shows the ADC block diagram.
Page 296: Function Overview
GD32L23x User Manual 14.4. Function overview Figure 14-1. ADC module block diagram Trig select DMA request Routine channel Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO ADC_IN15 Over routine data registers SAR ADC 6~12-bit sampler （16 bits） SENSE REFINT SLCD...
Page 297: Dual Clock Domain Architecture
GD32L23x User Manual Delay 14 CK_ADC to wait for ADC stability. Set RSTCLB (optional). Set CLB=1. Wait for CLB =0. Dual clock domain architecture 14.4.2. The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock, which can be asynchronous and independent from the APB clock.
Page 298: Routine Sequence
GD32L23x User Manual When V is V and V is V , The conversion result of channel n is 0x0000; REFN IN(n+1) REFP When V is V / 2 and V is V / 2, the conversion result of channel n is REFP IN(n+1) REFP...
Page 299: Figure 14-3. Continuous Operation Mode
GD32L23x User Manual Read the converted data from the ADC_RDATA register. Clear the EOC flag by writing 0. Continuous operation mode The continuous operation mode will be enabled when the CTN bit in the ADC_CTL1 register is set. In this mode, the ADC performs conversion on the channel specified in the RSQ0[4:0]. When the ADCON has been set high, the ADC samples and converts specified channel, once the corresponding software trigger or external trigger is active.
Page 300: Figure 14-4. Scan Operation Mode, Continuous Disable
GD32L23x User Manual bit in ADC_CTL1 register must be set when the routine sequence works in scan mode. After conversion of a routine sequence, the conversion can be restarted automatically if the CTN bit in the ADC_CTL1 register is set. Figure 14-4.
Page 301: Conversion Result Threshold Monitor Function
GD32L23x User Manual Figure 14-6. Discontinuous operation mode CH11 CH16 CH12 CH17 · · · Routine trigger One circle of routine sequence, RL=7, DISNUM=2 Convert Sample Software procedure for discontinuous operation mode on a routine sequence: Set the DISRC bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1 register; Configure the DISNUM [2:0] bits in the ADC_CTL0 register;...
Page 302: Sample Time Configuration
GD32L23x User Manual Figure 14-7. Data storage mode of 12-bit resolution Figure 14-8. Data storage mode of 10-bit resolution Figure 14-9. Data storage mode of 8-bit resolution Figure 14-10. Data storage mode of 6-bit resolution Routine channel data DAL=0 Routine channel data DAL=1 Sample time configuration 14.4.9.
Page 303: External Trigger Configuration
GD32L23x User Manual conversion time is “sampling time + 12.5” CK_ADC cycles. Example: CK_ADC = 16MHz and sampling time is 2.5 cycles, the total conversion time is “2.5+12.5” CK_ADC cycles, that means 0.9375us. External trigger configuration 14.4.10. The conversion of routine sequence can be triggered by rising edge of external trigger inputs. The external trigger source of routine sequence is controlled by the ETSRC [2:0] bits in the ADC_CTL1 register.
Page 304: Battery Voltage Monitoring
GD32L23x User Manual different on chip to chip (refer to the device datasheet for more information). To use the temperature sensor: Configure the ADC clock (not greater than 5MHz). Configure the conversion sequence (ADC_IN16) and the sampling time (t ) for the s_temp channel.
Page 305: Slcd Voltage Monitoring
GD32L23x User Manual will be enabled only when it is required. SLCD voltage monitoring 14.4.14. The V channel can be used to measure the voltage on the V pin. When the VSLCDEN SLCD SLCD bit in ADC_CTL1 register is set, V channel (ADC_IN19) is enabled and abridge divider by SLCD 3 integrated on the V...
Page 306: Figure 14-12. A Numerical Example With 5-Bit Shifting And Rounding
GD32L23x User Manual Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. Figure 14-12. A numerical example with 5-bit shifting and rounding shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 14-12.
Page 307: Programmable Resolution (Dres)
GD32L23x User Manual Oversampling work with ADC modes Most of the ADC work modes are available when oversampling is enabled. ◼ Routine sequence. ◼ ADC started by software or external triggers. ◼ Single or scan, continuous or discontinuous operation modes. ◼...
Page 308: Register Definition
GD32L23x User Manual 14.5. Register definition ADC base address: 0x4001 2400 Status register (ADC_STAT) 14.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Reserved STRC rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:5 Reserved...
Page 309 GD32L23x User Manual This register has to be accessed by word (32-bit). Reserved DRES [1:0] RWDEN Reserved Reserved Reserved Reserved DISNUM [2:0] DISRC WDSC WDEIE EOCIE WDCHSEL [4:0] Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. 25:24 DRES[1:0] ADC resolution 00: 12bit...
Page 310: Control Register 1 (Adc_Ctl1)
GD32L23x User Manual EOCIE Interrupt enable for EOC 0: Interrupt disable 1: Interrupt enable WDCHSEL[4:0] Analog watchdog channel select 00000: ADC channel 0 00001: ADC channel 1 00010: ADC channel 2 …… 10000: ADC channel16 10001: ADC channel17 10010: ADC channel18 10011: ADC channel19 Other values are reserved.
Page 311 GD32L23x User Manual 0: Channel 17 of ADC disable 1: Channel 17 of ADC enable TSVEN Channel 16 (temperature sensor) enable of ADC. 0: Channel 16 of ADC disable 1: Channel 16 of ADC enable SWRCST Software start conversion of routine sequence. Set 1 on this bit starts the conversion of a routine sequence if ETSRC is 111.
Page 312 GD32L23x User Manual 1: Calibration start Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC will be waked up when this bit is changed from low to high and take a stabilization time. When this bit is high and “1” is written to it with other bits of this register unchanged, the conversion will start.
Page 313 GD32L23x User Manual Reserved Must be kept at reset value.. ETERC External trigger enable for routine sequence 0: External trigger for routine sequence disable 1: External trigger for routine sequence enable 19:17 ETSRC[2:0] External trigger select for routine sequence 000: TIMER8 CH0 001: TIMER8 CH1 010: TIMER0_CH2 011: TIMER1 CH1...
Page 314: Sample Time Register 0 (Adc_Sampt0)
GD32L23x User Manual 1: Calibration start Continuous mode 0: Continuous operation mode disable 1: Continuous operation mode enable ADCON ADC ON. The ADC will be waked up when this bit is changed from low to high and take a stabilization time. When this bit is high and “1” is written to it with other bits of this register unchanged, the conversion will start.
Page 315: Sample Time Register 1 (Adc_Sampt1)
GD32L23x User Manual 011: channel sampling time is 28.5 cycles 100: channel sampling time is 41.5 cycles 101: channel sampling time is 55.5 cycles 110: channel sampling time is 71.5 cycles 111: channel sampling time is 239.5 cycles Sample time register 1 (ADC_SAMPT1) 14.5.5.
Page 316: Watchdog High Threshold Register (Adc_Wdht)
GD32L23x User Manual 111: channel sampling time is 239.5 cycles Watchdog high threshold register (ADC_WDHT) 14.5.6. Address offset: 0x24 Reset value: 0x0000 0FFF This register has to be accessed by word(32-bit). Reserved Reserved WDHT [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value.
Page 317: Routine Sequence Register 1 (Adc_Rsq1)
GD32L23x User Manual This register has to be accessed by word (32-bit). Reserved RL [3:0] RSQ15[4:1] RSQ15[0] RSQ14[4:0] RSQ13[4:0] RSQ12[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 RL[3:0] Routine sequence length The total number of conversion in routine sequence equals to RL[3:0] +1. 19:15 RSQ15[4:0] Refer to RSQ0[4:0] description...
Page 318: Routine Sequence Register 2 (Adc_Rsq2)
GD32L23x User Manual Routine sequence register 2 (ADC_RSQ2) 14.5.10. Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RSQ5[4:0] RSQ4[4:0] RSQ3[4:1] RSQ3[0] RSQ2[4:0] RSQ1[4:0] RSQ0[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ5[4:0] Refer to RSQ0[4:0] description...
Page 319: Oversampling Control Register (Adc_Ovsampctl)
GD32L23x User Manual Oversampling control register (ADC_OVSAMPCTL) 14.5.12. Address offset: 0x80 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved TOVS OVSS[3:0] OVSR[2:0] Reserved OVSEN Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software.
Page 320: Charge Control Register (Adc_Cctl)
GD32L23x User Manual 101: 64x 110: 128x 111: 256x Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress). Reserved Must be kept at reset value. OVSEN Oversampling enable This bit is set and cleared by software.
Page 321: Differential Mode Control Register (Adc_Difctl)
GD32L23x User Manual Differential mode control register (ADC_DIFCTL) 14.5.14. Only for GD32L235xx devices Address offset: 0xC4 Reset value: 0x00000000 This register has to be accessed by word(32-bit). Reserved DIFCTL[19:16] DIFCTL DIFCTL[14:0] [15] Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:15 DIFCTL[19:15] Differential mode for channel 19..15.
Page 322: Digital-To-Analog Converter (Dac)
GD32L23x User Manual Digital-to-analog converter (DAC) Overview 15.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured to 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 323: Function Overview
GD32L23x User Manual Table 15-1. DAC I/O description Name Description Signal type Analog power supply Input, analog supply Ground for analog power supply Input, analog supply ground Positive reference voltage of DAC Input, analog positive reference REFP DACy_OUTx DAC analog output Analog output signal The below table details the triggers and outputs of the DAC.
Page 324: Dac Data Configuration
GD32L23x User Manual DAC data configuration 15.3.3. The 12-bit DAC holding data (OUTx_DH) can be configured by writing any one of the OUTx_R12DH, OUTx_L12DH and OUTx_R8DH registers. When the data is loaded by OUTx_R8DH register, only the MSB 8 bits are configurable, the LSB 4 bits are forced to 4’b0000.
Page 325: Dac Output Voltage
GD32L23x User Manual LFSR noise wave mode: there is a Linear Feedback Shift Register (LFSR) in the DAC control logic, it controls the LFSR noise signal which is added to the OUTx_DH value, and then the result is stored into the OUTx_DO register When the configured DAC noise wave bit width is less than 12, the noise signal equals to the LSB DWBWx bits of the LFSR register, while the MSB bits are masked.
Page 326: Dma Request
GD32L23x User Manual DMA request 15.3.8. When the external trigger is enabled, the DMA request is enabled by setting the DDMAENx bit of the DAC_CTL0 register. A DMA request will be generated when an external hardware trigger (not a software trigger) occurs. If the second external trigger arrives before confirming the previous request, the new request will not be serviced, and an underrun error event occurs.
Page 327: Register Definition
GD32L23x User Manual Register definition 15.4. DAC0 base address: 0x4000 7400 DACx control register 0 (DAC_CTL0) 15.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DDUDR DDMA Reserved DDISC0 DWBW0[3:0] DWM0[1:0] DTSEL0[2:0] DTEN0 DBOFF0...
Page 328: Dacx Software Trigger Register (Dac_Swt)
GD32L23x User Manual 0111: The bit width of the wave signal is 8 1000: The bit width of the wave signal is 9 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DACx_OUT0 noise wave mode...
Page 329: Dacx_Out0 12-Bit Right-Aligned Data Holding Register (Dac_Out0_R12Dh)
GD32L23x User Manual Reserved Reserved SWTR0 Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. SWTR0 DACx_OUT0 software trigger, cleared by hardware. 0: Software trigger disabled 1: Software trigger enabled DACx_OUT0 12-bit right-aligned data holding register 15.4.3. (DAC_OUT0_R12DH) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 330: Dacx_Out0 8-Bit Right-Aligned Data Holding Register (Dac_Out0_R8Dh)
GD32L23x User Manual OUT0_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 OUT0_DH[11:0] DACx_OUT0 12-bit left-aligned data. These bits specify the data that is to be converted by DACx_OUT0. Reserved Must be kept at reset value. DACx_OUT0 8-bit right-aligned data holding register (DAC_OUT0_R8DH) 15.4.5.
Page 331: Dacx Status Register 0 (Dac_Stat0)
GD32L23x User Manual 31:12 Reserved Must be kept at reset value. 11:0 OUT0_DO [11:0] DACx_OUT0 12-bit output data These bits, which are read only, storage the data that is being converted by DACx_OUT0. DACx status register 0 (DAC_STAT0) 15.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved...
Page 332: Watchdog Timer (Wdgt)
GD32L23x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 333: Figure 16-1. Free Watchdog Block Diagram
GD32L23x User Manual Figure 16-1. Free watchdog block diagram Status: PUD 12-Bit Reset IRC32K Prescaler DownCounter /4/8…256 Reload Control register Reload Status: RUD register The free watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then counter starts counting down. When the counter reaches the value (0x000), there will be a reset.
Page 334: Table 16-1. Min/Max Fwdgt Timeout Period At 32Khz (Irc32K)
GD32L23x User Manual Table 16-1. Min/max FWDGT timeout period at 32KHz (IRC32K) Min timeout (ms) RL[11:0]= Max timeout (ms) RL[11:0]= Prescaler divider PSC[2:0] bits 0x000 0xFFF 0.03125 511.90625 0.03125 1023.78125 1/16 0.03125 2047.53125 1/32 0.03125 4095.03125 1/64 0.03125 8190.03125 1/128 0.03125 16380.03125 1/256...
Page 335: Register Definition
GD32L23x User Manual Register definition 16.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 336 GD32L23x User Manual FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 /4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit has been reset before changing the prescaler value.
Page 337 GD32L23x User Manual Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. Watchdog counter window value update. When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 338 GD32L23x User Manual writing these bits. If several window values are used by the application, it is mandatory to wait until WUD bit has been reset before changing the window value. However, after updating the window value it is not necessary to wait until WUD is reset before continuing code execution except in case of low-power mode entry(Before entering low-power mode, it is necessary to wait until WUD is reset).
Page 339: Window Watchdog Timer (Wwdgt)
GD32L23x User Manual 16.2. Window watchdog timer (WWDGT) Overview 16.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 340: Figure 16-3. Window Watchdog Timing Diagram
GD32L23x User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F(it implies that the CNT[6] bit should be set).
Page 341: Table 16-2. Min-Max Timeout Value At 64 Mhz
GD32L23x User Manual Table 16-2. Min-max timeout value at 64 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[3:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 1 / 1 0000 64μs 4.096ms 1 / 2 0001 128μs 8.192ms 1 / 4 0010 256μs 16.384ms...
Page 342: Register Definition
GD32L23x User Manual Register definition 16.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. WDGTEN Start the Window watchdog timer.
Page 343 GD32L23x User Manual 0000: (PCLK1 / 4096) / 1 0001: (PCLK1 / 4096) / 2 0010: (PCLK1 / 4096) / 4 0011: (PCLK1 / 4096) / 8 0100: (PCLK1 / 4096) / 16 0101: (PCLK1 / 4096) / 32 0110: (PCLK1 / 4096) / 64 0111: (PCLK1 / 4096) / 128 1000: (PCLK1 / 4096) / 256 1001: (PCLK1 / 4096) / 512...
Page 344 GD32L23x User Manual hardware even the interrupt is not enabled (EWIE in WWDGT_CFG is cleared). This bit is cleared by writing 0. There is no effect when writing 1.
Page 345: Real Time Clock (Rtc)
GD32L23x User Manual Real time clock (RTC) 17.1. Overview The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. Working in power saving mode and smart wakeup is software configurable.
Page 346: Function Overview
GD32L23x User Manual 17.3. Function overview Block diagram 17.3.1. Figure 17-1. Block diagram of RTC ALARM 1 Alarm-1 Flag ALARM 0 Alarm-0 Flag Alarm-0/1 Logic Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_apre (Default 256 Hz) ck_spre (Default 1 Hz) IRC32K 7-bit...
Page 347: Clock Source And Prescalers
GD32L23x User Manual Clock source and prescalers 17.3.2. RTC unit has three independent clock sources: LXTAL, IRC32K and HXTAL with divided by 32(configured in RCU_CFG register). In the RTC unit, there are two prescalers used for implementing the calendar and other functions.
Page 348: Configurable Periodic Auto-Wakeup Counter
GD32L23x User Manual masked, the Alarm Flag will assert 3 RTC clock later after ALRMxEN(x=0,1) is set. Configurable periodic auto-wakeup counter 17.3.5. In the RTC block, there is a 16-bit down counter designed to generate periodic wakeup flag. This function is enabled by set the WTEN to 1 and can be running in power saving mode. Two clock sources can be chose for the down counter: 1) RTC clock divided by 2/4/8/16 Assume RTC clock comes from LXTAL (32.768 KHz), this can periodically assert wakeup...
Page 349: Calendar Reading
GD32L23x User Manual Calendar initialization and configuration The prescaler and calendar value can be programmed by the following steps: Enter initialization mode (by setting INITM=1) and polling INITF bit until INITF=1. Program both the asynchronous and synchronous prescaler factors in RTC_PSC register. Write the initial calendar values into the shadow calendar registers (RTC_TIME and RTC_DATE), and use the CS bit in the RTC_CTL register to configure the time format (12 or 24 hours).
Page 350 GD32L23x User Manual reading calendar time register and date register twice if the two values are equal, the value can be seen as the correct value if the two values are not equal, a third reading should performed the third value can be seen as the correct value RSYNF is asserted once every 2 RTC clock and at this time point, the shadow registers will be updated to current time and date.
Page 351: Resetting The Rtc
GD32L23x User Manual Resetting the RTC 17.3.8. There are two reset sources used in RTC unit: system reset and backup domain reset. System reset will affect calendar shadow registers and some bits of the RTC_STAT. When system reset is valid, the bits or registers mentioned before are reset to the default value. Backup domain reset will affect the following registers and system reset will not affect them: RTC current real-time calendar registers RTC Control register (RTC_CTL)
Page 352: Rtc Reference Clock Detection
GD32L23x User Manual RTC reference clock detection 17.3.10. RTC reference clock detection is another way to increase the precision of RTC second. To enable this function, you should have an external clock source (50Hz or 60 Hz) which is more precise than LXTAL clock source.
Page 353 GD32L23x User Manual So using CMSK can mask clock cycles from 0 to 511 and thus the RTC frequency can be reduced by up to 487.1PPM. To increase the RTC frequency the FREQI bit can be set. If FREQI bit is set, there will be 512 additional cycles to be added during period time which means every 211/210/29(32/16/8 seconds) RTC clock insert one cycle.
Page 354: Time-Stamp Function
GD32L23x User Manual the measure is within 0.477PPM (0.5 RTCCLK cycles over 32s) When the calibration period is 16 seconds(by setting CWND16 bit) ◼ In this configuration, CMSK[0] is fixed to 0 by hardware. Using exactly 16s period to measure the accuracy of the calibration 1Hz output can guarantee the measure is within 0.954PPM (0.5 RTCCLK cycles over 16s) ◼...
Page 355 GD32L23x User Manual mode or level detection mode with configurable filtering setting. The purposes of the tamper detect configuration are the following: 1. The default configuration will erase the RTC backup registers 2. It can wakeup from DeepSleep and Standby modes, and generate an interrupt 3.
Page 356 GD32L23x User Manual Trigger output generation on tamper event The tamper event detection can be used as trigger input for the low-power timers To allow a new tamper detection on the same pin, the TPxF flag must be cleared by software When TPxMASK bit is cleared.
Page 357: Calibration Clock Output
GD32L23x User Manual Calibration clock output 17.3.14. Calibration clock can be output on the RTC_OUT if COEN bit is set to 1. When the COS bit is set to 0(this is default) and asynchronous prescaler is set to 0x7F(FACTOR_A), the frequency of RTC_CALIB is f /64.When the RTCCLK is 32.768KHz, rtcclk RTC_CALIB output is corresponding to 512Hz.It’s recommend to using rising edge of...
Page 358: Rtc Power Saving Mode Management
GD32L23x User Manual function OS[1:0] COEN TP0EN TSEN ALARMOUTTYP configuration (output (calibration (tamper (time E(RTC_ALARM and pin function selection output enabled) stamp output type enabled) Don’t care TIMESTAMP input floating Don’t care Standard GPIO It is possible to output RTC_OUT on PB2/PB14 pin thanks to OUT2EN bit in RTC_CTL[31]. This output is not available in VBAT only mode.
Page 359: Rtc Interrupts
GD32L23x User Manual RTC interrupts 17.3.18. All RTC interrupts are connected to the EXTI controller. Below steps should be followed if you want to use the RTC alarm/tamper/timestamp/auto wakeup interrupt: Configure enable corresponding interrupt line alarm/tamper/timestamp/auto wakeup event of EXTI and set the rising edge for triggering Configure and enable the RTC alarm/tamper/timestamp/auto wakeup interrupt Configure and enable the RTC alarm/tamper/timestamp/auto wakeup function Table 17-4 RTC interrupts control...
Page 360: Register Definition
GD32L23x User Manual 17.4. Register definition RTC base address: 0x4000 2800 Time register (RTC_TIME) 17.4.1. Address offset: 0x00 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state This register has to be accessed by word (32-bit) Reserved HRT[1:0]...
Page 361: Control Register (Rtc_Ctl)
GD32L23x User Manual This register has to be accessed by word (32-bit) Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[3:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. 23:20 Year tens in BCD code 19:16 YRU[3:0] Year units in BCD code 15:13 DOW[2:0]...
Page 362 GD32L23x User Manual 1: RTC_OUT is output on PB2/PB14 30:25 Reserved Must be kept at reset value. ITSEN Internal timestamp event enable 0: Disable Internal timestamp event 1: Enable Internal timestamp event COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0]...
Page 363 GD32L23x User Manual 1: Enable auto-wakeup timer interrupt ALRM1IE RTC alarm-1 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt ALRM0IE RTC alarm-0 interrupt enable 0: Disable alarm interrupt 1: Enable alarm interrupt TSEN Time-stamp function enable 0: Disable time-stamp function 1: Enable time-stamp function WTEN Auto-wakeup timer function enable...
Page 364: Status Register (Rtc_Stat)
GD32L23x User Manual 0x1:RTC Clock divided by 8 0x2:RTC Clock divided by 4 0x3:RTC Clock divided by 2 0x4:0x5: ck_spre (default 1Hz) clock 0x6:0x7: ck_spre (default 1Hz) clock and 2 is added to wake-up counter. Status register (RTC_STAT) 17.4.4. Address offset: 0x0C System reset: Only INITM, INITF and RSYNF bits are set to 0.
Page 365 GD32L23x User Manual before. Cleared by software writing 0. Time-stamp flag Set by hardware when time-stamp event is detected. Cleared by software writing 0. Wakeup timer flag Set by hardware when wakeup timer decreased to 0. Cleared by software writing 0. This flag must be cleared at least 1.5 RTC Clock periods before WTF is set to 1 again.
Page 366: Prescaler Register (Rtc_Psc)
GD32L23x User Manual 0: No shift operation is pending 1: Shift function operation is pending WTWF Wakeup timer write enable flag 0: Wakeup timer update is not allowed 1: Wakeup timer update is allowed ALRM1WF Alarm 1 configuration can be write flag Set by hardware if alarm register can be wrote after ALRM1EN bit has reset.
Page 367: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32L23x User Manual Backup domain reset value: 0x0000 FFFF This register is writing protected. This register has to be accessed by word (32-bit) Reserved WTRV[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 WTRV[15:0] Auto-wakeup timer reloads value. Every (WTRV[15:0]+1) ck_wut period the WTF bit is set after WTEN=1.The ck_wut is selected by WTCS[2:0] bits.
Page 368: Alarm 1 Time And Date Register (Rtc_Alrm1Td)
GD32L23x User Manual MSKH Alarm hour mask bit 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format 1: PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code MSKM Alarm minutes mask bit 0: Not mask minutes field...
Page 369: Write Protection Key Register (Rtc_Wpk)
GD32L23x User Manual 1: DAYU[3:0] indicates the week day and DAYT[3:0] has no means. 29:28 DAYT[1:0] Day tens in BCD code 27:24 DAYU[3:0] Day units or week day in BCD code MSKH Alarm hour mask bit 0: Not mask hour field 1: Mask hour field AM/PM flag 0: AM or 24-hour format...
Page 370: Sub Second Register (Rtc_Ss)
GD32L23x User Manual Sub second register (RTC_SS) 17.4.10. Address offset: 0x28 System reset value: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register has to be accessed by word (32-bit) Reserved SSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 371: Time Of Time Stamp Register (Rtc_Tts)
GD32L23x User Manual When only using SFS, the clock will delay because the synchronous prescaler is a down counter: Delay (seconds) = SFS / ( FACTOR_S + 1 ) When jointly using A1S and SFS, the clock will advance: Advance (seconds) = ( 1 – ( SFS / ( FACTOR_S + 1 ) ) ) Note: Writing to this register will cause RSYNF bit to be cleared.
Page 372: Date Of Time Stamp Register (Rtc_Dts)
GD32L23x User Manual Date of time stamp register (RTC_DTS) 17.4.13. Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1. Reset TSF bit will also clear this register. This register has to be accessed by word (32-bit) Reserved DOW[2:0]...
Page 373: High Resolution Frequency Compensation Register (Rtc_Hrfc)
GD32L23x User Manual 31:16 Reserved Must be kept at reset value. 15:0 SSC[15:0] Sub second value This value is the counter value of synchronous prescaler when TSF is set to 1. High resolution frequency compensation register (RTC_HRFC) 17.4.15. Address offset: 0x3C Backup domain reset: 0x0000 0000 System Reset: no effect This register is write protected.
Page 374: Tamper Register (Rtc_Tamp)
GD32L23x User Manual Tamper register (RTC_TAMP) 17.4.16. Address offset: 0x40 Backup domain reset: 0x0000 0000 System reset: no effect This register has to be accessed by word (32-bit) TP2NOER TP1NOER TP0NOER ALRMOU Reserved TP2IE TP1IE TP0IE Reserved TP2MASK TP1MASK TP0MASK Reserved Reserved TTYPE DISPU...
Page 375 GD32L23x User Manual Note: The Tamper 0 interrupt must not be enabled when TP0MASK is set. Reserved Must be kept at reset value. TP2NOERASE Tamper 2 no erase: 0:Tamper 2 event erases the backup registers 1:Tamper 2 event does not erase the backup registers TP1NOERASE Tamper 1 no erase: 0:Tamper 1 event erases the backup registers...
Page 376 GD32L23x User Manual 0x3: Sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) 0x4: Sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) 0x5: Sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) 0x6: Sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) 0x7: Sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) TPTS Make tamper function used for timestamp function 0:No effect...
Page 377: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32L23x User Manual 1:Enable tamper 0 detection function Note: It’s strongly recommended that reset the TpxEN before change the tamper configuration. Alarm 0 sub second register (RTC_ALRM0SS) 17.4.17. Address offset: 0x44 Backup domain reset: 0x0000 0000 System reset: no effect This register is write protected and can only be wrote when ALRM0EN=0 or INITM=1 This register has to be accessed by word (32-bit) Reserved...
Page 378: Alarm 1 Sub Second Register (Rtc_Alrm1Ss)
GD32L23x User Manual synchronous prescaler counter SSC. Bit number is controlled by MSKSSC bits. Alarm 1 sub second register (RTC_ALRM1SS) 17.4.18. Address offset: 0x48 Backup domain reset: 0x0000 0000 System reset: no effect This register is write protected and can only be wrote when ALRM1EN=0 or INITM=1 This register has to be accessed by word (32-bit) Reserved MSKSSC[3:0]...
Page 379: Backup Registers (Rtc_Bkpx) (X=0
GD32L23x User Manual Backup registers (RTC_BKPx) (x=0..4) 17.4.19. Address offset: 0x50~0x64 Backup domain reset: 0x0000 0000 System reset: no effect This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be wrote or read by software. The content remains valid even in power saving mode because they can powered-on by VBAT.
Page 380: Timer (Timerx)
GD32L23x User Manual Timer (TIMERx) Table 18-1. Timers (TIMERx) are devided into five sorts TIMER TIMER0 TIMER1/2 TIMER8/11 TIMER14/40 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L3 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, Count mode Center- UP ONLY...
Page 381: Advanced Timer (Timerx,X=0)
GD32L23x User Manual Advanced timer (TIMERx,x=0) 18.1. Overview 18.1.1. The advanced timer module (TIMER0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The advanced timer has a 16-bit counter that can be used as an unsigned counter.
Page 382: Block Diagram
GD32L23x User Manual Block diagram 18.1.3. Figure 18-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 18-1. Advanced timer block diagram CI0F_ED,CI0FE0,CI1FE1 TRGO Trigger Selector CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN...
Page 383: Figure 18-2. Normal Mode, Internal Clock Divided By 1
GD32L23x User Manual internal clock TIMER_CK is the counter prescaler driving clock source. Figure 18-2. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG ◼ TSCFG6[3:0] are setting to an available value (external clock mode 0). External input pin is selected as timer clock source.
Page 384: Figure 18-3. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32L23x User Manual Figure 18-3. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Counter up counting In this mode, the counter counts up continuously from 0 to the counter reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 385 GD32L23x User Manual Figure 18-4. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 386: Figure 18-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 18-5. Timing chart of up counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear...
Page 387 GD32L23x User Manual Figure 18-6. Timing chart of down counting mode, PSC=0/1 TIMER_CK CNT_CLK(PSC_CLK) TIMERx_PSC PSC == 0 CNT_REG 5C 5B Update event (UPE) Hardware set Update interrupt flag (UPIF) TIMERx_PSC PSC == 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF)
Page 388: Figure 18-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 18-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG 5D 5C Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 389: Figure 18-8. Timing Chart Of Center-Aligned Counting Mode
GD32L23x User Manual Figure 18-8. Timing chart of center-aligned counting shows some examples of the counter behavior when TIMERx_CAR=0x63. TIMERx_PSC=0x0. Figure 18-8. Timing chart of center-aligned counting mode TIMER_CK CNT_CLK (PSC_CLK) CNT_REG …. …. …. Underflow Overflow UPIF TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 390: Figure 18-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32L23x User Manual after starting the counter. Figure 18-9. Repetition counter timing chart of center-aligned counting mode TIMER_CK CNT_CLK …. …. …. …. …. Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Figure 18-10. Repetition counter timing chart of up counting mode TIMER_CK CNT_CLK 61 62 63 00 01 …...
Page 391: Figure 18-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32L23x User Manual Figure 18-11. Repetition counter timing chart of down counting mode TIMER_CK CNT_CLK CNT_REG …. …. …. …. …. Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare outputs.
Page 392: Figure 18-12. Input Capture Logic
GD32L23x User Manual Figure 18-12. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 CI0FED Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal The input signals of channelx (Cix) can be the TIMERx_CHx signal or the XOR signal of the TIMERx_CH0, TIMERx_CH1 and TIMERx_CH2 signals.
Page 393: Figure 18-13. Output Compare Logic (With Complementary Output, X=0,1,2)
GD32L23x User Manual in TIMERx_DMAINTEN. Direct generation: A DMA request or interrupt is generated by setting CHxG directly. The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connects to CI0 input. Select CI0 as channel 0 capture signals by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 394: Figure 18-15. Output-Compare In Three Modes
GD32L23x User Manual If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), ChxNE=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;...
Page 395: Figure 18-16. Timing Chart Of Eapwm
GD32L23x User Manual Figure 18-15. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the PWM output mode (by setting the CHxCOMCTL bit to 3’b110 (PWM mode 0) or to 3’b 111(PWM mode 1)), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 396 GD32L23x User Manual Figure 18-16. Timing chart of EAPWM Figure 18-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal As is shown in Figure 18-13.
Page 397 GD32L23x User Manual the CHxCOMCTL field to 0x00, setting to high by configuring the CHxCOMCTL field to 0x01, setting to low by configuring the CHxCOMCTL field to 0x02 or toggling signal by configuring the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
Page 398: Table 18-2. Complementary Outputs Controlled By Parameters
GD32L23x User Manual Table 18-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS ChxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 399: Figure 18-18. Complementary Output With Dead Time Insertion
GD32L23x User Manual Dead time insertion The dead time insertion is enabled when both ChxEN and CHxNEN are configured to 1’b1, it is also necessary to configure POEN to 1. The field named DTCFG defines the dead time delay that can be used for all channels except channel 3. Refer to the TIMERx_CCHP register for details about the delay time.
Page 400: Figure 18-19. Output Behavior Of The Channel In Response To A Break (The Break High Active)
GD32L23x User Manual sources are input break pin and HXTAL stuck event which is generated by Clock Monitor (CKM) in RCU. The break function is enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is configured by the BRKP bit in TIMERx_CCHP register. When a break occurs, the POEN bit is cleared asynchronously.
Page 401: Figure 18-20. Example Of Counter Operation In Quadrature Decoder Interface Mode
GD32L23x User Manual external clock with a direction selection. This means that the counter counts continuously from 0 to the counter-reload value. Therefore, users must configure the TIMERx_CAR register before the counter starts to count. Table 18-3. Counting direction versus quadrature decoder signals CI0FE0 CI1FE1 Counting mode...
Page 402: Figure 18-22. Hall Sensor Is Used To Bldc Motor
GD32L23x User Manual inverted Counter down Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 18-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers.
Page 403 GD32L23x User Manual ⚫ Enable ITIx connected to commutation function directly by setting CCUC and CCSE. ⚫ Configuration PWM parameter based on your request. Figure 18-22. Hall sensor is used to BLDC motor TIMER_in Input capture GPIO Core TIMER_out Output compare PWM output...
Page 404: Figure 18-23. Hall Sensor Timing Between Two Timers
GD32L23x User Manual Figure 18-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead-time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management The TIMERx can be synchronized with a trigger in several modes including restart mode, pause mode...
Page 405: Figure 18-24. Restart Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 1000: ETIFP configure the ETP for and prescaler can be used polarity selection and by configuring ETPSC. inversion. Exam1 Restart mode TSCFG3[3:0] = For ITI0, no polarity For the ITI0, no filter and The counter will 4’b 0001.ITI0 is selector can be used.
Page 406: Figure 18-25. Pause Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-25. Pause mode Exam3 Event mode TSCFG5[3:0] = ETP = 0, the polarity of ETPSC = 1, ETI is divided by The counter will 4’b 1000 ETI does not change. start to count ETIFP is selected.
Page 407: Figure 18-27. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
GD32L23x User Manual the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in TIMERx_CHCTL0/1 register. After a trigger rising occurs in the single pulse mode, the OxCPRE signal will immediately be forced to the state which the OxCPRE signal will change to, as the compare match event occurs without taking the comparison result into account.
Page 408: Figure 18-28. Triggering Timer0 With Enable Of Timer2
GD32L23x User Manual Configure TIMER2 master mode to send its enable signal as trigger output, and configure TIMER0 to select the input trigger from TIMER2 (TSCFG5[3:0] = 0011 in the SYSCFG_TIMERxCFG register). Start TIMER2 by writing 1 in the CEN bit (TIMER2_CTL0 register). Figure 18-28.
Page 409: Figure 18-30. Pause Timer0 With Enable Of Timer2
GD32L23x User Manual Figure 18-30. Pause TIMER0 with enable of TIMER2 TIMER0 counts on the divided internal clock only when TIMER2 is enable. Both counter clock frequencies are divided by 3 by the prescaler compared to TIMER_CK (f /3). Do as follow: CNT_CLK TIMER_CK Configure TIMER2 input master mode and Output enable signal as trigger output...
Page 410: Figure 18-31. Pause Timer0 With O0Cpreof Timer2
GD32L23x User Manual Figure 18-31. Pause TIMER0 with O0CPREof TIMER2 TIMER2 TIMER_CK CNT_REG O0CPRE TIMER0 TRGIF CNT_REG Timer DMA mode DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event.
Page 411: Timerx Registers(X=0)
GD32L23x User Manual TIMERx registers(x=0) 18.1.5. TIMER0 base address: 0x4001 2C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 412 GD32L23x User Manual center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when the counter is counting up and counting down, compare interrupt flag of channels can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down...
Page 413 GD32L23x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit...
Page 414 GD32L23x User Manual a window in which a slave timer is enabled. In this mode the master mode controller selects the counter enable signal as TRGO. The counter enable signal is set when CEN control bit is set or the trigger input in pause mode is high. There is a delay between the trigger input in pause mode and the TRGO output, except if the master- slave mode is selected.
Page 415 GD32L23x User Manual This register has to be accessed by word(32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge. 1: ETI is active at low level or falling edge.
Page 416 GD32L23x User Manual 0010: fSAMP= fTIMER_CK, N=4. 0011: fSAMP= fTIMER_CK, N=8. 0100: fSAMP=fDTS/2, N=6. 0101: fSAMP=fDTS/2, N=8. 0110: fSAMP=fDTS/4, N=6. 0111: fSAMP=fDTS/4, N=8. 1000: fSAMP=fDTS/8, N=6. 1001: fSAMP=fDTS/8, N=8. 1010: fSAMP=fDTS/16, N=5. 1011: fSAMP=fDTS/16, N=6. 1100: fSAMP=fDTS/16, N=8. 1101: fSAMP=fDTS/32, N=5. 1110: fSAMP=fDTS/32, N=6.
Page 417 GD32L23x User Manual 0: disabled 1: enabled CH3DEN Channel 3 capture/compare DMA request enable 0: disabled 1: enabled CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled...
Page 418 GD32L23x User Manual 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF...
Page 419 GD32L23x User Manual 1: An active level has been detected. TRGIF Trigger interrupt flag 0: No trigger event occurred. 1: Trigger interrupt occurred. CMTIF Channel commutation interrupt flag This flag is set by hardware when channel’s commutation event occurs, and cleared by software 0: No channel commutation interrupt occurred 1: Channel commutation interrupt occurred...
Page 420 GD32L23x User Manual 31:8 Reserved Must be kept at reset value. BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 421 GD32L23x User Manual 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0]...
Page 422 GD32L23x User Manual ETIF input. 0: Channel 0 output compare clear disable 1: Channel 0 output compare clear enable CH0COMCTL[2:0] Channel 0 compare output control This bit-field controls the behavior of the output reference signal O0CPRE which drives CH0_O and CH0_ON. O0CPRE is active high, while CH0_O and CH0_ON active level depends on CH0P and CH0NP bits.
Page 423 GD32L23x User Manual result of the comparison. 0: Channel 0 output quickly compare disable. The minimum delay from an edge on the trigger input to activate CH0_O output is 5 clock cycles. 1: Channel 0 output quickly compare enable. The minimum delay from an edge on the trigger input to activate CH0_O output is 3 clock cycles.
Page 424 GD32L23x User Manual 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
Page 425 GD32L23x User Manual This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH3EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 3 is configured as output 01: Channel 3 is configured as input, IS3 is connected to CI3FE3 10: Channel 3 is configured as input, IS3 is connected to CI2FE3 11: Channel 3 is configured as input, IS3 is connected to ITS, This mode is working...
Page 426 GD32L23x User Manual at each update event will be enabled. 0: Channel 2 output compare shadow disable 1: Channel 2 output compare shadow enable The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set). This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00.
Page 427 GD32L23x User Manual signal and the length of the digital filter applied to CI2. 0000: Filter disable, f , N=1 SAMP 0001: f , N=2 SAMP TIMER_CK 0010: f , N=4 SAMP TIMER_CK 0011: f , N=8 SAMP TIMER_CK 0100: f /2, N=6 SAMP 0101: f...
Page 428 GD32L23x User Manual CH3NP Channel3 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP Channel 2 complementary output polarity Refer to CH0NP description CH2NEN...
Page 429 GD32L23x User Manual When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 active high 1: Channel 0 active low When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0.
Page 430 GD32L23x User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock.
Page 431 GD32L23x User Manual This register has to be accessed by word(32-bit) Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated.
Page 432 GD32L23x User Manual This register has to be accessed by word(32-bit) Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 433 GD32L23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 434 GD32L23x User Manual channel outputs (CHx_O and CHx_ON) if the corresponding enable bits (ChxEN, CHxNEN in TIMERx_CHCTL2 register) have been set. 0: Channel outputs are disabled or forced to idle state. 1: Channel outputs are enabled. OAEN Output automatic enable This bit specifies whether the POEN bit can be set automatically by hardware.
Page 435 GD32L23x User Manual 01: PROT mode 0.The ISOx/ISOxN bits in TIMERx_CTL1 register and the BRKEN/BRKP/OAEN/DTCFG bits in TIMERx_CCHP register are writing protected. 10: PROT mode 1. In addition of the registers in PROT mode 0, the CHxP/CHxNP bits in TIMERx_CHCTL2 register (if related channel is configured in output mode) and the ROS/IOS bits in TIMERx_CCHP register are writing protected.
Page 436 GD32L23x User Manual This filed define the first address for the DMA access the TIMERx_DMATB. When access is done through the TIMERx_DMA address first time, this bit-field specifies the address you just access. And then the second access to the TIMERx_DMATB, you will access the address of start address + 0x4.
Page 437 GD32L23x User Manual 31:2 Reserved Must be kept at reset value CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect OUTSEL The output value selection...
Page 438: General Level0 Timer (Timerx, X=1, 2)
GD32L23x User Manual General level0 timer (TIMERx, x=1, 2) 18.2. Overview 18.2.1. The general level0 timer module (TIMER1, 2) is a four-channel timer that supports input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 439: Figure 18-33. General Level 0 Timer Block Diagram For Gd32L235
GD32L23x User Manual Figure 18-32. General Level 0 timer block diagram for GD32L233 CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic Trigger processor PSC_CLK Polarity selection TIMER_CK DMA REQ/ACK ETIFP...
Page 440: Function Overview
GD32L23x User Manual Function overview 18.2.4. Clock source configuration for GD32L233 The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit[2:0]). ◼ SMC[2:0] = 3’b000. Internal clock CK_TIMER is selected as timer clock source which is from module RCU.
Page 441 GD32L23x User Manual And, the counter prescaler can also be driven by rising edge on the internal trigger input pin ITI0/1/2/3. This mode can be selected by setting SMC[2:0] to 0x7 and the TRGS[2:0] to 0x0, 0x1, 0x2 or 0x3. ◼...
Page 442: Figure 18-35. Timing Chart Of Internal Clock Divided By 1
GD32L23x User Manual Figure 18-35. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG ◼ TSCFG6[3:0] != 4’b0000 (external clock mode 0). External input pin is selected as timer clock source.
Page 443: Figure 18-36. Timing Chart Of Psc Value Change From 0 To 2
GD32L23x User Manual Figure 18-36. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 444: Figure 18-38. Timing Chart Of Up Counting, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 18-37. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 18-38.
Page 445: Figure 18-39. Timing Chart Of Down Counting Mode, Psc=0/2
GD32L23x User Manual Counter down counting In this mode, the counter counts down continuously from the counter reload value, which is defined in the TIMERx_CAR register, in a count-down direction. Once the counter reaches 0, the counter will start counting down from the counter-reload value again. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode.
Page 446: Figure 18-40. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 18-40. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF) Hardware set...
Page 447: Figure 18-41. Timing Chart Of Center-Aligned Counting Mode
GD32L23x User Manual Figure 18-41. Timing chart of center-aligned counting mode shows the example of the counter behavior when TIMERx_CAR=0x99, TIMERx_PSC=0x0 Figure 18-41. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF...
Page 448: Figure 18-42. Channel Input Capture Principle
GD32L23x User Manual enabled when ChxIE=1. Figure 18-42. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling CI0FED Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0CAPPSC CH0MS TIMERx_CC_INT Capture INT From Other Channal The input signals of channelx (Cix) can be the TIMERx_CHx signal or the XOR signal of the TIMERx_CH0, TIMERx_CH1 and TIMERx_CH2 signals.
Page 449: Figure 18-43. Channel Output Compare Principle (X=0,1,2,3)
GD32L23x User Manual and DMA request will be asserted or not based on the configuration of ChxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: A DMA request or interrupt is generated by setting CHxG directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 450: Figure 18-44. Output-Compare Under Three Modes
GD32L23x User Manual Step2: Compare mode configuration. ◼ Set the shadow enable mode by CHxCOMSEN. ◼ Set the output mode (set/clear/toggle) by CHxCOMCTL. ◼ Select the active polarity by CHxP. ◼ Enable the output by ChxEN. Step3: Interrupt/DMA-request enables configuration by ChxIE/CxCDE. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV.
Page 451: Figure 18-45. Timing Chart Of Eapwm
GD32L23x User Manual interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV. Figure 18-46. Timing chart of CAPWM shows the CAPWM output and interrupts waveform. In up counting mode, if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR, the output will be always inactive in PWM mode 0 (CHxCOMCTL=3’b110).
Page 452 GD32L23x User Manual Figure 18-46. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal As is shown in Figure 18-43.
Page 453: Table 18-5. Counting Direction In Different Quadrature Decoder Mode
GD32L23x User Manual Configure the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 register, the OxCPRE signal can be forced to 0 when the ETIFP signal derived from the external ETI pin is set to a high level. The OxCPRE signal will not return to its active level until the next update event occurs. Quadrature decoder The quadrature decoder function uses two quadrature inputs CI0FE0 and CI1FE1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact to control the counter...
Page 454: Figure 18-47. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32L23x User Manual Figure 18-47. Counter behavior with CI0FE0 polarity non-inverted in mode 2 Figure 18-48. Counter behavior with CI0FE0 polarity inverted in mode 2 Hall sensor function Hall sensor is generally used to control BLDC Motor; the general level0 timer can support this function.
Page 455: Figure 18-49. Restart Mode
GD32L23x User Manual SYSCFG_TIMER1CFG or SYSCFG_TIMER2CFG (y=3,4,5), The trigger input of these modes can be selected by the TSCFGy[3:0] in SYSCFG_TIMER1CFG or correspond to different SYSCFG_TIMER2CFG, different TSCFGy[3:0] is trigger input. Table 18-6. Slave mode example table for GD32L233 Source Mode Selection Polarity Selection Filter and Prescaler...
Page 456: Figure 18-50. Pause Mode
GD32L23x User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 18-50. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode TRGS[2:0]=3’b1 ETP = 0 no polarity The counter will ETPSC = 1, divided by 2. change. start to count ETIF is the ETFC = 0, no filter when a rising...
Page 457: Figure 18-52. Restart Mode
GD32L23x User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection The counter can 4’b0001 selector can be used. prescaler can be used. be clear and ITI0 is the restart when a selection. rising trigger input. Figure 18-52. Restart mode TIMER_CK CNT_REG UPIF...
Page 458: Figure 18-54. Event Mode
GD32L23x User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 18-54. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 459 GD32L23x User Manual Figure 18-55. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 Timers interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode.
Page 460 GD32L23x User Manual registers DMATA+0x4, DMATA+0x8 and DMATA+0xC at the next 3 accesses to TIMERx_DMATB. In a word, one-time DMA internal interrupt event asserts, (DMATC+1) times request will be sent by TIMERx. If one more DMA request event occurs, TIMERx will repeat the process above. Timer debug mode When the Cortex -M23 is halted, and the TIMERx_HOLD configuration bit in DBG_CTL0...
Page 461: Timerx Registers(X=1, 2)
GD32L23x User Manual TIMERx registers(x=1, 2) 18.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 462 GD32L23x User Manual TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or quadrature decoder mode, this bit is read only.
Page 463 GD32L23x User Manual Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 464 GD32L23x User Manual Slave mode configuration register (TIMERx_SMCFG) For GD32L233xx devices Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 465 GD32L23x User Manual Basic principle of digital filter: continuously sample the external trigger signal according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level.
Page 466 GD32L23x User Manual SMC[2:0] Slave mode control. 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0. The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 467 GD32L23x User Manual When the slave mode is configured as restart mode, pause mode or event mode, the timer can still work in the external clock 1 mode by setting this bit. But the TSCFGy[3:0](y=3,4,5) must not be 4’b1000 in this case. The clock source of the timer will be ETIFP if external clock mode 0 and external clock mode 1 are configured at the same time.
Page 468 GD32L23x User Manual connected together. 0: Master-slave mode disable 1: Master-slave mode enable Reserved Must be kept at reset value. DMA and interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved TRGDEN Reserved CH3DEN CH2DEN CH1DEN CH0DEN UPDEN...
Page 469 GD32L23x User Manual Reserved Must be kept at reset value. TRGIE Trigger interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value. CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled CH1IE...
Page 470 GD32L23x User Manual Refer to CH0OF description CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software.
Page 471 GD32L23x User Manual This register has to be accessed by word(32-bit) Reserved Reserved TRGG Reserved CH3G CH2G CH1G CH0G Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 472 GD32L23x User Manual Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions...
Page 473 GD32L23x User Manual 1: Channel 0 output compare clear enable CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 474 GD32L23x User Manual TIMERx_CHCTL2 register is reset).). 00: Channel 0 is programmed as output mode 01: Channel 0 is programmed as input mode, IS0 is connected to CI0FE0 10: Channel 0 is programmed as input mode, IS0 is connected to CI1FE0 11: Channel 0 is programmed as input mode, IS0 is connected to ITS, This mode is working only if an internal trigger input is selected.
Page 475 GD32L23x User Manual 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 476 GD32L23x User Manual This bit-field is writable only when the channel is not active. (CH3EN bit in TIMERx_CHCTL2 register is reset). 00: Channel 3 is programmed as output mode 01: Channel 3 is programmed as input mode, IS3 is connected to CI3FE3 10: Channel 3 is programmed as input mode, IS3 is connected to CI2FE3 11: Channel 3 is programmed as input mode, IS3 is connected to ITS.
Page 477 GD32L23x User Manual 1: Channel 2 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1) CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM1 or PWM2 mode.
Page 478 GD32L23x User Manual CH2CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear.
Page 479 GD32L23x User Manual CH3NP Channel 3 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP Channel 2 complementary output polarity Refer to CH0NP description...
Page 480 GD32L23x User Manual trigger operation in slave mode. And CixFE0 will not be inverted. [CH0NP==0, CH0P==1]: CixFE0’s falling edge is the active signal for capture or trigger operation in slave mode. And CixFE0 will be inverted. [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CixFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode.
Page 481 GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 482 GD32L23x User Manual When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 483 GD32L23x User Manual 31:16 Reserved Must be kept at reset value 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 484 GD32L23x User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value.
Page 485 GD32L23x User Manual Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CHVSEL Write CHxVAL register selection This bit-field set and reset by software. 1: If write the CHxVAL register, the write value is same as the CHxVAL value, the write access ignored 0: No effect Reserved...
Page 486: General Level1 Timer (Timerx, X=8, 11)
GD32L23x User Manual General level1 timer (TIMERx, x=8, 11) 18.3. Overview 18.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 487: Block Diagram
GD32L23x User Manual Block diagram 18.3.3. Figure 18-56. General Level 1 timer block diagram for GD32L233 provides details on the internal configuration of the general level1 timer Figure 18- . General Level 1 timer block diagram for GD32L233 CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector...
Page 488: Function Overview
GD32L23x User Manual Function overview 18.3.4. Clock source configuration for GD32L233 The general level1 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when the SMC [2:0] == 3’b000.
Page 489: Figure 18-59. Timing Chart Of Internal Clock Divided By 1
GD32L23x User Manual Clock source configuration for GD32L235 The general level1 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by TSCFGy[3:0] in SYSCFG_TIMER8CFG or SYSCFG_TIMER11CFG (y=0,1…7) ◼ TSCFGy[3:0] = 4’b0000 in SYSCFG_TIMER8CFG or SYSCFG_TIMER11CFG (y=0,1…7).
Page 490: Figure 18-60. Timing Chart Of Psc Value Change From 0 To 2
GD32L23x User Manual And, the counter prescaler can also be driven by rising edge on the internal trigger input pin ITI0/1/2/3. This mode can be selected by setting TSCFG6[3:0] to 0x1,0x2,0x3,0x4. Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 491: Figure 18-62. Up-Counter Timechart, Change Timerx_Car On The Go
GD32L23x User Manual Figure 18-61. Up-counter timechart, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-62. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0...
Page 492: Figure 18-63. Channel Input Capture Principle
GD32L23x User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ◼...
Page 493: Figure 18-64. Output-Compare Under Three Modes
GD32L23x User Manual As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more. Step4: Interrupt enable. (ChxIE and CHxDEN in TIMERx_DMAINTEN) Enable the related interrupt enable; you can got the interrupt and DMA request. Step5: Capture enables.
Page 494 GD32L23x User Manual modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 18-64. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function Iin the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 495: Figure 18-65. Eapwm Timechart
GD32L23x User Manual Figure 18-65. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 18-66. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output reference signal...
Page 496: Table 18-8．Slave Mode Example Table For Gd32L233
GD32L23x User Manual The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 497: Figure 18-67. Restart Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-67. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF TRGS[2:0]=3’b101 Exam2 Pause mode TI0S=0.（Non-xor） Filter is bypass in this The counter can be [CH0NP==0, example. CI0FE0 paused when...
Page 498: Figure 18-69. Event Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-69. Event mode TIMER_CK CI0FE0 CNT_REG TRGIF Table 18-9．Slave mode example table for GD32L235 Mode Selection Source Selection Polarity Selection Filter and Prescaler TSCFGy[3:0] TSCFGy[3:0] LIST If you choose the For the ITIx no filter y=3 (restart mode) 0001: ITI0...
Page 499: Figure 18-71. Pause Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Exam2 Pause mode TSCFG4[3:0] = 4’b TI0S=0.（Non-xor） Filter is bypass in this The counter can be 0110 [CH0NP==0, example. paused when the CH0P==0] CI0FE0 is the trigger input is low. no inverted.
Page 500: Figure 18-73. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32L23x User Manual event. In order to get pulse waveform, you can set the TIMERx to PWM mode or compare by CHxCOMCTL. Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter.
Page 501: Timerx Registers(X=8, 11)
GD32L23x User Manual TIMERx registers(x=8, 11) 18.3.5. TIMER8 base address: 0x4001 4000 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits...
Page 502 GD32L23x User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 503 GD32L23x User Manual synchronize the counter. 000: ITI0 001: ITI1 010: ITI2 011: ITI3 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode.
Page 504 GD32L23x User Manual 0: Master-slave mode disable 1: Master-slave mode enable Reserved Must be kept at reset value. Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved TRGIE Reserved CH1IE CH0IE...
Page 505 GD32L23x User Manual Reserved CH1OF CH0OF Reserved TRGIF Reserved CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 506 GD32L23x User Manual Reserved Reserved TRGG Reserved. CH1G CH0G Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 507 GD32L23x User Manual CH1CO CH1CO CH0CO CH0CO CH1COMCTL[2:0] CH0COMCTL[2:0] Reserved Reserved MSEN MFEN MSEN MFEN CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL description CH1COMSEN Channel 1 output compare shadow enable...
Page 508 GD32L23x User Manual 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise. 111: PWM mode1.
Page 509 GD32L23x User Manual Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability.
Page 510 GD32L23x User Manual Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Reserved CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CH1NP Channel 1 complementary output polarity Refer to CH0NP description...
Page 511 GD32L23x User Manual [CH0NP==1, CH0P==1]: CixFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode. And CixFE0 will be not inverted. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state.
Page 512 GD32L23x User Manual The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 513 GD32L23x User Manual Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 514 GD32L23x User Manual Channel input remap register(TIMERx_IRMP, x=11) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CI0_RMP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER11_CH0) 01: Channel 0 input is connected to the IRC32K 10: Channel 0 input is connected to LXTAL...
Page 515: General Level3 Timer (Timerx, X=14,40)
GD32L23x User Manual General level3 timer (TIMERx, x=14,40) 18.4. Overview 18.4.1. The general level3 timer module (Timer14, 40) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 516: Function Overview
GD32L23x User Manual configuration of the general level3 timer. Figure 18-74. General level3 timer block diagram CI0F_ED,CI0FE0,CI1FE1 TRGO Trigger Selector CH0_IN Input Logic Synchronizer&Filter Edge selector Prescaler CH1_IN &Edge Detector TIMERx_CHxCV Counter PSC_CLK TIMER_CK TIMER_DMA_request DMA REQ/ACK DMA controller TIMERx_CH0 TIMERx_CH1 TIMERx_TG TIMERx_UP...
Page 517: Figure 18-75. Normal Mode, Internal Clock Divided By 1
GD32L23x User Manual clock CK_TIMER is the counter prescaler driving clock source. Figure 18-75. Normal mode, internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG ◼ TSCFG6[3:0] != 4’b0000 ( external clock mode 0 ).
Page 518: Figure 18-76. Counter Timing Diagram With Prescaler Division Change From 1 To 2
GD32L23x User Manual Figure 18-76. Counter timing diagram with prescaler division change from 1 to 2 TIMER_CK PSC_CLK CNT_REG FA FB FC Reload Pulse PSC value Prescaler BUF Prescaler CNT Up counting mode In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 519 GD32L23x User Manual Figure 18-77. Timing chart of up counting mode, PSC=0/1 TIMER_CK PSC = 0 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 1 CNT_CLK(PSC_CLK) CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set...
Page 520: Figure 18-78. Up-Counter Timechart, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 18-78. Up-counter timechart, change TIMERx_CAR ongoing TIMER_CK CNT_CLK(PSC_CLK) ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG Update event (UPE) Update interrupt flag (UPIF) Hardware set Software clear Hardware set...
Page 521: Figure 18-79. Repetition Counter Timing Chart Of Up Counting Mode
GD32L23x User Manual Figure 18-79. Repetition counter timing chart of up counting mode TIMER_CK CNT_CLK …. …. …. …. …. Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The general level3 timer has two independent channels which can be used as capture inputs or compare match outputs.
Page 522: Figure 18-80. Input Capture Logic
GD32L23x User Manual Figure 18-80. Input capture logic Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FE0 CI0FED Rising/Falling Capture Clock CI1FE0 presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal Channels’ input signals (Cix) is the TIMERx_CHx signal. First, the channel input signal (Cix) is synchronized to TIMER_CK domain, and then sampled by a digital filter to generate a filtered input signal.
Page 523: Figure 18-81. Output Compare Logic (With Complementary Output, X=0)
GD32L23x User Manual The input capture mode can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 524: Figure 18-83. Output-Compare In Three Modes
GD32L23x User Manual When CH0_O and CH0_ON are output at the same time, the specific outputs of CH0_O and CH0_ON are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the TIMERx_CCHP register. Please refer to Complementary outputs for more details.
Page 525: Figure 18-84. Pwm Mode Timechart
GD32L23x User Manual Figure 18-83. Output-compare in three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE PWM mode In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 526 GD32L23x User Manual Figure 18-84. PWM mode timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Channel output reference signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function.
Page 527: Table 18-10. Complementary Outputs Controlled By Parameters
GD32L23x User Manual Table 18-10. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS ChxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable CHx_O/ CHx_ON output “off-state” the CHx_O/ CHx_ON output inactive level firstly: CHx_O = CHxP, CHx_ON = CHxNP;...
Page 528: Figure 18-85. Complementary Output With Dead-Time Insertion
GD32L23x User Manual Dead time insertion The dead time insertion is enabled when both ChxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for channel 0. The detail about the delay time, refer to the register TIMERx_CCHP. The dead time delay insertion ensures that no two complementary signals drive the active state at the same time.
Page 529: Figure 18-86. Output Behavior In Response To A Break(The Break High Active)
GD32L23x User Manual and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 530: Figure 18-87. Restart Mode
GD32L23x User Manual Table 18-11. Slave mode example table Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST TSCFGy[3:0] TSCFGy[3:0] If you choose the CI0FE0 For the ITIx no filter and y=3 (restart mode) 0001: ITI0 or CI1FE1, configure the prescaler can be used.
Page 531: Figure 18-89. Event Mode
GD32L23x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler TIMER_CK CNT_REG 61 62 CI0FE0 TRGIF Exam3 Event mode TSCFG5[3:0] = TI0S=0.(Non-xor) Filter is bypass in this The counter will 4’b0110 [CH0NP==0, CH0P==0] example. start to count when CI0FE0 is the no inverted.
Page 532: Figure 18-90. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32L23x User Manual In the single pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHxCV value. In order to reduce the delay to a minimum value, the user can set the CHxCOMFEN bit in each TIMERx_CHCTL0/1 register.
Page 533 GD32L23x User Manual Timer debug mode When the Cortex™-M3 halted, and the TIMERx_HOLD configuration bit in DBG_CTL1 register set to 1, the TIMERx counter stops.
Page 534: Timerx Registers(X=14,40)
GD32L23x User Manual TIMERx registers(x=14,40) 18.4.5. TIMER14 base address: 0x4001 4000 TIMER40 base address: 0x4001 D000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields...
Page 535 GD32L23x User Manual The restart mode controller generates an update event. 1: Only counter overflow/underflow generates an update interrupt or DMA request. UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: update event enable. The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs: The UPG bit is set The counter generates an overflow or underflow event...
Page 536 GD32L23x User Manual 1: When POEN bit is reset, CH0_O is set high The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value MMC[2:0] Master mode control...
Page 537 GD32L23x User Manual 0: The shadow registers for ChxEN, CHxNEN and CHxCOMCTL bits are disabled. 1: The shadow registers for ChxEN, CHxNEN and CHxCOMCTL bits are enabled. After these bits have been written, they are updated based when commutation event coming.
Page 538 GD32L23x User Manual 31:15 Reserved Must be kept at reset value TRGDEN Trigger DMA request enable 0: disabled 1: enabled 13:11 Reserved Must be kept at reset value CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled...
Page 539 GD32L23x User Manual This register has to be accessed by word(32-bit) Reserved Reserved Reserved Reserved. CH1OF CH0OF BRKIF TRGIF CMTIF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:11 Reserved Must be kept at reset value CH1OF Channel 1 over capture flag Refer to CH0OF description...
Page 540 GD32L23x User Manual This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs. When channel 0 is in output mode, this flag is set when a compare event occurs. 0: No Channel 0 interrupt occurred 1: Channel 0 interrupt occurred UPIF...
Page 541 GD32L23x User Manual TIMERx_CTL1). 0: No affect 1: Generate channel’s c/c control update event Reserved Must be kept at reset value Channel 1’s capture or compare event generation CH1G Refer to CH0G description Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware.
Page 542 GD32L23x User Manual Refer to CH0COMCTL description CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description CH1COMFEN Channel 1 output compare fast enable Refer to CH0COMSEN description CH1MS[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active.
Page 543 GD32L23x User Manual CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled. 0: Channel 0 output compare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without validating the shadow register only in single pulse mode (SPM bit in TIMERx_CTL0 register is set).
Page 544 GD32L23x User Manual An event counter is used in the digital filter, in which a transition on the output occurs after N input events. This bit-field specifies the frequency used to sample CI0 input signal and the length of the digital filter applied to CI0. 0000: Filter disabled, f , N=1 SAMP...
Page 545 GD32L23x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value CH1NP Channel 1 complementary output polarity Refer to CH0NP description Reserved Must be kept at reset value CH1P Channel 1 capture/compare function polarity Refer to CH0P description CH1EN Channel 1 capture/compare function enable Refer to CH0EN description...
Page 546 GD32L23x User Manual CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT)
Page 547 GD32L23x User Manual this bit-filed will be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16...
Page 548 GD32L23x User Manual Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved CH0VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 549 GD32L23x User Manual shadow register updates every update event. Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN...
Page 550 GD32L23x User Manual 0: Break inputs disabled 1; Break inputs enabled This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. Run mode “off-state” enable When POEN bit is set (Run mode), this bit can be set to enable the “off-state” for the channels which has been configured in output mode.
Page 551 GD32L23x User Manual DTCFG [7:5] =3’b 111: Dtvalue = (32+DTCFG [4:0])xt *16. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DMATC[4:0]...
Page 552 GD32L23x User Manual DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 553: Basic Timer (Timerx, X=5, 6)
GD32L23x User Manual Basic timer (TIMERx, x=5, 6) 18.5. Overview 18.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 554: Figure 18-92. Timing Chart Of Internal Clock Divided By 1
GD32L23x User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 18-92. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG)
Page 555: Figure 18-93. Timing Chart Of Psc Value Change From 0 To 2
GD32L23x User Manual Figure 18-93. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 556: Figure 18-95. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32L23x User Manual Figure 18-94. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 18-95.
Page 557 GD32L23x User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. Once the timer is set to operate in the single pulse mode, it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 558: Timerx Registers(X=5,6)
GD32L23x User Manual TIMERx registers(x=5,6) 18.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8...
Page 559 GD32L23x User Manual The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 560 GD32L23x User Manual Reserved Must be kept at reset value. Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled...
Page 561 GD32L23x User Manual This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved Reserved Bits...
Page 562 GD32L23x User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 563: Low Power Timer (Lptimer)
GD32L23x User Manual Low power timer (LPTIMER) 19.1. Overview The LPTIMER is a 32-bit (GD32L233) or 16-bit (GD32L235) timer and it is able to keep running in all power modes except for standby mode with its diversity of clock sources. The LPTIMER provides a flexible mechanism of the clock, which reduces the power consumption to a minimum while also achieving the required functions and performance.
Page 564: Block Diagram
GD32L23x User Manual 19.3. Block diagram Figure 19-1. LPTIMER block diagram provides details of the internal configuration of the low power timer. Figure 19-1. LPTIMER block diagram High level counter IN1FP IN1F LPTIMER_IN1 Polarity Filter DECODER selection IN0FP Counter IN0F PCLK1 LPTIMER_IN0 LPTIMER_CK...
Page 565: Figure 19-2. Lptimer Clock Source Selection
GD32L23x User Manual Figure 19-2. LPTIMER clock source selection CKSSEL CK_LPTIMER LPTIMER_CK PSC_CLK LPTIMER_IN0 IN0P Polarity COUNTER selection IN0FP IN0F Polarity Filter selection CKSSEL CNTMEN LPTIMER has the capability of being clocked by either the internal clock signal or external clock signal controlled by bits CNTMEN and CKSSEL in LPTIMER_CTL0 register.
Page 566: Figure 19-3. Internal Clock Mode1 (Ckssel = 0 And Cntmen = 1 And Psc[2:0] = 000)
GD32L23x User Manual For this case, the LPTIMER counter can be clocked either on rising or falling edges of the external input clock signal, but not on both edges. Since the external signal added to the LPTIMER_IN0 pin is also used to clock the LPTIMER core logic, there is some initial delay (after the LPTIMER is enabled) before the counter is counting.
Page 567: Figure 19-4. Input Filter Timing Diagram (Eckflt=2'B01)
GD32L23x User Manual Prescaler divider PSC[2:0] bit-filed 1/128 Input filter 19.4.4. The external (mapped to GPIOs) or internal (mapped on-chip peripherals, such as comparators) signals on the LPTIMER_Inx needs to be filtered by a digital filter to prevent the glitches and noise interference from spreading in LPTIMER. This can be used to prevent false counts and triggers.
Page 568: Figure 19-5. External Inputs High Level Counter
GD32L23x User Manual the counter is cleared to 0. The INHLCOIF flag (in LPTIMER_INTF register) is set by hardware when the value of LPTIMER_Inx high level counter equal to the value of INHLCMVAL bits (in LPTIMER_INHLCMV register). An interrupr will generated if the INHLCOIE bit is enabled (in LPTIMER_INTEN register).
Page 569: Table 19-2. External Trigger Mapping
GD32L23x User Manual LPTEN bit equals “0”, any write on these bits will be discarded by hardware. External trigger mapping 19.4.7. The LPTIMER external trigger mapping is shown in Table 19-2. External trigger mapping. Table 19-2. External trigger mapping ETSEL[2:0] External trigger mapping ETI0 GPIO...
Page 570: Figure 19-6. Lptimer Output With Smst = 1(32-Bit)
GD32L23x User Manual Figure 19-6. LPTIMER output with SMST = 1(32-bit) External Trigger CARL[31:0] CMPVAL[31:0] COUNT LPTIMER_O When the OMSEL bit in the LPTIMER_CTL0 register is set, the set mode is enable. In this case, the counter is only started once after the first trigger, and all subsequent trigger events is ignored, as shown in Figure 19-7.
Page 571: Figure 19-8. Lptimer Output With Ctnmst = 1(32-Bit)
GD32L23x User Manual Figure 19-8. LPTIMER output with CTNMST = 1(32-bit) ignored ignored External Trigger CARL[31:0] CMPVAL[31:0] COUNT LPTIMER_O The SMST and CTNMST bits can be only when the timer is enabled (the LPTEN bit modified is set). And the single counting mode and continuous counting mode can be modified on the fly.
Page 572: Figure 19-9. Lptimer_O Output Mode With Opsel Bit(32-Bit)
GD32L23x User Manual ◼ OMSEL = 1: the LPTIMER to generate a set mode waveform. The OPSEL bit is used to configure the LPTIMER output polarity, the modification of this bit will take effect immediately. Therefore, any modification to the polarity configuration bit before enabling the LPTIMER will immediately change the output default value.
Page 573: Figure 19-10. Lptimer Timeout Mode(32-Bit)
GD32L23x User Manual Figure 19-10. LPTIMER timeout mode(32-bit) External Trigger TIMEOUT = 0 ignored CARL[31:0] CMPVAL[31:0] COUNT TIMEOUT = 1 CARL[31:0] CMPVAL[31:0] Counter CMPVMIE = 1 CMPVMIF Clear flag LPTIMER_ WAKEUP Decoder mode 19.4.11. The LPTIMER has two decoder modes: ◼...
Page 574: Figure 19-11. Counter Operation In Decoder Mode 0 With Rising-Edge-Mode
GD32L23x User Manual Therefore, users must configure the LPTIMER_CAR register before the counter starts to count. When the counter direction changes, the corresponding flag is set. When the counter direction moves from up to down, the DOWNIF bit is set. When the counter direction moves from down to up, the UPIF bit is set.
Page 575: Figure 19-12. Counter Operation In Decoder Mode 0 With Falling-Edge-Mode
GD32L23x User Manual Figure 19-12. Counter operation in decoder mode 0 with falling-edge-mode IN0F IN1F CARL Counter Down Down UPIF DOWNIF Decoder mode 1 The decoder mode 1 function uses two non-quadrature inputs derived from the LPTIMER_IN0 and LPTIMER_IN1 pins respectively to generate the counter value. At first, the CTNMST bit is set to 1 to enable the the continuous counting mode and the DECMEN bit is set to 1 to enable the decoder mode.
Page 576: Figure 19-13. Counter Operation In Decoder Mode 1 With Non-Inverted
GD32L23x User Manual Figure 19-13. Counter operation in decoder mode 1 with non-inverted IN1FP IN0FP CARL Counter IN1FP IN0FP CARL Counter When the inputs of LPTIMER_IN0 and LPTIMER_IN1 do not meet the timing relationship in Figure 19-13. Counter operation in decoder mode 1 with non-inverted, the counter cannot count.
Page 577: Figure 19-15. Counter Operation In Decoder Mode 1 With Non-Inverted(In0Eif)
GD32L23x User Manual Figure 19-15. Counter operation in decoder mode 1 with non-inverted(IN0EIF) IN1FP IN0FP CARL Counter IN0EIF Figure 19-16. Counter operation in decoder mode 1 with non-inverted(INRFOEIF) IN1FP IN1FP IN0FP IN0FP CARL CARL Counter Counter INRFOEIF INRFOEIF Figure 19-17. Counter operation in decoder mode 1 with non-inverted(INHLOEIF) IN1FP IN1FP IN0FP...
Page 578: Table 19-4. Lptimer Works In Low-Power Modes
GD32L23x User Manual provided ( 0) and the internal clock of LPTIMER cannot be prescaled (PSC [2:0] = CKSSEL = 000). In this case, the internal clock signal frequency should be at least four times the frequency of the external clock signal. Register update operation 19.4.12.
Page 579: Table 19-5. Lptimer Interrupt Events
GD32L23x User Manual Mode Description 0 /1 mode. LPTIMER interrupts cause the device to exit the Deep-sleep 2 Deep-sleep2 mode mode. Interrupts 19.4.14. The following events can generate interrupts or wake-up events, if they are enabled through the LPTIMER_INTEN register: ◼...
Page 580 GD32L23x User Manual Interrupt event Description Input high level counter max value Interrupt flag is set when the APB bus write operation to the register update LPTIMER_INHLCMV register has been successfully completed. LPTIMER counter direction Interrupt flag is set when the counter direction moves from up to change up to down down.
Page 581 GD32L23x User Manual 19.5. LPTIMER registers For GD32L233: LPTIMER base address: 0x4000 9400 For GD32L235: LPTIMER0 base address: 0x4000 9400 LPTIMER1 base address: 0x4000 7C00 Interrupt flag register (LPTIMER_INTF) 19.5.1. Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word (32-bit). HLCMV IN1EIF IN0EIF...
Page 582 GD32L23x User Manual Note: This flag just used in decoder mode 1. INHLOEIF The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag. This flag is set by hardware when the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap. INHLOEIF flag can be cleared by writing 1 to the INHLOEIC bit in the INTC register.
Page 583 GD32L23x User Manual CARMIC bit in the INTC register. CMPVMIF Compare value register match interrupt flag This flag is set by hardware when the LPTIMER_CNT value matches the value of the LPTIMER_CMPV register. The CMPVMIF flag can be cleared by writing 1 to the CMPVMIC bit in the INTC register.
Page 584 GD32L23x User Manual UPIC LPTIMER counter direction change down to up interrupt flag clear bit. Write 1 to this bit to clear the UPIF flag, and write 0 has no effect. CARUPIC Counter auto reload register update interrupt flag clear bit. Write 1 to this bit to clear the CARUPIF flag, and write 0 has no effect.
Page 585 GD32L23x User Manual interrupt enable bit 0: disabled 1: enabled This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). INHLOEIE The high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit.
Page 586 GD32L23x User Manual This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). ETEDEVIE External trigger edge event interrupt enable bit 0: disabled 1: enabled This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0).
Page 587 GD32L23x User Manual This bit can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). CNTMEN Counter mode select This bit is used to select the clock source of the LPTIMER counter. 0: The counter is count with each internal clock pulse 1: The counter is count with each active clock pulse on the LPTIMER_IN0.
Page 588 GD32L23x User Manual 01: Rising edge of external trigger enable 01: Falling edge of external trigger enable 11: Rising and falling edges of external trigger enable These bits can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0).
Page 589 GD32L23x User Manual 11: The active level change of the trigger need to be maintained at least 8 clock periods. These bits can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). Reserved Must be kept at reset value.
Page 590 GD32L23x User Manual If the LPTIMER external input high level counter enable（INHLCEN=1），the inputs of LPTIMER_IN0 and LPTIMER_IN1 are non-inverted. 11: not allowed These bits can be modified only when the LPTIMER is disabled (The LPTEN bit in LPTIMER_CTL1 register is 0). CKSSEL Clock source select This bit is used to select the clock source for LPTIMER.
Page 591 GD32L23x User Manual This bit is set by software and reset by hardware. This bit can be modified only when the LPTIMER is enabled (The LPTEN bit in LPTIMER_CTL1 register is 1). LPTEN LPTIMER enable This bit is set and reset by software. 0: LPTIMER is disabled 1: LPTIMER is enabled Compare value register (LPTIMER_CMPV)
Page 592 GD32L23x User Manual 15:0 CMPVAL[15:0] Compare value This bit-filed specifies the compare value of the counter. This bit-filed can be modified only when the LPTIMER is enabled (The LPTEN bit in LPTIMER_CTL1 register is 1). Counter auto reload register (LPTIMER_CAR) 19.5.7.
Page 593 GD32L23x User Manual LPTIMER_CTL1 register is 1). Counter register (LPTIMER_CNT) 19.5.8. For GD32L233xx devices Address offset: 0x1C Reset value: 0x0000 This register has to be accessed by word (32-bit). CNT[31:16] CNT[15:0] Bits Fields Descriptions 31:0 CNT[31:0] Counter value Note: When the LPTIMER uses an asynchronous clock, reads the LPTIMER_CNT register may return unreliable values.
Page 594 GD32L23x User Manual External input remap register (LPTIMER_EIRMP) 19.5.9. Address offset: 0x20 Reset value: 0x0000 This register has to be accessed by word (32-bit). Reserved Reserved IN1_RMP IN0_RMP Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. IN1_RMP External input1 remap 0: External input is remaped to GPIO.
Page 595 GD32L23x User Manual Universal synchronous/asynchronous receiver transmitter (USART) 20.1. Overview The Universal Synchronous / Asynchronous Receiver / Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK (PCLK, CK_SYS, LXTAL or IRC16M) to produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 596 GD32L23x User Manual Transmits parity bit. – Checks parity of received data byte. – ◼ LIN break generation and detection. ◼ IrDA support. ◼ Synchronous mode and transmitter clock output for synchronous transmission. ◼ ISO 7816-3 compliant smartcard interface: Character mode (T=0). –...
Page 597: Figure 20-1. Usart Module Block Diagram
GD32L23x User Manual 20.3. Function overview The interface is externally connected to another device by the main pins listed in Table 20-1. Description of USART important pins. Table 20-1. Description of USART important pins Type Description Input Receive Data Output I/O (single- Transmit Data.
Page 598: Figure 20-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32L23x User Manual Figure 20-2. USART character frame (8 bits data and 1 stop bit) CLOCK Data frame or parity bit Start bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 Start Stop Idle frame Start Start Stop Break frame In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register.
Page 599 GD32L23x User Manual Get the value of USART_BAUD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, the nearest integer is 6, so FRADIV=6 (0x6). USART_BAUD=0x1E6. Note: If the roundness FRADIV is 16 (overflow), the carry must be added to the integer part.
Page 600: Figure 20-3. Usart Transmit Procedure
GD32L23x User Manual Figure 20-3. USART transmit procedure It is necessary to wait for the TC bit to be asserted before disabling the USART or entering the power saving mode. This bit can be cleared by set the TCC bit in USART_INTC register. The break frame is sent when the SBKCMD bit is set, and SBKCMD bit is reset after the transmission.
Page 601: Figure 20-4. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32L23x User Manual frame bit is 0, the frame bit is confirmed as a 0, else 1. If the value of the three samples of any bit are not the same, whatever it is a start bit, data bit, parity bit or stop bit, a noisy error (NERR) status will be generated for the frame.
Page 602: Figure 20-5. Configuration Step When Using Dma For Usart Transmission
GD32L23x User Manual Use DMA for data buffer access 20.3.5. To reduce the burden of the processor, DMA can be used to access the transmitting and receiving data buffer. The DENT bit in USART_CTL2 is used to enable the DMA transmission, and the DENR bit in USART_CTL2 is used to enable the DMA reception.
Page 603: Figure 20-6. Configuration Step When Using Dma For Usart Reception
GD32L23x User Manual Figure 20-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 604: Figure 20-8. Hardware Flow Control
GD32L23x User Manual RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The USART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 605 GD32L23x User Manual The idle frame wake up method is selected by default. If the RWU bit is reset, an idle frame is detected on the RX pin, the IDLEF bit in USART_STAT will be set. If the RWU bit is set, an idle frame is detected on the RX pin, the hardware clears the RWU bit and exits the mute mode.
Page 606: Figure 20-9. Break Frame Occurs During Idle State
GD32L23x User Manual Figure 20-9. Break frame occurs during idle state frame0 frame1 frame2 RX pin 1 frame time FERR data0 data1 00000000 data2 USART_RDATA LBDF As shown in Figure 20-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame.
Page 607: Figure 20-11. Example Of Usart In Synchronous Mode
GD32L23x User Manual Figure 20-11. Example of USART in synchronous mode Figure 20-12. 8-bit format USART synchronous waveform (CLEN=1) Idle frame data (8bit) Idle CK pin (CPL=0, CPH=0) CK pin(CPL=1, CPH=0) CK pin (CPL=0, CPH=1) CK pin (CPL=1, CPH=1) Start Master data output bit0 bit1...
Page 608: Figure 20-13. Irda Sir Endec Module
GD32L23x User Manual Figure 20-13. IrDA SIR ENDEC module Inside chip Outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX and RX pins is different. The TX pin is usually at low state, while the RX pin is usually at high state.
Page 609: Figure 20-15. Iso7816-3 Frame Format
GD32L23x User Manual Half-duplex communication mode 20.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be cleared in half-duplex communication mode. Only one wire is used in half-duplex mode. The TX and RX pins are connected together internally.
Page 610 GD32L23x User Manual During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits. The USART can automatically resend data according to the protocol for SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame.
Page 611 GD32L23x User Manual programming the BL value. However, before the start of the block, the maximum value of BL (0xFF) may be programmed. The real value will be programmed after the reception of the third character. The total block length (including prologue, epilogue and information fields) equals BL+4. The end of the block is signaled to the software through the EBF flag and interrupt (when EBIE bit is set).
Page 612: Figure 20-16. Usart Receive Fifo Structure
GD32L23x User Manual Figure 20-16. USART Receive FIFO structure Rx Module Rx shift register Rx FIFO EN FIFO 0 Rx Buffer FIFO 1 FIFO 2 FIFO 3 If the software read receive data buffer in the routing of the RBNE interrupt, the RBNEIE bit should be reset at the beginning of the routing and set after all of the receive data is read out.
Page 613 GD32L23x User Manual Interrupt event Event flag Enable Control bit Transmission complete TCIE Received data ready to be RBNE read RBNEIE Overrun error detected ORERR Receive FIFO full RFFINT RFFIE Idle line detected IDLEF IDLEIE Parity error flag PERR PERRIE Break detected flag in LIN LBDF LBDIE...
Page 614: Figure 20-17. Usart Interrupt Mapping Diagram
GD32L23x User Manual Figure 20-17. USART interrupt mapping diagram RFFINT RFFIE IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ORERR ERRIE LBDF LBDIE USART_INT AMIE RTIE EBIE WUIE TCIE TBEIE CTSF CTSIE...
Page 615 GD32L23x User Manual 20.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Control register 0 (USART_CTL0) 20.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE...
Page 616 GD32L23x User Manual OVSMOD Oversample mode 0: Oversampling by 16 1: Oversampling by 8 This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be written when the USART is enabled (UEN=1). AMIE ADDR match interrupt enable 0: ADDR match interrupt is disabled 1: ADDR match interrupt is enabled Mute mode enable...
Page 617 GD32L23x User Manual 1: An interrupt will occur whenever the ORERR bit is set or the RBNE bit is set in USART_STAT. IDLEIE IDLE line detected interrupt enable 0: IDLE line detected interrupt disabled 1: An interrupt will occur whenever the IDLEF bit is set in USART_STAT. Transmitter enable 0: Transmitter is disabled 1: Transmitter is enabled...
Page 618 GD32L23x User Manual received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set on matching. This bit field cannot be written when both reception (REN=1) and USART (UEN=1) are enabled. RTEN Receiver timeout enable 0: Receiver timeout function disabled 1: Receiver timeout function enabled This bit is reserved in UART3 and UART4.
Page 619 GD32L23x User Manual This bit field cannot be written when the USART is enabled (UEN=1). CKEN CK pin enable 0: CK pin disabled 1: CK pin enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in UART3 and UART4. Clock polarity 0: Steady low value on CK pin outside transmission window in synchronous mode 1: Steady high value on CK pin outside transmission window in synchronous mode...
Page 620 GD32L23x User Manual Control register 2 (USART_CTL2) 20.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits...
Page 621 GD32L23x User Manual Driver enable polarity mode 0: DE signal is active high 1: DE signal is active low This bit field cannot be written when the USART is enabled (UEN=1) Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin.
Page 622 GD32L23x User Manual 1: RTS hardware flow control enablNed, data can be requested only when there is space in the receive buffer. This bit field cannot be written when the USART is enabled (UEN=1). DENT DMA enable for transmission 0: DMA mode is disabled for transmission 1: DMA mode is enabled for transmission DENR DMA enable for reception...
Page 623 GD32L23x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). This register cannot be written when the USART is enabled (UEN=1). Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 BRR[15:4] Integer of baud-rate divider...
Page 624 GD32L23x User Manual 00000010: divides the source clock by 2 In IrDA normal mode, 00000001: can be set this value only In smartcard mode, the prescaler value for dividing the system clock is stored in PSC[4:0] bits. And the bits of PSC[7:5] must be kept at reset value. The division factor is twice as the prescaler value.
Page 625 GD32L23x User Manual the RT value after the last received character. In smartcard mode, the CWT and BWT are implemented by this value. In this case, the timeout measurement is started from the start bit of the last received character. These bits can be written on the fly.
Page 626 GD32L23x User Manual Reserved Reserved CTSF LBDF RBNE IDLEF ORERR NERR FERR PERR Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknowledge flag This bit, which is set / reset by hardware, reflects the receive enable state of the USART core logic.
Page 627 GD32L23x User Manual Cleared by hardware during the stop bit of break transmission. ADDR match flag 0: ADDR does not match the received character 1: ADDR matches the received character, An interrupt is generated if AMIE=1 in the USART_CTL0 register. Set by hardware, when the character defined by ADDR [7:0] is received.
Page 628 GD32L23x User Manual 1: LIN Break is detected. An interrupt will occur if the LBDIE bit is set in USART_CTL1. Set by hardware when the LIN break is detected. Cleared by writing 1 to LBDC bit in USART_INTC register. This bit is reserved in UART3 and UART4. Transmit data register empty 0: Data is not transferred to the shift register 1: Data is transferred to the shift register.
Page 629 GD32L23x User Manual into the USART_RDATA register while the RBNE bit is set. Cleared by writing 1 to OREC bit in USART_INTC register. NERR Noise error flag 0: No noise error is detected 1: Noise error is detected. In multibuffer communication, an interrupt will occur if the ERRIE bit is set in USART_CTL2.
Page 630 GD32L23x User Manual This bit is reserved in UART3 and UART4. 19:18 Reserved Must be kept at reset value. ADDR match clear Writing 1 to this bit clears the AMF bit in the USART_STAT register. 16:13 Reserved Must be kept at reset value. End of block clear Writing 1 to this bit clears the EBF bit in the USART_STAT register.
Page 631 GD32L23x User Manual This register has to be accessed by word (32-bit). Reserved Reserved RDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. RDATA[8:0] Receive Data value The received data character is contained in these bits. The value read in the MSB (bit 7 or bit 8 depending on the data length) will be the received parity bit, if receiving with the parity is enabled (PCEN bit set to 1 in the USART_CTL0 register).
Page 632 GD32L23x User Manual This register has to be accessed by word (32-bit). Reserved Reserved EPERR Reserved rc_w0 Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. EPERR Early parity error flag. This flag will be set as soon as the parity bit has been detected, which is before RBNE flag.
Page 633 GD32L23x User Manual Receive FIFO empty flag 0: Receive FIFO not empty 1: Receive FIFO empty RFFIE Receive FIFO full interrupt enable 0: Receive FIFO full interrupt disable 1: Receive FIFO full interrupt enable RFEN Receive FIFO enable This bit can be set when UESM = 1. 0: Receive FIFO disable 1: Receive FIFO enable Reserved...
Page 634 GD32L23x User Manual Low-power universal asynchronous receiver /transmitter (LPUART) 21.1. Overview The Low-power universal Asynchronous Receiver/Transmitter (LPUART) provides a flexible serial data exchange interface with a limited power consumption. LPUART can perform asynchronous serial communication even with low power consumption. Data frames can be transferred in full duplex or half duplex mode, asynchronously through this interface.
Page 635: Table 21-1. Description Of Lpuart Important Pins
GD32L23x User Manual ◼ Parity control: Transmits parity bit. – Checks parity of received data byte. – ◼ Multiprocessor communication: Enter into mute mode if address match does not occur. – Wake up from mute mode by idle line or address match detection. –...
Page 636: Figure 21-1. Lpuart Module Block Diagram
GD32L23x User Manual Figure 21-1. LPUART module block diagram CPU/DMA Transmit Shift Register LPUART Data Register Receive Shift Register nRTS Hardware Flow nCTS Controler LPUART Control Registers LPUART Address Transmitter Transimit clock Controler Receiver Receiver Wakeup Unit Controler clock LPUCLK /LPUARTDIV (PCLK1 or CK_SYS or IRC16M or LXTAL)
Page 637 GD32L23x User Manual In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the LPUART_CTL1 register: STB[1:0] = 00: 1 stop bit length – STB[1:0] = 10: 2 stop bit length – In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal LPUART frame.
Page 638: Figure 21-3. Lpuart Transmit Procedure
GD32L23x User Manual The LPUART transmit procedure is shown in Table 21-3. LPUART interrupt requests. The software operating process is as follows: Write the WL[1:0] bits in LPUART_CTL0 to set the data bits length. Set the STB[1:0] bits in LPUART_CTL1 to configure the number of stop bits. Enable DMA (DENT bit) in LPUART_CTL2 if multibuffer communication is selected.
Page 639 GD32L23x User Manual When a frame is received, the RBNE bit in LPUART_STAT is asserted, an interrupt is generated if the corresponding interrupt enable bit (RBNEIE) is set in the LPUART_CTL0 register. The status of the reception are stored in the LPUART_STAT register. The software can get the received data by reading the LPUART_RDATA register directly, or through DMA.
Page 640: Figure 21-4. Configuration Step When Using Dma For Lpuart Transmission
GD32L23x User Manual Figure 21-4. Configuration step when using DMA for LPUART transmission Clear the TC bit in LPUART_STAT Set the address of LPUART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 641: Figure 21-5. Configuration Step When Using Dma For Lpuart Reception
GD32L23x User Manual Figure 21-5. Configuration step when using DMA for LPUART reception Set the address of LPUART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 642: Figure 21-7. Hardware Flow Control
GD32L23x User Manual RTS flow control The LPUART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. The nRTS signal keeps high when the receive buffer is full. CTS flow control The LPUART transmitter monitors the nCTS input pin to decide whether a data frame can be transmitted.
Page 643 GD32L23x User Manual big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, user can enable the mute mode using the MEN bit in the LPUART_CTL0 register, software can put an LPUART module into a mute mode by writing 1 to the MMCMD bit in LPUART_CMD register.
Page 644: Table 21-3. Lpuart Interrupt Requests
GD32L23x User Manual be IRC16M or LXTAL, it is possible to keep enabled this clock during Deep-sleep mode by setting the UCESM bit in LPUART_CTL2 register. When using the standard RBNE interrupt, the RBNEIE bit must be set before entering Deep- sleep mode.
Page 645: Figure 21-8. Lpuart Interrupt Mapping Diagram
GD32L23x User Manual Figure 21-8. LPUART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE FERR NERR ORERR ERRIE LPUART_INT AMIE WUIE TCIE TBEIE CTSF CTSIE...
Page 646 GD32L23x User Manual 21.4. Register definition For GD32L233xx devices LPUART0 base address: 0x4000 8000 For GD32L235xx devices LPUART0 base address: 0x4000 8000 LPUART1 base address: 0x4000 4800 Control register 0 (LPUART_CTL0) 21.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved DEA[4:0]...
Page 647 GD32L23x User Manual transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in LPUART CLK cycles. This bit field cannot be written when the LPUART is enabled (UEN=1). Reserved Must be kept at reset value. AMIE ADDR match interrupt enable 0: ADDR match interrupt is disabled...
Page 648 GD32L23x User Manual 1: Transmission complete interrupt is enabled RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 0: Read data register not empty interrupt and overrun error interrupt disabled 1: An interrupt will occur whenever the ORERR bit is set or the RBNE bit is set in LPUART_STAT.
Page 649 GD32L23x User Manual which is equal to 1, will be compared to these bits. When the ADDM bit is reset, only the ADDR[3:0] bits are used to compare. In normal reception, these bits are also used for character detection. The whole received character (8-bit) is compared to the ADDR[7:0] value and AMF flag is set on matching.
Page 650 GD32L23x User Manual detection is done on 6-bit, 7-bit and 8-bit address (ADDR[5:0], ADDR[6:0] and ADDR[7:0]) respectively This bit field cannot be written when the LPUART is enabled (UEN=1). Reserved Must be kept at reset value. Control register 2 (LPUART_CTL2) 21.4.3.
Page 651 GD32L23x User Manual This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin. 0: DE function is disabled 1: DE function is enabled This bit field cannot be written when the LPUART is enabled (UEN=1). DDRE Disable DMA on reception error 0: DMA is not disabled in case of reception error.
Page 652 GD32L23x User Manual 1: DMA mode is enabled for reception Reserved Must be kept at reset value. HDEN Half-duplex enable 0: Half duplex mode is disabled 1: Half duplex mode is enabled This bit field cannot be written when the LPUART is enabled (UEN=1). Reserved Must be kept at reset value.
Page 653 GD32L23x User Manual Reserved RXFCMD MMCMD Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. RXFCMD Receive data flush command Writing 1 to this bit clears the RBNE flag to discard the received data without reading MMCMD Mute mode command Writing 1 to this bit makes the LPUART into mute mode and sets the RWU flag.
Page 654 GD32L23x User Manual LPUART_CTL2 register and the MCU is in Deep-sleep mode. This bit is set by hardware when a wakeup event, which is defined by the WUM bit field, is detected. Cleared by writing a 1 to the WUC in the LPUART_INTC register. This bit can also be cleared when UESM is cleared.
Page 655 GD32L23x User Manual Set by hardware when the content of the LPUART_TDATA register has been transferred into the transmit shift register. Cleared by a write to the LPUART_TDATA. Transmission completed 0: Transmission is not completed 1: Transmission is complete. An interrupt will occur if the TCIE bit is set in LPUART_CTL0.
Page 656 GD32L23x User Manual 1: Frame error flag is detected. An interrupt will occur if the ERRIE bit is set in LPUART_CTL2. Set by hardware when a de-synchronization, excessive noise is detected. This bit will be set. Cleared by writing 1 to FEC bit in LPUART_INTC register. PERR Parity error flag 0: No parity error is detected...
Page 657 GD32L23x User Manual Reserved Must be kept at reset value IDLEC Idle line detected clear Writing 1 to this bit clears the IDLEF bit in the LPUART_STAT register. OREC Overrun error clear Writing 1 to this bit clears the ORERR bit in the LPUART_STAT register. Noise detected clear Writing 1 to this bit clears the NERR bit in the LPUART_STAT register.
Page 658 GD32L23x User Manual Reserved Reserved TDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. TDATA[8:0] Transmit Data value The transmit data character is contained in these bits. The value written in the MSB (bit 7 or bit 8 depending on the data length) will be replaced by the parity, when transmitting with the parity is enabled (PCEN bit set to 1 in the LPUART_CTL0 register).
Page 659: Figure 22-1. I2C Module Block Diagram
GD32L23x User Manual Inter-integrated circuit interface (I2C) Overview 22.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard mode, fast mode and fast mode plus as well as CRC calculation and checking, SMBus (system management bus), and PMBus (power management bus).
Page 660: Table 22-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32L23x User Manual Figure 22-1. I2C module block diagram PEC register SDA Controller CRC Calculation / Analog Digital Check Noise Noise filter filter Wakeup on Receive address macth Data Register Shift Register Transmit SCL Controller Data Analog Digital Register Noise Noise filter filter...
Page 661: Figure 22-2. Data Validation
GD32L23x User Manual ◼ <t I2CCLK HIGH with: : SCL low time : SCL high time HIGH : When the filters are enabled, represent the delays by the analog filter and digital filter. filters Analog filter delay is maximum 200ns for GD32L233xx devices and 125ns for GD32L235xx DNF[3:0]×t devices.
Page 662: Figure 22-3. Start And Stop Signal
GD32L23x User Manual signal. Figure 22-3. START and STOP signal START STOP Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device.
Page 663: Figure 22-5. I2C Communication Flow With 7-Bit Address (Master Transmit)
GD32L23x User Manual Figure 22-5. I2C communication flow with 7-bit address (Master Transmit) Figure 22-6. I2C communication flow with 7-bit address (Master Receive) …… Start Slave address DATA0 DATAN NACK Stop R(1) data transfer (N+1 bytes) From master to slave From slave to master In 10-bit addressing mode, the HEAD10R bit can configured to decide whether the complete address sequence must be executed, or only the header to be sent.
Page 664: Figure 22-9. Data Hold Time
GD32L23x User Manual Noise filter 22.3.3. Analog noise filter and digital noise filter are integrated in I2C peripherals, the noise filters can be configured before the I2C peripheral is enabled according to the actual requirements. The analog noise filter is disabled by setting the ANOFF bit in I2C_CTL0 register and enabled when ANOFF is 0.
Page 665: Figure 22-10. Data Setup Time
GD32L23x User Manual Figure 22-10. Data setup time SU;DAT When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is t =SDADELY*t where t = ( PSC+1 ) *t SDADELY I2CCLK I2CCLK effects t .
Page 666: Table 22-2. Data Setup Time And Data Hold Time
GD32L23x User Manual Table 22-2. Data setup time and data hold time Standard Fast mode Fast mode SMBus Symbol Parameter mode plus Unit Data hold time HD;DAT Data valid time 3.45 0.45 VD;DAT Data setup time SU;DAT Rising time of 1000 1000 SCL and SDA...
Page 667: Figure 22-11. Data Transmission
GD32L23x User Manual Figure 22-11. Data transmission SCL Stretch Shift register write data1 write data2 data0 data1 data2 I2C_TDATA Data Reception When receiving data, the data will be received in the shift register first. If RBNE is 0, the data in the shift register will move into I2C_RDATA register.
Page 668 GD32L23x User Manual Working mode Action SMBus mode PEC generation/checking The number of bytes to be transferred is configured by BYTENUM[7:0] in I2C_CTL1 register. If BYTENUM is greater than 255, or in slave byte control mode, the reload mode must be enabled by setting the RELOAD bit in I2C_CTL1 register.
Page 669 GD32L23x User Manual ◼ The SCL is stretched when the ADDSEND bit is set, and released when the ADDSEND bit is cleared. ◼ In slave transmitting mode, after the ADDSEND bit is cleared, the SCL will be stretched before the first data byte writing to the I2C_TDATA register. Or the SCL will be stretched before the new data is written to the I2C_TDATA register after the previous data transmission is completed.
Page 670: Figure 22-13. I2C Initialization In Slave Mode
GD32L23x User Manual 2. The slave has not been addressed. 3. ADDSEND=1. Only when the ADDSEND=1 or TCR=1, the RELOAD bit can be modified. Figure 22-13. I2C initialization in slave mode START I2CEN=0 Configure DNF[3:0] in I2C_CTL0 Configure PSC[3:0], SDADELY[3:0], SCLDELY[3:0] in I2C_TIMING Configure SS in I2C_CTL0 I2CEN=1...
Page 671: Figure 22-14. Programming Model For Slave Transmitting When Ss=0
GD32L23x User Manual the TBE bit. When SBCTL=1, the slave works in slave byte control mode, the BYTENUM[7:0] must be configured in the ADDSEND interrupt service routine. And the number of TI events is equal to the value of BYTENUM[7:0]. When SS=1, the SCL will not be stretched when ADDSEND bit in I2C_STAT register is set.
Page 672: Figure 22-15. Programming Model For Slave Transmitting When Ss=1
GD32L23x User Manual Figure 22-15. Programming model for slave transmitting when SS=1 I2C Line State Hardware Action Software Flow I2C initialization IDLE Set TBE Write DATA(1) to I2C_TDATA Master generates START condition Master sends Address read READDR and TR in Set ADDSEND Slave sends Acknowledge I2C_STAT, clear ADDSEND...
Page 673: Figure 22-16. Programming Model For Slave Receiving
GD32L23x User Manual Figure 22-16. Programming model for slave receiving I2C Line State Hardware Action Software Flow IDLE Master generates START Software initialization condition Master sends Address Slave sends Acknowledge read READDR and TR in Set ADDSEND I2C_STAT, clear ADDSEND SCL stretched by slave (only when SS=0) Master sends DATA(1)
Page 674: Figure 22-17. I2C Initialization In Master Mode
GD32L23x User Manual configured in I2C_CTL1 register. When the addressing mode is 10-bit in master receiving mode, the HEAD10R bit must be configured to decide whether the complete address sequence must be executed, or only the header to be sent. The number of bytes to be transferred should be configured in BYTENUM[7:0] in I2C_CTL1 register.
Page 675: Figure 22-18. Programming Model For Master Transmitting (N<=255)
GD32L23x User Manual ◼ If data of BYTENUM[7:0] bytes have been transferred and RELOAD=0, the AUTOEND bit in I2C_CTL1 can be set to generate a STOP signal automatically. When AUTOEND is 0, the TC bit in I2C_STAT register will be set and the SCL is stretched. In this case, the master can generate a STOP signal by setting the STOP bit in the I2C_CTL1 register.
Page 676: Figure 22-19. Programming Model For Master Transmitting (N>255)
GD32L23x User Manual Figure 22-19. Programming model for master transmitting (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 IDLE BYTENUM[7:0]=0xFF Master generates START N=N-255 condition Set START Master sends Address Slave sends Acknowledge Write DATA(1) to Set TI I2C_TDATA Wait for ACK from slave...
Page 677: Figure 22-20. Programming Model For Master Receiving (N<=255)
GD32L23x User Manual Figure 22-20. Programming model for master receiving (N<=255) I2C Line State Hardware Action Software Flow Software initialization AUTOEND=0 BYTENUM[7:0]=N IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 678: Figure 22-21. Programming Model For Master Receiving (N>255)
GD32L23x User Manual Figure 22-21. Programming model for master receiving (N>255) I2C Line State Hardware Action Software Flow Software initialization RELOAD =1 BYTENUM[7:0]=0xFF N=N-255 IDLE Set START START Condition Master sends Address Slave sends Acknowledge Slave sends DATA(1) Master sends Acknowledge Set RBNE Read DATA(1) （Data transmission）...
Page 679 GD32L23x User Manual Configuration and Power Management Interface (abbreviated to ACPI) specifications. Address resolution protocol The SMBus uses I2C hardware and I2C hardware addressing, but adds second-level software for building special systems. Additionally, its specifications include an Address Resolution Protocol that can make dynamic address allocations. Dynamic reconfiguration of the hardware and software allow bus devices to be ‘hot-plugged’...
Page 680 GD32L23x User Manual (BUSTOA+1)*2048*t , the TIMEOUT flag will be set in I2C_STAT register. I2CCLK The BUSTOB[11:0] is used to check the t of the slave and the t of the LOW:SEXT LOW:MEXT master. The timer can be enabled by setting the EXTOEN bit in the I2C_TIMEOUT register, after the EXTOEN bit is set, the BUSTOB[11:0] cannot be changed.
Page 681 GD32L23x User Manual The BUSTOA[11:0] bits must be programmed with the timer reload value to enable the t IDLE check in order to obtain the t parameter. To detect SCL and SDA high level timeouts, the IDLE TOIDLE bit must be set. Then setting the TOEN bit in the I2C_TIMEOUT register to enable the timer, after the TOEN bit is set, the BUSTOA[11:0] bit and the TOIDLE bit cannot be changed.
Page 682: Figure 22-22. Smbus Master Transmitter And Slave Receiver Communication Flow
GD32L23x User Manual Note: After the RELOAD bit is set, the PECTRANS cannot be changed. Figure 22-22. SMBus master transmitter and slave receiver communication flow Start Slave address DATA0 …… DATA N-1 Stop W(0) data transfer (N+1 bytes) From master to slave From slave to master SMBus master receiver and slave transmitter If the SMBus master is required to receive PEC at the end of bytes transfer, automatic end...
Page 683: Table 22-4. I2C Error Flags
GD32L23x User Manual is used as the clock of I2C to receive the address. When address matching is detected, I2C stretches SCL during MCU wake-up. The SCL is released until the software clears the ADDSEND flag and the transmission proceeds normally. If the detected address does not match, IRC16M will be closed again and the MCU will not be wake up.
Page 684 GD32L23x User Manual nterrupt event Event flag Enable control bit Transfer complete reload TCIE Transfer complete Address match ADDSEND ADDMIE Not acknowledge received NACK NACKIE Bus error BERR Arbitration Lost LOSTARB Overrun / Underrun error OUERR ERRIE PEC error PECERR Timeout error TIMEOUT SMBus Alert...
Page 685 GD32L23x User Manual Register definition 22.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 I2C2 base address: 0x4000 C000 Control register 0 (I2C_CTL0) 22.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SMBALT SMBDAE SMBHAE...
Page 686 GD32L23x User Manual 0: Slave won’t response to a General Call 1: Slave will response to a General Call WUEN Wakeup from power saving mode enable, including Deep-sleep mode, Deep-sleep 1 mode and Deep-sleep 2 mode. This bit is cleared when mcu wakeup from power saving mode. 0: Wakeup from power saving mode disable.
Page 687 GD32L23x User Manual 1: Error interrupt enabled. When BERR, LOSTARB, OUERR, PECERR, TIMEOUT or SMBALT bit is set, an interrupt will be generated. TCIE Transfer complete interrupt enable 0: Transfer complete interrupt is disabled 1: Transfer complete interrupt is enabled STPDETIE Stop detection interrupt enable 0: Stop detection (STPDET) interrupt is disabled...
Page 688 GD32L23x User Manual 31:27 Reserved Must be kept at reset value. PECTRANS PEC Transfer Set by software. Cleared by hardware in the following cases: When PEC byte is transferred or ADDSEND bit is set or STOP signal is detected or I2CEN=0.
Page 689 GD32L23x User Manual cleared by hardware. It can be cleared by software by setting the ADDSENDC bit in I2C_STATC register. 0: START will not be sent 1: START will be sent HEAD10R 10-bit address header executes read direction only in master receive mode 0: The 10 bit master receive address sequence is START + header of 10-bit address (write) + slave address byte 2 + RESTART + header of 10-bit address (read).
Page 690 GD32L23x User Manual ADDRES ADDFOR ADDRES Reserved ADDRESS[9:8] ADDRESS[7:1] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. ADDRESSEN I2C address enable 0: I2C address disable. 1: I2C address enable. 14:11 Reserved Must be kept at reset value. ADDFORMAT Address mode for the I2C slave 0: 7-bit address...
Page 691 GD32L23x User Manual 14:11 Reserved Must be kept at reset value. 10:8 ADDMSK2[2:0] ADDRESS2[7:1] mask Defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don’t care). 000: No mask, all the bits must be compared. N(001~110): ADDRESS2[n:0] is masked.
Page 692 GD32L23x User Manual A delay t between SCL falling edge and SDA edge can be generated by SDADELY configuring these bits. And during t , the SCL line is stretched low in master SDADELY mode and in slave mode when SS = 0. =SDADELY*t SDADELY 15:8...
Page 693 GD32L23x User Manual If the SCL stretch time greater than t when TOIDLE =0 or high for more TIMEOUT than t when TOIDLE =1, a timeout error is detected. IDLE 0: SCL timeout detection is disabled 1: SCL timeout detection is enabled 14:13 Reserved Must be kept at reset value.
Page 694 GD32L23x User Manual 0: No I2C communication. 1: I2C communication active. Reserved Must be kept at reset value. SMBALT SMBus Alert When SMBHAEN=1, SMBALTEN=1, and a SMBALERT event (falling edge) is detected on SMBA pin, this bit will be set by hardware. It is cleared by software by setting the SMBALTC bit.
Page 695 GD32L23x User Manual been transferred. It is cleared by software when BYTENUM[7:0] is written to a non- zero value. 0: When RELOAD=1, transfer of BYTENUM[7:0] bytes is not completed 1: When RELOAD=1, transfer of BYTENUM[7:0] bytes is completed Transfer complete in master mode This bit is set by hardware when RELOAD=0, AUTOEND=0 and data of BYTENUM[7:0] bytes have been transferred.
Page 696 GD32L23x User Manual when the next data to be sent is written in the I2C_TDATA register. This bit can be set by software in order to empty the I2C_TDATA register. 0: I2C_TDATA is not empty 1: I2C_TDATA is empty Status clear register (I2C_STATC) 22.4.8.
Page 697 GD32L23x User Manual Software can clear the ADDSEND bit of I2C_STAT by writing 1 to this bit. Reserved Must be kept at reset value. PEC register (I2C_PEC) 22.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PECV[7:0]...
Page 698 GD32L23x User Manual This register has to be accessed by word (32-bit). Reserved Reserved TDATA [7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data value Control register 2 (I2C_CTL2) 22.4.12. Address offset: 0x90 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 699 GD32L23x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 23.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The serial peripheral interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 700: Figure 23-1. Block Diagram Of Spi
GD32L23x User Manual ◼ Transmission and reception using DMA. 23.3. SPI function overview SPI block diagram 23.3.1. Figure 23-1. Block diagram of SPI SYSCLK MOSI TXBuffer/ TXFIFO MISO RX Buffer/ RXFIFO SPI signal description 23.3.2. Normal configuration (Not Quad-SPI Mode) Table 23-1.
Page 701: Table 23-2. Quad-Spi Signal Description
GD32L23x User Manual Pin name Direction Description output, suitable for single master application; when NSSDRV=0, it is NSS input, suitable for multi-master application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 702: Figure 23-2. Spi0 Timing Diagram In Normal Mode
GD32L23x User Manual Figure 23-2. SPI0 timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[4] D[0] D[1] D[2] D[5] D[6] D[7] LF=1 DZ[3:0]=7 MISO D[2] D[1] D[5] D[6] D[7] D[0] D[3]...
Page 703: Figure 23-5. Spi0 Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32L23x User Manual Figure 23-5. SPI0 timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample D[4] D[0] D[4] D[0] MOSI D[5] D[1] D[5] D[1] MISO D[6] D[2] D[6] D[2] D[7] D[3] D[7] D[3] Separate transmission and reception FIFO 23.3.4. The separate 32-bit reception FIFO (RXFIFO) and transmission FIFO (TXFIFO) are used in different directions for SPI data transactions, and they can enable the SPI to work in a continuous flow (only available in SPI0).
Page 704: Table 23-3. Nss Function In Slave Mode
GD32L23x User Manual TXFIFO empty or full appears below and there is no special explanation, the meaning is the same as that described here. For SPI0, the meaning of RXFIFO empty is divided into the following two conditions: If BYTEN bit in SPI_CTL1 is set, the RXFIFO empty means the RXFIFO level is less than quarter of its capacity.
Page 705: Table 23-4. Nss Function In Master Mode
GD32L23x User Manual Mode Register configuration Description SWNSS = 0: NSS level is low SWNSS = 1: NSS level is high Master mode In master mode (MSTMOD=1) if the application uses multi-master connection, NSS can be configured to hardware input mode (SWNSSEN=0, NSSDRV=0) or software mode (SWNSSEN=1).
Page 706: Table 23-5. Spi Operation Modes
GD32L23x User Manual SPI operation modes 23.3.6. Table 23-5. SPI operation modes Mode Description Register configuration Data pin usage MSTMOD = 1 RO = 0 MOSI: Transmission Master full-duplex BDEN = 0 MISO: Reception BDOEN: Don’t care MSTMOD = 1 Master transmission with RO = 0 MOSI: Transmission...
Page 707: Figure 23-7. A Typical Full-Duplex Connection
GD32L23x User Manual Mode Description Register configuration Data pin usage BDEN = 1 BDOEN = 0 Figure 23-7. A typical full-duplex connection Figure 23-8. A typical simplex connection (Master: Receive, Slave: Transmit) Figure 23-9. A typical simplex connection (Master: Transmit only, Slave: Receive) Master MTU Slave SRU MISO...
Page 708: Figure 23-10. A Typical Bidirectional Connection
GD32L23x User Manual Figure 23-10. A typical bidirectional connection Initialization sequence SPI0: Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 709 GD32L23x User Manual Program data format (FF16 bit in the SPI_CTL0 register). Program the clock timing register (CKPL and CKPH bits in the SPI_CTL0 register). Program the frame format (LF bit in the SPI_CTL0 register). Program the NSS mode (SWNSSEN and NSSDRV bits in the SPI_CTL0 register) NSS function according to the application’s demand as described above in section.
Page 710: Figure 23-11. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32L23x User Manual The transmission mode (MTU, MTB, STU or STB) is similar to the transmission sequence of full-duplex mode regardless of the RBNE and OVRE bits. The master reception mode (MRU or MRB) is different from the reception sequence of full- duplex mode.
Page 711: Figure 23-13. Timing Diagram Of Ti Slave Mode
GD32L23x User Manual Figure 23-13. Timing diagram of TI slave mode In slave TI mode, after the last rising edge of SCK in transfer, the slave begins to transmit the LSB bit of the last data byte, and after a half-bit time, the master begins to sample the line. To make sure that the master samples the right value, the slave should continue to drive this bit after the falling sample edge of SCK for a period of time before releasing the pin.
Page 712: Figure 23-14. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32L23x User Manual Figure 23-14. Timing diagram of NSS pulse with continuous transmit MOSI MISO Don t Care Don t Care Don t Care 1 SCK Quad-SPI mode operation sequence The Quad-SPI mode is designed to control Quad-SPI flash. In order to enter Quad-SPI mode, the software should first verify that the TBE bit is set and TRANS bit is cleared, then set QMOD bit in SPI_QCTL register.
Page 713: Figure 23-15. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32L23x User Manual Figure 23-15. Timing diagram of quad write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[0] D0[4] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 714: Figure 23-16. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32L23x User Manual Figure 23-16. Timing diagram of quad read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[0] D0[4] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7]...
Page 715 GD32L23x User Manual For SPI1, application can disable the SPI when it doesn’t want to receive data, and then wait until the TRANS=0 to ensure the ongoing transfer completes. TI mode The disabling sequence of TI mode is the same as the sequences described above. NSS pulse mode The disabling sequence of NSSP mode is the same as the sequences described above.
Page 716 GD32L23x User Manual Application can enable the CRC function by setting CRCEN bit in SPI_CTL0 register. The CRC calculators continuously calculate CRC for each bit transmitted and received on lines, and the calculated CRC values can be read from SPI_TCRC and SPI_RCRC registers. To transmit the calculated CRC value, application should set the CRCNT bit in SPI_CTL0 register after the last data is written to the transmit buffer/TXFIFO.
Page 717: Table 23-6. Spi Interrupt Requests
GD32L23x User Manual is set when the RXFIFO level is greater or equal to 1/4(8-bit). For SPI1, this bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register.
Page 718: Figure 23-17. Block Diagram Of I2S
GD32L23x User Manual Interrupt Flag Description Clear method enable bit Receive buffer/RXFIFO not RBNE Read SPI_DATA register. RBNEIE empty Read or write SPI_STAT register, CONFERR Configuration fault error then write SPI_CTL0 register. Read SPI_DATA register, then read RXORERR Rx overrun error ERRIE SPI_STAT register.
Page 719: Figure 23-18. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32L23x User Manual I2S_CK is the serial clock signal, which shares the same pin with SPI_SCK. I2S_WS is the frame control signal, which shares the same pin with SPI_NSS. I2S_SD is the serial data signal, which shares the same pin with SPI_MOSI. I2S_MCK is the master clock signal. It produces a frequency rate equal to 256 x Fs, and Fs is the audio sampling frequency.
Page 720: Figure 23-19. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32L23x User Manual Figure 23-19. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data I2S_SD When the packet type is 16-bit data packed in 16-bit frame, only one write or read operation the transmission of to or from the SPI_DATA register is needed to complete a frame.
Page 721: Figure 23-24. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32L23x User Manual bit data D[23:0] is going to be sent, the first data written to the SPI_DATA register should be the higher 16 bits: D[23:8], and the second one should be a 16-bit data. The higher 8 bits of this 16-bit data should be D[7:0] and the lower 8 bits can be any value.
Page 722: Figure 23-28. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32L23x User Manual Figure 23-28. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 23-29. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 723: Figure 23-34. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32L23x User Manual than the data length, the valid data is aligned to LSB for LSB justified standard while the valid data is aligned to MSB for MSB justified standard. The timing diagrams for the cases that the channel length is greater than the data length are shown below. Figure 23-34.
Page 724: Figure 23-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32L23x User Manual PCM standard For PCM standard, I2S_WS and I2S_SD are updated on the rising edge of I2S_CK, and the I2S_WS signal indicates frame synchronization information. Both the short frame synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register.
Page 725: Figure 23-43. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32L23x User Manual (DTLEN=01, CHLEN=1, CKPL=0) Figure 23-43. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 23-44. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 frame 2 16-bit data 16-bit 0 Figure 23-45.
Page 726: Figure 23-48. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32L23x User Manual (DTLEN=00, CHLEN=0, CKPL=1) Figure 23-48. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 23-49. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2 13 bits 32 bits Figure 23-50.
Page 727: Figure 23-53. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32L23x User Manual Figure 23-53. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 I2S_CK 13 bits I2S_WS 16-bit data 16-bit 0 I2S_SD I2S clock 23.4.4. Figure 23-54. Block diagram of I2S clock generator 8-bit I2SCLK Configurable...
Page 728: Table 23-8. Audio Sampling Frequency Calculation Formulas
GD32L23x User Manual Table 23-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) Operation 23.4.5.
Page 729: Figure 23-55. I2S Initialization Sequence
GD32L23x User Manual Figure 23-55. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD[1:0] bits and the PCMSMOD...
Page 730 GD32L23x User Manual and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmit buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 731: Figure 23-56. I2S Master Reception Disabling Sequence
GD32L23x User Manual Figure 23-56. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTD==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD!=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 732 GD32L23x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 733: Table 23-10. I2S Interrupt
GD32L23x User Manual ◼ Transmission underrun error flag (TXURERR) This situation occurs when the transmit buffer is empty when the valid SCK signal starts in slave transmission mode. ◼ Reception overrun error flag (RXORERR) This situation occurs when the receive buffer is full and a newly incoming data has been completely received.
Page 734 GD32L23x User Manual 23.5. Register definition SPI0 base address: 0x4001 3000 SPI1/ I2S1 base address: 0x4000 3800 Control register 0 (SPI_CTL0) 23.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 735 GD32L23x User Manual received. FF16 Data frame format (for SPI1) 0: 8-bit data frame format 1: 16-bit data frame format CRCL CRC length (only for SPI0) 0: 8-bit crc length. 1: 16-bit crc length. Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN...
Page 736 GD32L23x User Manual MSTMOD Master mode enable 0: Slave mode 1: Master mode CKPL Clock polarity selection 0: CLK pin is pulled low when SPI is idle. 1: CLK pin is pulled high when SPI is idle. CKPH Clock phase selection 0: Capture the first data at the first clock transition.
Page 737 GD32L23x User Manual This bit is used to indicate the access size to FIFO, and set the threshold of the RXFIFO that generate RBNE. 0: Half-word access, and RBNE is generated when RXLVL >= 2. 1: Byte access, and RBNE is generated when RXLVL >= 1. 11:8 DZ[3:0] Date size (only for SPI0)
Page 738 GD32L23x User Manual DMAREN Receive buffer / RXFIFO DMA enable 0: Receive buffer / RXFIFO DMA is disabled. 1: Receive buffer / RXFIFO DMA is enabled, when the RBNE bit in SPI_STAT is set, it will be a DMA request on corresponding DMA channel. Status register (SPI_STAT) 23.5.3.
Page 739 GD32L23x User Manual TRANS Transmitting ongoing bit 0: SPI is idle. 1: SPI is currently transmitting and/or receiving a frame. This bit is set and cleared by hardware. RXORERR Reception overrun error bit 0: No reception overrun error occurs. 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register.
Page 740 GD32L23x User Manual Reset value: 0x0000 0000 For SPI0, this register can be accessed by byte (8-bit) or half-word (16-bit).For SPI1, this register can be accessed by half-word (16-bit) or word (32-bit). Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register.
Page 741 GD32L23x User Manual 31:16 Reserved Must be kept at reset value 15:0 CRCPOLY[15:0] CRC polynomial register This register contains the CRC polynomial and it is used for CRC calculation. The default value is 0007h. Receive CRC register (SPI_RCRC) 23.5.6. Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit).
Page 742 GD32L23x User Manual TCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 TCRC[15:0] TX CRC value When the CRCEN bit of SPI_CTL0 is set, the hardware computes the CRC value of the transmitted bytes and saves them in TCRC register. For SPI1, if the data frame format is set to 8-bit data, CRC calculation is based on CRC8 standard, and saves the value in TCRC[7:0], when the data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC[15:0].
Page 743 GD32L23x User Manual This bit should be configured when SPI/I2S is disabled. I2SEN I2S enable 0: I2S is disabled 1: I2S is enabled This bit is not used in SPI mode. I2SOPMOD[1:0] I2S operation mode 00: Slave transmission mode 01: Slave reception mode 10: Master transmission mode 11: Master reception mode This bit should be configured when I2S mode is disabled.
Page 744 GD32L23x User Manual 1: 32 bits The channel length must be equal to or greater than the data length. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. I2S clock prescaler register (SPI_I2SPSC) 23.5.9.
Page 745 GD32L23x User Manual Reserved IO23_DR Reserved QMOD Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. IO23_DRV Drive IO2 and IO3 enable 0: IO2 and IO3 are not driven in single wire mode. 1: IO2 and IO3 are driven to high in single wire mode. This bit is only available in SPI0.
Page 746: Figure 24-1. Precision Reference Connection For Gd32L233Xx
GD32L23x User Manual VREF Overview 24.1. A precision internal reference circuit is inside. The precision internal reference is used to provide reference voltage for ADC/DAC, or used by off-chip circuit connecting to V pin. Characteristics 24.2. The precision internal reference features are described as follows: ◼...
Page 747: Figure 24-2. Precision Reference Connection For Gd32L235Xx
GD32L23x User Manual Figure 24-2. Precision Reference Connection for GD32L235xx To External Circuitry 2.5V/2.048V Voltage Reference 1uF/(1uF+10nF) The internal reference voltage can be configured in four different modes depending on VREFEN and HIPM bits configuration. These modes are provided in the table below: Table 24-1 VREF MODES VREFEN HIPM...
Page 748 GD32L23x User Manual Control and status register (VREF_CS) 24.4.1. For GD32L233xx devices Address offset: 0x00 Reset value: 0x0000 0002 This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved VREFRDY Reserved HIPM VREFEN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. VREFRDY VREF ready 0: The VREF output is not ready.
Page 749 GD32L23x User Manual 31:4 Reserved Must be kept at reset value. VREFRDY VREF ready 0: The VREF output is not ready. 1: The VREF output is ready. VREFS Voltage reference select This bit sets the value of voltage reference output by the VREF 0: The voltage reference is around 2.048 V.
Page 750 GD32L23x User Manual Segment LCD controller (SLCD) Overview 25.1. The SLCD controller directly drives LCD displays by creating the AC segment and common voltage signals automatically. It can drive the monochrome passive liquid crystal display (LCD) which composed of a plurality of segments (pixels or complete symbols) that can be converted to visible or invisible.
Page 751: Figure 25-1. Slcd Block Diagram
GD32L23x User Manual Figure 25-1. SLCD Block Diagram COM0...7 control signal ANALOG matrix SEG0...31 data data The SLCD REG is the register of SLCD controller, which configured by APB bus, and generate interrupt to CPU. It includes SLCD_CTL, SLCD_CFG, SLCD_STAT, SLCD_STATC, SLCD_DATAx registers.
Page 752: Figure 25-2. 1/3 Bias, 1/4 Duty
GD32L23x User Manual Note: The DUTY is the number defined as 1/ (the number of common terminals on a given SLCD display). The SOF bit in SLCD_STAT register is set by the hardware at the start of the frame, and the SLCD interrupt is executed if the SOFIE bit in SLCD_CFG is set.
Page 753: Table 25-1. The Odd Frame Voltage
GD32L23x User Manual Table 25-1. The odd frame voltage BIAS Static 1/2 bias 1/3 bias 1/4 bias COM active VSLCD VSLCD VSLCD VSLCD COM inactive 1/2 VSLCD 1/3 VSLCD 1/4 VSLCD SEG active SEG inactive VSLCD VSLCD 2/3 VSLCD 1/2 VSLCD Table 25-2.
Page 754: Figure 25-3. 1/4 Bias, 1/6 Duty
GD32L23x User Manual Figure 25-3. 1/4 Bias, 1/6 Duty VSLCD 3/4VSLCD COM0 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM2 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM3 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM5 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD SEG2 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD SEG4 1/2VSLCD 1/4VSLCD DEAD time: The dead time is using DTD bits in SLCD_CFG register.
Page 755 GD32L23x User Manual Double buffer memory 25.3.5. The double buffer memory is used to ensure the coherency of the displayed information. The application access the first buffer according to modify the SLCD_DATAx registers. After writing the displayed information into the SLCD_DATAx registers, the application need to set the UPRF bit in SLCD_STAT register, then the hardware will transfer the data from the first buffer to the seconed buffer, during this time, the UPRF keeps set and the SLCD_DATAx registers are write protected.
Page 756: Figure 25-5. Slcd Resistr Divider Network For Gd32L233 Series
GD32L23x User Manual Figure 25-5. SLCD Resistr divider network for GD32L233 series SLCD SLCDrai l3 SLCDrai l2 SLCDrai l1 Figure 25-6. SLCD Resistr divider network for GD32L235 series SLCD SLCDrai l3 SLCDrai l2 SLCDrai l1 During the transitions, the low value resistors (R ) are switched on to increase the current in order to quickly reach the static state.
Page 757 GD32L23x User Manual can only be configured when the SLCD controller is not activated. Note: GD32L235 series does not support enhance mode. voltage source 25.3.7. SLCD voltage monitoring: SLCD The VSLCDEN bit in the ADC_CTL1 register is used to measure the V voltage.
Page 758 GD32L23x User Manual For GD32L233 and GD32L235 series, when the SLCD selects an external voltage source, th the VSRC should be configured 1’b1 and the PD6 pin needs to be configured in analog mode and connected to an external voltage source. When an SLCD selects an external voltage source, the following procedure should be followed.
Page 759 GD32L23x User Manual 25.4. Register definition SLCD base address: 0x4000 2400 Control register (SLCD_CTL) 25.4.1. For GD32L233xx devices Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved VODEN COMS BIAS[1:0] DUTY[2:0] VSRC SLCDON Bits...
Page 760 GD32L23x User Manual 000: Static duty 001: 1/2 duty 010: 1/3 duty 011: 1/4 duty 100: 1/8 duty 101: 1/6 duty 110: Reserved 111: Reserved VSRC SLCD Voltage source Set this bit determines which is the SLCD voltage source. 0: Internal source 1: External source (VSLCD pin) SLCDON SLCD controller start...
Page 761 GD32L23x User Manual 00: 1/4 Bias (5 voltage levels: VSS, 1/4VSLCD, 1/2VSLCD, 3/4VSLCD, VSLCD) 01: 1/2 Bias (3 voltage levels: VSS, 1/2VSLCD, VSLCD) 10: 1/3 Bias (4 voltage levels: VSS, 1/3VSLCD, 2/3VSLCD, VSLCD) 11: Reserved DUTY[2:0] Duty select These bits determine the duty cycle. Duty is the number defined as 1/(number of common terminals on a given SLCD display).
Page 762 GD32L23x User Manual 31:26 Reserved Must be kept at reset value. 25:22 PSC[3:0] SLCD clock prescaler Set these bits define the prescaler of SLCD clock. 0000: f in_clk 0001: f in_clk 0010: f in_clk 1111: f /32768 in_clk 21:18 DIV[3:0] SLCD clock divider Set these bits define the division factor of the DIV divider.
Page 763 GD32L23x User Manual 111: VSLCD7 DTD[2:0] Dead time duration Set these bits configure the length of the dead time between frames. 000: No dead time 001: 1 phase dead time 010: 2 phase dead time 111: 7 phase dead time PULSE[2:0] Pulse ON duration Set these bits define the pulse duration in terms of PSC pulses.
Page 764 GD32L23x User Manual Reserved RSEL PSC[3:0] DIV[3:0] BLKMOD[1:0] BLKDIV[2:0] Reserved DTD[2:0] PULSE[2:0] UPDIE Reserved SOFIE HDEN Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:26 RSEL[1:0] Weak driving resistance select 00: 6M 01: 4M 10: 2M 11: 1M 25:22 PSC[3:0] SLCD clock prescaler...
Page 765 GD32L23x User Manual 111: f /1024 BLINK SLCD 12:10 Reserved Must be kept at reset value. DTD[2:0] Dead time duration Set these bits configure the length of the dead time between frames. 000: No dead time 001: 1 phase dead time 010: 2 phase dead time 111: 7 phase dead time PULSE[2:0]...
Page 766 GD32L23x User Manual Reset value: 0x0000 0020 This register has to be accessed by word(32-bit). Reserved Reserved SYNF VRDYF UPDF UPRF Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. SYNF SLCD_CFG register synchronization flag This bit is set when SLCD_CFG register update to SLCD clock domain, and It is cleared by hardware when writing to the SLCD_CFG register.
Page 767 GD32L23x User Manual 0: SLCD Controller disabled. 1: SLCD Controller enabled For GD32L235xx devices Address offset: 0x08 Reset value: 0x0000 0020 This register has to be accessed by word(32-bit). Reserved Reserved SYNF Reserved UPDF UPRF Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
Page 768 GD32L23x User Manual SLCD controller on flag This bit is set by hardware when SLCDON is set to 1, it is cleard by hardware after the SLCDON is cleared and the last frame is displayed. 0: SLCD Controller disabled. 1: SLCD Controller enabled Status flag clear register (SLCD_STATC) 25.4.4.
Page 769 GD32L23x User Manual DATAx[15:0] Bits Fields Descriptions 31:0 SEG_DATAx[31:0] Each bit corresponds to one pixel to display. 0: Pixel inactive 1: Pixel active...
Page 770 GD32L23x User Manual Comparator (CMP) Overview 26.1. The general purpose CMP can work either standalone (all terminal are available on I / Os) or together with the timers. It can be used to wake up the MCU from low-power mode by an analog signal, provide a trigger source when an analog signal is in a certain condition.
Page 771: Figure 26-1. Cmp Block Diagram
GD32L23x User Manual Figure 26-1. CMP block diagram CMP0BLK[2:0] Polarity Selection CMP0PL CMP0MSEL[2:0] WINDOW MODE CMP1PSEL[2:0] CMP1BLK[2:0] Polarity Selection CMP1PL CMP1MSEL[2:0] Note: V is 1.2V. REFINT CMP clock 26.3.1. The clock of the CMP which is connected to APB bus, is synchronous with PCLK. CMP I / O configuration 26.3.2.
Page 772: Table 26-1 Cmp Inputs And Outputs Summary
GD32L23x User Manual ◼ CMP output to the TIMER input channel. In order to work even in Deep-sleep mode, the polarity selection logic and the output redirection to the port work independently from PCLK. Table 26-1 CMP inputs and outputs summary details the inputs and outputs of the CMP.
Page 773: Figure 26-2. Cmp Hysteresis
GD32L23x User Manual CMP hysteresis 26.3.5. In order to avoid spurious output transitions that caused by the noise signal, a programmable hysteresis is designed to force the hysteresis value by configuring CMPx_CS register. This function could be shut down if it is unnecessary. Figure 26-2.
Page 774: Figure 26-3 The Cmp Outputs Signal Blanking
GD32L23x User Manual Figure 26-3 The CMP outputs signal blanking CMP_IM CMP_IP Blanking signal CMP outputs raw singal CMP outputs final singal CMP voltage scaler function 26.3.8. The voltage scaler function can provide selectable 1 / 4, 1 / 2, 3 / 4 reference voltage for CMP input.
Page 775 GD32L23x User Manual 26.4. Register definition CMP base address: 0x4001 7C00 CMP0 Control / Status register (CMP0_CS) 26.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP0LK CMP0O Reserved CMP0SEN CMP0BEN Reserved CMP0BLK[2:0] CMP0HST[1:0] CMP0PL...
Page 776 GD32L23x User Manual 000: No blanking 001: Select TIMER1_CH1 output compare signal as blanking source 010: Select TIMER2_CH1 output compare signal as blanking source 011: Select TIMER8_CH1 output compare signal as blanking source 100: Select TIMER11_CH1 output compare signal as blanking source 101~111: Reserved 17:16 CMP0HST[1:0]...
Page 777 GD32L23x User Manual 11: Low speed / low power Reserved Must be kept at reset value. CMP0EN CMP0 enable 0: CMP0 disabled 1: CMP0 enabled CMP1 Control / Status register (CMP1_CS) 26.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1LK CMP1O Reserved...
Page 778 GD32L23x User Manual 20:18 CMP1BLK[2:0] CMP1 output blanking source This bit is used to select which timer output controls the CMP1 output blanking. 000: No blanking 001: Select TIMER1_CH1 output compare signal as blanking source 010: Select TIMER2_CH1 output compare signal as blanking source 011: Select TIMER8_CH1 output compare signal as blanking source 100: Select TIMER11_CH1 output compare signal as blanking source All other values: reserved...
Page 779 GD32L23x User Manual 000: V REFINT 001: V REFINT 010: V * 3 / 4 REFINT 011: V REFINT 100: PA2 101: PA4 (DAC0_OUT0) 110: PB3 111: Reserved CMP1M[1:0] CMP1 mode These bits are used to control the operating mode of the CMP1 adjust the speed / consumption.
Page 780 GD32L23x User Manual Controller area network (CAN) Overview 27.1. CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A and B.
Page 781: Figure 27-1. Can Module Block Diagram
GD32L23x User Manual Function overview 27.3. Figure 27-1. CAN module block diagram shows the CAN block diagram. Figure 27-1. CAN module block diagram Transmit Receive CAN Tx/Rx mailbox[0..2] FIFO[0..1] Working mode 27.3.1. The CAN interface has three working modes: Sleep working mode. ◼...
Page 782 GD32L23x User Manual the IWS bit in CAN_STAT register is set. Initial working mode to sleep working mode: set SLPWMOD bit and clear IWMOD bit in CAN_CTL register. Initial working mode to normal working mode: clear IWMOD bit and clear SLPWMOD bit in CAN_CTL register.
Page 783: Figure 27-2. Transmission Register
GD32L23x User Manual Loopback and silent communication mode Loopback and silent communication mode means the RX and TX pins are disconnected from the CAN network while the transmitted messages are transferred into the Rx FIFOs. Setting LCMOD and SCMOD bit in CAN_BT register to enter loopback and silent communication mode, while clearing them to leave.
Page 784: Figure 27-3. State Of Transmit Mailbox
GD32L23x User Manual Figure 27-3. State of transmit mailbox. free (empty state). As is shown in Figure 27-3. State of transmit mailbox Transmit status and error The CAN_TSTAT register includes the transmit status and error bits: MTF, MTFNERR, MAL, MTE. ◼...
Page 785: Figure 27-4. Reception Register
GD32L23x User Manual Priority When more than one transmit mailbox is pending, the transmission order is given by the TFO bit in CAN_CTL register. In case that TFO is 1, the three transmit mailboxes work first-in first-out (FIFO). In case that TFO is 0, the transmit mailbox with lowest identifier has the highest priority of transmission.
Page 786: Figure 27-5. 32-Bit Filter
GD32L23x User Manual CAN_RFIFOMI0, CAN_RFIFOMP0, CAN_RFIFOMDATA00 and CAN_RFIFOMDATA10 registers. After reading the current frame, set RFD bit in CAN_RFIFO0 to release a frame in the Rx FIFO and the software can read the next frame. Rx FIFO status RFL (Rx FIFO length) bits in CAN_RFIFOx register is 0 when no frame is stored in the Rx FIFO and it is 3 when FIFOx is full.
Page 787: Figure 27-6. 16-Bit Filter
GD32L23x User Manual Figure 27-6. 16-bit filter Mask mode For the Identifier of a data frame to be filtered, the mask mode is used to specify which bits must be the same as the preset Identifier and which bits need not be judged. 32-bit mask Figure 27-7.
Page 788 GD32L23x User Manual Table 27-1. 32-bit filter number Filter Filter Filter data register bank number F0DATA0-32bit-ID F0DATA1-32bit-Mask F1DATA0-32bit-ID F1DATA1-32bit-ID Associated FIFO 28 banks can be associated with FIFO0 or FIFO1. If the bank is associated with FIFO0, the frames passed the bank will be stored in the FIFO0. Active The filter bank needs to be activated if the bank is to be used, otherwise, the filter bank should be left deactivated.
Page 789: Table 27-2. Filtering Index
GD32L23x User Manual Table 27-2. Filtering index Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank nunber bank nunber F0DATA0-32bits-ID F2DATA0[15:0]-16bits-ID F2DATA0[31:16]-16bits- F0DATA1-32bits-Mask Mask F1DATA0-32bits-ID F2DATA1[15:0]-16bits-ID F2DATA1[31:16]-16bits- F1DATA1-32bits-ID Mask F3DATA0[15:0]-16bits-ID F4DATA0-32bits-ID F3DATA0[31:16]-16bits- F4DATA1-32bits-Mask Mask F3DATA1[15:0]-16bits-ID F5DATA0-32bits-ID F3DATA1[31:16]-16bits- F5DATA1-32bits-ID Mask F7DATA0[15:0]-16bits-ID F6DATA0[15:0]-16bits-ID F7DATA0[31:16]-16bits- F6DATA0[31:16]-16bits- ID...
Page 790 GD32L23x User Manual Time-triggered communication 27.3.6. The time-triggered CAN protocol is a higher layer protocol on top of the CAN data link layer. Time-triggered communication means that activities are triggered by the elapsing of time segments. In a time-triggered communication system, all time points of message transmission are pre-defined.
Page 791: Figure 27-11. The Bit Time
GD32L23x User Manual delay segment and Phase buffer segment 1 in the CAN standard. Its duration is programmable from 1 to 16 time quanta but it may be automatically lengthened to compensate for positive phase drifts due to different frequency of the various nodes of the network.
Page 792 GD32L23x User Manual Error flags 27.3.8. The state of CAN bus can be reflected by Transmit Error Counter (TECNT) and Receive Error Counter (RECNT) of CAN_ERR register. The value can be increased or decreased by the hardware according to the error, and the software can judge the stability of the CAN network by these values.
Page 793 GD32L23x User Manual Receive FIFO0 interrupt The Rx FIFO0 interrupt can be generated by the following conditions: ◼ Rx FIFO0 not empty: RFL0 bits in the CAN_RFIFO0 register are not ‘00’ and RFNEIE0 in CAN_INTEN register is set. ◼ Rx FIFO0 full: RFF0 bit in the CAN_RFIFO0 register is set and RFFIE0 in CAN_INTEN register is set.
Page 794 GD32L23x User Manual CAN registers 27.4. CAN0 base address: 0x4000 6400 Control register (CAN_CTL) 27.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit). Reserved SLPWMO SWRST Reserved ABOR RFOD IWMOD Bits Fields Descriptions 31:17 Reserved Must be kept at reset value.
Page 795 GD32L23x User Manual 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission 1: Disable automatic retransmission RFOD Rx FIFO overwrite disable 0: Enable Rx FIFO overwrite when Rx FIFO is full and overwrite the FIFO with the incoming frame 1: Disable Rx FIFO overwrite when Rx FIFO is full and discard the incoming frame Tx FIFO order...
Page 796 GD32L23x User Manual Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
Page 797 GD32L23x User Manual This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed.
Page 798 GD32L23x User Manual TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty. These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted at last if all mailboxes are full.
Page 799 GD32L23x User Manual MAL1 Mailbox 1 arbitration lost This bit is set when the arbitration lost occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when next transmit starts.
Page 800 GD32L23x User Manual Receive message FIFO0 register (CAN_RFIFO0) 27.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RFD0 Rx FIFO0 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO0.
Page 801 GD32L23x User Manual Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w1 rc_w1 Bits Fields Descriptions Must be kept at reset value. 31:6 Reserved Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. RFD1 This bit is reset by hardware when the dequeuing is done.
Page 802 GD32L23x User Manual 1: Sleep working interrupt enabled Wakeup interrupt enable 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled ERRIE Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled 14:12 Reserved Must be kept at reset value. ERRNIE Error number interrupt enable 0: Error number interrupt disabled 1: Error number interrupt enabled...
Page 803 GD32L23x User Manual 0: Rx FIFO0 not empty interrupt disabled 1: Rx FIFO0 not empty interrupt enabled TMEIE Transmit mailbox empty interrupt enable 0: Transmit mailbox empty interrupt disabled 1: Transmit mailbox empty interrupt enabled Error register (CAN_ERR) 27.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 804 GD32L23x User Manual hardware. WERR Warning error Whenever the TECNT or RECNT is greater than or equal to 96, the bit will be set by hardware. Bit timing register (CAN_BT) 27.4.8. Address offset: 0x1C Reset value: 0x0123 0000 This register has to be accessed by word(32-bit). SCMOD LCMOD Reserved...
Page 805 GD32L23x User Manual Transmit mailbox identifier register (CAN_TMIx) (x = 0…2) 27.4.9. Address offset: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (bit0 = 0) This register has to be accessed by word(32-bit). SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:1 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier...
Page 806 GD32L23x User Manual TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value. TSEN Time stamp enable 0: Time stamp disabled 1: Time stamp enabled. The TS[15:0] will be transmitted in the DB6 and DB7 in This bit is available when the TTC bit in CAN_CTL is set.
Page 807 GD32L23x User Manual Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) 27.4.12. Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8...
Page 808 GD32L23x User Manual EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame 1: Extended format frame Frame type 0: Data frame 1: Remote frame Reserved Must be kept at reset value. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x = 0, 1) 27.4.14.
Page 809 GD32L23x User Manual DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x = 0, 1) 27.4.16. Address offset: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 810 GD32L23x User Manual Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. Filter lock disable 0: Filter lock enabled 1: Filter lock disabled Filter mode configuration register (CAN_FMCFG) 27.4.18. Address offset: 0x204 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set.
Page 811 GD32L23x User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter scale 0: Filter x with 16-bit scale 1: Filter x with 32-bit scale Filter associated FIFO register (CAN_FAFIFO) 27.4.20. Address offset: 0x214 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 812 GD32L23x User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter working 0: Filter x working disabled 1: Filter x working enabled Filter x data y register (CAN_FxDATAy) (x = 0…27, y = 0, 1) 27.4.22.
Page 813: Figure 28-1. Usbd Block Diagram
GD32L23x User Manual Universal Serial Bus full-speed device interface (USBD) Overview 28.1. The Universal Serial Bus full-speed device interface (USBD) module provides a device solution for implementing a USB 2.0 full-speed compliant peripheral. It contains a full-speed internal USB PHY and no more external PHY chip is needed. USBD supports all the four types of transfer (control, bulk, interrupt and isochronous) defined in USB 2.0 protocol.
Page 814: Table 28-1. Usbd Signal Description
GD32L23x User Manual Signal description 28.4. Table 28-1. USBD signal description I/O port Type Description VBUS Input Bus power port Input / Output Differential data line – port Input / Output Differential data line + port Note: As soon as the USBD is enabled, these pins are connected to the USBD internal transceiver automatically.
Page 815 GD32L23x User Manual ◼ Programmable buffer starting address and buffer length. ◼ Configurable response to a packet. ◼ Control transfer (only for endpoint 0). Endpoint buffer The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus.
Page 816: Figure 28-2. An Example With Buffer Descriptor Table Usage (Usbd_Baddr = 0)
GD32L23x User Manual Figure 28-2. An example with buffer descriptor table usage (USBD_BADDR = 0) offset 0x1FF IN endpoint 1 double buffer 0 IN endpoint 1 double buffer 1 Endpoint 0 reception buffer Endpoint 0 transmission buffer COUNT1_TX1 ADDR1_TX1 COUNT1_TX0 Endpoint 1 buffer descriptor (double buffer) ADDR1_TX0 COUNT0_RX...
Page 817: Table 28-2. Double-Buffering Buffer Flag Definition
GD32L23x User Manual Table 28-2. Double-buffering buffer flag definition Buffer flag Tx endpoint Rx endpoint TX_DTG (USBD_EpxCS bit 6) RX_DTG (USBD_EpxCS bit 14) SW_BUF RX_DTG (USBD_EpxCS bit 14) TX_DTG (USBD_EpxCS bit 6) The DTG bit and the SW_BUF bit are responsible for the flow control. When a transfer completes, the USB peripheral toggle the DTG bit;...
Page 818 GD32L23x User Manual After the transaction process is completed, an endpoint-specific interrupt is generated. In the interrupt routine, the application can process it accordingly. Transaction formatting is performed by the hardware, including CRC generation and checking. Once the endpoint is enabled, endpoint control and status register, buffer address and COUNT filed should not be modified by the application software.
Page 819 GD32L23x User Manual length of data is greater than actually allocated length, the excess data are not copied. This is a buffer overrun situation. A STALL handshake is sent, and this transaction fails. If an addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the ACK, according to the endpoint status and no data is written to the endpoint data buffers.
Page 820 GD32L23x User Manual the data transmission or reception of data in another buffer. The DTOG bit indicates which buffer that the USB peripheral is currently using. The application software initializes the DTOG according to the first buffer to be used. At the end of each transaction, the RX_ST or TX_ST bit is set, depending on the enabled direction regardless of CRC errors or buffer-overrun conditions (if errors occur, the ERRIF bit will be set).
Page 821 GD32L23x User Manual ◼ A device in the non-configured state should draw a maximum of 100mA from the USB bus. ◼ A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor. The maximum value is 500mA. ◼...
Page 822 GD32L23x User Manual 2. Clear USBD_INTF register to remove any spurious pending interrupt. 3. Program USBD_BADDR register to set endpoint buffer base address. 4. Set USBD_CTL register to enable interrupts. 5. Wait for the reset interrupt (RSTIF). 6. In the reset interrupt, initialize default control endpoint 0 to start enumeration process and program USBD_BADDR to set the device address to 0 and enable USB module function.
Page 823 GD32L23x User Manual 3. Wait for successful transfer interrupt (STIF). 4. In the interrupt handler, application can get the transaction type by reading the STEUP bit in USBD_EpxCS register. Then application will read the data payload from the endpoint data buffer with the start address defined in USBD_EPxRBAR register. Last application will interpret the data and process the corresponding transaction.
Page 824 GD32L23x User Manual Registers definition 28.7. USBD base address: 0x4000 5C00 USBD control register (USBD_CTL) 28.7.1. Address offset: 0x40 Reset value: 0x0000 0003 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved L1RSRE STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE...
Page 825 GD32L23x User Manual 0: Start of frame interrupt disabled 1: Interrupt generated when SOFIF bit in USBD_INTF register is set. ESOFIE Expected start of frame interrupt enable 0: Expected start of frame interrupt disabled 1: Interrupt generated when ESOFIF bit in USBD_INTF register is set. L1REQIE LPM L1 state request interrupt enable 0: LPM L1 state request interrupt disabled...
Page 826 GD32L23x User Manual Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved STIF PMOUIF ERRIF WKUPIF SPSIF RSTIF SOFIF ESOFIF L1REQ Reserved EPNUM[3:0] rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved...
Page 827 GD32L23x User Manual Direction of transaction Set by the hardware to indicate the direction of the transaction 0: OUT type 1: IN type EPNUM[3:0] Endpoint Number Set by the hardware to identify the endpoint which the transaction is directed to USBD status register (USBD_STAT) 28.7.3.
Page 828 GD32L23x User Manual Reserved Reserved USBEN USBDAR[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. USBEN USB device enable Set by software to enable the USB device 0: The USB device disabled. No transactions handled. 1: The USB device enabled. USBDAR[6:0] USBD device address After bus reset, the address is reset to...
Page 829 GD32L23x User Manual Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved RX_ST RX_DTG RX_STA[1:0] SETUP EP_CTL[1:0] EP_KCTL TX_ST TX_DTG TX_STA[1:0] EP_ADDR[3:0] rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. RX_ST Reception successful transferred Set by hardware when a successful OUT/SETUP transaction complete...
Page 830: Table 28-4. Reception Status Encoding
GD32L23x User Manual TX_STA[1:0] Status bits, for transmission transfers Refer to Table 28-7. Transmission status encoding EP_ADDR Endpoint address Used to direct the transaction to the target endpoint Table 28-4. Reception status encoding RX_STA[1:0] Meaning DISABLED: ignore all reception requests of this endpoint STALL: STALL handshake status NAK: NAK handshake status VALID: enable endpoint for reception...
Page 831 GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:1 EPTXBAR[15:1] Endpoint transmission buffer address Start address of the packet buffer containing data to be sent when receive next IN token EPTXBAR[0] Must be set to 0 USBD endpoint transmission...
Page 832 GD32L23x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:1 EPRBAR[15:1] Endpoint reception buffer address Start address of packet buffer containing the data received by the endpoint at the next OUT/SETUP token EPRBAR[0] Must be set to 0 USBD endpoint reception...
Page 833 GD32L23x User Manual Reserved RHIRD BLSTAT[3:0] REMWK Reserved LPMACK LPMEN Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 CHIRD Configured HIRD value 15:12 Reserved Must be kept at reset value 11:8 RHIRD Received HIRD value BLSTAT[3:0] bLinkState value This filed contain the bLinkState value received with last ACKed LPM token.
Page 834 GD32L23x User Manual 31:16 Reserved Must be kept at reset value. DPUEN DP pull-up control. 0:Disable the embedded pull-up on the DP line, disconnect to host. 1:Enable the embedded pull-up on the DP line, connect to host. 14:0 Reserved Must be kept at reset value...
Page 835: Table 29-1. List Of Abbreviations Used In Register
GD32L23x User Manual Document appendix List of abbreviations used in registers 29.1. Table 29-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. Read-only ® Software can only read this bit. Write-only (w) Software can only write to this bit.
Page 836: Table 30-1. Revision History
GD32L23x User Manual Revision history Table 30-1. Revision history Revision No. Description Date Initial Release Jul. 2023 Delete some power saving modes supported by GD32L235 Oct.30,2023 from the Power management unit (PMU) Section 1.3.1 Added parity check support for GD32L235xx SRAM Changed the start address 0x0803E000 on page 63 in Table 2.1 to 0x0803F000 Revise the description of optional voltages for NPLDO and...
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