GigaDevice Semiconductor GD32VF103 Manuals

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GigaDevice Semiconductor GD32VF103 User Manual (536 pages)

RISC-V 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 10 MB

Table of Contents

2
List of Figures

14
List of Tables

20
1 System and Memory Architecture

22
- Risc-V Cpu
  22
- System Architecture
  22
- Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix
  
  23
- Figure 1-1. GD32VF103 System Architecture
  
  24
- Memory Map
  24
  - Table 1-2. Memory Map of GD32VF103 Devices
    
    25
    
    Table 1-3. Boot Modes
    29
    
    Table 2-1. Base Address and Size for Flash Memory
    32
    
    Page Erase
    33
    
    Read Operations
    33
    
    Unlock the FMC_CTL Registers
    33
  - Memory Density Information
    30
  - Unique Device ID (96 Bits)
    30
- On-Chip Flash Memory Overview
  28
- On-Chip SRAM Memory
  28
- Boot Configuration
  29
- Device Electronic Signature
  29
2 Flash Memory Controller (FMC)

32
- Characteristics
  32
- Function Overview
  32
  - Flash Memory Architecture
    32
- Overview
  32
  - Figure 2-1. Process of Page Erase Operation
    
    34
    
    Figure 2-2. Process of Mass Erase Operation
    35
    
    Figure 2-3. Process of Word Program Operation
    37
    
    Option Bytes Erase
    37
    
    Option Bytes Description
    38
    
    Option Bytes Modify
    38
    
    Table 2-2. Option Byte
    38
    
    Page Erase/Program Protection
    39
    
    Security Protection
    40
    
    Register Definition
    41
    
    Unlock Key Register (FMC_KEY)
    41
    
    Wait State Register (FMC_WS)
    41
    
    Option Byte Unlock Key Register (FMC_OBKEY)
    42
    
    Status Register (FMC_STAT)
    42
    
    Control Register (FMC_CTL)
    43
    
    Address Register (FMC_ADDR)
    44
    
    Erase/Program Protection Register (FMC_WP)
    45
    
    Option Byte Status Register (FMC_OBSTAT)
    45
    
    Product ID Register (FMC_PID)
    46
  - Main Flash Programming
    35
- Mass Erase
  34
3 Power Management Unit (PMU)

47
- Characteristics
  47
- Figure 3-1. Power Supply Overview
  
  47
- Function Overview
  47
- Overview
  47
- Battery Backup Domain
  48
- VDD /V Dda
  48
- Power Domain
  51
- Power Saving Modes
  51
4 Backup Registers (BKP)

57
- Overview
  57
- Characteristics
  57
- Function Overview
  57
  - RTC Clock Calibration
    57
  - Tamper Detection
    58
- Register Definition
  59
5 Reset and Clock Unit (RCU)

62
6 Interrupt/Event Controller (EXTI)

94
7 General-Purpose and Alternate-Function I/Os (GPIO and AFIO)

102
- Characteristics
  102
- Function Overview
  102
- Overview
  102
  - Figure 7.1. Basic Structure of a Standard I/O Port Bit
    
    103
    
    Figure 7.2. Input Configuration
    104
    
    Figure 7.3. Output Configuration
    105
    
    Alternate Function (AF) Configuration
    106
    
    Analog Configuration
    106
  - Output Configuration
    105
- Alternate Functions (AF)
  104
- External Interrupt/Event Lines
  104
- Input Configuration
  104
- Figure 7.5. Alternate Function Configuration
  
  106
- Figure 7.4. Analog Configuration
  
  106
- GPIO Locking Function
  107
- IO Pin Function Selection
  107
- Remapping Function I/O and Debug Configuration
  108
  - Introduction
    108
  - JTAG Alternate Function Remapping
    108
  - Main Features
    108
  - Table 7.2. Debug Interface Signals
    
    108
  - Table 7.3. Debug Port Mapping
    
    108
  - Table 7.4. TIMER0 Alternate Function Remapping
    
    109
  - Table 7.6. TIMER2 Alternate Function Remapping
    
    109
  - Table 7.7. TIMER3 Alternate Function Remapping
    
    109
  - Table 7.8. TIMER4 Alternate Function Remapping
    
    110
  - Table 7.9. USART0 Alternate Function Remapping
    
    110
  - USART AF Remapping
    110
  - CAN0 AF Remapping
    111
  - CAN1 AF Remapping
    111
  - SPI0 AF Remapping
    111
  - SPI2/I2S2 AF Remapping
    111
- Table 7.5. TIMER1 Alternate Function Remapping
  
  109
- TIMER AF Remapping
  109
- I2C0 AF Remapping
  110
- Table 7.10. USART1 Alternate Function Remapping
  
  110
- Table 7.14. SPI2/I2S2 Alternate Function Remapping
  
  111
- CLK Pins AF Remapping
  112
8 CRC Calculation Unit (CRC)

129
- Overview
  129
- Characteristics
  129
9 Direct Memory Access Controller (DMA)

133
- Characteristics
  133
- Overview
  133
- Block Diagram
  134
- Figure 9-1. Block Diagram of DMA
  
  134
- Function Overview
  134
  - DMA Operation
    134
    
    Table 9-1. DMA Transfer Operation
    135
    
    Figure 9-2. Handshake Mechanism
    136
    
    Figure 9-3. DMA Interrupt Logic
    138
    
    Interrupt
    138
    
    Table 9-2. Interrupt Events
    138
    
    DMA Request Mapping
    139
  - Peripheral Handshake
    136
  - Address Generation
    137
  - Channel Configuration
    137
  - Circular Mode
    137
  - Memory to Memory Mode
    137
- Arbitration
  136
- Table 9-4. DMA1 Requests for each Channel
  
  139
- Table 9-3. DMA0 Requests for each Channel
  
  139
- Figure 9-4. DMA0 Request Mapping
  
  139
- Figure 9-5. DMA1 Request Mapping
  
  140
- Register Definition
  142
10 Debug (DBG)

148
- Overview
  148
- JTAG Function Overview
  148
  - Pin Assignment
    148
  - JTAG Daisy Chained Structure
    148
  - Debug Reset
    149
- Debug Hold Function Overview
  149
  - Debug Support for Power Saving Mode
    149
  - Debug Support for TIMER, I2C, WWDGT, FWDGT and CAN
    149
- Register Definition
  150
  - ID Code Register (DBG_ID)
    150
  - Control Register (DBG_CTL)
    150
11 Analog-To-Digital Converter (ADC)

153
12 Digital-To-Analog Converter (DAC)

188
13 Watchdog Timer (WDGT)

202
- Free Watchdog Timer (FWDGT)
  202
  - Overview
    202
  - Characteristics
    202
  - Function Overview
    202
- Table 13.1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)
  
  203
- Figure 13.1. Free Watchdog Block Diagram
  
  203
- Register Definition
  205
- Window Watchdog Timer (WWDGT)
  208
  - Overview
    208
  - Characteristics
    208
  - Function Overview
    208
- Figure 13.2. Window Watchdog Timer Block Diagram
  
  209
- Table 13.2. Min/Max Timeout Value at 54 Mhz
  
  210
- Register Definition
  211
Figure 13.3. Window Watchdog Timing Diagram

210
14 Real-Time Clock (RTC)

213
- Characteristics
  213
- Function Overview
  213
  - RTC Reset
    214
  - RTC Reading
    214
- Overview
  213
  - Figure 14.1. Block Diagram of RTC
    
    214
    
    Figure 14.2. RTC Second and Alarm Waveform Example (RTC_PSC = 3, RTC_ALRM = 2)
    215
    
    Figure 14.3. RTC Second and Overflow Waveform Example (RTC_PSC= 3)
    216
    
    Table 15-1. Timers (Timerx) Are Devided into Three Sorts
    222
    
    Advanced Timer (Timerx, X=0)
    223
    
    Characteristics
    223
    
    Overview
    223
    
    Block Diagram
    224
    
    Function Overview
    224
  - Register Definition
    217
    
    RTC Control Register(RTC_CTL)
    217
    
    RTC Interrupt Enable Register(RTC_INTEN)
    217
    
    RTC Prescaler High Register (RTC_PSCH)
    218
    
    RTC Divider High Register (RTC_DIVH)
    219
    
    RTC Divider Low Register (RTC_DIVL)
    219
    
    RTC Prescaler Low Register (RTC_PSCL)
    219
    
    RTC Counter High Register (RTC_CNTH)
    220
    
    RTC Counter Low Register (RTC_CNTL)
    220
    
    RTC Alarm High Register (RTC_ALRMH)
    221
    
    RTC Alarm Low Register (RTC_ALRML)
    221
- RTC Configuration
  215
- RTC Flag Assertion
  215
15 Timer(Timerx)

222
16 Universal Synchronous/Asynchronous Receiver /Transmitter (USART)

328
- Characteristics
  328
- Overview
  328
- Function Overview
  329
- USART Frame Format
  330
- USART Receiver
  333
  - Figure 16-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
    
    339
  - Figure 16-14. Irda Data Modulation
    
    340
  - Figure 16-13. Irda SIR ENDEC Module
    
    340
  - Figure 16-15. ISO7816-3 Frame Format
    
    341
  - Table 16-3. USART Interrupt Requests
    
    342
  - USART Interrupts
    342
  - Figure 16-16. USART Interrupt Mapping Diagram
    
    343
  - Register Definition
    344
    
    Status Register (USART_STAT)
    344
    
    Baud Rate Register (USART_BAUD)
    346
    
    Data Register (USART_DATA)
    346
    
    Control Register 0 (USART_CTL0)
    347
    
    Control Register 1 (USART_CTL1)
    349
    
    Control Register 2 (USART_CTL2)
    350
    
    Guard Time and Prescaler Register (USART_GP)
    352
- Figure 16-11. Example of USART in Synchronous Mode
  
  339
- Half-Duplex Communication Mode
  341
- Smartcard (ISO7816-3) Mode
  341
17 Inter-Integrated Circuit Interface (I2C)

354
18 Serial Peripheral Interface/Inter-IC Sound (SPI/I2S)

380
19 External Memory Controller (EXMC)

416
- Characteristics
  416
- Function Overview
  416
  - Block Diagram
    416
  - Basic Regulation of EXMC Access
    417
- Overview
  416
- Figure 19-1. the EXMC Block Diagram
  
  417
- External Device Address Mapping
  418
- Figure 19-3. Region of Bank0 Address Mapping
  
  418
- Figure 19-2. EXMC Memory Banks
  
  418
- NOR/PSRAM Controller
  418
- Table 19-1. nor Flash Interface Signals Description
  
  419
- Table 19-3. EXMC Bank 0 Supports All Transactions
  
  419
- Table 19-2. PSRAM Muxed Signal Description
  
  419
- Table 19-4. nor / PSRAM Controller Timing Parameters
  
  420
- Figure 19-5. Multiplex Mode Write Access
  
  421
- Figure 19-4. Multiplex Mode Read Access
  
  421
- Table 19-5. Exmc_Timing Models
  
  421
- Table 19-6. Multiplex Mode Related Registers Configuration
  
  422
- Figure 19-7. Write Access Timing Diagram under Async-Wait Signal Assertion
  
  423
- Figure 19-6. Read Access Timing Diagram under Async-Wait Signal Assertion
  
  423
- Register Definition
  424
  - NOR/PSRAM Controller Registers
    424
20 Controller Area Network (CAN)

427
- Characteristics
  427
- Overview
  427
- Figure 20-1. CAN Module Block Diagram
  
  428
- Function Overview
  428
  - Working Mode
    428
- Communication Modes
  429
- Data Transmission
  430
  - Figure 20-2. Transmission Register
    
    430
  - Figure 20-3. State of Transmission Mailbox
    
    431
  - Figure 20-4. Reception Register
    
    432
  - Filtering Function
    433
- Data Reception
  432
- Figure 20-5. 32-Bit Filter
  
  434
- Figure 20-10. 16-Bit List Mode Filter
  
  434
- Figure 20-9. 32-Bit List Mode Filter
  
  434
- Figure 20-8. 16-Bit Mask Mode Filter
  
  434
- Time-Triggered Communication
  436
- Communication Parameters
  437
- Error Flags
  438
21 Universal Serial Bus Full-Speed Interface (USBFS)

461
- Characteristics
  461
- Overview
  461
- Block Diagram
  462
- Figure 21-1. USBFS Block Diagram
  
  462
- Function Overview
  462
  - USBFS Clocks and Working Modes
    462
- Signal Description
  462
- Figure 21-2. Connection with Host or Device Mode
  
  463
- Figure 21-3. Connection with OTG Mode
  
  464
- Figure 21-4. State Transition Diagram of Host Port
  
  464
- USB Host Function
  464
- USB Device Function
  466
- OTG Function Overview
  467
- Data FIFO
  468
22 Revision History

535
Table 22-1. Revision History

535

GigaDevice Semiconductor GD32VF103 User Manual (65 pages)

Brand: GigaDevice Semiconductor | Category: Computer Hardware | Size: 2 MB

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Microcontrollers Computer Hardware Motherboard Semiconductors Adapter

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GigaDevice Semiconductor GD32VF103 Manuals

GigaDevice Semiconductor GD32VF103 User Manual (536 pages)

Table of Contents

Table of Contents

List of Figures

List of Tables

1 System and Memory Architecture

Table 1-1. the Interconnection Relationship of the AHB Interconnect Matrix

Figure 1-1. GD32VF103 System Architecture

Table 1-2. Memory Map of GD32VF103 Devices

2 Flash Memory Controller (FMC)

Figure 2-1. Process of Page Erase Operation

3 Power Management Unit (PMU)

Figure 3-1. Power Supply Overview

Figure 3-2. Waveform of the POR/PDR

Figure 3-3. Waveform of the LVD Threshold

Table 3-1. Power Saving Mode Summary

4 Backup Registers (BKP)

5 Reset and Clock Unit (RCU)

Figure 5-1. the System Reset Circuit

Table 5-1. Clock Output 0 Source Select

Table 5-2. 1.2V Domain Voltage Selected in Deep-Sleep Mode

6 Interrupt/Event Controller (EXTI)

Table 6-1. Interrupt Vector Table

Figure 6-1. Block Diagram of EXTI

Table 6-2. EXTI Source

Table 7.1. GPIO Configuration Table

7 General-Purpose and Alternate-Function I/Os (GPIO and AFIO)

Figure 7.1. Basic Structure of a Standard I/O Port Bit

Figure 7.5. Alternate Function Configuration

Figure 7.4. Analog Configuration

Table 7.2. Debug Interface Signals

Table 7.3. Debug Port Mapping

Table 7.4. TIMER0 Alternate Function Remapping

Table 7.6. TIMER2 Alternate Function Remapping

Table 7.7. TIMER3 Alternate Function Remapping

Table 7.8. TIMER4 Alternate Function Remapping

Table 7.9. USART0 Alternate Function Remapping

Table 7.5. TIMER1 Alternate Function Remapping

Table 7.11. USART2 Alternate Function Remapping

Table 7.16. CAN1 Alternate Function Remapping

Table 7.10. USART1 Alternate Function Remapping

Table 7.14. SPI2/I2S2 Alternate Function Remapping

8 CRC Calculation Unit (CRC)

9 Direct Memory Access Controller (DMA)

Figure 9-1. Block Diagram of DMA

Table 9-4. DMA1 Requests for each Channel

Table 9-3. DMA0 Requests for each Channel

Figure 9-4. DMA0 Request Mapping

Figure 9-5. DMA1 Request Mapping

10 Debug (DBG)

11 Analog-To-Digital Converter (ADC)

Figure 11-1. ADC Module Block Diagram

Table 11-1. ADC Internal Signals

Table 11-2. ADC Pins Definition

Figure 11-2. Single Conversion Mode

Figure 11-21. Trigger Occurs During Inserted Conversion

Figure 11-3. Continuous Conversion Mode

Figure 11-4. Scan Conversion Mode, Continuous Disable

Figure 11-5. Scan Conversion Mode, Continuous Enable

Figure 11-6. Discontinuous Conversion Mode

12 Digital-To-Analog Converter (DAC)

Table 12-1. DAC Pins

Table 12-2. External Triggers of DAC

Figure 12-3. DAC Triangle Noise Wave

Figure 12-2. DAC LFSR Algorithm

13 Watchdog Timer (WDGT)

Table 13.1. Min/Max FWDGT Timeout Period at 40 Khz (IRC40K)

Figure 13.1. Free Watchdog Block Diagram

Figure 13.2. Window Watchdog Timer Block Diagram

Table 13.2. Min/Max Timeout Value at 54 Mhz

Figure 13.3. Window Watchdog Timing Diagram

14 Real-Time Clock (RTC)

Figure 14.1. Block Diagram of RTC

15 Timer(Timerx)

Figure 15-1. Advanced Timer Block Diagram

Figure 15-2. Normal Mode, Internal Clock Divided by 1

Figure 15-37. Timing Chart of up Counting Mode, PSC=0/1

Figure 15-49. Pause Mode

Figure 15-50. Event Mode