Target Interface Reference Voltage And Signals; Target Reference Voltage Sensing (Vref); Bidirectional Signal Pins; Output Driver Structure - Xilinx Platform Cable USB II Manual

For a complete description on using Platform Cable USB II for indirect programming of third-BPI PROMs and for a complete
list of supported BPI PROMs, refer to XAPP973, Indirect Programming of BPI PROMs with Virtex-5 FPGAs.

Target Interface Reference Voltage and Signals

Target Reference Voltage Sensing (VREF)

Platform Cable USB II incorporates an over-voltage clamp on the V
clamped voltage (V
REF_CLAMP
Structure). V must be a regulated voltage.
REF
Note:
Do not insert a current-limiting resistor in the target system between the V
When Platform Cable USB II is idle, a nominal amount of current is drawn from the target system V
V current as a function of V
REF
No damage to Platform Cable USB II occurs if the A–B cable is unplugged from the host while the ribbon cable or flying leads
are attached to a powered target system. Similarly, no damage to target systems occurs if Platform Cable USB II is powered
and attached to the target system while the target system power is off.

Bidirectional Signal Pins

Platform Cable USB II provides five bidirectional signal pins: TDI_DIN_MOSI, TDO_DONE_MISO, TCK_CCLK_SCK,
TMS_PROG_SS and HALT_INT_WP. Each pin incorporates the same I/O structure. The state of each pin (reading or
writing) is determined by the current mode of the cable (JTAG, SPI or Slave Serial).

Output Driver Structure

Each output signal is routed through a NC7SZ126 ultra high-speed CMOS buffer
resistors (30.1Ω) reduce reflections. Weak pull-up resistors (20 kΩ) terminating at V
when the buffers are set to high-Z. Schottky diodes provide the output buffers with undershoot protection.
The FPGA sets the output buffers to high-Z when V
clamps V to approximately 3.9V.
REF_CLAMP
Figure 21, page 21 shows the relationship between the output drive voltage and V
Note:
The output drivers are enabled only during cable operations; otherwise, they are set to high-Z between operations.
Xilinx design tools actively drive the outputs to logic 1 before setting the respective buffer to high-Z, avoiding the possibility
of a slow rise-time transition caused by a charge path through the pull-up resistor into parasitic capacitance on the target
system.
DS593 (v1.2.1) March 17, 2011
) supplies high-slew-rate buffers that drive each of the output signals (see
voltage.
REF
REF
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pin of the 2-mm ribbon cable connector. The
REF
supply and pin 2 on the 2-mm connector.
REF
drops below 1.30 V. In addition, an over-voltage Zener on V
Platform Cable USB II
Output Driver
. Figure 19
REF
(Figure 20, page 20). Series-damping
maintain a defined logic level
REF_CLAMP
.
REF
shows the
REF
19