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parity checking is done on the data flow between the channels and instruction
processing function.
For System/370 mode of operation, the fast release function of the START 1/0
FAST RELEASE (SIOF) instruction is implemented in 4381 Processors as is
queuing of SIOF instructions. These two functions are inherent in the design of the
channel subsystem for System/370-XA mode of operation. These facilities reduce
the instruction processing function processing time required for an SIOF instruction
when compared with the time required for a START 1/0 (SIO) instruction.
Optionally, one Channel-to-Channel Adapter can be installed in a 4381 Processor
Model Group 14 or 3 and attached to any block multiplexer channel. The other
channel to which the adapter is attached can be contained in another 4381
Processor or a System/360, System/370, 30XX, 4341, 4361, 4331, or 4321
processor. Three control unit positions on each channel and one nonshared UCW
for each of the two channels interconnected via the 4381 Channel-to-Channel
Adapter are required. The adapter operates in burst mode and transfers data at the
rate of the lower speed channel to which it is attached.
The Channel-to-Channel Adapter provided for 4381 Processors is functionally
equivalent to the adapter provided for System/370 and 4300 processors but is
implemented in a higher density technology that reduces its size.
The 3088 Multisystem Channel Communication Unit can also be used to
interconnect 303X, 308X, 3090, 4341, and 4381 processors via block multiplexer
channels.
Device Addresses and Unit Control Words For System/370 Mode
Each byte multiplexer channel and each block multiplexer channel installed in a
4381 Processor Model Group 14 or 3 can have 256 device addresses (00 to FF).
For each channel group, any device addresses can be used for block multiplexer
channels 1 through 8 or for channel 5 when it is a byte multiplexer channel. For
byte multiplexer channel 0 in the channel group for instruction processing function
0, addresses OFO to OFF are reserved for support processor subsystem devices
attached via the local channel adapter and any device addresses other than these
can be used for the
I/
0 devices attached to byte multiplexer channel 0 via external
control units. Thus, only 240 de~ice addresses (000 to OEF) can be assigned to
user devices natively attached to this channel 0 or via external control units. Any
device addresses can be used for byte multiplexer 0 in the channel group for
instruction processing function 1.
Each instruction processing function in a 4381 Processor Model Group 14 or 3 can
have a minimum of 128 and a maximum of 2048 UCWs as a standard feature for
System/370 mode of operation. UCWs are allocated by the customer engineer or
operator, using the display console. UCWs above 128 are allocated in groups of
64. Each UCW is 64 bytes in size and resides in auxiliary storage. Each group of
64 UCWs requires 4K bytes of storage. Thus, a minimum of 8K bytes and a
maximum of 128K bytes are required for UCW storage.
The UCWs allocated for each instruction processing function are assigned a
three-digit reference number 000 to N-1, where N is the number of UCWs
allocated. UCWs for instruction processing function 0 with the reference numbers
000 to 030 are reserved for internal functions (support processor, for example) and
76
A
Guide to the
IBM
4381 Processor
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