Table of Contents
Advertisement
31-Bit Addressing
The 31-bit addressing capability significantly increases the amount of virtual and
real storage that can be addressed in a virtual storage environment-over 2 billion
bytes versus over 16 million bytes for the 24-bit addressing capability used in 4381
System/370 mode of operation. To maintain problem program compatibility for
System/370 and System/370-XA modes, bimodal operation is supported for
System/370-XA mode that permits concurrent execution of problem programs that
use 24-bit addressing and those that use 31-bit addressing.
The addressing mode in effect is determined by bit 32 in the current PSW. When
bit 32 is zero, 24-bit addressing mode is in effect. When bit 32 is one, 31-bit
addressing is in effect. The addressing mode controls the size of the effective
address generated for instructions and instruction operands. It does not control the
size of PER addresses or of the addresses used to access DAT, ASSN, linkage,
entry, and trace tables. These addresses are always 31 bits in size.
Note that the 24-bit addresses that are generated when 24-bit addressing mode is
in effect are converted to 31-bit addresses by the addition of seven high-order
zeros.
Dynamic Channel Subsystem
The dynamic channel subsystem defined for System/370-XA mode of operation
provides improvements and additional functional capabilities. The major
differences between the channel architecture for System/370-XA mode and
System/370 mode in 4381 Processors are the following:
•
Channels are not assigned a channel number. The instruction processor issues
1/0 requests that specify the 1/0 device to be used. A channel is not
specified. All types of
1/0
requests are queued (not just SIOF requests, as in
System/370 mode of operation), and instruction processing function execution
continues after any
1/0
request is issued without waiting for any status
information from channel control hardware. A new set of 1/0 instructions is
defined for handling 1/0 operations.
•
Channel path management is performed by the channel control function rather
than by the 1/0 supervisor portion of the control program. The channel path
to be used to access an 1/0 device is selected by the channel control function.
When multiple channel paths exist to a device, the set of paths specified for the
device is inspected in the sequence defined by the installation using the
Input/Output Control Program, which is discussed in Section 20:20. The 4381
Processor supports up to four paths per
1/0
device.
•
A dynamic reconnection capability is supported that permits an 1/0 device to
reconnect a disconnected channel program to the first available channel path to
the device when multiple paths to the device exist, rather than only to the
channel path from which the channel program disconnected. This capability is
utilized, for example, by 3880 Storage Control Models 2 and 3 with attached
3380 Model AA4 Direct Access Storage (which has dynamic path selection).
For devices without dynamic path selection, reconnection occurs only to the
path from which the channel program disconnected.
Section 10: Technology and Architecture
25
Advertisement
Table of Contents
