IBM 4381 Manual page 82

The channels read into and write from processor storage using the input/ output
data register in the storage control function. When a channel writes data (input
operation from an
1/0
device), each buffer directory is interrogated. If data from
the affected processor storage address is being maintained in a high-speed buffer,
the channel writes the data to that high-speed buffer and processor storage is not
modified. Otherwise, the data is written to processor storage only.
When a channel attempts a read or write operation, each buffer directory is
interrogated. If the required data is present in the local buffer, the channel read or
write is done from/to that buffer and processor storage is not affected. If the
required data is not present in the local buffer and is either not present or present
and not modified in the other buffer, the channel read or write is done from/to
processor storage. If the required data is not present in the local buffer, but is
present in the other buffer and modified, the block of data is transferred to
processor storage and then the channel read or write is done from/to processor
storage.
The store-in approach used for the high-speed buffers in 4381 Processors is like
that used in 4341, 4331 Model Group 2, 4361, 308X, and 3090 processors but
contrasts with the store-through approach used in the high-speed buffers in
System/370 and 303X processors in which processor storage is altered whenever
data is stored in the buffer. The store-in approach reduces the number of accesses
to processor storage, since changed buffer data is written to processor storage only
if it must be replaced by another block (or when a buffer purge is required). The
store-in approach becomes more and more advantageous as the difference between
processor storage and high-speed buffer storage cycle times becomes greater.
Buffer reconfiguration, which is not implemented in 4341 Processors, is standard in
4381 Processors. If a double-bit error occurs during the loading of a buffer block,
the load is tried once more. If the error is not corrected, buffer reconfiguration is
done, if possible, as part of the instruction retry function. The high-speed buffer
array for each instruction processor in a Model Group 14 or 3 contains spare space
that is used for reconfiguration purposes. When an uncorrectable storage error
occurs in a byte in a buffer block, space in the reconfiguration area is allocated and
a bit is set to indicate the reconfiguration area is to be used for this buffer block.
The buffer load is retried and operations continue using the reconfiguration area
for that buffer block if the load is successful.
If a load is not successful after the reconfiguration (assigned reconfiguration array
location is malfunctioning), the buffer block location that caused the error can no
longer be used and the malfunctioning bit in the directory entry for the
malfunctioning block is turned on. The operator is notified that degradation is
occurring and system operation continues.
Up to eight buffer block errors can be reconfigured as long as no more than one
error occurs in a given byte position within a doubleword. When this limit is
reached, the operator is notified that the buffer should be repaired.
Reconfiguration is also attempted for errors that occur in the swap buffer for the
high-speed buffer in instruction processing function 0. A substitute array for the
swap buffer is provided and, as for a high-speed buffer, up to eight errors can be
reconfigured as long as no more than one error occurs in a given byte-pair position
within a 16-byte data entry in the array. If the reconfiguration limit is reached or
an error occurs in a reconfigured byte position of the swap array, the operator is
notified that repair is required.
Section 30: 4381 Processor Multiprocessor Model Groups
73