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High-Speed Buffer Storage
The high-speed buffer is a standard feature and provides high-speed data access for
instruction processing function fetches and stores. The 43 81 Model Group 14 has
one standard 64Kb high-speed buffer storage for each instruction processing
function. The 4381 Processor Model Group 3 has one standard 32K-byte
high-speed buffer storage for each instruction processing function.
Buffer storage control and use are handled entirely by buffer control function
hardware and are transparent to the programmer, who need not adhere to any
particular program structure in order to obtain close to optimum use of the buffer.
Parity checking is used for data verification in the buffer.
The flow of data from each instruction processing function to and from processor
storage via the high-speed buffers in a 43 81 Model Group 14 or 3 is shown in
Figure 12. One ECC checking function is shared by the two instruction processing
functions. The data flow control logic provides a data path between ( 1) the ECC
checking function and high-speed buffers 0 and 1 for data fetch/store operations
from/to processor storage and (2) high-speed buffers 0 and 1 for interbuffer data
transfers.
Processor
Storage
n
v
ECC
Checking
Logic
~a.
u
Doto Flow
....
...
Doto Flow
Control 0
"""
~
Control 1
.4t.
~a.
,,
Cross
,,
High-speed
....
Interrogation Controls
...
High-speed
Buffer 0
.....
...-
Buffer 1
.4t.
~l
,,
,,
Instruction
Instruction
Processing
Processing
Function 0
Function 1
Figure 12.
Data flow to and from processor storage via the high-speed buffers in a 4381
Model Group 14 or 3
Section 30: 4381 Processor Multiprocessor Model Groups
71
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