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Address Translation
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System/370-XA mode and supported by MVS/XA. Multiple virtual storages of
2Gb each are supported by MVS/XA.
The address translation process (a two-level table lookup) using segment and page
tables and the DAT hardware is the same in 4381, 30XX, System/370, and other
4300 processors, as described in IBM System/ 3 70 Principles of Operation
(GA22-7000) and IBM System/ 3 70 Extended Architecture Principles of Operation
(SA22-7085).
However, there are differences in the format and contents of the segment and page
table entries for System/370 and System/370-XA modes of operation. In
addition, a 24-bit address is generated for System/370 mode and a 31-bit address
is generated for System/370-XA mode.
For System/370 mode of operation, the segment table entry has page table length,
page table origin (to supply a 24-bit address), segment protection, common
segment, and segment invalid fields. The segment protection bit in an entry
controls whether storing is permitted into the associated segment of virtual storage.
When this bit is zero, both fetching and storing are permitted for the segment.
When this bit is on, only fetching is permitted and a program interruption for
protection occurs if a store is attempted. The common segment bit is used with the
translation lookaside buffer (TLB), as described below.
For System/370-XA mode of operation, the segment table entry has page table
length, page table origin (to supply a 31-bit address), common segment, and
segment invalid fields. The common segment bit is functionally the same for
System/370 and System/370-XA modes. The common segment bit indicates
whether a page is contained in a private or common segment. The common
segment bit indicates the pages in the segment have the same addresses in every
virtual storage in which they appear. The common segment bit is used to avoid
invalidating entries in the TLB that are identified as common when the TLB must
be purged in a multiple virtual storage environment (such as MVS/370, MVS/XA,
or VM/370).
For System/370 mode of operation, the page table entry (a two-byte entry) has a
page frame address (to supply a 24-bit address) and an invalid bit. One bit is
available for programming use. One extended storage address bit in a page table
entry (defined for the Extended Addressing feature) is used in 4381 Processors
with more than 16Mb installed.
For System/370-XA mode of operation, the page table entry (a four-byte entry)
has a page frame address (to supply a 31-bit address), invalid bit, and page
protection bit. Eight bits are available for program use. The page protection bit
controls whether storing is permitted into the associated page of virtual storage.
When this bit is zero, both fetching and storing are permitted for the page. When
this bit is on, only fetching is permitted and a program interruption for protection
occurs if a store is attempted.
Section 50: Virtual Storage and Address Translation
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