IBM 4381 Manual page 105

Translation Lookaside Buffer
The time required for address translation utilizing the DAT hardware for
System/370 or System/370-XA mode is eliminated if the translation lookaside
buffer can be used for the translation. A translation lookaside buffer is
implemented primarily to minimize the amount of time required to perform address
translation when DAT mode is enabled.
However, in a 4381 Processor, the TLB is also used when System/370 mode is in
effect for BC mode operations and when EC mode is in effect without DAT
enabled. The TLB is used also for System/370-XA mode when DAT is not
enabled. The TLB is used for all modes so that the same microcode can be used,
regardless of the other modes in effect, and because accessing the protect key in
the TLB is faster than accessing the key stack.
The TLB contains 32 rows and 2 columns. Each row contains two entries (one per
column). Each entry contains one address translation, three status bits, a five-bit
store and fetch protect key, a common segment bit, and a page protect bit (to
support segment protection in System/370 mode and page protection in
System/370-XA mode). One least recently used (LRU) bit is associated with each
row (pair of entries) to determine which column to assign when a new translation is
loaded.
Two instructions are provided to perform programmed TLB invalidation. When
the INVALIDATE PAGE TABLE ENTRY (IPTE) instruction is issued, the
specified page table entry is invalidated and the TLB is inspected by hardware for
entries that use the now invalid page table entry. This instruction eliminates the
need to purge the entire TLB when only one TLB entry is invalidated.
All entries in the TLB are automatically invalidated when the segment or page size
in effect changes. The PURGE TLB instruction provides the capability of
invalidating all the TLB entries by programming (such as when control is switched
from one virtual storage to another). Any TLB entry with its common segment bit
on is not invalidated when TLB purging is done. The control program purges the
TLB as required.
Operation of the TLB cannot be disabled in a 4381 Processor. If an error occurs in
the TLB, the instruction in execution when the error occurred is retried if it is a
retryable instruction. For unretryable or uncorrectable errors, a machine check
error condition (system damage or instruction processing damage, depending on
the instruction being executed) exists.
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A Guide to the IBM 4381 Processor