Instruction Set - IBM 4381 Manual

Instruction Set
The instruction processing function contains a data local storage area of 256
doublewords for use during the execution of instructions. This data local storage
contains certain control registers, the general registers, the floating-point registers,
twelve channel work areas, save areas, and work areas.
A trace array of 32 entries is included in the instruction processing function to
trace the addresses of executed microcode. The array is always updated during
instruction execution and can be set to operate in one of two modes. In one mode,
the trace array contains the addresses of the last 32 microinstructions executed. In
the other mode, the trace array contains the addresses of the last 32
microinstructions that caused switching from one microcode module to another.
The trace array is provided to aid in error detection and recovery. The array helps
to indicate the cycle that caused the error when a machine check occurs.
A reconfiguration function is implemented for reloadable control storage, which
contains a spare area for this function. (Reconfiguration is provided for each
reloadable control storage in a 4381 Model Group 14 or 3 processor). If a parity
error occurs during a read from control storage, the read operation is retried once.
If the error is not corrected, reconfiguration is performed by the instruction retry
facility. The failing control storage address is placed in a reconfiguration register
and a space is allocated from the spare area. This space is then loaded with the
required microcode from the appropriate functional diskette. Thereafter, when the
reconfigured address is referenced, the spare area is accessed.
The operator is not notified when control storage reconfiguration is done and no
performance degradation occurs. Up to eight errors can be reconfigured. When
the ninth error occurs, reconfiguration is no longer possible, system operation
terminates, and the operator is notified that repair must be performed.
The address translation facilities provided for System/370 and System/370-XA
modes are discussed in Section 50. Other significant features of the instruction
processing function of 4381 Processors are discussed in the remainder of this
subsection.
The standard instruction set for 4381 Processors contains all the instructions
implemented for 4381 Processors (no instructions are optional). The standard
instruction set for a 4381 Processor Model Group 11, 12, 13, 1, or 2 operating in
System/370 mode consists of all the System/370 instructions defined in IBM
System/ 3 70 Principles of Operation
(GA22-7000) except those associated with
features not implemented in these 4381 model groups (READ DIRECT, WRITE
DIRECT, RESUME I/O, and multiprocessing and channel set switching
instructions).
The standard instruction set for a 4381 Processor operating in System/370-XA
mode consists of all the instructions defined in IBM System/ 3 70 Extended
Architecture Principles of Operation (SA22-7085).
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A Guide to the IBM 4381 Processor