IBM 4381 Manual page 73

The following facilities are implemented in a 4381 Model Group 14 or 3 to support
multiprocessing:
• Prefixing - a method of assigning unique areas of processor storage to
addresses 0 to 4095 for each instruction processor. The SET PREFIX and
STORE PREFIX instructions are provided.
• Processor addressing and STORE CPU ADDRESS instruction - required to
specifically identify each instruction processor. The instruction processor
address (0 or
1)
is stored during certain external interruptions to identify the
instruction processor involved and the STORE CPU ADDRESS instruction
enables a program to obtain the address of the instruction processor in which it
is executing.
• Interprocessor programmed communication via the SIGNAL PROCESSOR
(SIGP) instruction - required to enable an instruction processor to request
services of the other instruction processor and to alert it to conditions to which
it must respond during dual processor mode operations. For example, this
capability is used during the initialization of dual processor mode operations,
for reconfiguring hardware components, and in recovery procedures that occur
after an instruction processor failure.
In the 4381 Model Group 14 or 3, the CPU reset and initial CPU reset SIGP
orders are not implemented for System/370 mode and the IML SIGP order is
not implemented for System/370 or System/370-XA mode. See the Principles
of Operation manuals for the orders provided for the SIGP instruction.
• Interprocessor hardware communication - required to alert an instruction
processor to conditions in the other instruction processor and to synchronize
certain operations in both instruction processors during dual processor mode
operations.
The communication facilities include the following:
Synchronization of the two physical time-of-day clocks to provide one
logical clock for the dual processor configuration
Malfunction alert indication sent to the operational instruction processor
when one instruction processor enters the clock stopped state because of a
machine check error
High-speed buffer intercommunication to permit the buffer storage
controls to ensure that all real storage references by each instruction
processor result in access to the most current copy of the addressed data.
This communication is discussed in Section 30: 15 under "High-Speed
Buffer Storage."
The address translation facilities provided for System/370 and System/370-XA
modes for all 4381 model groups are discussed in Section 50. Other significant
features of the instruction processing functions in 4381 Model Groups 14 and 3 are
discussed in the remainder of this subsection.
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A Guide to the IBM 4381 Processor