IBM 4381 Manual page 50

The channels read into and write from processor storage using the input/ output
data register in the storage control function. When a channel writes data (input
operation from an
1/0
device), the buffer directory is interrogated. If data from
the affected processor storage address is being maintained in the buffer, the
channel writes the data to the high-speed buffer and processor storage is not
modified. Otherwise, the data is written to processor storage only.
When a channel reads data (output operation to an
1/0
device), the buffer
directory is interrogated, and if the required data is in the buffer and valid, it is read
from the buffer and presented to the channel. If the buffer does not contain the
required data, the channel reads the data from processor storage and the buffer is
not modified.
The store-in approach used for the high-speed buffers in 4381 Processors is like
that used in 4341, 4331 Model Group 2, 4361, 308X, and 3090 processors but
contrasts with the store-through approach used in the high-speed buffers in
System/370 and 303X processors in which processor storage is altered whenever
data is stored in the buffer. The store-in approach reduces the number of accesses
to processor storage, since changed buffer data is written to processor storage only
if it must be replaced by another block (or when a buffer purge is required). The
store-in approach becomes more and more advantageous as the difference between
processor storage and high-speed buffer storage cycle times becomes greater.
Buffer reconfiguration, which is not implemented in 4341 Processors, is standard in
4381 Processors. If a double-bit error occurs during the loading of a buffer block,
the load is tried once more. If the error is not corrected, buffer reconfiguration is
done, if possible, as part of the instruction retry function. The buffer array in
Model Groups 12, 13, and 2 contains spare space that is used for reconfiguration
purposes.
When an uncorrectable storage error occurs in a byte in a buffer block, space in the
reconfiguration area is allocated and a bit is set to indicate the reconfiguration area
is to be used for this buffer block. The buffer load is retried and operations
continue using the reconfiguration area for that buffer block if the load is
successful.
If a load is not successful after the reconfiguration (assigned reconfiguration array
location is malfunctioning), the buffer block location that caused the error can no
longer be used and the malfunctioning bit in the directory entry for the
malfunctioning block is turned on. The operator is notified that degradation is
occurring and system operation continues.
Up to eight buffer block errors can be reconfigured as long as no more than one
error occurs in a given byte position within a doubleword. When this limit is
reached, the operator is notified that the buffer should be repaired.
Reconfiguration is also attempted for errors that occur in the swap buffer. A
substitute array for the swap buffer is provided and, as for the high-speed buffer,
up to eight errors can be reconfigured as long as no more than one error occurs in a
given byte-pair position within a 16-byte data entry in the array. If the
reconfiguration limit is reached or an error occurs in a reconfigured byte position of
the swap array, the operator is notified that repair is required.
Operation of the entire high-speed buffer cannot be disabled in a 4381 Processor.
However, utilization of an individual buffer block can be disabled by turning on the
Section 20: 4381 Processor Uniprocessor Model Groups
41