IBM 4381 Manual page 81

Cross interrogation controls are provided for the two high-speed buffers to permit
each buffer storage control to access the buffer directory of the other high-speed
buffer.
General operation of the two high-speed buffers is as follows. When a fetch
request is made by an instruction processing function (say O) for instructions or
data, its high-speed buffer storage control determines whether the requested
doubleword is in high-speed buffer 0 by interrogating buffer directory 0, which
indicates the current contents of buffer 0. If the doubleword requested is present
in buffer 0 and valid, it is sent directly to instruction processing function 0 without
a processor storage reference.
If the requested doubleword is not currently in high-speed buffer 0, the cross
interrogation controls are used to search the buffer directory for high-speed buffer
1. If the requested doubleword is not in high-speed buffer 1 either, a processor
storage fetch is made, the data is assigned a buffer location and stored in buffer 0,
and the requested doubleword is sent to instruction processing function 0.
When data is stored by instruction processing function 0, high-speed buffer 0 is
updated if the contents of the processor storage location being altered are currently
being maintained in buffer 0. Processor storage is not modified, however, since the
high-speed buffer in 4381 Processors is a store-in, rather than a store-through, type
of buffer. If the data is not currently being maintained in buffer 0, the cross
interrogation controls are used to search the buffer directory for high-speed buffer
1. If the data is not currently being maintained in high-speed buffer 1 either, a
processor storage fetch is made to obtain the required block of data and load it into
buffer 0. The store is then made to the just loaded buffer location and processor
storage is not modified.
When a fetch or store request is made by instruction processing function 0 and the
referenced data is not in high-speed buffer 0 but is being maintained in high-speed
1, the action taken depends on whether the referenced data block in high-speed
buffer 1 has been modified. If it has, a buffer-to-buffer transfer is performed to
move the referenced block from buffer 1 to buffer 0 and this block is marked
invalid in buffer 1. The fetch or store is then made to the block in buffer 0.
If the referenced data block has not been modified in buffer 1 and a store request
was issued, the referenced block is invalidated in buffer 1, the referenced block of
data is loaded into buffer 0 from processor storage, and store is made to the block
in buffer 0. For a fetch request, the referenced block of data is loaded in buffer 0
from processor storage. The referenced block in buffer 1 is not invalidated but a
bit (copy) is set for this block in each buffer directory. If a write is subsequently
issued for a buffer block whose copy bit is on, the buffer block is changed in the
addressed buffer and invalidated in the other buffer.
If
the data in the buffer location that is to receive new block of data for a fetch or a
store request had been changed while in the buffer, this data must be unloaded
before the new data can be loaded. In order to reduce the time the instruction
processing function must wait for the requested data in this situation, a swap buffer
is implemented for each high-speed buffer. The changed data is written to the
swap buffer while processor storage is being accessed for the new block of data to
overlap most block unload time with processor storage access time. After the new
block is loaded and the requested data is sent to the instruction processing function,
the data in the swap buffer is written to processor storage.
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A Guide to the IBM 4381 Processor