Table of Contents
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M
mantissa field (floating point data) 4-17
manual terminology 1-10
manufacturers' documents D-1
manufacturing test process 3-23
MC68040 or MC68LC040 MPU 1-14
TRAP instructions 4-9
MC68xx040 cache 1-14
MCchip 2-6
ASIC 2-4
Register map 1-36
MCECC Internal Register memory map 1-37
memory boards 2-11
Memory Management Units (MMUs) 4-10
memory maps 1-25
VMEchip2 LCSR 1-32
memory
mezzanine 2-11
options 1-15
requirements 3-11
metasymbols, 162Bug 4-2
mezzanine
board dimensions G-11
boards 2-11
signals G-1
MK48T08 1-18
BBRAM/TOD Clock memory map 1-43
MPAR 3-21
MPCR 3-20
MPU clock speed calculation 3-11
Multiprocessor Address Register 3-21
Multiprocessor Control Register method 3-20
MVME162Bug 2-2, 3-1
debugging package J-1
http://www.mcg.mot.com/literature
MVME162FX C-1
board-level hardware features 1-1
block diagram 1-11
models 1-3
module installation 2-13
specifications 1-7
switch, header, connector, fuse, and
LED locations 2-3
MVME320 - Winchester/Floppy Controller
B-1, B-2
MVME323 - ESDI Winchester Controller
B-1, B-3
MVME327A - SCSI Controller B-1, B-3
MVME328 - SCSI Controller B-1, B-4
MVME350 - Streaming Tape
Controller B-1, B-4
MVME374 C-1
MVME376 C-1
N
negation 1-10
network
boot control module 3-19
I/O error codes 3-19
I/O support 3-18
No VMEbus Interface Option 1-14
Non-Volatile RAM (NVRAM) 1-18, A-3
normal address range 1-25
numeric values, expression of 4-3
O
object code 4-9
offset registers 4-6
operating environment, debugger 4-10
operational parameters A-3
option field, command line 4-1
overview 1-1
I
N
D
E
X
IN-5
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